Memory circuit and operating method thereof

Abstract

The embodiment of the invention discloses a memory circuit and an operating method thereof. The memory circuit may include a memory array, a first tracking unit, a second tracking unit, a first tracking circuit, and a second tracking circuit. A first portion of the memory array may include a plurality of first nominal memory cells coupled to a first bit line section extending in a first lateral direction. A second portion of the memory array may include a plurality of second nominal memory cells coupled to a second bit line section and a third bit line section each extending in the first lateral direction. The first tracking circuit may be configured to activate the first tracking cell in response to at least one of the first nominal memory cells being selected. The second tracking circuit may be configured to activate the second tracking cell in response to at least one of the second nominal memory cells being selected.

Description

Technical Field

[0001] Embodiments of the present application relate to memory circuits and methods of operating the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components such as transistors, diodes, resistors, capacitors, etc. In large part, the increase in integration density comes from the repeated reduction of the minimum feature size, which allows more components to be integrated into a given area. The flying bit line scheme is an effective technique for reducing the storage area because it allows the integration of peripheral devices in a single location. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory circuit is provided, comprising: a first portion of a memory array, comprising a plurality of first nominal memory cells coupled to a first bit line segment extending along a first lateral direction; a first tracking unit, arranged next to the first portion of the memory array along a second lateral direction perpendicular to the first lateral direction; a second portion of the memory array, comprising a plurality of second nominal memory cells coupled to a second bit line segment and a third bit line segment, both extending along the first lateral direction, wherein the third bit line segment is arranged vertically above the first bit line segment; a second tracking unit, arranged next to the second portion of the memory array along the second lateral direction; a first tracking circuit, configured to activate the first tracking unit in response to at least one of the first nominal memory cells being selected; and a second tracking circuit, configured to activate the second tracking unit in response to at least one of the second nominal memory cells being selected.

[0004] According to another aspect of an embodiment of the present application, a memory circuit is provided, comprising: a first portion of a memory array, comprising a plurality of first nominal memory cells; a first bit line coupled to the first nominal memory cells, wherein the first bit line comprises a first bit line segment disposed in a first metallization layer; a second portion of the memory array, comprising a plurality of second nominal memory cells; a second bit line coupled to the second nominal memory cells, wherein the second bit line comprises a second bit line segment and a third bit line segment disposed in the first metallization layer and the second metallization layer, respectively; a first tracking unit configured to simulate each of the plurality of first nominal memory cells; a second tracking unit configured to simulate each of the plurality of second nominal memory cells; a first tracking circuit configured to activate the first tracking unit in response to at least one of the first nominal memory cells being selected; and a second tracking circuit configured to activate the second tracking unit in response to at least one of the second nominal memory cells being selected.

[0005] According to another aspect of an embodiment of the present application, a method for operating a memory circuit is provided, comprising: determining a selection of at least one nominal memory cell of a memory array, wherein the memory array comprises a first portion and a second portion, wherein the first portion comprises a plurality of first nominal memory cells coupled to a first bit line segment extending along a first lateral direction, and the second portion comprises a plurality of second nominal memory cells coupled to a second bit line segment and a third bit line segment both extending along the first lateral direction; in response to at least one of the first nominal memory cells being selected, activating a first tracking cell, wherein the first tracking cell is disposed next to a first portion of the memory array along a second lateral direction perpendicular to the first lateral direction; and in response to at least one of the second nominal memory cells being selected, activating a second tracking cell, wherein the second tracking cell is disposed next to a second portion of the memory array along a second lateral direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a block diagram illustrating an example of a memory array according to some embodiments.

[0008] Figure 2 is a circuit diagram illustrating an example 6T memory cell according to some embodiments.

[0009] Figure 3 An example schematic diagram of a memory circuit according to some embodiments is shown.

[0010] Figure 4 is a block diagram illustrating an example flying bit line structure according to some embodiments.

[0011] Figure 5 is a block diagram illustrating a cross-section of an example semiconductor structure in accordance with some embodiments.

[0012] Figure 6 An example schematic diagram of a memory circuit according to some embodiments is shown.

[0013] Figure 7 A method for operating according to some embodiments is shown. Figure 6 Example waveforms of multiple control signals for a memory circuit including dual tracking for a flying bit line static random access memory (SRAM) architecture.

[0014] Figure 8Example waveforms for dual tracking of a flying bitline static random access memory (SRAM) architecture are shown in accordance with some embodiments.

[0015] Fig. 9 Example waveforms for dual tracking of a flying bitline static random access memory (SRAM) architecture are shown in accordance with some embodiments.

[0016] Fig.10 An example schematic diagram of a memory circuit according to some embodiments is shown.

[0017] Fig.11 An example schematic diagram of a memory circuit according to some embodiments is shown.

[0018] Fig.12 An example method of forming a dual-track memory circuit for a flying bitline static random access memory (SRAM) architecture according to some embodiments.

[0019] Fig.13 An example method of operating a dual-track memory circuit for a flying bitline static random access memory (SRAM) architecture according to some embodiments. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0021] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0022] The flying bit line (BL) scheme has proven to be effective in reducing storage area by integrating peripheral devices into a single location. However, the scheme also introduces higher capacitance and resistance due to the additional metallization layer (e.g., M2 layer) that brings the BL to the memory I / O. The increased resistance and capacitance (RC) requires additional power and timing. To alleviate this situation, a shared tracking method is used to synchronize the timing of the flying BL segment and the non-flying BL segment. The timing circuit is tuned to ensure that the read margin and write margin meet the requirements of the flying BL, and the timing circuit is also used for the non-flying BL segment. Unfortunately, the shared timing circuit causes the read and write margins of the non-flying BL segment to be higher than expected, resulting in an increase in the power consumption of the segment by about 20%. The effective power consumption is calculated as the average of the flying BL and non-flying BL segments. In addition, the word line (WL) in the upper segment and the WL in the lower segment are both synchronized using the same timing signal input clock.

[0023] The present disclosure provides various embodiments of a memory circuit, which is configured in a dual tracking flying bit line (BL) static random access memory (SRAM) architecture and is designed to solve the above technical problems without compromising design constraints. The memory circuit may include a memory array, a first tracking unit, a second tracking unit, a first tracking circuit, and a second tracking circuit. The first portion of the memory array may include a plurality of first nominal memory cells coupled to a first bit line segment extending along a first lateral direction. The first tracking unit may be arranged next to the first portion of the memory array along a second lateral direction perpendicular to the first lateral direction. The second portion of the memory array may include a plurality of second nominal memory cells coupled to a second bit line segment and a third bit line segment extending along the first lateral direction. The second tracking unit may be arranged next to the second portion of the memory array along the second lateral direction. The first tracking circuit may be configured to activate the first tracking unit in response to at least one of the first nominal memory cells being selected. The second tracking circuit may be configured to activate the second tracking unit in response to selecting at least one second nominal memory cell. In some embodiments, implementing separate timing circuits for the Fly BL and non-Fly BL segments allows for precise timing of each segment, eliminating margin overruns in the non-Fly BL segments. This optimization results in reduced power consumption for the non-Fly BL segments, with an average power reduction of approximately 20%. This power saving advantage can be observed for 512Kb instances (e.g., 0.5Mb), which typically consume approximately 8uA / MHz of active power. It is worth noting that smaller instances can achieve proportionally reduced power consumption.

[0024] Figure 1 is a block diagram illustrating an example of a memory array 10 according to some embodiments. Figure 1A memory array 10 having a plurality of memory cells 100 or bit cells 100 is shown. One or more peripheral circuits (not shown) may be located at one or more regions of the periphery or interior of the memory array 10. The memory cells 100 and the peripheral circuits may be coupled via word lines and / or complementary bit lines BL and BLB, and data may be read and written from the memory cells 100 via the bit lines BL and the complementary bit lines BLB. Different voltage combinations applied to the word lines and bit lines may define a read, erase, or write (program) operation on the memory cells.

[0025] Figure 2 is a circuit diagram illustrating an example 6T memory cell according to some embodiments. Figure 2 , shows an example circuit diagram of a memory cell (storage bit or bit cell) 200. According to some embodiments of the present disclosure, the memory cell 200 is configured as a static random access memory (SRAM) cell including a plurality of transistors. For example, in Figure 2 , the memory cell 200 includes a six-transistor (6T) SRAM cell. Each transistor can be formed in a nanostructure transistor configuration, which will be discussed in further detail below. In some other embodiments, the memory cell 200 can be implemented as any of a variety of other SRAM cells, for example, a two-transistor two-resistor (2T-2R) SRAM cell, a four-transistor (4T) SRAM cell, an eight-transistor (8T) SRAM cell, a ten-transistor (10T) SRAM cell, etc. In addition, although the discussion of the present disclosure is directed to SRAM cells, it should be understood that other embodiments of the present disclosure can also be used for any memory cell, such as a dynamic random access (DRAM) memory cell.

[0026] like Figure 2 As shown, the memory cell 200 includes 6 transistors: T1, T2, T3, T4, T5 and T6. Transistors T1 and T2 are formed as a first inverter, and transistors T3 and T4 are formed as a second inverter, wherein the first and second inverters are cross-coupled to each other. Specifically, the first and second inverters are both coupled between a first voltage reference 201 and a second voltage reference 203. In some embodiments, the first voltage reference 201 is a voltage level of a power supply voltage applied to the memory cell 200, commonly referred to as "Vdd". The second voltage reference 203 is commonly referred to as ground. The first inverter (formed by transistors T1 and T2) is coupled to transistor T5, and the second inverter (formed by transistors T3 and T4) is coupled to transistor T6. In addition to being coupled to the first and second inverters, transistors T6 and T5 are each coupled to a word line (WL) 205, and to a bit line (BL) 207 and a complementary bit line 209 (sometimes referred to as an inverted bit line or BLB).

[0027] In some embodiments, transistors T1 and T3 are referred to as pull-up transistors of memory cell 200 (hereinafter referred to as "pull-up transistor T1" and "pull-up transistor T3", respectively); transistors T2 and T4 are referred to as pull-down transistors of memory cell 200 (hereinafter referred to as "pull-down transistor T2" and "pull-down transistor T4", respectively); transistors T5 and T6 are referred to as access transistors of memory cell 200 (hereinafter referred to as "access transistor T5" and "access transistor T6", respectively). In some embodiments, transistors T2, T4, T5, and T6 each include an n-type metal oxide semiconductor (NMOS) transistor, and T1 and T3 each include a p-type metal oxide semiconductor (PMOS) transistor. Although Figure 1 and Figure 2 The embodiment shown. Figure 3 It is shown that the transistors T1-T6 are NMOS or PMOS transistors, and any of various transistors or devices suitable for memory devices can be implemented as at least one of the transistors T1-T6, such as a bipolar junction transistor (BJT), a high electron mobility transistor (HEMT), etc.

[0028] Access transistors T5 and T6 each have a gate coupled to WL 205. The gates of transistors T5 and T6 are configured to receive a pulse signal through WL 205 to correspondingly allow or prevent access to memory cell 200, which will be discussed in further detail below. Transistors T2 and T5 are coupled to each other at node 210 through the drain of transistor T2 and the source of transistor T5. Node 210 is also coupled to the drain of transistor T1 and node 212. Transistors T4 and T6 are coupled to each other at node 214 through the drain of transistor T4 and the source of transistor T6. Node 214 is also coupled to the drain of transistor T3 and node 216.

[0029] When a memory cell (e.g., memory cell 200) stores a data bit, the first node of the bit cell is configured to be in a first logic state (logic 1 or logic 0), and the second node is configured to be in a second logic state (or logic 0 or logic 1). The first and second logic states are complementary to each other. In some embodiments, the first logic state at the first node can represent the logic state of the data bit stored in the memory cell. For example, in Figure 1 and Figure 2 In the illustrated embodiment, when the memory cell 200 stores a data bit at a logic 1 state, the node 210 is configured to be at a logic 1 state and the node 214 is configured to be at a logic 0 state.

[0030] To read the logic state of the data bit stored in the memory cell 200, the BL 207 and the BLB 209 are precharged to Vdd (e.g., logic high, such as using a capacitor to hold the charge). Then, the WL 205 is asserted or activated to logic high by the assert signal, which turns on the access transistors T5 and T6. Specifically, the rising edge of the assert signal is received at the gates of the access transistors T5 and T6, respectively, to turn on the access transistors T5 and T6. Once the access transistors T5 and T6 are turned on, the precharged BL 207 or BLB 209 can begin to discharge based on the logic state of the data bit. For example, when the memory cell 200 stores a logic 0, the node 214 (e.g., Q) can present a voltage corresponding to a logic 1, and the node 210 (e.g., Qbar) can present a voltage corresponding to a complementary logic 0. In response to the conduction of access transistors T5 and T6, a discharge path can be provided from the precharged BLB 209, through the access transistor T5, the pull-down transistor T2, to the ground 203. When the voltage level on the BLB 209 is pulled down by this discharge path, the pull-down transistor T4 can remain turned off. Therefore, BL 207 and BLB 209 can respectively present voltage levels that produce a sufficiently large voltage difference between BL 207 and BL 209. Therefore, the sense amplifier coupled to BL 207 and BLB 209 can use the polarity of the voltage difference to determine whether the logic state of the data bit is a logic 1 or a logic 0.

[0031] In order to write the logic state of the data bit stored in the memory cell 200, the data to be written is applied to the BL 207 and / or the BLB 209. For example, the BLB 209 is connected / shorted to 0V (e.g., ground 203) through a low impedance connection. Then, WL205 is asserted or activated to a logic high by the assertion signal, which turns on the access transistors T5 and T6. Once the access transistors T5 and T6 are turned on, based on the logic state of the BLB 209, the node 210 can begin to discharge. For example, before T5 and T6 are turned on, the BLB 209 can present a voltage corresponding to a logic 0, and the node 210 can present a voltage corresponding to a complementary logic 1. In response to the access transistors T5 and T6 being turned on, a discharge path from the node 210 through the access transistor T5 to the ground 203 can be provided. Once the voltage level on node 210 is pulled down below the Vth (threshold voltage) of pull-down transistor T4, T4 may be turned off and T3 may be turned on, causing node 214 to be pulled up to Vdd 201. Once node 214 is less than the Vth of Vdd 201, T1 may be turned off and T2 may be turned off, causing node 210 to be pulled down to ground 203. Then, when WL 205 is de-asserted, the logic state applied to BL 207 and / or BLB 209 has been stored in memory cell 200.

[0032] Figure 3 1 shows a memory circuit 300 (eg, a memory array configured in an SRAM architecture (eg, Figure 1 10)) in the example schematic diagram. Specifically, Figure 3 An example schematic diagram 300 of a dual tracking flying bit line (BL) static random access memory (SRAM) architecture according to some embodiments is shown. As a brief overview, the memory circuit 300 may include a memory array 302, a first tracking unit 316, a second tracking unit 336, a first tracking circuit 318, and a second tracking circuit 338. Although Figure 3 Although not shown in FIG. 3 , all components of memory circuit 300 may be coupled to each other and to a control (CTRL) logic circuit to receive control signals (eg, D, Q, CLK, CEB, WEB signals). Figure 3 In the illustrated embodiment, each component is shown as a separate block for clarity of illustration, but in some other embodiments. Figure 3 Some or all of the components shown in can be integrated together. For example, memory array 302 can include embedded I / O circuits (e.g., 350). For illustrative purposes, Figure 3 The memory circuit 300 is simplified, therefore, it should be understood that Figure 3 Can be omitted Figure 1 and Figure 2 Some components in .

[0033] In some embodiments, the memory array 302 may include a plurality of nonvolatile memory cells 312, 314, 332, 334. A nonvolatile memory cell may retain stored data in the absence of power, whereas a volatile memory device loses its data storage content when power is removed. The nonvolatile memory cell may include any of a variety of nonvolatile memory cells, such as a static random access memory (SRAM) cell, a resistive random access memory (RRAM) cell, a spin transfer torque random access memory (STT-RAM) cell, a ferroelectric random access memory (FeRAM) cell, a magnetoresistive random access memory (MRAM) cell, a phase change random access memory (PCRAM) cell, etc. In some embodiments, the nonvolatile memory cell may be configured to be programmed from a first state to a second state.

[0034] In some embodiments, a first portion 310 (e.g., a lower section, a non-flying BL section) of the memory array 302 may include a plurality of first nominal memory cells 312, 314. The plurality of first nominal memory cells 312, 314 may be coupled to a first bit line section 313 extending along a first lateral direction (e.g., a Y direction).

[0035] In some embodiments, a second portion 330 (e.g., an upper section, a flying BL section) of the memory array 302 may include a plurality of second nominal memory cells 332, 334. The plurality of second nominal memory cells 332, 334 may be coupled to a second bit line section 333 and a third bit line section 335 extending along a first lateral direction (e.g., a Y direction). The third bit line section 335 may be vertically disposed above the first bit line section 313.

[0036] In some embodiments, the first bit line segment 313 and the second bit line segment 333 may be disposed in a first metallization layer (e.g., M0 or M1). In some embodiments, the third bit line segment 335 may be disposed in the same metallization layer (e.g., M0 or M1). In some embodiments, the third bit line segment 335 may be disposed in a different metallization layer (e.g., second metallization layer M2) above the first metallization layer. In various embodiments, a flying shared bit line structure may be configured in the memory circuit 300. The term "flying shared bit line" may refer to at least two pairs of bit lines having a segment connection with a corresponding component (e.g., a memory cell) at different positions (e.g., a lower segment and an upper segment). For example, the first bit line segment 313 may physically extend through the first portion 310 of the substrate along a first lateral direction (e.g., a Y direction), wherein a plurality of first nominal memory cells 312, 314 are formed by a memory I / O (MIO) device 350. The second bit line segment 333 can physically extend through the second portion 330 along a first lateral direction (e.g., the Y direction), wherein the plurality of second nominal memory cells 332, 334 are formed by the first portion 310. The third bit line segment 335 can physically extend through the first portion 310 from the memory I / O device 350 along the first lateral direction (e.g., the Y direction). The third bit line segment 335 can be disposed vertically above the first bit line segment 313.

[0037] In some embodiments, the first tracking unit 316 can be disposed adjacent to the first portion 310 of the memory array 302 along a second lateral direction (e.g., X direction) perpendicular to the first lateral direction (e.g., Y direction). The first tracking unit 316 can be a component or subsystem within an electronic system that is responsible for monitoring and maintaining a specific parameter or signal within a desired range. In the context of a memory architecture such as SRAM, the first tracking unit 316 can be used to ensure that timing signals, voltages, or currents associated with different segments or components of the memory operate within specified limits.

[0038] In some embodiments, the second tracking unit 336 can be disposed adjacent to the second portion 330 of the memory array 302 along a second lateral direction (e.g., the X direction). The second tracking unit 336 can be a component or subsystem within an electronic system that is responsible for monitoring and maintaining a specific parameter or signal within a desired range. In the context of a memory architecture such as SRAM, the second tracking unit 336 can be used to ensure that timing signals, voltages, or currents associated with different segments or components of the memory operate within specified limits.

[0039] In some embodiments, the first tracking circuit 318 may be configured to activate the first tracking unit 316 in response to at least one of the first nominal memory cells 312, 314 being selected. The first tracking circuit 318 may include at least one of a first AND gate 322, a first tracking word line 323 coupled to a gate terminal of the first tracking unit 316, or a first buffer 324. The first AND gate 322 may have a first input terminal 322b configured to receive a clock signal (e.g., internal CLK) and a second input terminal 322a configured to receive a first control signal (e.g., SLE2) asserted to a first logic state (e.g., "1") when at least one of the first nominal memory cells 312, 314 is selected. The first AND gate 322 may be configured to assert the first tracking word line 323 to a first logic state (e.g., "1") when at least one of the first nominal memory cells 312, 314 is selected. In some embodiments, the first tracking circuit 318 may be configured to provide a timing signal for a non-flying BL.

[0040] In some embodiments, the first tracking circuit 318 may also include at least one of the following: a first NAND (NAND) gate 326 and a first inverter 328, the first inverter 328 being coupled to a first word line 325 coupled to the at least one first nominal memory cell 312. The first NAND gate 326 may have a first input terminal 326a and a second input terminal 326b, the first input terminal 326 being configured to receive a first address signal (e.g., DecX) asserted to a first logic state when the at least one first nominal memory cell 312 is selected, and the second input terminal 326b is configured to receive a first signal (e.g., CLKX_Non-Fly) present on a first tracking bit line 327 coupled to the first tracking cell 316. If the Fly BL segment is selected, all of the S1, S2, and S3 signals may be set to "0"

[0041] In some embodiments, the second tracking circuit 338 may be configured to activate the second tracking unit 336 in response to at least one of the second nominal memory cells 332, 334 being selected. The second tracking circuit 338 may include at least one of a second AND gate 342, a second tracking word line 343 coupled to a gate terminal of the second tracking unit 336, or a second buffer 344. The second AND gate 342 may have a first input terminal 342b configured to receive a clock signal (e.g., internal CLK) and a third input terminal 342a configured to receive a second control signal (e.g., SEL1) asserted to a first logic state (e.g., "1") when at least one second nominal memory cell 332, 334 is selected. The second AND gate 342 may be configured to assert the second tracking word line 343 to a first logic state (e.g., "1") when at least one second nominal memory cell 332, 334 is selected. In some embodiments, the second tracking circuit 338 may be configured to provide a timing signal for the flying BL.

[0042] In some embodiments, the second tracking circuit 338 may include at least one of the following: a second NAND gate 346 and a second inverter 348, the second inverter 348 being coupled to a second word line 345 coupled to at least one second nominal memory cell 332. The second NAND gate 346 may have a first input terminal 346a and a second input terminal 346b, the first input terminal 34da being configured to receive a second address signal (e.g., DecX) asserted as a first logic state when selecting at least one second nominal memory cell 332, and a second input terminal 346b being configured to receive a second signal (e.g., CLKX_Fly) present on a second tracking bit line 347 coupled to the second tracking cell 336. In some embodiments, DecX may be a corresponding row enable signal generated by a row decoder. The internal CLK (ICLK) may be generated by a clock generator of the global control circuit based on the input clock (CLK). In some embodiments, the wiring path of the non-flying BL may be shorter than the wiring path of the flying BL. In some embodiments, WL 345 in upper section 330 and WL 325 in lower section 310 may use different timing signals, such as CLKX_Fly and CLKX_Non-Fly. In some embodiments, when at least one first nominal memory cell is selected, a first signal present on a first word line has a first pulse width. When at least one second nominal memory cell is selected, a second signal present on a second word line has a second pulse width. The first pulse width is narrower than the second pulse width.

[0043] In some embodiments, the memory circuit 300 may include a memory I / O (MIO) device 350. The memory I / O device may include a sense amplifier, a write driver, an input buffer, and an output buffer. The memory I / O device may include several key components necessary for data transmission and communication within a computer system. These components may include a sense amplifier, which is responsible for detecting and amplifying weak signals from memory cells during read operations, ensuring accurate data retrieval. In addition, a write driver is used to send data from the memory system to an external device or storage medium, thereby effectively facilitating write operations. In addition, the input and output buffers can manage the data flow between the memory system and the external device, ensuring uninterrupted communication and data transmission. Overall, these components together form a memory I / O device, enabling efficient data exchange between the memory circuits 300.

[0044] By incorporating different timing signals (eg, SEL1 and SEL2) for the flying lead BLs in the upper bank 330 and the non-flying lead BLs in the lower bank 310 of the SRAM, as well as separate read trace and write trace paths for each bank, several advantages emerge.

[0045] Figure 4 is a diagram showing some embodiments of the present invention. Figure 3 Block diagram of an example flying bit line structure 400 of a portion of a memory circuit 300 is shown. In a flying bit line (BL) static random access memory (SRAM) architecture 400, flying BLs 333, 335 (e.g., BL-N at M2) in an upper segment 330 are designed to fly over BLs 313 (e.g., BL-N at M0) in a lower segment 310. BL 313 may include a first bit line segment 313. The flying line BL may include a second bit line segment 333 and a third bit line segment 335 both extending along a first lateral direction (e.g., Y direction). The third bit line segment 335 may be vertically disposed above the first bit line segment 313. All segments 313, 333, 315 may be connected to the same memory I / O device 350, thereby facilitating efficient data transfer and communication within the memory system. This design allows for a compact layout while ensuring that the flying BL and non-flying BL segments operate efficiently, contributing to the overall performance and functionality of the SRAM memory architecture.

[0046] In some embodiments, the first tracking unit 316 can be disposed adjacent to the first portion 310 of the memory array 302 along a second lateral direction (e.g., X direction) perpendicular to the first lateral direction (e.g., Y direction). The second tracking unit 336 can be disposed adjacent to the second portion 330 of the memory array 302 along a second lateral direction (e.g., X direction). The individual tracking units 316, 336 can be components or subsystems within the memory circuit 300 responsible for monitoring and maintaining a particular parameter or signal within a desired range. In some embodiments, implementing separate timing circuits for the flying BL 330 and the non-flying BL segments 310 allows for precise timing of each segment, eliminating margin overruns in the non-flying BL segments. This optimization results in reduced power consumption for the non-flying BL segments, with an average power reduction of approximately 20%. This power saving advantage can be observed for a 512Kb instance (e.g., 0.5Mb), which typically consumes approximately 8uA / MHz of effective power. It is noteworthy that smaller instances can proportionally reduce power consumption.

[0047] To further explain Figure 3 and Figure 4 The relative (e.g., vertical) arrangement of these structures in Figure 5 An example semiconductor structure 500 (eg, Figure 3 The embodiment shown includes a FEOL layer including a semiconductor structure and a BEOL layer including an interconnect metal layer structure.

[0048] In the illustrated embodiment, the FEOL layer shows a transmission gate FinFET transistor 510. The transmission gate FinFET transistor 510 includes a semiconductor substrate, fins, isolation regions, a polysilicon structure (e.g., polysilicon), conductive contact members S and D connected to the fins, and a conductive G contact member connected to the polysilicon structure. In the illustrated embodiment, the current conduction path is the fin (the fin may also be referred to as a diffusion region or an oxide diffusion region). The polysilicon structure serves as a gate, allowing current to flow in the fin from the S (e.g., source) contact member to the D (e.g., drain) contact member. For example, for the voltage potential between the S and D contact members, current can flow in the fin from S to D according to the voltage applied to the polysilicon structure. If a voltage less than the threshold voltage is applied to the polysilicon, a perceivable current cannot flow in the fin from the S contact member to the D contact member, and the transistor 510 is "off". If a current greater than or equal to the threshold voltage is applied to the polysilicon, a perceivable current flows through the fin from S to D, and the transistor 510 is in the "on" state. In some embodiments, the S, D, and G contact members form connections between multiple fins and polysilicon structures in the FEOL layer, thereby connecting the source, drain, and gate of one or more transistors. In some embodiments, the source, drain, and gate of the transistor 510 are connected to an interconnect metal layer structure in the BEOL layer. For example, typically the gate of the transistor 510 is connected to a word line, which is one of the metal strips in a layer of the interconnect metal structure in the BEOL layer, and the S / D contact members of the transmission gate transistor 510 can be similarly connected to complementary bit lines BL and BLB, which are other metal strips in one or more metal layers in the BEOL layer. In some embodiments, the BEOL layer is used to connect the transistor 510 to peripheral circuits, such as for read / write operations. In the illustrated embodiment, the D and G contact members are connected to the metal strips in the BEOL layer using vias. For example, Via1 (via 1) forms a connection between the D contact member and the metal strip (e.g., bit line) in the first metal layer M1 above the FEOL layer. In the illustrated embodiment, a separate Via1 connects the G contact member to a conductive landing pad in the M1 layer, and Via2 connects the conductive landing pad to a metal strip in the M2 layer, such as a word line. In some embodiments, the conductive landing pad in the M1 layer can be formed by a metal strip that is cut or disconnected within its metal layer plane.

[0049] Figure 6 FIG. shows an example schematic diagram of a memory circuit 600 according to some embodiments. Figure 6 is shown by introducing trace bit cells 616, 636 for writing and trace bit cells 626, 646 for reading Figure 3The memory circuit 600 may include a memory array, a first tracking unit 616 , a second tracking unit 636 , a third tracking unit 626 , a fourth tracking unit 646 , a first tracking circuit 618 , a second tracking circuit 638 , a third tracking circuit 628 , and a fourth tracking circuit 648 . Figure 6 The memory circuit 600 is Figure 3 The memory circuit 300 is substantially similar except for the additional tracking cells 616, 618, 636, 638 and the additional tracking circuits 618, 628, 638, 648. The implementation of separate read / write tracking paths provides greater tuning flexibility, improving the overall performance and efficiency of the SRAM architecture.

[0050] In some embodiments, a first tracking cell 616 (e.g., a tracking bit cell for write (WTBC2)) can be disposed adjacent to the first portion 310 of the memory array 302 along a second lateral direction (e.g., X direction) perpendicular to the first lateral direction (e.g., Y direction). The first tracking cell 616 can be a component or subsystem within the memory circuit 600 that is responsible for monitoring and maintaining a specific parameter or write signal within a desired range. In the context of a memory architecture such as SRAM, the first tracking cell 616 can be used to ensure that write timing signals, voltages, or currents associated with different segments or components of the memory operate within specified limits.

[0051] In some embodiments, a second tracking unit 636 (e.g., a tracking bit cell for write (WTBC1)) can be disposed adjacent to the second portion 330 of the memory array 302 along a second lateral direction (e.g., X direction) perpendicular to the first lateral direction (e.g., Y direction). The second tracking unit 636 can be a component or subsystem within the memory circuit 600 that is responsible for monitoring and maintaining a specific parameter or write signal within a desired range. In the context of a memory architecture such as SRAM, the second tracking unit 636 can be used to ensure that write timing signals, voltages, or currents associated with different segments or components of the memory operate within specified limits.

[0052] In some embodiments, a third tracking cell 618 (e.g., a tracking bit cell for read (RTBC2)) can be disposed adjacent to the first portion 310 of the memory array 302 along a second lateral direction (e.g., X direction) perpendicular to the first lateral direction (e.g., Y direction). The third tracking cell 618 can be a component or subsystem within the memory circuit 600 that is responsible for monitoring and maintaining a specific parameter or read signal within a desired range. In the context of a memory architecture such as SRAM, the third tracking cell 618 can be used to ensure that read timing signals, voltages, or currents associated with different segments or components of the memory operate within specified limits.

[0053] In some embodiments, a fourth tracking cell 638 (e.g., a tracking bit cell for read (RTBC1)) can be disposed adjacent to the second portion 330 of the memory array 302 along a second lateral direction (e.g., X direction) perpendicular to the first lateral direction (e.g., Y direction). The fourth tracking cell 638 can be a component or subsystem within the memory circuit 600 that is responsible for monitoring and maintaining a specific parameter or read signal within a desired range. In the context of a memory architecture such as SRAM, the fourth tracking cell 638 can be used to ensure that read timing signals, voltages, or currents associated with different segments or components of the memory operate within specified limits.

[0054] In some embodiments, the first tracking circuit 618 may be configured to activate the first tracking unit 616 in response to at least one first nominal memory cell in the lower segment 310 being selected. The first tracking circuit 618 may include at least one of a first AND gate 622, a first tracking word line 623 coupled to a gate terminal of the first tracking unit 316, or a first buffer 624. The first AND gate 622 may have a first input terminal configured to receive a clock signal (e.g., an internal CLK), and a second input terminal configured to receive a first control signal (e.g., a read segment select (non-flying BL)) asserted to a first logic state (e.g., “1”) when at least one first nominal memory cell in the lower segment 310 is selected. The first AND gate 622 may be configured to assert the first tracking word line 623 to a first logic state (e.g., “1”) when at least one first nominal memory cell in the lower segment 310 is selected. In some embodiments, the first tracking circuit 618 may be configured to provide a read timing signal for the non-flying BL.

[0055] In some embodiments, the second tracking circuit 638 may be configured to activate the second tracking unit 636 in response to at least one second nominal memory cell in the upper section 330 being selected. The second tracking circuit 638 may include at least one of a second AND gate 642, a second tracking word line 643 coupled to a gate terminal of the second tracking unit 636, or a second buffer 644. The second AND gate 642 may have a first input terminal configured to receive a clock signal (e.g., an internal CLK), and a second input terminal configured to receive a second control signal (e.g., a read section select (fly-BL)) asserted to a first logic state (e.g., “1”) when at least one second nominal memory cell in the upper section 330 is selected. The second AND gate 642 may be configured to assert the second tracking word line 643 to a first logic state (e.g., “1”) when at least one second nominal memory cell in the upper section 330 is selected. In some embodiments, the second tracking circuit 638 may be configured to provide a read timing signal for the fly-BL.

[0056] In some embodiments, the third tracking circuit 628 may be configured to activate the third tracking unit 628 in response to at least one of the first nominal memory cells in the lower segment 310 being selected. The third tracking circuit 628 may include at least one of a third AND gate 632, a first tracking word line 633 coupled to the gate terminal of the third tracking unit 618, or a third buffer 634. The third AND gate 632 may have a first input terminal configured to receive a clock signal (e.g., an internal CLK), and a second input terminal configured to receive a first control signal (e.g., a write segment select (non-flying line BL)) asserted as a first logic state (e.g., “1”) when at least one of the first nominal memory cells in the lower segment 310 is selected. The third AND gate 632 may be configured to assert the third tracking word line 633 as a first logic state (e.g., “1”) when at least one of the first nominal memory cells in the lower segment 310 is selected. In some embodiments, the third tracking circuit 628 may be configured to provide a write timing signal for the non-flying BL.

[0057] In some embodiments, the fourth tracking circuit 648 may be configured to activate the fourth tracking cell 638 in response to at least one second nominal memory cell in the upper section 330 being selected. The fourth tracking circuit 648 may include at least one of a fourth AND gate 652, a fourth tracking word line 653 coupled to a gate terminal of the fourth tracking cell 638, or a fourth buffer 654. The fourth AND gate 652 may have a first input terminal configured to receive a clock signal (e.g., an internal CLK), and a second input terminal configured to receive a second control signal (e.g., a write segment select (fly-BL)) asserted to a first logic state (e.g., “1”) when at least one second nominal memory cell in the upper section 330 is selected. The fourth AND gate 652 may be configured to assert the fourth tracking word line 653 to a first logic state (e.g., “1”) when at least one second nominal memory cell in the upper section 330 is selected. In some embodiments, the fourth tracking circuit 648 may be configured to provide a write timing signal for the fly-BL. In some embodiments, when at least one first nominal memory cell is selected, a first signal present on a first word line has a first pulse width. When at least one second nominal memory cell is selected, a second signal present on a second word line has a second pulse width. The first pulse width is narrower than the second pulse width.

[0058] In some embodiments, the memory circuit 600 may include a global control circuit 660. The global control circuit 660 may be configured to generate control signals based on CLK, CEB, and / or WEB signals. CLK may represent a clock signal, where "H" represents a high (active) state and "L" represents a low (inactive) state. CEB may represent an inverted chip enable, where "L" represents chip enable and "H" represents chip disable. WEB may represent an inverted write enable, where "H" represents write disable and "L" represents write enable. The operation may be based on the state of the clock signal (CLK), the inverted chip enable (CEB), and / or the inverted write enable (WEB) signal. If the clock is high (active), the chip is enabled (CEB is low), and the write is disabled (WEB is high), then the operation may be a read operation. If the clock is high (active), the chip is enabled (CEB is low) and the write is enabled (WEB is low). If the clock is low (inactive), the operation may be in a standby state regardless of the state of CEB and WEB. If the clock is high (active) and the chip is disabled (CEB is high), the operation can also be in standby mode regardless of the state of WEB.

[0059] In the operation logic of the storage system, only one of the following operations can be enabled at any given timing: upper segment read, upper segment write, lower segment write, or lower segment read. This ensures that the memory operates in a controlled and sequential manner, preventing conflicting operations and maintaining data integrity. In addition, at any given moment, only one of the operations represented by WTBC1, RTBC1, WTBC2, or RTBC2 can be activated. This design ensures efficient resource utilization and prevents concurrent access conflicts, helping to improve the overall stability and reliability of the storage system.

[0060] In the memory architecture, read and write operations in the upper segment involving the flying BL utilize different timing signals tailored to the specific requirements of that segment. At the same time, read and write operations in the lower segment involving the non-flying BL also use different timing signals optimized for the function of that segment. This approach ensures that each segment operates efficiently and independently, improving the overall performance and reliability of the memory system. By using separate timing signals for the flying BL and non-flying BL segments, the memory architecture can effectively manage data access and transfer, helping to improve functionality and reduce operational complexity.

[0061] Figure 7 A method for operating according to some embodiments is shown. Figure 6 Example waveforms of a plurality of control signals for a memory circuit 600 including dual trace for a flying-wire static random access memory (SRAM) architecture.

[0062] The waveforms of the multiple control signals begin with the activation of the internal CLK that goes high after the rising edge of the main CLK signal (stage 702). Subsequently, CLKX and DecX are activated (stage 704), where CLKX experiences a tracking delay when passing through the tracking bit cell and the tracking bit line. At the same time, DecX also reaches high (stage 704). When both DecX and CLKX are in the "1" state, indicating that they are activated, WL_Non-fly is asserted (stage 706). After a period of time marked by the DecX activation, the internal CLK transitions from high to low (stage 708). Subsequently, DecX transitions to a low state (stage 710), resulting in the de-assertion of WL_Non-fly (stage 712). At this point, the sense amplifier is engaged and once the voltage difference reaches a sufficient level, the voltage difference between BL and BLB is sensed to complete the specified operation within the memory circuit 600.

[0063] Figure 8 An example waveform (read trace) for dual tracking of a flying bitline static random access memory (SRAM) architecture according to some embodiments is shown. In waveforms that do not implement dual tracking flying bitline SRAM architecture, the pulse width of the non-flying segment WL is the same as the flying segment WL.

[0064] The proposed modification is intended to optimize the power consumption during the read operation in the memory circuit 300, 600. Due to the larger capacitance of the non-flying segment WL, the WL pulse width of the non-flying segment can be shorter than the pulse width of the flying segment. The pulse width of the non-flying segment WL can be shortened. This adjustment is intended to reduce the power consumption during the read operation, and the efficiency improvement is achieved by utilizing the capacitance difference between the two segments (the flying segment and the non-flying segment). In the present disclosure, separating the read and write tracking allows for enhanced tuning flexibility. Therefore, each segment can have two tracking elements—one dedicated to read operations and the other for write operations. This separation enables more fine control and optimization of timing parameters, which helps to improve the performance and reliability of the memory circuit 300, 600.

[0065] Fig. 9 An example waveform (write trace) for dual tracking of a flying bit line static random access memory (SRAM) architecture according to some embodiments is shown. In the waveform without implementing the dual tracking flying bit line SRAM architecture, the pulse width (write margin) of the non-flying segment WL is the same as the flying segment WL.

[0066] The proposed modification is intended to optimize the power consumption during write operations in the memory circuit 300, 600. Due to the larger capacitance of the non-flying segment WL, the pulse width (write margin) of the WL of the non-flying segment may be shorter than the pulse width of the flying segment. The pulse width of the non-flying segment WL can be shortened. This adjustment is intended to reduce the power consumption during the write operation, using the capacitance difference between the two segments (the flying segment and the non-flying segment) to improve efficiency. In the present disclosure, separating the read and write tracking allows for enhanced tuning flexibility. Therefore, each segment can have two tracking elements—one dedicated to read operations and the other for write operations. This separation enables more fine control and optimization of timing parameters, which helps to improve the performance and reliability of the memory circuit 300, 600.

[0067] Fig.10 An example schematic diagram of a memory circuit 1000 is shown in accordance with some embodiments. Fig.10 By introducing delay buffers 1002, 1004, it is shown Figure 3 The memory circuit 1000 may include a memory array 302, a first tracking / delay circuit 318, a second tracking / delay circuit 338, a first delay buffer 1002, and a second delay buffer 1004. In addition to the delay buffers 1002 and 1004, Fig.10 The memory circuit 1000 is Figure 3 The memory circuit 300 is substantially similar to the memory circuit 300. The implementation of the delay buffer provides greater tuning flexibility and improves the overall performance and efficiency of the SRAM architecture.

[0068] In some embodiments, the memory circuit 1000 includes a delay buffer to fine-tune the timing signals of the non-flying BL segment 310 and the flying BL segment 330. Considering that the non-flying bit line segment 310 requires a shorter delay, the first tracking / delay circuit 318 of the non-flying BL can include a smaller buffer 1002 to achieve the adjustment. On the contrary, since the flying BL segment 330 requires a longer delay, the second tracking / delay circuit 338 of the flying BL can include a larger buffer 1004 to meet this requirement. This differential buffering method ensures that the timing signal is accurately adjusted for each segment, thereby optimizing the performance and function of the memory circuit. In some embodiments, the first tracking / delay circuit 318 can be configured to provide a timing signal for the non-flying BL (shorter delay). The second tracking / delay circuit 338 can be configured to provide a timing signal for the flying BL (longer delay).

[0069] Fig.11 An example schematic diagram of a memory circuit 1100 is shown in accordance with some embodiments. Fig.11 By introducing delay buffers 1102, 1104, it is shown Figure 6The memory circuit 1100 may include a memory array, a first tracking / delay circuit 618, a second tracking / delay circuit 638, a third tracking / delay circuit 628, a fourth tracking / delay circuit 648, a first delay buffer 1102, and a second delay buffer 1104. In addition to the delay buffers 1102 and 1104, Fig.11 The memory circuit 1100 is Figure 6 The memory circuit 600 is substantially similar to the memory circuit 600. The implementation of the delay buffer provides greater tuning flexibility and improves the overall performance and efficiency of the SRAM architecture.

[0070] In some embodiments, the memory circuit 1100 incorporates a delay buffer to fine-tune the timing signals of the non-flying BL segment 310 and the flying BL segment 330. Considering that the non-flying bit line segment 310 requires a shorter delay, the first tracking / delay circuit 618 and the third tracking / delay circuit 628 for the non-flying BL can be combined with a smaller buffer 1102 to achieve the adjustment. In contrast, since the flying bit line segment 330 requires a longer delay, the second tracking / delay circuit 638 and the fourth tracking / delay circuit 648 for the flying BL can include a larger buffer 1104 to meet this requirement. This differential buffering method ensures that the timing signals are accurately adjusted for each segment, thereby optimizing the performance and function of the memory circuit. In some embodiments, the first tracking / delay circuit 618 can be configured to provide a read timing signal for the non-flying BL (shorter delay). The third tracking / delay circuit 628 can be configured to provide a write timing signal for the non-flying BL (shorter delay). The second tracking / delay circuit 638 can be configured to provide a read timing signal for the flying BL (longer delay). The fourth tracking / delay circuit 648 may be configured to provide write timing signals for the flying BL (longer delay).

[0071] In the memory circuit, read and write operations in the upper segment, especially those involving the flying BL, can be controlled by different timing signals tailored to the unique requirements of the segment. Similarly, read and write operations in the lower segment associated with the non-flying BL also utilize different timing signals optimized for the characteristics of the segment. This approach ensures that each segment operates efficiently and independently, preventing interference and optimizing data access and transmission within the memory system. By adopting separate timing signals for the flying BL and non-flying BL segments, the memory architecture can effectively manage read and write operations, improving overall performance and reliability.

[0072] Fig.12 is an example method of forming a dual-track memory circuit for a flying bitline static random access memory (SRAM) architecture according to some embodiments. In general, method 1200 can include fabricating a memory circuit for a dual-track flying bitline static random access memory (SRAM) architecture.

[0073] Referring to (1202), in some embodiments, a first portion 310 (e.g., a lower section, a non-flying BL section) of a memory array can be formed in a first region of a substrate. The first portion 310 of the memory array can include a plurality of first nominal cells 312, 314. The first portion 310 (e.g., a lower section, a non-flying BL section) of the memory array 302 can include a plurality of first nominal memory cells 312, 314.

[0074] Referring to (1204), in some embodiments, a second portion 330 (e.g., an upper section, a flying BL section) of the memory array can be formed in a second region of the substrate. The second portion 330 of the memory array can include a plurality of second nominal cells 312, 314, and the second region is located next to the first region along a first lateral direction (e.g., Y direction).

[0075] Referring to (1206), in some embodiments, a first tracking circuit 318 may be formed that is configured to activate the first tracking cell 316 for simulating at least one of the first nominal cells 312, 314. The first tracking circuit 318 may include at least one of a first AND gate 322, a first tracking word line 323 coupled to a gate terminal of the first tracking cell 316, or a first buffer 324. The first AND gate 322 may have a first input terminal 322b configured to receive a clock signal (e.g., internal CLK) and a second input terminal 322a configured to receive a first control signal (e.g., SLE2) asserted to a first logic state (e.g., "1") when at least one of the first nominal memory cells 312, 314 is selected. The first AND gate 322 may be configured to assert the first tracking word line 323 to a first logic state (e.g., "1") when at least one of the first nominal memory cells 312, 314 is selected. In some embodiments, the first tracking circuit 318 may be configured to provide a timing signal for a non-flying BL.

[0076] Referring to (1208), in some embodiments, a second tracking circuit 338 may be formed that is configured to activate a second tracking cell 336 that emulates at least one of the second nominal cells 332, 334. The second tracking circuit 338 may include at least one of a second AND gate 342, a second tracking word line 343 coupled to a gate terminal of the second tracking cell 336, or a second buffer 344. The second AND gate 342 may have a first input terminal 342b configured to receive a clock signal (e.g., internal CLK) and a second input terminal 342a configured to receive a second control signal (e.g., SEL1) asserted to a first logic state (e.g., "1") when at least one second nominal memory cell 332, 334 is selected. The second AND gate 342 may be configured to assert the second tracking word line 343 to a first logic state (e.g., "1") when at least one second nominal memory cell 332, 334 is selected. In some embodiments, the second tracking circuit 338 may be configured to provide a timing signal for the flying BL.

[0077] Referring to (1210), in some embodiments, a first bit line 310 can be formed that is operably coupled to the first nominal cells 312, 314. The first bit line 310 can include a first bit line segment 313 extending along a first lateral direction (e.g., the Y direction). A plurality of first nominal memory cells 312, 314 can be coupled to the first bit line segment 313 extending along the first lateral direction (e.g., the Y direction).

[0078] Referring to (1212), in some embodiments, a second bit line operably coupled to the second nominal cells 332, 334 may be formed. The second bit line may include a second bit line segment 333 and a third bit line segment 335, both extending along the first lateral direction, and the third bit line segment is disposed above the first bit line segment. A plurality of second nominal memory cells 312, 314 may be coupled to the second bit line segment 333 and the third bit line segment 335 extending along the first lateral direction (e.g., the Y direction). The third bit line segment 335 may be disposed vertically above the first bit line segment 313. In some embodiments, the first bit line segment 313 and the second bit line segment 333 may be disposed in a first metallization layer (e.g., M0 or M1). In some embodiments, the third bit line segment 335 may be disposed in the same metallization layer (e.g., M0 or M1). In some embodiments, the third bit line segment 335 may be disposed in a different metallization layer (e.g., the second metallization layer M2) above the first metallization layer.

[0079] In some embodiments, the first tracking unit 316 may be disposed in a first region next to the first portion 310 of the memory array along a second lateral direction (e.g., X direction) perpendicular to the first lateral direction (e.g., Y direction). The second tracking unit 316 may be disposed in a second region next to the second portion 330 of the memory array along a second lateral direction (e.g., X direction). In some embodiments, the first tracking circuit 318 and the second tracking circuit 338 may be formed in a third region of the substrate. The first region may be between the second region and the third region along the first lateral direction.

[0080] Fig.13 is an example method of operating a dual-track memory circuit for a flying bitline static random access memory (SRAM) architecture according to some embodiments. It should be noted that method 1300 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 1300 may be used in Fig.13 Any additional operations are provided during, before, and after the method 1300, and some other operations may only be briefly described herein. The method 1300 may be used to operate the memory circuit 300, and therefore, will be combined with Figure 1-Figure 12 The operations of method 1300 are discussed with reference to the components discussed in .

[0081] Briefly, the method 1300 begins with an operation 1302 of determining a selection of at least one nominal memory cell of the memory array 302. In some embodiments, the memory circuit 300 may determine a selection of at least one nominal memory cell of the memory array 302. The memory array 302 may include a first portion 310 and a second portion 330. The first portion 310 may include a plurality of first nominal memory cells 312, 314 coupled to a first bit line segment 313 extending along a first lateral direction (e.g., a Y direction). The second portion 330 may include a plurality of second nominal memory cells 332, 334 coupled to a second bit line segment 333 and a third bit line segment 335 extending along the first lateral direction. The third bit line segment 335 may be disposed vertically above the first bit line segment 313.

[0082] Corresponds to Fig.13 At operation 1304, the memory circuit 300 may activate a first tracking cell 316 in response to at least one of the first nominal memory cells being selected. The first tracking cell 316 may be disposed adjacent to the first portion 310 of the memory array 302 along a second lateral direction (e.g., an X direction) perpendicular to the first lateral direction. In some embodiments, the first tracking circuit may include: a first AND gate and a first tracking word line coupled to a gate terminal of the first tracking cell. In some embodiments, when at least one of the first nominal memory cells is selected, the memory circuit 300 may receive a first control signal asserted as a first logic state (e.g., "1").

[0083] Corresponds to Fig.13 At operation 1306, the memory circuit 300 may activate the second tracking cell 226 in response to selecting at least one of the second nominal memory cells. The second tracking cell 226 may be disposed along the second lateral direction next to the second portion 330 of the memory array 302. In some embodiments, the second tracking circuit may include: a second AND gate and a second tracking word line coupled to a gate terminal of the second tracking cell. In some embodiments, when the at least one second nominal memory cell is selected, the memory circuit 300 may receive a second control signal asserted to the first logic state.

[0084] As used herein, the terms "about" and "approximately" generally refer to plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0085] According to one aspect of an embodiment of the present application, a memory circuit is provided, comprising: a first portion of a memory array, comprising a plurality of first nominal memory cells coupled to a first bit line segment extending along a first lateral direction; a first tracking unit, arranged next to the first portion of the memory array along a second lateral direction perpendicular to the first lateral direction; a second portion of the memory array, comprising a plurality of second nominal memory cells coupled to a second bit line segment and a third bit line segment, both extending along the first lateral direction, wherein the third bit line segment is vertically arranged above the first bit line segment; a second tracking unit, arranged next to the second portion of the memory array along the second lateral direction; a first tracking circuit, configured to activate the first tracking unit in response to at least one of the first nominal memory cells being selected; and a second tracking circuit, configured to activate the second tracking unit in response to at least one of the second nominal memory cells being selected.

[0086] In some embodiments, the first tracking circuit includes: a first AND gate; and a first tracking word line coupled to a gate terminal of the first tracking unit; and the second tracking circuit includes: a second AND gate; and a second tracking word line coupled to a gate terminal of the second tracking unit.

[0087] In some embodiments, the first AND gate has the first input terminal configured to receive a clock signal, and the second input terminal configured to receive a first control signal asserted as a first logic state when the at least one first nominal memory cell is selected; and the second AND gate has a first input terminal configured to receive the clock signal, and a second input terminal configured to receive a second control signal asserted as the first logic state when the at least one second nominal memory cell is selected.

[0088] In some embodiments, the first AND gate is configured to assert the first tracking word line to the first logic state when the at least one first nominal memory cell is selected, and the second AND gate is configured to assert the second tracking word line to the first logic state when the at least one second nominal memory cell is selected.

[0089] In some embodiments, the first tracking circuit further includes: a first NAND gate; and a first inverter coupled to a first word line, the first word line coupled to the at least one first nominal memory cell; and the second tracking circuit includes: a second NAND gate; and a second inverter coupled to a second word line, the second word line coupled to the at least one second nominal memory cell.

[0090] In some embodiments, the first NAND gate has a first input terminal configured to receive a first address signal asserted as the first logic state when the at least one first nominal memory cell is selected, and a second input terminal configured to receive a first signal present on a first tracking bit line coupled to the first tracking cell; and the second NAND gate has a first input terminal configured to receive a second address signal asserted as the first logic state when the at least one second nominal memory cell is selected, and a second input terminal configured to receive a second signal present on a second tracking bit line coupled to the second tracking cell.

[0091] In some embodiments, when the at least one first nominal memory cell is selected, a first signal present on the first word line has a first pulse width, and when the at least one second nominal memory cell is selected, a second signal present on the second word line has a second pulse width.

[0092] In some embodiments, the first pulse width is narrower than the second pulse width.

[0093] In some embodiments, the first bit line segment and the second bit line segment are disposed in a first metallization layer, and the third bit line segment is disposed in a second metallization layer above the first metallization layer.

[0094] According to another aspect of an embodiment of the present application, a memory circuit is provided, comprising: a first portion of a memory array, comprising a plurality of first nominal memory cells; a first bit line coupled to the first nominal memory cell, wherein the first bit line comprises a first bit line segment arranged in a first metallization layer; a second portion of the memory array, comprising a plurality of second nominal memory cells; a second bit line coupled to the second nominal memory cell, wherein the second bit line comprises a second bit line segment and a third bit line segment respectively arranged in the first metallization layer and the second metallization layer; a first tracking unit configured to simulate each of the plurality of first nominal memory cells; a second tracking unit configured to simulate each of the plurality of second nominal memory cells; a first tracking circuit configured to activate the first tracking unit in response to at least one of the first nominal memory cells being selected; and a second tracking circuit configured to activate the second tracking unit in response to at least one of the second nominal memory cells being selected.

[0095] In some embodiments, the first tracking circuit includes: a first AND gate; and a first tracking word line coupled to a gate terminal of the first tracking unit; and the second tracking circuit includes: a second AND gate; and a second tracking word line coupled to a gate terminal of the second tracking unit.

[0096] In some embodiments, the first AND gate has a first input terminal configured to receive a clock signal and a second input terminal configured to receive a first control signal asserted as a first logic state when the at least one first nominal memory cell is selected; and the second AND gate has a first input terminal configured to receive a clock signal and a second input terminal configured to receive a second control signal asserted as the first logic state when the at least one second nominal memory cell is selected.

[0097] In some embodiments, the first AND gate is configured to assert the first tracking word line to the first logic state when the at least one first nominal memory cell is selected, and the second AND gate is configured to assert the second tracking word line to the first logic state when the at least one second nominal memory cell is selected.

[0098] In some embodiments, the first tracking circuit further includes: a first NAND gate; and a first inverter coupled to a first word line, the first word line coupled to the at least one first nominal memory cell; and the second tracking circuit includes: a second NAND gate; and a second inverter coupled to a second word line, the second word line coupled to the at least one second nominal memory cell.

[0099] In some embodiments, when the at least one first nominal memory cell is selected, a first signal present on the first word line has a first pulse width, and when the at least one second nominal memory cell is selected, a second signal present on the second word line has a second pulse width.

[0100] In some embodiments, the first pulse width is narrower than the second pulse width.

[0101] In some embodiments, the third bit line segment is disposed vertically above the first bit line segment.

[0102] According to another aspect of an embodiment of the present application, a method for operating a memory circuit is provided, comprising: determining a selection of at least one nominal memory cell of a memory array, wherein the memory array comprises a first portion and a second portion, wherein the first portion comprises a plurality of first nominal memory cells coupled to a first bit line segment extending along a first lateral direction, and the second portion comprises a plurality of second nominal memory cells coupled to a second bit line segment and a third bit line segment both extending along the first lateral direction; in response to at least one of the first nominal memory cells being selected, activating a first tracking cell, wherein the first tracking cell is disposed next to the first portion of the memory array along a second lateral direction perpendicular to the first lateral direction; and in response to at least one of the second nominal memory cells being selected, activating a second tracking cell, wherein the second tracking cell is disposed next to the second portion of the memory array along the second lateral direction.

[0103] In some embodiments, the first tracking circuit includes: a first AND gate, wherein the first AND gate has a first input terminal configured to receive a clock signal; and a first tracking word line coupled to a gate terminal of the first tracking unit; and the second tracking circuit includes: a second AND gate, wherein the second AND gate has a first input terminal configured to receive the clock signal; and a second tracking word line coupled to a gate terminal of the second tracking unit.

[0104] In some embodiments, a method includes receiving a first control signal asserted to a first logic state when the at least one first nominal memory cell is selected, and receiving a second control signal asserted to the first logic state when the at least one second nominal memory cell is selected.

[0105] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A memory circuit, comprising: a first portion of a memory array including a plurality of first nominal memory cells coupled to a first bit line segment extending along a first lateral direction; a first tracking unit disposed beside the first portion of the memory array along a second lateral direction perpendicular to the first lateral direction; a second portion of the memory array including a plurality of second nominal memory cells coupled to a second bit line segment and a third bit line segment each extending along the first lateral direction, wherein the third bit line segment is disposed vertically above the first bit line segment; a second tracking unit disposed beside the second portion of the memory array along the second lateral direction; a first tracking circuit configured to activate the first tracking cell in response to at least one of the first nominal memory cells being selected; and A second tracking circuit is configured to activate the second tracking cell in response to at least one of the second nominal memory cells being selected.

2. The memory circuit according to claim 1, wherein: The first tracking circuit comprises: The first AND gate; and a first tracking word line coupled to a gate terminal of the first tracking cell; and the second tracking circuit comprising: The second AND gate; and A second tracking word line is coupled to a gate terminal of the second tracking cell.

3. The memory circuit according to claim 2, wherein: the first AND gate having a first input terminal configured to receive a clock signal, and the second input terminal configured to receive a first control signal asserted to a first logic state when the at least one first nominal memory cell is selected; as well as The second AND gate has a first input terminal configured to receive the clock signal and a second input terminal configured to receive a second control signal asserted to the first logic state when the at least one second nominal memory cell is selected.

4. The memory circuit according to claim 3, wherein: The first AND gate is configured to assert the first tracking word line to the first logic state when the at least one first nominal memory cell is selected, and the second AND gate is configured to assert the second tracking word line to the first logic state when the at least one second nominal memory cell is selected.

5. The memory circuit according to claim 3, wherein: The first tracking circuit further includes: first NAND gate; and a first inverter coupled to a first word line coupled to the at least one first nominal memory cell; and The second tracking circuit comprises: The second NAND gate; and A second inverter is coupled to a second word line coupled to the at least one second nominal memory cell.

6. The memory circuit according to claim 5, wherein: the first NAND gate having a first input terminal configured to receive a first address signal asserted to the first logic state when the at least one first nominal memory cell is selected, and a second input terminal configured to receive a first signal present on a first tracking bit line coupled to the first tracking cell; as well as The second NAND gate has a first input terminal configured to receive a second address signal asserted to the first logic state when the at least one second nominal memory cell is selected, and a second input terminal configured to receive a second signal present on a second tracking bit line coupled to the second tracking cell.

7. The memory circuit according to claim 5, wherein: When the at least one first nominal memory cell is selected, a first signal present on the first word line has a first pulse width, and when the at least one second nominal memory cell is selected, a second signal present on the second word line has a second pulse width.

8. A memory circuit comprising: a first portion of a memory array including a first plurality of nominal memory cells; a first bit line coupled to the first nominal memory cell, wherein the first bit line comprises a first bit line segment disposed in a first metallization layer; a second portion of the memory array comprising a second plurality of nominal memory cells; a second bit line coupled to the second nominal memory cell, wherein the second bit line includes a second bit line segment and a third bit line segment disposed in the first metallization layer and the second metallization layer, respectively; a first tracking unit configured to emulate each of the plurality of first nominal memory cells; a second tracking unit configured to emulate each of the plurality of second nominal memory cells; a first tracking circuit configured to activate the first tracking cell in response to at least one of the first nominal memory cells being selected; and A second tracking circuit is configured to activate the second tracking cell in response to at least one of the second nominal memory cells being selected.

9. The memory circuit according to claim 8, wherein: The third bit line segment is disposed vertically above the first bit line segment.

10. A method of operating a memory circuit, comprising: determining a selection of at least one nominal memory cell of a memory array, wherein the memory array comprises a first portion and a second portion, wherein the first portion comprises a plurality of first nominal memory cells coupled to a first bit line segment extending along a first lateral direction, and the second portion comprises a plurality of second nominal memory cells coupled to a second bit line segment and a third bit line segment extending along the first lateral direction; activating a first tracking cell in response to at least one of the first nominal memory cells being selected, wherein the first tracking cell is disposed alongside the first portion of the memory array along a second lateral direction perpendicular to the first lateral direction; and In response to at least one of the second nominal memory cells being selected, a second tracking cell is activated, wherein the second tracking cell is disposed alongside the second portion of the memory array along the second lateral direction.

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