Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing the same. In one example, a semiconductor device structure relates to an electronic device including a device top surface, a device bottom surface opposite the device top surface, a device side surface extending between the device top surface and the device bottom surface, and a pad disposed on the device top surface. Interconnects are connected to the pads, and the interconnects include first regions each extending from a respective pad in an upward direction, and second regions each connected to a respective first region, where each second region extends from the respective first region in a lateral direction. The interconnect includes a redistribution pattern on the pad. Other examples and related methods are also disclosed herein.

Description

[0001] This application is a divisional application of the invention patent application for semiconductor device and method for manufacturing semiconductor device, with the application date of July 2, 2020, the priority date of July 6, 2019, the application number of 202010632085.0 and the invention name of the invention is semiconductor device and method for manufacturing semiconductor device. Technical Field

[0002] The present disclosure relates generally to electronic devices, and more particularly to semiconductor devices and methods of fabricating semiconductor devices. Background Art

[0003] Existing semiconductor packages and methods of forming semiconductor packages are inadequate, for example, resulting in excessive cost, reduced reliability, relatively low performance, or excessive package size. Other limitations and disadvantages of conventional and traditional methods will be apparent to those skilled in the art by comparing such methods with the present disclosure and referring to the drawings. Summary of the invention

[0004] The present invention describes, among other features, a packaged electronic device structure and related methods including an interconnect attached to the electronic device. The interconnect includes a first region extending from the electronic device in an upward direction and a second region connected to the first region. The second region extends from the first region in a lateral direction. In some instances, portions of the electronic device and the interconnect are covered with an encapsulation. In some instances, other portions of the interconnect are exposed from the encapsulation. Among other things, the structure and method provide a more cost-effective redistribution mode for the electronic device, which uses a simplified process flow, provides better form factor redistribution, and provides a faster electrical path.

[0005] More specifically, in one example, a packaged electronic device structure includes an electronic device having a device top surface, a device bottom surface opposite to the device top surface, and a device side surface extending between the device top surface and the device bottom surface. An interconnect is connected to the device top surface and includes a first region extending from the device top surface in an upward direction and a second region connected to the first region, wherein the second region extends from the first region in a lateral direction. An encapsulation covers the device top surface, the device side surface, and the periphery of the first region, wherein a first portion of the second region is exposed from the first surface of the encapsulation, a second portion of the second region is exposed from the second surface of the encapsulation, and the encapsulation covers a third portion of the second region. In some examples, the electronic device includes an active or passive device. In other examples, the electronic device includes a semiconductor device. In some examples, the first region and the second region are integrated structures provided as part of a subsequently singulated lead frame structure. In some examples, the second region extends laterally beyond the perimeter of the electronic device. In the packaged electronic device structure, the lateral direction is substantially parallel to the top surface of the device; and the second portion extends to overlap the side surface of the device so as to extend outside the perimeter of the electronic device. In the packaged electronic device structure, the first portion is directly connected to the pad of the electronic device; and the upward direction is substantially perpendicular to the top surface of the device. In the packaged electronic device structure, the bottom surface of the device is exposed from the third surface of the encapsulation; and the third surface is opposite to the first surface. In the packaged electronic device structure, the first surface includes the top surface of the encapsulation; and the top surface is substantially coplanar with the first portion of the second region. In the packaged electronic device structure, the second portion of the second region includes an end portion; the second surface includes a side surface of the encapsulation; and the side surface is substantially coplanar with the end portion.

[0006] In another example, a semiconductor device structure includes an electronic device having a device top surface, a device bottom surface opposite to the device top surface, a device side surface extending between the device top surface and the device bottom surface, and a pad disposed on the device top surface. An interconnect is connected to the pad, and the interconnect includes a first region each extending from a corresponding pad in an upward direction and a second region each connected to the corresponding first region, wherein each second region extends from the corresponding first region in a lateral direction. The interconnect includes a redistribution pattern on the pad. The semiconductor device structure also includes: an encapsulation covering the device top surface, the device side surface, and the periphery of the first region, wherein: a first portion of the second region is exposed from the first surface of the encapsulation; a second portion of the second region is exposed from the second surface of the encapsulation; and a third portion of the second region is covered by the encapsulation. In the semiconductor device structure, the device bottom surface is exposed from the third surface of the encapsulation; and the third surface is opposite to the first surface. In the semiconductor device structure, the first surface includes the top surface of the encapsulation; and the top surface is substantially coplanar with the first portion of the second region. In the semiconductor device structure, the second portion of the second region includes an end portion; the second surface includes a side surface of the encapsulation; and the side surface is substantially coplanar with the end portion. In the semiconductor device structure, the lateral direction is substantially parallel to the device top surface; and the second portion extends to overlap the device side surface so as to extend outside the perimeter of the electronic device. In the semiconductor device structure, the upward direction is substantially perpendicular to the device top surface. In the semiconductor device structure, each second portion is integrated with a corresponding first portion.

[0007] In another example, a method for making a semiconductor device includes providing a substrate including a plurality of electronic devices formed as part of the substrate. The method includes attaching interconnects to pads on the electronic devices, wherein each interconnect spans between adjacent electronic devices, wherein each interconnect has a first region coupled to a corresponding pad of a corresponding adjacent electronic device and extending in an upward direction, and a second region structure connecting the first regions to each other in a lateral direction. The method includes singulating the substrate and the plurality of interconnects to separate each second region into a second region and to separate the substrate into individual electronic devices. The method also includes: forming a groove extending partially inward from a first surface of the substrate between the plurality of electronic devices; providing an encapsulation on the first surface of the substrate and within the groove so that the encapsulation fills a portion between each of the interconnects and fills a portion between each of the interconnects and the first surface of the substrate; and removing a portion of the substrate from a second surface of the substrate opposite to the first surface to expose the encapsulation from the second surface. In the method, forming the groove occurs before coupling the interconnects; and singulation occurs after removing a portion of the substrate. In the method, a portion of the encapsulation remains on a side surface of the electronic device after the singulation step. In the method, providing an encapsulation includes covering a first side of each second region structure with the encapsulation while exposing a second side of each second region structure from the encapsulation. In the method, coupling the interconnect includes coupling the interconnect provided as a lead frame.

[0008] Other examples are included in the present disclosure. Such examples can be found in the figures, claims and / or description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A cross-sectional view of an example semiconductor device is shown.

[0010] Figure 2 A plan view of an example semiconductor device is shown.

[0011] Figure 3 A bottom view of an example semiconductor device is shown.

[0012] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F and Figure 4G A cross-sectional view illustrating an example method for fabricating an example semiconductor device.

[0013] Figure 5 A cross-sectional view of an example semiconductor device is shown.

[0014] Figure 6 A plan view of an example semiconductor device is shown.

[0015] Fig. 7A , Figure 7B , Figure 7C and Fig.7D A cross-sectional view illustrating an example method for fabricating an example semiconductor device. DETAILED DESCRIPTION

[0016] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. Such examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0017] The figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted so as not to unnecessarily obscure the present disclosure. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be enlarged relative to other elements to help improve the understanding of the examples discussed in the present disclosure. The same reference numerals in different figures represent the same elements.

[0018] The term "or" means any one or more of the items in the list connected by "or". As an example, "x or y" means any element in the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0019] The terms “comprising” and “including” are “open” terms and specify the presence of stated features but do not preclude the presence or addition of one or more other features.

[0020] The terms "first," "second," etc. may be used herein to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element discussed in the present disclosure may be referred to as a second element without departing from the teachings of the present disclosure.

[0021] Unless otherwise specified, the term "coupled" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected by one or more other elements. For example, if element A is coupled to element B, element A may directly contact element B or be indirectly connected to element B by an intervening element C. Similarly, the term "on..." or "on..." may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly connected by one or more other elements. It should be further understood that the examples illustrated and described below may appropriately have examples and / or may be practiced in the absence of any elements not specifically disclosed herein.

[0022] Figure 1 showing a cross-sectional view of an example semiconductor device, Figure 2 A plan view of an example semiconductor device is shown, and Figure 3 A bottom view of an example semiconductor device is shown.

[0023] refer to Figures 1 to 3 , an example semiconductor device 100 may include an electronic device 110 , an interconnect 120 , and an encapsulation 130 .

[0024] The electronic device 110 may be a semiconductor die, a semiconductor component, an optical device, a sensor device, or other active or passive devices known to those skilled in the art. The electronic device 110 may include a substantially flat device top surface 110a or first surface 110a, a substantially flat device bottom surface 110b or second surface 110b opposite to the first surface 110a, and a device side surface 110c or third surface 110c extending between the first surface 110a and the second surface 110b. A pad 111 through which an electrical signal is input / output to / from the electronic device 110 and a dielectric 112 covering the periphery of the pad 111 may be provided on the first surface 110a of the electronic device 110.

[0025] The pad 111 may include a plurality of pads located on the first surface 110a of the electronic device 110 and spaced apart from each other. The pad 111 is exposed from the first surface 110a of the electronic device 110, and an external electrical signal may be input / output to / from the electronic device 110 through the pad 111. The pad 111 may be referred to as a bonding pad or a die pad, and may include any one of copper, gold, silver, and aluminum.

[0026] In addition to any portion corresponding to the pad 111, a dielectric 112 may be provided to cover the periphery of the pad 111 on the first surface 110a of the electronic device 110 and may electrically insulate the first surface 110a of the electronic device 110. The dielectric 112 may be referred to as a non-conductive material or a passivation layer. The dielectric 112 may be provided to have the same height as the pad 111 or a slightly greater height. In some examples, the dielectric 112 may extend to cover the periphery of the top pad surface of the pad 111 without covering the contact portion of the top pad surface.

[0027] The electronic device 110 may be electrically connected to the outside of the semiconductor device 100 through various interconnects 120 coupled to the pad 111. The interconnect 120 may include or be referred to as a lead or as a redistribution structure or pattern. In some examples, the interconnect 120 may be part of a lead frame. The interconnect 120 may include, for example, copper, gold, silver, or aluminum. Each of the interconnects 120 may include a first region 121 connected to the pad 111 and a second region 122 extending from the first region 121. The first region 121 may be electrically coupled to the pad 111 and may protrude from the pad 111 in a first direction, such as vertically or upwardly. In addition, in an example embodiment of the present disclosure, the first region 121 may extend in a first direction substantially perpendicular to the pad 111. The second region 122 may extend from the first region 121 in a second direction, such as horizontally or laterally. The second direction may be different from the first direction in which the first region 121 extends. In one example, the second region 122 may extend in a direction substantially perpendicular to the first region 121. The interconnect 120 may also be configured to extend through the footprint or area of ​​the electronic device 110 by the extended length of the second region 122. Thus, the interconnect 120 may be used to perform redistribution on the pad 111 of the electronic device 110.

[0028] The interconnector 120 may be directly connected to the pad 111 of the electronic device 110 , thereby shortening the electrical path. Through the interconnector 120 , an electrical pattern may be formed at any location without being limited to the location of the pad 111 of the electronic device 110 .

[0029] An encapsulation 130 may be provided to fill a gap between the electronic device 110 and the interconnect 120. The encapsulation 130 made of a non-conductive material may maintain the interconnects 120 insulated from each other. In addition, the encapsulation 130 may encapsulate the side surface 110c of the electronic device 110 and encapsulate some regions of the pad 111 and the dielectric 112 of the electronic device 110. The encapsulation 130 encapsulating the periphery of the first region 121 of each of the interconnects 120 connected to the pad 111 may maintain the structural integrity of the connection between the pad 111 and the interconnect 120. The encapsulation 130 may include or be referred to as a molding compound or resin, but this is not a limitation of the present disclosure.

[0030] The first surface 130a of the encapsulant 130 may be substantially coplanar with the top surface of the second region 122 of each interconnect 120, thereby exposing the second region 122. The third surface 130c of the encapsulant 130 may be substantially coplanar with the end portion of the second region 122 extending in the second direction to expose the end portion of the second region 122. Therefore, the second region 122 of the interconnect 120 may be exposed from the encapsulant 130 and may be subsequently connected to a circuit or device outside the semiconductor device 100. The second surface 130b of the encapsulant 130 may be parallel to the second surface 110b of the electronic device 110, and in some examples may expose the second surface 110b of the electronic device 110. The exposed second surface 110b may improve heat radiation from the electronic device 110. In some examples, the first surface 130a, the second surface 130b, and the third surface 130c of the encapsulant 130 may be referred to as the top surface, the bottom surface, and the side surface of the encapsulant 130, respectively.

[0031] Figures 4A to 4G A cross-sectional view illustrating an example method of manufacturing an example semiconductor device.

[0032] refer to Figure 4A , an example method for manufacturing a semiconductor device 100 according to the present disclosure may include providing a substrate 10. The substrate 10 may be configured so that a plurality of electronic devices are arranged in series. The substrate 10 may also be referred to as a wafer, a strip, or a plane. A pad 111 and a dielectric 112 may be provided on a first surface 110a of the substrate 10 so as to correspond to a region of each electronic device. The first surface 110a of the substrate 10 may constitute a first surface of the electronic device. In addition, the dielectric 112 may be provided across the first surface 110a of the substrate 10 while filling a gap between a pad 111 and an adjacent pad 111.

[0033] refer to Figure 4B , the groove 11 may be formed inward from the first surface 110a of the substrate 10 at a later stage. The groove 11 may be formed by partially sawing or etching from the first surface 110a of the substrate 10. The first surface 110a of the substrate 10 may be divided into regions along the groove 11 corresponding to regions of corresponding electronic devices. In addition, the groove 11 may perform the function of a scribing line for singulation at a later stage.

[0034] refer to Figure 4C, the interconnect 120 may be provided around the groove 11. The interconnect 120 may connect the pads 111 to each other between adjacent electronic devices. In detail, the interconnect 120 may include a plurality of first regions 121 coupled to the corresponding pads 111 in a first direction and a second region 122 connecting the first regions 121 to each other in a second direction. The first region 121 and the second region 122 of the interconnect 120 may be integrally formed. For example, the first region 121 and the second region 122 may be formed of the same workpiece or material and bent to provide a desired shape as part of a lead frame. In addition, the interconnect 120 may be a prefabricated structure to be coupled to the pad 111. In some examples, the interconnect 120 may be formed as a lead frame or formed from a lead frame. The interconnect 120 may be made of copper, gold, silver, or aluminum.

[0035] refer to Figure 4D , the encapsulant 130 may be provided on the first surface 110a of the substrate 10. The encapsulant 130 may fill the groove 11 on the first surface 110a of the substrate 10. In addition, the encapsulant 130 may fill the portion between each of the interconnects 120 and the portion between each of the interconnects 120 and the first surface 110a of the substrate 10. The encapsulant 130 may have the same height as the interconnects 120 to expose the interconnects 120. In some examples, the initial encapsulant height of the encapsulant 130 may be higher than the height of the interconnects 120, thereby completely encapsulating the interconnects 120, and then the initial encapsulant height may be reduced, for example, by grinding, to reveal the top of the interconnects 120.

[0036] refer to Figure 4E , the substrate 10 may be removed from a second surface 110b of the substrate 10 opposite to the first surface 110a by a predetermined thickness. The second surface 110b of the substrate 10 may be removed by grinding or polishing. In some cases, the second surface 110b of the substrate 10 may also be removed by etching. The second surface 110b of the substrate 10 may be the bottom surface of the substrate 10. In addition, the removal of some areas of the second surface 110b may include removing the second surface 110b to a predetermined thickness to expose the groove 11. Therefore, the substrate 10 may be divided into areas of corresponding electronic devices. In addition, the second surface 110b of the substrate 10 may constitute the second surface of the corresponding electronic device.

[0037] refer to Figure 4F , a singulation or singulation process may be performed on the substrate 10. The singulation may be performed using sawing. Due to the singulation, the individual electronic devices 110 may be separated from the substrate 10. In addition, the singulation may be performed along the groove 11 of the substrate 10. The singulation width may be smaller than the width of the groove 11. Therefore, similar to Figure 4GIn the configuration of the semiconductor device 100 shown in FIG. 1 , the encapsulant 130 previously positioned in the existing groove 11 may be positioned on the side surface 110 c of the electronic device 110 that has undergone singulation. In addition, since the side surface 110 c of the electronic device 110 is not exposed to the outside, the encapsulant 130 may protect the electronic device 110 from external factors. Figure 4G As shown in FIG. 1 , the second region 122 overlaps the side surface 110c of the electronic device 110 so as to extend outside the perimeter of the electronic device 110. Figure 4G 1, a first portion 122a of the second region 122 is exposed from a first surface 130a of the encapsulation 130 and may be substantially coplanar with the first surface 130a. A second portion 122b of the second region 122, such as an end portion, is exposed in another surface 130c of the encapsulation 130 and may be substantially coplanar with the surface 130c. A third portion 122c of the second region 122 may be covered by the encapsulation 130.

[0038] According to the manufacturing method of the present invention, the electrical connection of the electronic device 110 can be performed through the interconnection 120, thereby quickly establishing an electrical path and simplifying the overall process of manufacturing the semiconductor device 100.

[0039] Figure 5 A cross-sectional view of an example semiconductor device is shown. Figure 6 A plan view of an example semiconductor device is shown.

[0040] refer to Figure 5 and 6 , the example semiconductor device 200 may include an electronic device 110 and an interconnect 120 .

[0041] The electronic device 110 may include a substantially flat first surface 110a, and a substantially flat second surface 110b opposite to the first surface 110a. A pad 111 through which an electrical signal is input / output to / from the electronic device 110 and a dielectric 112 covering the periphery of the pad 111 may be provided on the first surface 110a of the electronic device 110.

[0042] The pad 111 may include a plurality of pads located on the first surface 110a of the electronic device 110 and spaced apart from each other. The pad 111 is exposed from the first surface 110a of the electronic device 110, and an external electrical signal may be input / output to / from the electronic device 110 through the pad 111. The pad 111 may be referred to as a bonding pad or a die pad, and may include any one of copper, gold, silver, and aluminum.

[0043] The pad 111 may be exposed as shown in the drawings. When the pad 111 is made of a material such as copper or silver, electroplating for preventing oxidation may also be provided on a portion of the pad 111 that is intended to be electrically connected to the interconnect 120. The electroplating may be provided using, for example, nickel, zinc, or tin. If the pad 111 is actually made of a material such as aluminum, an oxide film is naturally formed by anodizing the remaining portion of the pad 111 except for the portion electrically connected to the interconnect 120, thereby performing an insulating function.

[0044] The dielectric 112 may be provided to cover the periphery of the pad 111 on the first surface 110a of the electronic device 110 and may electrically insulate the first surface 110a of the electronic device 110, except for any portion corresponding to the pad 111. The dielectric 112 may be referred to as a non-conductive material or a passivation layer. The dielectric 112 may have the same height as the pad 111 or a slightly greater height. In some examples, the dielectric 112 may extend to cover the periphery of the top pad surface of the pad 111 without covering the contact portion of the top pad surface.

[0045] The interconnect 120 may be coupled to the pad 111 of the electronic device 110. The interconnect 120 may include or be referred to as a lead or as a redistribution structure or pattern. In some examples, the interconnect 120 may be part of a lead frame. The interconnect 120 may include, for example, copper, gold, silver, or aluminum. Each of the interconnects 120 may include a first region 121 connected to the pad 111 and a second region 122 extending from the first region 121. The first region 121 may be electrically coupled to the pad 111 and may protrude from the pad 111 in a first direction. In addition, in an example embodiment of the present disclosure, the first region 121 may extend in a first direction substantially perpendicular to the pad 111. The second region 122 may extend from the first region 121 in a second direction. The second direction may be different from the first direction in which the first region 121 extends. In one example, the second region 122 may extend in a direction substantially perpendicular to the first region 121. The interconnect 120 may also be configured to extend through the footprint or area of ​​the electronic device 110 to the extension length of the second region 122. Therefore, the interconnect 120 may be used to perform redistribution on the pad 111 of the electronic device 110 .

[0046] Figures 7A to 7D A cross-sectional view illustrating an example method of manufacturing an example semiconductor device.

[0047] refer to Fig. 7A, an example method for manufacturing a semiconductor device 200 according to the present disclosure may include providing a substrate 10. The substrate 10 may be configured so that a plurality of electronic devices are arranged in series. The substrate 10 may also be referred to as a wafer, a strip, or a plane. A pad 111 and a dielectric 112 may be provided on a first surface 110a of the substrate 10 so as to correspond to a region of each electronic device. The first surface 110a of the substrate 10 may constitute a first surface of the electronic device. In addition, a dielectric 112 may be provided on the entire first surface 110a of the substrate 10 while filling a gap between a pad 111 and an adjacent pad 111.

[0048] refer to Figure 7B , the interconnection 120 may be provided on the connection pads 111 of the adjacent electronic device on the first surface 110a of the substrate 10. The interconnection 120 may connect the pads 111 of the adjacent electronic device.

[0049] The interconnect 120 may include a plurality of first regions 121 coupled to the corresponding pads 111 in a first direction and a second region 122 connecting the first regions 121 to each other in a second direction. The first region 121 and the second region 122 of the interconnect 120 may be integrally formed. In addition, the interconnect 120 may be a prefabricated structure to be coupled to the pad 111. In some examples, the interconnect 120 may be formed as a lead frame or formed from a lead frame. The interconnect 120 may be made of copper, gold, silver, or aluminum.

[0050] refer to Figure 7C , a singulation or singulation process may be performed on the substrate 10. The singulation may be performed using sawing or cutting. Due to the singulation, the individual electronic devices 110 may be separated from the substrate 10. In addition, the singulation may be performed to separate the second region 122 of the interconnect 120 together with the substrate 10. Therefore, the pads 111 of the adjacent electronic devices 110 connected to each other through the interconnect 120 may be separated from each other.

[0051] like Fig.7D , the electronic device 110 that has undergone singulation may be configured to include interconnects 120 individually connected to corresponding pads 111. In addition, since the semiconductor device 200 is configured such that the interconnects 120 are formed on the electronic device 110, the manufacturing process may be simplified and an electrical path may be quickly established through the interconnects 120. In addition, redistribution may be performed on the pads 111 of the electronic device 110 through a configuration in which the first region 121 and the second region 122 of the interconnect 120 extend.

[0052] From all of the foregoing, one skilled in the art can determine that according to another example, a method for making a semiconductor device includes providing a substrate including a plurality of electronic devices formed as part of the substrate. The method includes forming a groove extending partially inward from a first surface of the substrate between the plurality of electronic devices. The method includes coupling an interconnect to a pad on the electronic device, wherein each interconnect spans one of the grooves between adjacent electronic devices, wherein each interconnect includes a first region coupled to a corresponding pad of a corresponding adjacent electronic device in an upward direction, and a second region structure connecting the first regions to each other in a lateral direction. The method includes providing an encapsulation on the first surface of the substrate and within the groove, such that the encapsulation fills a portion between each of the interconnects and fills a portion between each of the interconnects and the first surface of the substrate. The method includes removing a portion of the substrate from a second surface of the substrate opposite to the first surface to expose the encapsulation from the second surface. The method includes singulating the substrate and the interconnect through portions of the groove to separate the interconnect and the substrate into individual electronic devices.

[0053] In another example, a portion of the encapsulant remains on the side surface of the electronic device after the singulation step. In yet another example, coupling the interconnect includes coupling the interconnect provided as a lead frame. In another example, providing the encapsulant includes covering the first side of the second region with the encapsulant while exposing the second side of the second region from the encapsulant.

[0054] In summary, structures and methods related to electronic devices having interconnect structures have been described. In some instances, the interconnect structure includes a plurality of interconnects, each having a first region extending from a surface of the electronic device in a first or upward direction, and a second region connected to the first region extending from the first region in a second or lateral direction. In some instances, the interconnect is provided as part of a lead frame that can be attached to a substrate containing a plurality of electronic devices as part of a manufacturing method. In some instances, a single split can be used to simultaneously separate the interconnect and the substrate to provide an electronic device. The interconnect can be part of a redistribution pattern or structure for an electronic device that provides a better form factor. Among other things, the structure and method provide a more cost-effective redistribution pattern for an electronic device that uses a simplified process flow and provides an efficient electrical path.

[0055] The present disclosure includes references to certain examples, however, it will be appreciated by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present disclosure. In addition, modifications may be made to the disclosed examples without departing from the scope of the present disclosure. Therefore, it is contemplated that the present disclosure is not limited to the disclosed examples, but that the present disclosure will include all examples within the scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor device, include: A substrate is provided, the substrate comprising: a first surface of a substrate; a second surface of the substrate, which is opposite to the first surface of the substrate; and electronic devices formed as part of the substrate and separated from each other by spacing, wherein each of the electronic devices has a pad formed over a first surface of the substrate; attaching leadframe interconnects to the pads, wherein each leadframe interconnect spans a space between adjacent electronic devices, and wherein each leadframe interconnect comprises: a first region coupled to a corresponding pad of a corresponding adjacent electronic device and extending in a first direction, and a second region structure coupling the first regions to each other in a second direction, the second direction being different from the first direction; providing an encapsulation on the first surface of the substrate such that the encapsulation is between each of the leadframe interconnects and between each of the leadframe interconnects and the first surface of the substrate; and The substrate and the leadframe interconnects are singulated to separate each second region structure into second regions and to separate the substrate into individual electronic devices.

2. The method according to claim 1, further comprising: include: forming a groove extending partially inwardly from the first surface of the substrate and within the gap, wherein: Providing the encapsulation includes providing the encapsulation in the groove.

3. The method according to claim 2, in: Forming the groove occurs prior to attaching the leadframe interconnect.

4. The method according to claim 1, in: The first direction is substantially perpendicular to the second direction.

5. The method according to claim 1, in: The second direction is substantially parallel to the first surface of the substrate.

6. The method according to claim 1, further comprising: include: Prior to singulating the substrate, a portion of the second surface of the substrate is removed.

7. The method according to claim 1, wherein: After the aforementioned singulation, a portion of the encapsulation remains on the side surface of the electronic device.

8. The method according to claim 1, in: One of the electronic devices has a side surface that is free of the encapsulation.

9. The method according to claim 1, in: Providing the encapsulation includes covering a first side of each second zone structure with the encapsulation and leaving a second side of each second zone structure exposed from the encapsulation.

10. The method according to claim 1, in: The aforementioned singulation includes singulating the lead frame interconnection member so that the second region extends to laterally overlap a side surface of the electronic device.

11. A semiconductor device, include: An electronic device, comprising: a top surface of the device; a device bottom surface, the device bottom surface being opposite to the device top surface; a device side surface extending between the device top surface and the device bottom surface; and a gasket disposed over a top surface of the device; and an interconnect coupled to the pad, the interconnect comprising a first region and a second region, wherein: The first regions are each coupled to a respective pad and extend in a first direction relative to the device top surface; The second regions each extend in a second direction relative to the device top surface; The second direction is substantially parallel to the device top surface; and The interconnects include leadframe leads.

12. The semiconductor device according to claim 11, further comprising: include: an encapsulation covering the top surface of the device and the first region, wherein: A first portion of the second region is exposed from a first surface of the encapsulation; A second portion of the second region is exposed from a second surface of the encapsulation; A third portion of the second region is covered by the encapsulation; and The first portion and the second portion of the second region adjoin at an edge region of the encapsulation.

13. The semiconductor device according to claim 12, in: The device side surface is free of the encapsulation.

14. The semiconductor device according to claim 12, in: The second portion of the second region is a terminal portion; The second surface is a side surface of the encapsulation; and The side surface is substantially coplanar with the end portion.

15. The semiconductor device according to claim 11, in: The first direction is substantially perpendicular to the device top surface.

16. A method for manufacturing a semiconductor device, include: providing a substrate, the substrate comprising a plurality of electronic devices formed as part of the substrate; forming a groove extending partially inwardly from the first surface of the substrate between the plurality of electronic devices; attaching leadframe interconnects to pads on the plurality of electronic devices, wherein each interconnect spans between adjacent electronic devices, wherein each leadframe interconnect comprises: a first region coupled to a corresponding pad of a corresponding adjacent electronic device and extending in an upward direction, and a second zone structure connecting the first zones to each other in a lateral direction; providing an encapsulation on the first surface of the substrate and within the recess such that the encapsulation fills a portion between each of the leadframe interconnects and a portion between each of the leadframe interconnects and the first surface of the substrate; removing a portion of the substrate from a second surface of the substrate opposite the first surface to expose the encapsulation from the second surface; and Singulating the substrate and the leadframe interconnects has separated each second region structure into second regions and separated the substrate into individual electronic devices.

17. The method according to claim 16, in: Forming the groove occurs before coupling the leadframe interconnect; and The aforementioned singulation occurs after removing the portion of the substrate.

18. The method according to claim 16, in: After the singulation step, portions of the encapsulation remain on the side surfaces of each of the plurality of electronic devices.

19. The method according to claim 16, in: Providing the encapsulation includes covering a first side of each second zone structure with the encapsulation while leaving a second side of each second zone structure exposed from the encapsulation.

20. The method according to claim 16, in: The aforementioned singulation includes singulating the lead frame interconnection such that the second region extends to laterally overlap a side surface of each of the plurality of electronic devices so as to extend outside a perimeter of each of the plurality of electronic devices.

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