Low-cost high-voltage charge pump voltage stabilizing circuit and control method thereof

Abstract

The invention discloses a low-cost high-voltage charge pump voltage stabilizing circuit and a control method thereof, the low-cost high-voltage charge pump voltage stabilizing circuit comprises a voltage stabilizing circuit and a high-voltage charge pump, the voltage stabilizing circuit outputs a stable output voltage VLDO, and the high-voltage charge pump periodically charges a load capacitor, so that the output voltage VCP is always kept on VS + VGSN4 + VGSP5 + VGSP6 to realize rising of power supply voltage VS, and the voltage stabilizing circuit is connected with the high-voltage charge pump through the VS + VGSN4 + VGSP5 + VGSP6. Wherein the VGSN4 is the gate-source voltage of the low-voltage isolation NMOS tube NMISO4, the VGSP5 is the gate-source voltage of the low-voltage isolation PMOS tube PMISO5, and the VGSP6 is the gate-source voltage of the low-voltage isolation PMOS tube PMISO6. The MIM capacitor which is large in unit capacitance value and does not need to resist high voltage is adopted, so that the chip area is saved, and the cost is reduced; and the voltage stabilizing circuit does not need to design a high-voltage operational amplifier, so that the design complexity is greatly reduced.

Description

Technical Field

[0001] The present invention relates to a charge pump voltage stabilizing circuit and a control method thereof, in particular to a low-cost high-voltage charge pump voltage stabilizing circuit and a control method thereof, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] As an important part of the chip, the charge pump converts the input power supply voltage into a higher voltage through a capacitor, providing a higher voltage than the power supply voltage for the non-volatile memory and the N-type load switch to ensure that the chip can work properly. In some applications, there are both low power supply voltage and high power supply voltage. In order to work properly under high power supply voltage, the charge pump needs to withstand high voltage, which increases the cost of the chip. Therefore, it is very important to provide a low-cost high-voltage charge pump.

[0003] The block diagram of the traditional high-voltage charge pump and its voltage stabilization circuit is as follows: Figure 2 As shown, the working principle of the voltage regulator circuit is that VREF provides a reference voltage for the negative input terminal of the high-voltage operational amplifier HV_AMP1, the output terminal of the high-voltage operational amplifier HV_AMP1 is input to the gate terminal of the high-voltage PMOS adjustment tube PDM1, and the drain terminal of the high-voltage PMOS adjustment tube PDM1 is input to the positive input terminal of the high-voltage operational amplifier HV_AMP1 through the resistor R2, forming a negative feedback loop. Through this negative feedback loop, the positive input terminal and the negative input terminal of the high-voltage operational amplifier HV_AMP1 are clamped to be equal, then the output voltage VLDO of the voltage regulator circuit is: VLDO = VREF*(R1+R2) / R1 The working principle of the high-voltage charge pump is that when CLK is high, the output of the inverter INV1 is low, and the output of the inverter INV2 is high. At this time, the voltage of node B is raised to VS+VLDO, the low-voltage isolation NMOS tube NM_ISO1 is turned on, and the power supply voltage VS charges node A through the low-voltage isolation NMOS tube NM_ISO1, so that the voltage of node A reaches VS, the low-voltage isolation PMOS tube PM_ISO2 is turned on, and node B charges the load capacitor to raise the output voltage. When CLK is low, the output of the inverter INV1 is high, and the output of the inverter INV2 is low. At this time, the voltage of node A is raised to VS+VLDO, the low-voltage isolation NMOS tube NM_ISO2 is turned on, the power supply voltage VS charges node B through the low-voltage isolation NMOS tube NM_ISO2, so that the voltage of node B reaches VS, the low-voltage isolation PMOS tube PM_ISO1 is turned on, and node A charges the load capacitor MIM_CAP1 to raise the output voltage. By periodically charging the load capacitor, the output voltage VCP is always maintained at VS+VLDO, thereby raising the power supply voltage VS.

[0004] From the above analysis, it can be seen that in the traditional high-voltage charge pump, node A and node B are high voltage, so the capacitor in the high-voltage charge pump must use a MOM capacitor that can withstand high voltage to ensure that the capacitor is not broken down. However, the unit capacitance of the MOM capacitor that withstands high voltage is small, and a large chip area needs to be used, which increases the cost. In addition, in order to realize negative feedback clamping under high voltage, its voltage stabilizing circuit needs to design a high-voltage operational amplifier, which greatly increases the complexity of the design. Therefore, it is crucial to provide a low-cost high-voltage charge pump and its voltage stabilizing circuit. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a low-cost high-voltage charge pump voltage stabilizing circuit and a control method thereof, which does not require high-voltage resistant capacitors and does not require the design of high-voltage operational amplifiers.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A low-cost high-voltage charge pump voltage regulator circuit comprises a voltage regulator circuit and a high-voltage charge pump. The voltage regulator circuit outputs a stable output voltage VLDO. The high-voltage charge pump periodically charges a load capacitor so that the output voltage VCP is always maintained at VS+VGSN4+|VGSP5|+|VGSP6| to raise the power supply voltage VS, wherein VGSN4 is the gate-source voltage of a low-voltage isolated NMOS tube NM_ISO4, VGSP5 is the gate-source voltage of a low-voltage isolated PMOS tube PM_ISO5, and VGSP6 is the gate-source voltage of a low-voltage isolated PMOS tube PM_ISO6.

[0007] Furthermore, the voltage stabilizing circuit comprises a low voltage NMOS tube NM1, a low voltage NMOS tube NM2, a low voltage NMOS tube NM3, a low voltage isolation NMOS tube NM_ISO3, a low voltage isolation NMOS tube NM_ISO4, a high voltage NMOS tube NDM1, a high voltage NMOS tube NDM2, a high voltage NMOS tube NDM3, a low voltage isolation PMOS tube PM_ISO3, a low voltage isolation PMOS tube PM_ISO4, a low voltage isolation PMOS tube PM_ISO5, a low voltage isolation PMOS tube PM_ISO6, a high voltage PMOS tube PDM1, a high voltage PMOS tube PDM2, a resistor R1 and a Zener diode Z1, and the gate of the low voltage NMOS tube NM1 is connected to the low voltage N The drain of the MOS tube NM1, the gate of the low-voltage NMOS tube NM2 and the gate of the low-voltage NMOS tube NM3 are connected and connected to the reference current IREF, the drain of the low-voltage NMOS tube NM2 is connected to the source of the high-voltage NMOS tube NDM1, the drain of the low-voltage NMOS tube NM3 is connected to the source of the high-voltage NMOS tube NDM2 and the gate of the high-voltage NMOS tube NDM3, the source of the low-voltage NMOS tube NM1, the source of the low-voltage NMOS tube NM2, the source of the low-voltage NMOS tube NM3 and the gate of the high-voltage NMOS tube NDM3 are grounded, the gate of the high-voltage NMOS tube NDM1 is connected to the gate of the high-voltage NMOS tube NDM2 and connected to the enable signal EN, and the high-voltage NMOS tube NDM The drain of 1 is connected to one end of the resistor R1, the gate of the high-voltage PMOS tube PDM1 and the gate of the high-voltage PMOS tube PDM2, the other end of the resistor R1 is connected to the drain of the high-voltage PMOS tube PDM1, the gate of the low-voltage isolation PMOS tube PM_ISO3 and the gate of the low-voltage isolation PMOS tube PM_ISO4, the source of the low-voltage isolation PMOS tube PM_ISO3 and the source of the low-voltage isolation PMOS tube PM_ISO4, the source of the low-voltage isolation PMOS tube PM_ISO5 and the cathode of the Zener diode Z1 are connected to the power supply VS, the source of the high-voltage PMOS tube PDM1 is connected to the drain of the low-voltage isolation PMOS tube PM_ISO3, the drain of the high-voltage NMOS tube NDM2 is connected to the The high-voltage PMOS tube PDM2 is connected to the drain of the high-voltage PMOS tube PDM2, the source of the high-voltage PMOS tube PDM2 is connected to the drain of the low-voltage isolation PMOS tube PM_ISO4 and the drain of the low-voltage isolation NMOS tube NM_ISO3, the gate of the low-voltage isolation NMOS tube NM_ISO3 is connected to the gate of the low-voltage isolation NMOS tube NM_ISO4, the drain of the low-voltage isolation NMOS tube NM_ISO4, the drain of the low-voltage isolation PMOS tube PM_ISO6 and the gate of the low-voltage isolation PMOS tube PM_ISO6, the source of the low-voltage isolation PMOS tube PM_ISO6 is connected to the drain of the low-voltage isolation PMOS tube PM_ISO5 and the gate of the low-voltage isolation PMOS tube PM_ISO5,The source of the low voltage isolation NMOS tube NM_ISO3 is connected to the source of the low voltage isolation NMOS tube NM_ISO4, the anode of the Zener diode Z1 and the drain of the high voltage NMOS tube NDM3 and outputs a stable output voltage VLDO.

[0008] Furthermore, the low-voltage NMOS tube NM1, the low-voltage NMOS tube NM2 and the low-voltage NMOS tube NM3 form a first NMOS current mirror, and the current mirror current ratio is 1:1:1.

[0009] Furthermore, the low-voltage isolation PMOS tube PM_ISO3 and the low-voltage isolation PMOS tube PM_ISO4 form a first PMOS current mirror, and the current mirror current ratio is 1:2.

[0010] Further, the high-voltage charge pump comprises a low-voltage isolation NMOS tube NM_ISO1, a low-voltage isolation NMOS tube NM_ISO2, a low-voltage isolation PMOS tube PM_ISO1, a low-voltage isolation PMOS tube PM_ISO2, an inverter INV_ISO1, an inverter INV_ISO2, a MIM capacitor MIM_CAP1, a MIM capacitor MIM_CAP2 and a MIM capacitor MIM_CAP3, the drain of the low-voltage isolation NMOS tube NM_ISO1 is connected to one end of the MIM capacitor MIM_CAP3 and the drain of the low-voltage isolation NMOS tube NM_ISO2 and connected to a power supply VS, the source of the low-voltage isolation NMOS tube NM_ISO1 is connected to the gate of the low-voltage isolation NMOS tube NM_ISO2, the drain of the low-voltage isolation PMOS tube PM_ISO1 and the gate of the low-voltage isolation PMOS tube PM_ISO2 and one end of the MIM capacitor MIM_CAP1 are connected to node A, the gate of the low-voltage isolation NMOS tube NM_ISO1 is connected to The source of the low-voltage isolation NMOS tube NM_ISO2, one end of the MIM capacitor MIM_CAP2, the drain of the low-voltage isolation PMOS tube PM_ISO2 and the gate of the low-voltage isolation PMOS tube PM_ISO1 are connected to the node B, the source of the low-voltage isolation PMOS tube PM_ISO1 is connected to the other end of the MIM capacitor MIM_CAP3 and the source of the low-voltage isolation PMOS tube PM_ISO2 and generates an output voltage VCP, the other end of the MIM capacitor MIM_CAP1 is connected to the output end of the inverter INV_ISO1 and the input end of the inverter INV_ISO2, the other end of the MIM capacitor MIM_CAP2 is connected to the output end of the inverter INV_ISO2, the input end of the inverter INV_ISO1 is connected to the clock signal CLK, the power supply ends of the inverter INV_ISO1 and the inverter INV_ISO2 are connected to the power supply VS, and the ground ends of the inverter INV_ISO1 and the inverter INV_ISO2 are connected to the output voltage VLDO.

[0011] A low-cost control method for a high-voltage charge pump voltage regulator circuit comprises the following steps: The low voltage NMOS tube NM1, the low voltage NMOS tube NM2 and the low voltage NMOS tube NM3 form a first NMOS current mirror, the mirror ratio of the first NMOS current mirror is 1:1:1, the high voltage NMOS tube NDM1 and the high voltage NMOS tube NDM2 are used to withstand voltage to prevent the low voltage NMOS tube NM1 and the low voltage NMOS tube NM2 from being broken down; the low voltage isolation PMOS tube PM_ISO3 and the low voltage isolation PMOS tube PM_ISO4 form a first PMOS current mirror, the mirror ratio of the first PMOS current mirror is 1:2, the high voltage PMOS tube PDM1 and the high voltage PMOS tube PDM2 are used to withstand voltage to prevent the low voltage isolation PMOS tube PM_ISO3 and the low voltage isolation PMOS tube PM_ISO4 from being broken down; Through the mirror ratio of the first NMOS current mirror and the first PMOS current mirror, it can be known that, assuming that the current in the low-voltage isolation PMOS tube PM_ISO4 is 2I, half of the current I flows into the low-voltage NMOS tube NM3, and the other half of the current I flows into the low-voltage isolation NMOS tube NM_ISO3; the low-voltage isolation NMOS tube NM_ISO3 and the low-voltage isolation NMOS tube NM_ISO4 form a second NMOS current mirror, and the mirror ratio of the second NMOS current mirror is 1:1, then the current in the low-voltage isolation NMOS tube NM_ISO4 and the low-voltage isolation PMOS tube PM_ISO5 and the low-voltage isolation PMOS tube PM_ISO6 is I, and the voltage drop generated after the low-voltage isolation NMOS tube NM_ISO4 and the low-voltage isolation PMOS tube PM_ISO5 and the low-voltage isolation PMOS tube PM_ISO6 are turned on is VGSN4+|VGSP5|+|VGSP6|, Wherein VGSN4 is the gate-source voltage of the low-voltage isolated NMOS tube NM_ISO4, VGSP5 is the gate-source voltage of the low-voltage isolated PMOS tube PM_ISO5, and VGSP6 is the gate-source voltage of the low-voltage isolated PMOS tube PM_ISO6; Then the output voltage of the voltage regulator circuit VLDO=VS-VGSN4-|VGSP5|-|VGSP6|; The Zener diode Z1 is used to clamp the low-voltage isolation NMOS tube NM_ISO4 and the low-voltage isolation PMOS tube PM_ISO5 and low-voltage isolation PMOS tube PM_ISO6 so that the voltage drop VGSN4+|VGSP5|+|VGSP6| is lower than the clamping voltage VZ1 of the Zener diode Z1 to prevent the three low-voltage isolation tubes and the subsequent circuit from being broken down; When the clock signal CLK in the high-voltage charge pump is high, the output of the inverter INV_ISO1 is low, and the output of the inverter INV_ISO2 is high. At this time, the voltage of node B is raised to VS+VGSN4+|VGSP5|+|VGSP6|, the low-voltage isolation NMOS tube NM_ISO1 is turned on, and the power supply VS charges the node A through the low-voltage isolation NMOS tube NM_ISO1, so that the voltage of node A reaches VS, the low-voltage isolation PMOS tube PM_ISO2 is turned on, and the node B charges the load capacitor to raise the output voltage VCP; When the clock signal CLK is at a low level, the output of the inverter INV_ISO1 is at a high level, and the output of the inverter INV_ISO2 is at a low level. At this time, the voltage of node A is raised to VS+VGSN4+|VGSP5|+|VGSP6|, the low-voltage isolation NMOS tube NM_ISO2 is turned on, and the power supply VS charges the node B through the low-voltage isolation NMOS tube NM_ISO2, so that the voltage of node B reaches VS, the low-voltage isolation PMOS tube PM_ISO1 is turned on, and node A charges the load capacitor to raise the output voltage VCP; By periodically charging the load capacitor, the output voltage VCP is always maintained at VS+VGSN4+|VGSP5|+|VGSP6|, thereby raising the power supply voltage VS.

[0012] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides a low-cost high-voltage charge pump voltage stabilizing circuit and a control method thereof; the high-voltage charge pump adopts a MIM capacitor with a large unit capacitance and no need to withstand high voltage, thereby saving chip area and reducing costs; the voltage stabilizing circuit does not need to design a high-voltage operational amplifier, which greatly reduces the complexity of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of a low-cost high-voltage charge pump voltage stabilizing circuit of the present invention.

[0014] Figure 2 It is a schematic diagram of a high-voltage charge pump voltage stabilizing circuit in the prior art. DETAILED DESCRIPTION

[0015] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0016] like Figure 1 As shown, a low-cost high-voltage charge pump voltage stabilizing circuit of the present invention includes a voltage stabilizing circuit and a high-voltage charge pump. The voltage stabilizing circuit outputs a stable output voltage VLDO. The high-voltage charge pump periodically charges the load capacitor so that the output voltage VCP is always maintained at VS+VGSN4+|VGSP5|+|VGSP6| to achieve the raising of the power supply voltage VS, wherein VGSN4 is the gate-source voltage of the low-voltage isolation NMOS tube NM_ISO4, VGSP5 is the gate-source voltage of the low-voltage isolation PMOS tube PM_ISO5, and VGSP6 is the gate-source voltage of the low-voltage isolation PMOS tube PM_ISO6.

[0017] The voltage stabilizing circuit includes a low-voltage NMOS tube NM1, a low-voltage NMOS tube NM2, a low-voltage NMOS tube NM3, a low-voltage isolation NMOS tube NM_ISO3, a low-voltage isolation NMOS tube NM_ISO4, a high-voltage NMOS tube NDM1, a high-voltage NMOS tube NDM2, a high-voltage NMOS tube NDM3, a low-voltage isolation PMOS tube PM_ISO3, a low-voltage isolation PMOS tube PM_ISO4, a low-voltage isolation PMOS tube PM_ISO5, a low-voltage isolation PMOS tube PM_ISO6, a high-voltage PMOS tube PDM1, a high-voltage PMOS tube PDM2, a resistor R1 and a Zener diode Z1. The gate of the low-voltage NMOS tube NM1 is connected to the low-voltage NMOS tube NM The drain of the low-voltage NMOS tube NM1, the gate of the low-voltage NMOS tube NM2 and the gate of the low-voltage NMOS tube NM3 are connected and connected to the reference current IREF, the drain of the low-voltage NMOS tube NM2 is connected to the source of the high-voltage NMOS tube NDM1, the drain of the low-voltage NMOS tube NM3 is connected to the source of the high-voltage NMOS tube NDM2 and the gate of the high-voltage NMOS tube NDM3, the source of the low-voltage NMOS tube NM1, the source of the low-voltage NMOS tube NM2, the source of the low-voltage NMOS tube NM3 and the gate of the high-voltage NMOS tube NDM3 are grounded, the gate of the high-voltage NMOS tube NDM1 is connected to the gate of the high-voltage NMOS tube NDM2 and connected to the enable signal EN, the drain of the high-voltage NMOS tube NDM1 The first terminal of the resistor R1 is connected to one end of the resistor R1, the gate of the high-voltage PMOS tube PDM1 and the gate of the high-voltage PMOS tube PDM2. The other end of the resistor R1 is connected to the drain of the high-voltage PMOS tube PDM1, the gate of the low-voltage isolation PMOS tube PM_ISO3 and the gate of the low-voltage isolation PMOS tube PM_ISO4. The source of the low-voltage isolation PMOS tube PM_ISO3, the source of the low-voltage isolation PMOS tube PM_ISO4, the source of the low-voltage isolation PMOS tube PM_ISO5 and the cathode of the Zener diode Z1 are connected to the power supply VS. The source of the high-voltage PMOS tube PDM1 is connected to the drain of the low-voltage isolation PMOS tube PM_ISO3, and the drain of the high-voltage NMOS tube NDM2 is connected to the high The drain of the high-voltage PMOS tube PDM2 is connected, the source of the high-voltage PMOS tube PDM2 is connected to the drain of the low-voltage isolation PMOS tube PM_ISO4 and the drain of the low-voltage isolation NMOS tube NM_ISO3, the gate of the low-voltage isolation NMOS tube NM_ISO3 is connected to the gate of the low-voltage isolation NMOS tube NM_ISO4, the drain of the low-voltage isolation NMOS tube NM_ISO4, the drain of the low-voltage isolation PMOS tube PM_ISO6 and the gate of the low-voltage isolation PMOS tube PM_ISO6, the source of the low-voltage isolation PMOS tube PM_ISO6 is connected to the drain of the low-voltage isolation PMOS tube PM_ISO5 and the gate of the low-voltage isolation PMOS tube PM_ISO5,The source of the low voltage isolation NMOS tube NM_ISO3 is connected to the source of the low voltage isolation NMOS tube NM_ISO4, the anode of the Zener diode Z1 and the drain of the high voltage NMOS tube NDM3 and outputs a stable output voltage VLDO.

[0018] The low voltage NMOS tube NM1 , the low voltage NMOS tube NM2 and the low voltage NMOS tube NM3 constitute a first NMOS current mirror, and the current ratio of the current mirror is 1:1:1.

[0019] The low voltage isolation PMOS tube PM_ISO3 and the low voltage isolation PMOS tube PM_ISO4 form a first PMOS current mirror, and the current mirror current ratio is 1:2.

[0020] The high-voltage charge pump includes a low-voltage isolation NMOS tube NM_ISO1, a low-voltage isolation NMOS tube NM_ISO2, a low-voltage isolation PMOS tube PM_ISO1, a low-voltage isolation PMOS tube PM_ISO2, an inverter INV_ISO1, an inverter INV_ISO2, a MIM capacitor MIM_CAP1, a MIM capacitor MIM_CAP2 and a MIM capacitor MIM_CAP3. The drain of the low-voltage isolation NMOS tube NM_ISO1 is connected to one end of the MIM capacitor MIM_CAP3 and the drain of the low-voltage isolation NMOS tube NM_ISO2 and is connected to the power supply VS. The source of the low-voltage isolation NMOS tube NM_ISO1 is connected to the gate of the low-voltage isolation NMOS tube NM_ISO2, the drain of the low-voltage isolation PMOS tube PM_ISO1, the gate of the low-voltage isolation PMOS tube PM_ISO2 and one end of the MIM capacitor MIM_CAP1 are connected to node A. The gate of the low-voltage isolation NMOS tube NM_ISO1 is connected to the low-voltage isolation The source of the NMOS tube NM_ISO2, one end of the MIM capacitor MIM_CAP2, the drain of the low-voltage isolation PMOS tube PM_ISO2 and the gate of the low-voltage isolation PMOS tube PM_ISO1 are connected to the node B, the source of the low-voltage isolation PMOS tube PM_ISO1 is connected to the other end of the MIM capacitor MIM_CAP3 and the source of the low-voltage isolation PMOS tube PM_ISO2 and generates an output voltage VCP, the other end of the MIM capacitor MIM_CAP1 is connected to the output end of the inverter INV_ISO1 and the input end of the inverter INV_ISO2, the other end of the MIM capacitor MIM_CAP2 is connected to the output end of the inverter INV_ISO2, the input end of the inverter INV_ISO1 is connected to the clock signal CLK, the power supply ends of the inverter INV_ISO1 and the inverter INV_ISO2 are connected to the power supply VS, and the ground ends of the inverter INV_ISO1 and the inverter INV_ISO2 are connected to the output voltage VLDO.

[0021] A low-cost control method for a high-voltage charge pump voltage regulator circuit comprises the following steps: The low voltage NMOS tube NM1, the low voltage NMOS tube NM2 and the low voltage NMOS tube NM3 form a first NMOS current mirror, the mirror ratio of the first NMOS current mirror is 1:1:1, the high voltage NMOS tube NDM1 and the high voltage NMOS tube NDM2 are used for withstand voltage to prevent the low voltage NMOS tube NM1 and the low voltage NMOS tube NM2 from being broken down; the low voltage isolation PMOS tube PM_ISO3 and the low voltage isolation PMOS tube PM_ISO4 form a first PMOS current mirror, the mirror ratio of the first PMOS current mirror is 1:2, the high voltage PMOS tube PDM1 and the high voltage PMOS tube PDM2 are used for withstand voltage to prevent the low voltage isolation PMOS tube PM_ISO3 and the low voltage isolation PMOS tube PM_ISO4 from being broken down.

[0022] Through the mirror ratio of the first NMOS current mirror and the first PMOS current mirror, it can be known that, assuming that the current in the low-voltage isolation PMOS tube PM_ISO4 is 2I, half of the current I flows into the low-voltage NMOS tube NM3, and the other half of the current I flows into the low-voltage isolation NMOS tube NM_ISO3; the low-voltage isolation NMOS tube NM_ISO3 and the low-voltage isolation NMOS tube NM_ISO4 form a second NMOS current mirror, and the mirror ratio of the second NMOS current mirror is 1:1, then the current in the low-voltage isolation NMOS tube NM_ISO4 and the low-voltage isolation PMOS tube PM_ISO5 and the low-voltage isolation PMOS tube PM_ISO6 is I, and the voltage drop generated after the low-voltage isolation NMOS tube NM_ISO4 and the low-voltage isolation PMOS tube PM_ISO5 and the low-voltage isolation PMOS tube PM_ISO6 are turned on is VGSN4+|VGSP5|+|VGSP6|, Among them, VGSN4 is the gate-source voltage of the low-voltage isolated NMOS tube NM_ISO4, VGSP5 is the gate-source voltage of the low-voltage isolated PMOS tube PM_ISO5, and VGSP6 is the gate-source voltage of the low-voltage isolated PMOS tube PM_ISO6.

[0023] Then the output voltage VLDO of the voltage regulator circuit = VS-VGSN4-|VGSP5|-|VGSP6|.

[0024] The Zener diode Z1 is used to clamp the voltage drops VGSN4+|VGSP5|+|VGSP6| on the low-voltage isolation NMOS tube NM_ISO4 and the low-voltage isolation PMOS tube PM_ISO5 and the low-voltage isolation PMOS tube PM_ISO6 to be lower than the clamping voltage VZ1 of the Zener diode Z1 to prevent the three low-voltage isolation tubes and the subsequent circuit from being broken down.

[0025] When the clock signal CLK in the high-voltage charge pump is high, the output of the inverter INV_ISO1 is low, and the output of the inverter INV_ISO2 is high. At this time, the voltage of node B is raised to VS+VGSN4+|VGSP5|+|VGSP6|, the low-voltage isolation NMOS tube NM_ISO1 is turned on, and the power supply VS charges the node A through the low-voltage isolation NMOS tube NM_ISO1, so that the voltage of node A reaches VS, the low-voltage isolation PMOS tube PM_ISO2 is turned on, and the node B charges the load capacitor to raise the output voltage VCP.

[0026] When the clock signal CLK is at a low level, the output of the inverter INV_ISO1 is at a high level, and the output of the inverter INV_ISO2 is at a low level. At this time, the voltage of node A is raised to VS+VGSN4+|VGSP5|+|VGSP6|, the low-voltage isolation NMOS tube NM_ISO2 is turned on, and the power supply VS charges the node B through the low-voltage isolation NMOS tube NM_ISO2, so that the voltage of node B reaches VS, the low-voltage isolation PMOS tube PM_ISO1 is turned on, and node A charges the load capacitor to raise the output voltage VCP.

[0027] By periodically charging the load capacitor, the output voltage VCP is always maintained at VS+VGSN4+|VGSP5|+|VGSP6|, thereby raising the power supply voltage VS.

[0028] Since the voltage difference between VLDO and VCP is low voltage, the capacitor does not need to withstand high voltage, and MIM capacitors with larger unit capacitance can be used, thereby saving chip area and reducing costs. In addition, its voltage stabilization circuit does not need to design a high-voltage operational amplifier, which greatly reduces the complexity of the design.

[0029] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. A low-cost high-voltage charge pump voltage regulator circuit, characterized in that: It includes a voltage regulator circuit and a high-voltage charge pump. The voltage regulator circuit outputs a stable output voltage VLDO. The high-voltage charge pump periodically charges the load capacitor so that the output voltage VCP is always maintained at VS+VGSN4+|VGSP5|+|VGSP6| to raise the power supply voltage VS, wherein VGSN4 is the gate-source voltage of the low-voltage isolated NMOS tube NM_ISO4, VGSP5 is the gate-source voltage of the low-voltage isolated PMOS tube PM_ISO5, and VGSP6 is the gate-source voltage of the low-voltage isolated PMOS tube PM_ISO6.

2. A low-cost high-voltage charge pump voltage stabilizing circuit according to claim 1, characterized in that: The voltage stabilizing circuit comprises a low voltage NMOS tube NM1, a low voltage NMOS tube NM2, a low voltage NMOS tube NM3, a low voltage isolation NMOS tube NM_ISO3, a low voltage isolation NMOS tube NM_ISO4, a high voltage NMOS tube NDM1, a high voltage NMOS tube NDM2, a high voltage NMOS tube NDM3, a low voltage isolation PMOS tube PM_ISO3, a low voltage isolation PMOS tube PM_ISO4, a low voltage isolation PMOS tube PM_ISO5, a low voltage isolation PMOS tube PM_ISO6, a high voltage PMOS tube PDM1, a high voltage PMOS tube PDM2, a resistor R1 and a Zener diode Z1. The gate of the low voltage NMOS tube NM1 is connected to the low voltage NMOS tube The drain of NM1, the gate of the low-voltage NMOS tube NM2 and the gate of the low-voltage NMOS tube NM3 are connected and connected to the reference current IREF, the drain of the low-voltage NMOS tube NM2 is connected to the source of the high-voltage NMOS tube NDM1, the drain of the low-voltage NMOS tube NM3 is connected to the source of the high-voltage NMOS tube NDM2 and the gate of the high-voltage NMOS tube NDM3, the source of the low-voltage NMOS tube NM1, the source of the low-voltage NMOS tube NM2, the source of the low-voltage NMOS tube NM3 and the gate of the high-voltage NMOS tube NDM3 are grounded, the gate of the high-voltage NMOS tube NDM1 is connected to the gate of the high-voltage NMOS tube NDM2 and connected to the enable signal EN, the drain of the high-voltage NMOS tube NDM1 is connected to the source of the high-voltage NMOS tube NDM2 and the enable signal EN, and the drain of the high-voltage NMOS tube NDM1 is connected to the source of the high-voltage NMOS tube NDM2. The electrode is connected to one end of the resistor R1, the gate of the high-voltage PMOS tube PDM1 and the gate of the high-voltage PMOS tube PDM2, the other end of the resistor R1 is connected to the drain of the high-voltage PMOS tube PDM1, the gate of the low-voltage isolation PMOS tube PM_ISO3 and the gate of the low-voltage isolation PMOS tube PM_ISO4, the source of the low-voltage isolation PMOS tube PM_ISO3 and the source of the low-voltage isolation PMOS tube PM_ISO4, the source of the low-voltage isolation PMOS tube PM_ISO5 and the cathode of the Zener diode Z1 are connected to the power supply VS, the source of the high-voltage PMOS tube PDM1 is connected to the drain of the low-voltage isolation PMOS tube PM_ISO3, the drain of the high-voltage NMOS tube NDM2 is connected to The drain of the high-voltage PMOS tube PDM2 is connected, the source of the high-voltage PMOS tube PDM2 is connected to the drain of the low-voltage isolation PMOS tube PM_ISO4 and the drain of the low-voltage isolation NMOS tube NM_ISO3, the gate of the low-voltage isolation NMOS tube NM_ISO3 is connected to the gate of the low-voltage isolation NMOS tube NM_ISO4, the drain of the low-voltage isolation NMOS tube NM_ISO4, the drain of the low-voltage isolation PMOS tube PM_ISO6 and the gate of the low-voltage isolation PMOS tube PM_ISO6, the source of the low-voltage isolation PMOS tube PM_ISO6 is connected to the drain of the low-voltage isolation PMOS tube PM_ISO5 and the gate of the low-voltage isolation PMOS tube PM_ISO5,The source of the low voltage isolation NMOS tube NM_ISO3 is connected to the source of the low voltage isolation NMOS tube NM_ISO4, the anode of the Zener diode Z1 and the drain of the high voltage NMOS tube NDM3 and outputs a stable output voltage VLDO.

3. A low-cost high-voltage charge pump voltage stabilizing circuit according to claim 2, characterized in that: The low voltage NMOS tube NM1, the low voltage NMOS tube NM2 and the low voltage NMOS tube NM3 form a first NMOS current mirror, and the current ratio of the current mirror is 1:1:

1.

4. A low-cost high-voltage charge pump voltage stabilizing circuit according to claim 2, characterized in that: The low voltage isolation PMOS tube PM_ISO3 and the low voltage isolation PMOS tube PM_ISO4 form a first PMOS current mirror, and the current mirror current ratio is 1:

2.

5. The low-cost high-voltage charge pump voltage stabilizing circuit according to claim 1, characterized in that: The high-voltage charge pump comprises a low-voltage isolation NMOS tube NM_ISO1, a low-voltage isolation NMOS tube NM_ISO2, a low-voltage isolation PMOS tube PM_ISO1, a low-voltage isolation PMOS tube PM_ISO2, an inverter INV_ISO1, an inverter INV_ISO2, a MIM capacitor MIM_CAP1, a MIM capacitor MIM_CAP2 and a MIM capacitor MIM_CAP3. The drain of the low-voltage isolation NMOS tube NM_ISO1 is connected to one end of the MIM capacitor MIM_CAP3 and the drain of the low-voltage isolation NMOS tube NM_ISO2 and is connected to a power source VS. The source of the low-voltage isolation NMOS tube NM_ISO1 is connected to the gate of the low-voltage isolation NMOS tube NM_ISO2, the drain of the low-voltage isolation PMOS tube PM_ISO1, the gate of the low-voltage isolation PMOS tube PM_ISO2 and one end of the MIM capacitor MIM_CAP1 are connected to a node A. The gate of the low-voltage isolation NMOS tube NM_ISO1 is connected to the low-voltage isolation The source of the isolated NMOS tube NM_ISO2, one end of the MIM capacitor MIM_CAP2, the drain of the low-voltage isolation PMOS tube PM_ISO2 and the gate of the low-voltage isolation PMOS tube PM_ISO1 are connected to the node B, the source of the low-voltage isolation PMOS tube PM_ISO1 is connected to the other end of the MIM capacitor MIM_CAP3 and the source of the low-voltage isolation PMOS tube PM_ISO2 to generate an output voltage VCP, the other end of the MIM capacitor MIM_CAP1 is connected to the output end of the inverter INV_ISO1 and the input end of the inverter INV_ISO2, the other end of the MIM capacitor MIM_CAP2 is connected to the output end of the inverter INV_ISO2, the input end of the inverter INV_ISO1 is connected to the clock signal CLK, the power supply ends of the inverter INV_ISO1 and the inverter INV_ISO2 are connected to the power supply VS, and the ground ends of the inverter INV_ISO1 and the inverter INV_ISO2 are connected to the output voltage VLDO.

6. A control method for a low-cost high-voltage charge pump voltage regulator circuit according to any one of claims 1 to 5, characterized in that The following steps are involved: The low voltage NMOS tube NM1, the low voltage NMOS tube NM2 and the low voltage NMOS tube NM3 form a first NMOS current mirror, the mirror ratio of the first NMOS current mirror is 1:1:1, the high voltage NMOS tube NDM1 and the high voltage NMOS tube NDM2 are used to withstand voltage to prevent the low voltage NMOS tube NM1 and the low voltage NMOS tube NM2 from being broken down; the low voltage isolation PMOS tube PM_ISO3 and the low voltage isolation PMOS tube PM_ISO4 form a first PMOS current mirror, the mirror ratio of the first PMOS current mirror is 1:2, the high voltage PMOS tube PDM1 and the high voltage PMOS tube PDM2 are used to withstand voltage to prevent the low voltage isolation PMOS tube PM_ISO3 and the low voltage isolation PMOS tube PM_ISO4 from being broken down; Through the mirror ratio of the first NMOS current mirror and the first PMOS current mirror, it can be known that, assuming that the current in the low-voltage isolation PMOS tube PM_ISO4 is 2I, half of the current I flows into the low-voltage NMOS tube NM3, and the other half of the current I flows into the low-voltage isolation NMOS tube NM_ISO3; the low-voltage isolation NMOS tube NM_ISO3 and the low-voltage isolation NMOS tube NM_ISO4 form a second NMOS current mirror, and the mirror ratio of the second NMOS current mirror is 1:1, then the current in the low-voltage isolation NMOS tube NM_ISO4 and the low-voltage isolation PMOS tube PM_ISO5 and the low-voltage isolation PMOS tube PM_ISO6 is I, and the voltage drop generated after the low-voltage isolation NMOS tube NM_ISO4 and the low-voltage isolation PMOS tube PM_ISO5 and the low-voltage isolation PMOS tube PM_ISO6 are turned on is VGSN4+|VGSP5|+|VGSP6|, Wherein VGSN4 is the gate-source voltage of the low-voltage isolated NMOS tube NM_ISO4, VGSP5 is the gate-source voltage of the low-voltage isolated PMOS tube PM_ISO5, and VGSP6 is the gate-source voltage of the low-voltage isolated PMOS tube PM_ISO6; Then the output voltage of the voltage regulator circuit VLDO=VS-VGSN4-|VGSP5|-|VGSP6|; The Zener diode Z1 is used to clamp the low-voltage isolation NMOS tube NM_ISO4 and the low-voltage isolation PMOS tube PM_ISO5 and low-voltage isolation PMOS tube PM_ISO6 so that the voltage drop VGSN4+|VGSP5|+|VGSP6| is lower than the clamping voltage VZ1 of the Zener diode Z1 to prevent the three low-voltage isolation tubes and the subsequent circuit from being broken down; When the clock signal CLK in the high-voltage charge pump is high, the output of the inverter INV_ISO1 is low, and the output of the inverter INV_ISO2 is high. At this time, the voltage of node B is raised to VS+VGSN4+|VGSP5|+|VGSP6|, the low-voltage isolation NMOS tube NM_ISO1 is turned on, and the power supply VS charges the node A through the low-voltage isolation NMOS tube NM_ISO1, so that the voltage of node A reaches VS, the low-voltage isolation PMOS tube PM_ISO2 is turned on, and the node B charges the load capacitor to raise the output voltage VCP; When the clock signal CLK is at a low level, the output of the inverter INV_ISO1 is at a high level, and the output of the inverter INV_ISO2 is at a low level. At this time, the voltage of node A is raised to VS+VGSN4+|VGSP5|+|VGSP6|, the low-voltage isolation NMOS tube NM_ISO2 is turned on, and the power supply VS charges the node B through the low-voltage isolation NMOS tube NM_ISO2, so that the voltage of node B reaches VS, the low-voltage isolation PMOS tube PM_ISO1 is turned on, and node A charges the load capacitor to raise the output voltage VCP; By periodically charging the load capacitor, the output voltage VCP is always maintained at VS+VGSN4+|VGSP5|+|VGSP6|, thereby raising the power supply voltage VS.

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