Clock modulation circuit and clock modulation method for generating spread spectrum clock signal

Abstract

The invention discloses a clock modulation circuit and a clock modulation method for generating a spread spectrum clock signal. The clock modulation circuit comprises a current generator used for respectively generating a trimming current with a preset value and a modulation current changing along with time, and a current control type oscillator used for respectively generating a standard clock signal and a spread spectrum clock signal according to the trimming current and the modulation current, the current adjusting precision of the modulation current is higher than that of the trimming current. According to the clock modulation circuit, high-precision frequency jump of spread spectrum clock signals can be realized by using a high-precision jitter current channel, and overshoot or undershoot of the spread spectrum clock signals during frequency jump can be suppressed.

Description

Technical Field

[0001] The present disclosure relates to the technical field of signal processing, and more particularly, to a clock modulation circuit and a clock modulation method for generating a spread spectrum clock signal. Background Art

[0002] In high-speed digital circuits and high-speed data communications, the use of spread spectrum clock signals (Spread Spectrum Clocking, SSC) is an effective way to reduce electromagnetic interference (EMI). Spread spectrum clock signals have a clock frequency that changes over time within a predetermined range. By modulating the clock frequency within a predetermined frequency range, the energy density at a specific frequency is reduced, effectively reducing electromagnetic interference, thereby ensuring that electronic equipment meets EMI standards while operating at high performance.

[0003] See also Figure 1 In an existing clock modulation circuit 100, a source clock signal CLK with a fixed frequency generated by an oscillator 101 is subjected to a logic operation with modulation data Din to generate a spread spectrum clock signal CK. For example, an XOR gate 102 is used to perform a logic operation to enable or disable certain edges of the clock signal, thereby changing the frequency of the spread spectrum clock signal CK. However, the use of a logic operation will cause the frequency of the spread spectrum clock signal CK to vary too much, which may even cause the circuit to malfunction for high-speed digital circuits and high-speed data communications.

[0004] In another existing clock modulation circuit, if the analog oscillator has a trimming terminal for receiving trimming data, the spread spectrum clock signal CK can be directly generated by modifying the trimming data. When the time domain response of the analog oscillator is a linear characteristic, the modulation of the trimming data can obtain the desired clock frequency jitter. When the time domain response of the analog oscillator is a nonlinear characteristic, the modulation of the trimming data may cause overshoot or undershoot of the clock frequency, making it difficult to obtain the desired spread spectrum clock signal. For high-speed digital circuits and high-speed data communications, it may even cause the circuit to fail to work properly. In the frequency locked loop (abbreviated as FLL) architecture, the modulation of the trimming data usually exhibits peak behavior due to feedback loop stability compensation. For oscillators in the range of about several 10MHz, stability compensation requires a large on-chip capacitor to reduce the peak behavior in the time domain, resulting in an increase in chip area.

[0005] Therefore, it is desirable to further improve the design of the clock modulation circuit to optimize the frequency transition characteristics of the spread spectrum clock signal. Summary of the invention

[0006] In view of this, an object of the present invention is to provide a clock modulation circuit and a clock modulation method for generating a spread spectrum clock signal, wherein a high-precision jitter current channel is used to achieve a high-precision frequency transition of the spread spectrum clock signal, and to suppress overshoot or undershoot of the spread spectrum clock signal during the frequency transition.

[0007] According to one aspect of the present invention, there is provided a clock modulation circuit, comprising: a current generator for generating a trimming current of a predetermined value and a modulation current that varies with time, and a current-controlled oscillator for generating a standard clock signal and a spread spectrum clock signal according to the trimming current and the modulation current, respectively, wherein the jitter current accuracy of the modulation current is higher than the trimming current accuracy of the trimming current.

[0008] Optionally, the current generator comprises a current-type digital-to-analog converter, which is used to convert the trimming data into the trimming current, and convert the trimming data and the modulation data into a valley value and a peak value of the modulation current, respectively.

[0009] Optionally, it also includes: a multiplexer connected to the current-type digital-to-analog converter, used to periodically select the trimming data and the modulation data according to the modulation signal, and provide the trimming data and the modulation data to the current-controlled oscillator to generate the modulation current.

[0010] Optionally, the high significant bits of the trimming data are valid adjustment data, and the low significant bits of the modulation data are valid adjustment data, so that the high-weight current channel and the low-weight current channel of the current-type digital-to-analog converter serve as the trimming current channel and the jitter current channel, respectively.

[0011] Optionally, the current generator includes a first current channel and a second current channel, which are respectively used to provide the trimming current and the jittering current, and the first current channel and the second current channel are coupled to a common node to obtain the modulation current, and the modulation current is a combined current of the trimming current and the jittering current.

[0012] Optionally, the first current channel includes a first current-type digital-to-analog converter, and the first current-type digital-to-analog converter performs digital-to-analog conversion on the trimming data to generate the trimming current.

[0013] Optionally, the second current channel includes: a second current-type digital-to-analog converter, which performs digital-to-analog conversion on the modulation data to generate a reference current; and a modulation module, which is used to convert the reference current into a jitter current that varies with time.

[0014] Optionally, the modulation module selectively couples the reference current into one of a sinking current, a sourcing current, and a zero current of the common node to obtain the jittering current.

[0015] Optionally, the modulation module includes: a first transistor and a second transistor, coupled to each other to form a first current mirror; a third transistor and a fourth transistor, coupled to each other to form a second current mirror; and a first switch, wherein the first transistor is coupled in series with the second current-type digital-to-analog converter, the second transistor and the third transistor are coupled in series, and the first switch is coupled between the fourth transistor and the common node, thereby mirroring the reference current into a sink current or zero current flowing into the common node.

[0016] Optionally, the modulation module also includes: a fifth transistor, coupled with the first transistor to form a third current mirror; and a second switch, wherein the second switch is coupled between the common node of the fifth transistor, thereby mirroring the reference current into a pull current or zero current flowing out of the common node.

[0017] Optionally, the bit weight of the second current-mode digital-to-analog converter is smaller than the bit weight of the first current-mode digital-to-analog converter, thereby improving the bit accuracy of the jitter current relative to the trimming current.

[0018] Optionally, the modulation module scales down the reference current so as to improve the bit accuracy of the jitter current relative to the trimmed current.

[0019] Optionally, the current-controlled oscillator includes: a third switch; a capacitor connected in parallel with the third switch, and the modulation current is used to charge the capacitor to generate a ramp signal during the period when the third switch is turned off; and a control module, used to generate the spread spectrum clock signal according to the comparison result of the ramp signal and a reference voltage, wherein the third switch is turned on for a certain time in response to the rising edge of the spread spectrum clock signal to reset the voltage of the capacitor, and the third switch is turned off after the voltage of the capacitor is reset.

[0020] Optionally, the current-controlled oscillator includes: a first current source and a second current source, for respectively generating a first current and a second current corresponding to the modulation current; a fourth switch and a fifth switch, which are connected in series between the first current source and the second current source; a capacitor, which is coupled to an intermediate node between the fourth switch and the fifth switch, and is charged with the first current and discharged with the second current, thereby generating a ramp signal; and a trigger, which is used to generate the spread spectrum clock signal according to a comparison result between the ramp signal and a reference voltage, wherein, in a valid state of the spread spectrum clock signal, the fourth switch is turned on and the fifth switch is turned off, and in an invalid state of the spread spectrum clock signal, the fourth switch is turned off and the fifth switch is turned on, thereby alternately charging and discharging the capacitor in a clock cycle of the spread spectrum clock signal.

[0021] According to another aspect of the present invention, there is provided a clock modulation method, comprising: using a current generator to generate a trimming current of a predetermined value and a modulation current that varies with time; and generating a standard clock signal and a spread spectrum clock signal according to the trimming current and the modulation current, respectively, wherein the jitter current accuracy of the modulation current is higher than the trimming current accuracy of the trimming current.

[0022] Optionally, the step of generating a trimmed current of a predetermined value and a modulation current that varies with time includes: periodically selecting trimmed data and modulation data according to a modulation signal; and providing the trimmed data and modulation data to a current controlled oscillator to generate the modulation current.

[0023] Optionally, the step of generating a trimming current of a predetermined value and a modulation current that varies with time includes: generating a trimming current and a jittering current according to trimming data and jittering data, respectively, wherein the modulation current is a combined current of the trimming current and the jittering current.

[0024] According to the clock modulation circuit of the embodiment of the present invention, a standard clock signal and a spread spectrum clock signal are generated according to the trimming current and the modulation current, respectively, wherein the jitter current precision of the modulation current is higher than the trimming current precision of the trimming current. The clock modulation circuit uses a high-precision jitter current to achieve a high-precision frequency jump of the spread spectrum clock signal and suppress overshoot or undershoot of the spread spectrum clock signal during frequency jump.

[0025] In a preferred embodiment, the trimming current channel and the dithering current channel are independent of each other and each includes its own current-mode digital-to-analog converter, which generates a trimming current and a dithering current according to trimming data and dithering data respectively, and then combines the two into a modulated current. Since a high-precision current-mode digital-to-analog converter is used in the dithering current channel to generate a high-precision dithering current, high-precision frequency jumps of the spread-spectrum clock signal can be achieved, and overshoot or undershoot of the spread-spectrum clock signal during frequency jumps can be suppressed.

[0026] In another preferred embodiment, the trimming current channel and the dithering current channel share a current-mode digital-to-analog converter. Since at least some circuit modules of the existing trimming current channel that share a clock modulation circuit are used, the circuit structure can be simplified and the circuit cost can be reduced. The clock modulation circuit uses different significant bits of the current-mode digital-to-analog converter to implement trimming current channels and dithering current channels with different precisions. The lower significant bits of the current-mode digital-to-analog converter are used to implement a high-precision dithering current channel. Therefore, compared with the trimming frequency accuracy of a standard clock signal, high-precision frequency jumps of the spread-spectrum clock signal can be achieved, and overshoot or undershoot of the spread-spectrum clock signal during frequency jumps can be suppressed.

[0027] In yet another preferred embodiment, a modulation module in the current generator performs a K:1 scaling on the reference current Iref to obtain a dithering current that is scaled down compared to the reference current. The current generator uses the scaling down of the reference current to implement a high-precision dithering current channel. Therefore, compared with the trimming frequency accuracy of a standard clock signal, high-precision frequency jumps of the spread-spectrum clock signal can be achieved, and overshoot or undershoot of the spread-spectrum clock signal during frequency jumps can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic block diagram showing a clock modulation circuit according to the prior art.

[0029] Figure 2 A schematic block diagram showing a clock modulation circuit according to the first embodiment of the present invention.

[0030] Figure 3 Showing Figure 2 A schematic circuit diagram showing the current-mode DAC in the shown clock modulation circuit.

[0031] Figure 4 Showing Figure 2 A schematic circuit diagram showing a first example of a current-controlled oscillator in the shown clock modulation circuit.

[0032] Figure 5 Showing Figure 2 A schematic circuit diagram showing a second example of a current-controlled oscillator in the shown clock modulation circuit.

[0033] Figure 6 FIG. 4 is a schematic block diagram of a clock modulation circuit according to a second embodiment of the present invention.

[0034] Figure 7 Show Figure 6 A schematic circuit diagram of a current generator in the clock modulation circuit shown.

[0035] Figure 8 A flow chart of a clock modulation method according to a third embodiment of the present invention is shown.

[0036] Fig. 9 Schematic waveform diagrams of spread spectrum clock signals of a clock modulation circuit according to the prior art and a clock modulation circuit according to an embodiment of the present invention are shown.

[0037] Fig.10 FIG. 4 is a diagram showing a measured waveform of a spread spectrum clock signal of a clock modulation circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The preferred embodiments of the present disclosure are described in detail below in conjunction with the accompanying drawings, but the present disclosure is not limited to these embodiments. The present disclosure covers any substitution, modification, equivalent method and scheme made within the spirit and scope of the present disclosure.

[0039] In order to make the public have a thorough understanding of the present disclosure, specific details are described in detail in the following preferred embodiments of the present disclosure, but those skilled in the art can fully understand the present disclosure without description of these details.

[0040] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. It should be noted that the accompanying drawings are all in a relatively simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0041] Figure 2 FIG. 2 is a schematic block diagram of a clock modulation circuit according to a first embodiment of the present invention. The clock modulation circuit 200 includes a current generator 210 and a current controlled oscillator 220 .

[0042] The current generator 210 includes a multiplexer 211 and a current-type DAC 212. Under the control of the modulation signal MOD, the multiplexer 211 periodically selects one of the trimming data Dtrim and the modulation data Dmod, thereby generating a modulated current Imod. In the present embodiment, the trimming data Dtrim and the modulation data Dmod are both N-bit binary numbers. Among them, the effective adjustment data of the trimming data Dtrim is a total of a high-significant bits of the N-bit binary number, which is used to generate a trimming current Itrim of level 2^a. The effective adjustment data of the modulation data Dmod is a total of b low-significant bits of the N-bit binary number, which is used to generate a jitter current Ijitter of level 2^b. Among them, N, a and b are all integers, and N>=a+b. In the present embodiment, N is equal to 4, for example, the trimming data Dtrim and the modulation data Dmod are binary numbers 1000 and 1010, respectively. However, the present invention is not limited to this, and the trimming data Dtrim and the modulation data Dmod can be binary numbers of any number of bits set according to chip design requirements and application requirements.

[0043] The current-type DAC 212 is connected to the multiplexer 211 and converts the trimming data Dtrim and the modulation data Dmod into the valley value and peak value of the modulation current Imod. Figure 3 For example, the current-type DAC 212 includes a plurality of current sources IS1-IS4, whose output terminals are respectively connected to a plurality of single-pole double-throw switches S1-S4, thereby forming a plurality of current channels with different weight currents, for example, the weight currents of the plurality of current channels are 1, 1 / 2, 1 / 4, and 1 / 8, respectively. When receiving the trimming data Dtrim and the modulation data Dmod, the plurality of single-pole double-throw switches S1-S4 selectively connect the corresponding current sources to the output terminals or to the ground according to the digital values ​​of the trimming data Dtrim and the modulation data Dmod, thereby generating a current valley value and a current peak value corresponding to the trimming data Dtrim and the modulation data Dmod.

[0044] The current controlled oscillator 220 is connected to the current generator 210 and generates a standard clock signal CLK or a spread spectrum clock signal CK according to the modulation current Imod.

[0045] When the frequency jittering function of the clock modulation circuit is disabled, the multiplexer 211 always selects the trimming data Dtrim and provides the trimming data Dtrim to the current-type DAC 212 to generate a trimming current Itrim of a predetermined value. After the chip of the clock modulation circuit is manufactured, the value of the trimming data Dtrim is determined according to the chip test results to correct the frequency fluctuation of the clock signal caused by the chip manufacturing process. After the chip leaves the factory, the trimming data Dtrim has been set to a predetermined value unless the chip is trimmed again. Therefore, the trimming current Itrim generated by the current-type DAC 212 is a fixed current corresponding to the trimming data Dtrim. At this time, the current-controlled oscillator 220 generates a standard clock signal CLK.

[0046] When the frequency-jittering function of the clock modulation circuit is enabled, the multiplexer 211 periodically selects one of the trimming data Dtrim and the modulation data Dmod, and provides it to the current-type DAC 212 to generate a modulation current Imod. At this time, the modulation current Imod is a pulse current with the same period as the modulation signal MOD, and its valley value and peak value correspond to the trimming data Dtrim and the modulation data Dmod, respectively. At this time, the current-controlled oscillator 220 generates a spread spectrum clock signal CK composed of two clock signals of different frequencies. However, the present invention is not limited to this. In the case where the input data received by the multiplexer 211 includes multiple modulation data Dmod, a spread spectrum clock signal CK composed of three or more clock signals of different frequencies can be generated.

[0047] In this embodiment, the trimming data Dtrim and the modulation data Dmod are binary numbers 1000 and 1010, respectively. The effective adjustment data of the trimming data Dtrim is 2 high-significant bits, so the precision of the trimming current Itrim is equal to the weighted current I / 2 of the current source IS2 in the current-type DAC 212. The effective adjustment data of the modulation data Dmod is 2 low-significant bits, so the precision of the jitter current Ijitter is equal to the weighted current I / 8 of the current source IS4 in the current-type DAC 212.

[0048] According to the clock modulation circuit 200 of the present embodiment, the trimming current channel and the jittering current channel share the current-type DAC 212. Since at least some circuit modules of the existing trimming current channel of the clock modulation circuit are shared, the circuit structure can be simplified and the circuit cost can be reduced. The clock modulation circuit 200 uses different effective bits of the current-type DAC 212 to realize trimming current channels and jittering current channels with different precisions, wherein the low effective bits of the current-type DAC 212 are used to realize a high-precision jittering current channel. Therefore, compared with the trimming frequency precision of the standard clock signal, a high-precision frequency jump of the spread spectrum clock signal can be realized, and the overshoot or undershoot of the spread spectrum clock signal during the frequency jump can be suppressed.

[0049] Figure 4 Show Figure 2 The schematic circuit diagram of the first example of the current controlled oscillator in the clock modulation circuit is shown. The input terminal of the current controlled oscillator 220 receives the modulation current Imod, and the output terminal provides the spread spectrum clock signal CK.

[0050] The current controlled oscillator 220 includes a capacitor C11 , a switch S11 , and a control module 21 .

[0051] The capacitor C11 and the switch S11 are connected in parallel between the input terminal of the current-controlled oscillator 220 and the ground. During the period when the switch S11 is turned off, the modulation current Imod charges the capacitor C11 to generate the ramp signal Vslope. During the period when the switch S11 is closed, the voltage on the capacitor C11 is reset, that is, the ramp signal Vslope is reset. The input end of the control module 21 is connected to the high potential end of the capacitor C11 to receive the ramp signal Vslope, and the control module 21 compares the ramp signal Vslope with the reference voltage Vref. When the ramp signal Vslope is less than the reference voltage Vref, the spread spectrum clock signal is in an invalid state. When the ramp signal Vslope is greater than or equal to the reference voltage Vref, the spread spectrum clock signal jumps from the invalid state to the valid state. Set the switch S11 to be turned on for a certain time in response to the rising edge of the spread spectrum clock signal to reset the voltage of the capacitor C11. After the voltage of the capacitor C11 is reset, the switch S11 is turned off, and the modulation current Imod charges the capacitor C11 again. By setting appropriate modulation current Imod and reference voltage Vref, a clock signal of a desired frequency can be obtained. For example, the control end of switch S11 receives spread spectrum clock signal CK as a switch control signal.

[0052] In this embodiment, since the modulation current Imod is a pulse current with the same period as the modulation signal MOD, the spread spectrum clock signal CK generated by the current controlled oscillator 220 is composed of two clock signals with different frequencies, which correspond to the peak value and the valley value of the modulation current Imod respectively. However, the present invention is not limited to this. In the case where the input data received by the multiplexer 211 includes a plurality of modulation data Dmod, a spread spectrum clock signal CK composed of three or more clock signals with different frequencies can be generated.

[0053] Figure 5 Show Figure 2 The schematic circuit diagram of the second example of the current controlled oscillator in the clock modulation circuit is shown. The input terminal of the current controlled oscillator 230 receives the modulation current Imod, and the output terminal provides the spread spectrum clock signal CK.

[0054] The current controlled oscillator 230 includes a capacitor C11 , current sources IS11 and IS12 , switches S11 and S12 , comparators COMP1 and COMP2 , an RS flip-flop 11 , and an inverter 12 .

[0055] Current sources IS11 and IS12 generate replica currents of modulation current Imod, respectively. Current mirror IS12, switch S12, switch S11 and current source IS11 are connected in series between the power supply terminal and the ground in sequence. The first end of capacitor C11 is connected to the middle node of switches S11 and S12, and the second end is grounded. The control end of switch S11 receives the spread spectrum clock signal CK as a switch control signal, and the control end of switch S12 receives the inverted signal CKi of the spread spectrum clock signal CK as a switch control signal. In the effective state of the spread spectrum clock signal CK, switch S11 is turned off, switch S12 is closed, and current source IS12 charges capacitor C11. In the invalid state of the spread spectrum clock signal CK, switch S11 is closed, switch S12 is turned off, and capacitor C11 is discharged via current source IS11. The charging and discharging cycle of capacitor C11 is the same as the clock cycle of the spread spectrum clock signal CK. Since the clock period of the spread spectrum clock signal CK is much shorter than the signal period of the modulation signal MOD, the voltage on the capacitor C11 is a slope signal Vslope with a substantially equal rising slope and falling slope.

[0056] Comparators COMP1 and COMP2 form a window comparator, and the upper and lower limits of the voltage range of the window comparator are reference voltages Vref2 and Vref1, respectively. The window comparator compares the ramp signal Vslope with the reference voltages Vref2 and Vref1. The output terminals of comparators COMP1 and COMP2 are respectively connected to the reset terminal and the set terminal of the RS trigger 11. The RS trigger 11 is connected to the output terminal via an inverter 12. When the ramp signal Vslope is less than the reference voltage Vref1, the reset signal received by the RS trigger 11 is valid, and the spread spectrum clock signal is set to a valid state, thereby charging the capacitor C11. When the ramp signal Vslope is greater than or equal to the reference voltage Vref2, the set signal received by the RS trigger 11 is valid, and the spread spectrum clock signal is set to an invalid state, thereby discharging the capacitor C11. By setting appropriate modulation current Imod and reference voltages Vref1 and Vref2, a clock signal with a desired frequency and duty cycle can be obtained.

[0057] Figure 6 FIG. 3 is a schematic block diagram of a clock modulation circuit according to a second embodiment of the present invention. The clock modulation circuit 300 includes a current generator 310 and a current controlled oscillator 220 .

[0058] The current generator 310 includes a first current channel for generating a trimming current Itrim and a second current channel for generating a jittering current Ijitter.

[0059] The first current channel includes a current-type DAC 311. The current-type DAC 311 receives the trimming data Dtrim and converts the trimming data Dtrim into a trimming current Itrim. For example, after the chip of the clock modulation circuit is manufactured, the value of the trimming data Dtrim is determined according to the chip test results to correct the frequency fluctuation of the clock signal caused by the chip manufacturing process. After the chip leaves the factory, the trimming data Dtrim has been set to a fixed value unless the chip is trimmed again. The trimming data Dtrim is, for example, an M-bit binary number to generate a 2^M-level trimming current Itrim. In the present embodiment, M is equal to 2, for example, the trimming data Dtrim is a binary number 10. However, the present invention is not limited to this, and the trimming data Dtrim can be a binary number of any number of bits set according to chip design requirements and application requirements.

[0060] The second current channel includes a current-type DAC 312 and a modulation module 313. The current-type DAC 312 receives the jitter data Djitter and converts the jitter data Djitter into a reference current Iref. The jitter data Djitter is, for example, an N-bit binary number to generate a 2^N-level reference current Iref. In the present embodiment, N is equal to 2, for example, the jitter data Djitter is a binary number 10. However, the present invention is not limited thereto, and the jitter data Djitter can be a binary number of any number of bits set according to chip design requirements and application requirements. The modulation module 313 is connected to the current-type DAC 312 to convert the reference current Iref into the jitter current Ijitter.

[0061] The first current channel and the second current channel of the current generator 310 are coupled to a common node. Therefore, the modulation current Imod generated by the current generator 310 is a combined current of the trimming current Itrim and the jittering current Ijitter.

[0062] The current controlled oscillator 220 is connected to the current generator 310 and generates a standard clock signal CLK or a spread spectrum clock signal CK according to the modulation current Imod.

[0063] The current-mode DAC 311 , the current-mode DAC 312 , and the current-controlled oscillator 220 in the clock modulation circuit according to the second embodiment are completely identical to the corresponding circuit modules in the clock modulation circuit according to the first embodiment, and will not be described in detail herein.

[0064] When the frequency jittering function of the clock modulation circuit is disabled, the current generator 310 disables the second current channel, and at this time, the modulation module 313 always maintains the off state. The first current channel of the current generator 310 is always in an enabled state. The current-type DAC 311 in the current generator 310 converts the trimming data Dtrim into a trimming current Itrim of a predetermined value. After the chip of the clock modulation circuit is manufactured, the value of the trimming data Dtrim is determined according to the chip test results to correct the frequency fluctuation of the clock signal caused by the chip manufacturing process. After the chip leaves the factory, the trimming data Dtrim has been set to a predetermined value unless the chip is trimmed again. Therefore, the trimming current Itrim generated by the current-type DAC 311 is a fixed current corresponding to the trimming data Dtrim. At this time, the current-controlled oscillator 220 generates a standard clock signal CLK.

[0065] In the case of enabling the frequency jittering function of the clock modulation circuit, the current generator 310 enables the second current channel. At this time, the modulation module 313 is periodically in the on state and the off state, thereby modulating the reference current Iref to generate the jittering current Ijitter. At this time, the modulation current Imod is a pulse current with the same period as the modulation signal MOD, and its valley value is the difference between the trimming current Itrim and the jittering current Ijitter, and the peak value is the sum of the trimming current Itrim and the jittering current Ijitter. The trimming current Itrim and the jittering current Ijitter correspond to the trimming data Dtrim and the jittering data Djitter, respectively. At this time, the current-controlled oscillator 220 generates a spread spectrum clock signal CK composed of two clock signals of different frequencies. However, the present invention is not limited to this. In the case where multiple current-type DACs 311 generate multiple reference currents Iref according to the jittering data Djitter, a spread spectrum clock signal CK composed of three or more clock signals of different frequencies can be generated.

[0066] In this embodiment, the trimming data Dtrim and the jitter data Djitter are binary numbers 10, respectively. In one embodiment, the modulation module 313 in the current generator 310 performs 1:1 scaling on the reference current Iref, and the current-type DAC 311 and the current-type DAC 312 have different resolutions to achieve trimming current channels and jitter current channels of different precisions, wherein the resolution of the current-type DAC 312 is higher than the resolution of the current-type DAC 311, and is used to achieve a high-precision jitter current channel. In another embodiment, the modulation module 313 in the current generator 310 performs K:1 scaling on the reference current Iref to obtain a jitter current that is scaled down compared to the reference current Iref, and the current-type DAC 311 and the current-type DAC 312 have the same resolution, and the current generator 310 uses the scaled-down reference current Iref to achieve a high-precision jitter current channel. Therefore, compared with the trimming frequency accuracy of the standard clock signal, a high-precision frequency jump of the spread spectrum clock signal can be achieved, and overshoot or undershoot of the spread spectrum clock signal during frequency jump can be suppressed.

[0067] Figure 7 Show Figure 6 A schematic circuit diagram of a current generator in the clock modulation circuit shown.

[0068] In the figure, the current source DAC 311 and the current source DAC 312 in the current generator 300 are respectively represented as current sources. The current source DAC 311 is used to provide the trimming current Itrim corresponding to the trimming data Dtrim, and the current source DAC 312 is used to provide the reference current Iref corresponding to the jitter data Djitter.

[0069] The modulation module 313 includes a transistor M11 , transistors M21 and M22 that are complementary to each other, transistors M31 and M32 that are complementary to each other, and transistors M33 and M34 that are complementary to each other.

[0070] The transistor M11 and the current-type DAC 312 are connected in series between the power supply terminal and the ground, thereby receiving the reference current Iref generated by the current-type DAC 312. The transistors M22 and M21 are connected in series between the power supply terminal and the ground in sequence. The transistors M11 and M21 are connected to form a first current mirror, thereby mirroring the reference current Iref into an intermediate current.

[0071] Transistors M32, M34, M33 and M31 are connected in series between the power supply terminal and the ground. Among them, transistors M34 and M33 are respectively used as complementary switches, and the control signal is the modulation signal MOD. Transistor M32 is connected to transistor M22 to form a second current mirror, so that the intermediate current is mirrored into a sink current flowing into the common node. Transistor M31 is connected to transistor M11 to form a third current mirror, so that the reference current Iref is mirrored into a pull current flowing out of the common node. The modulation module 313 controls the switching state of transistors M34 and M33 according to the modulation signal MOD, thereby selectively coupling the reference current Iref into a sink current and a pull current of the common node to obtain a jitter current Ijitter.

[0072] In the modulation module 313, by selecting the mirror ratio of the first current mirror, the second current mirror and the third current mirror, the modulation module 313 performs K:1 scaling on the reference current Iref, and the jitter current Ijitter=1 / K*Iref. The modulation current Imod is the combined current of the trimming current Itrim and the jitter current Ijitter. The valley value of the modulation current Imod is Imod_min=Itrim-1 / K*Iref, and the peak value is Imod_max=Itrim+1 / K*Iref.

[0073] In a preferred embodiment, the scaling factor K of the modulation module 313 is greater than 1. Therefore, the modulation module 313 scales down the reference current Iref, which can improve the bit accuracy of the jitter current Ijitter relative to the trimming current Itrim.

[0074] In the above embodiment, the modulation module 313 selectively couples the reference current Iref into a sink current and a source current of the common node according to the modulation signal MOD to obtain the jitter current Ijitter.

[0075] In an alternative embodiment, transistors M31 and M33 may be omitted, and the modulation module 313 selectively couples the reference current Iref into a sink current and a zero current of the common node according to the modulation signal MOD. The valley value Imod_min of the modulation current Imod is Imod_min=Itrim, and the peak value Imod_max=Itrim+1 / K*Iref.

[0076] In another alternative embodiment, transistors M32 and M34 can be omitted, and the modulation module 313 selectively couples the reference current Iref into a source current and a zero current of the common node according to the modulation signal MOD. The valley value of the modulation current Imod is Imod_min=Itrim-1 / K*Iref, and the peak value is Imod_max=Itrim.

[0077] Figure 8A flow chart of a clock modulation method according to a third embodiment of the present invention is shown. Figure 2 and Figure 6 The clock modulation circuit shown is used to generate a combined modulation current based on the trimming data and the jitter data to achieve a high-precision frequency jump of the spread spectrum clock signal.

[0078] In step S01, a current generator is used to generate a trimming current of a predetermined value and a modulation current that varies with time, wherein the jitter current accuracy of the modulation current is higher than the trimming current accuracy of the trimming current.

[0079] In one embodiment, the step of generating a trimmed current of a predetermined value and a modulated current that varies with time includes: periodically selecting trimmed data and modulated data according to a modulation signal; and providing the trimmed data and modulated data to a current-controlled oscillator to generate the modulated current. For example, the high-significant bit of the trimmed data is the effective adjustment data, and the low-significant bit of the modulated data is the effective adjustment data, so that the high-weight current channel and the low-weight current channel of the current-type digital-to-analog converter serve as the trimmed current channel and the jitter current channel, respectively.

[0080] In another embodiment, the step of generating a trimming current of a predetermined value and a modulation current that varies with time includes: generating a trimming current and a jittering current respectively according to trimming data and jittering data, wherein the modulation current is a combined current of the trimming current and the jittering current. For example, current-type digital-to-analog converters with different bit precisions are used to generate the trimming current and the jittering current respectively, so that the bit precision of the jittering current is higher than the bit precision of the trimming current.

[0081] In yet another embodiment, the steps of generating a trimming current of a predetermined value and a modulation current that varies with time include: using a current-type digital-to-analog converter to generate a reference current; and using current mirrors with different mirror ratios to mirror the reference current into the trimming current and the jitter current, respectively, wherein the current mirror reduces the ratio of the reference current, thereby improving the bit accuracy of the jitter current relative to the trimming current.

[0082] In step S02, a standard clock signal and a spread spectrum clock signal are generated according to the trimmed current and the modulated current respectively.

[0083] Fig. 9 Schematic waveform diagrams of spread spectrum clock signals of a clock modulation circuit according to the prior art and a clock modulation circuit according to an embodiment of the present invention are shown.

[0084] In the clock modulation circuit according to the prior art, the trimming data is directly modified on the trimming terminal of the analog oscillator to generate a jitter current that varies with time to generate a spread spectrum clock signal CK. Referring to the curve FREQ_coarse in the figure, the modulation of the trimming data may cause an overshoot or undershoot of the clock frequency, making it difficult to obtain a desired spread spectrum clock signal.

[0085] In the clock modulation circuit according to the embodiment of the present invention, in the analog oscillator, the jitter current channel and the trimming channel are independent of each other, and a high-precision jitter current channel relative to the trimming current channel is used to achieve a high-precision frequency jump of the spread spectrum clock signal. Referring to the curve FREQ_fine in the figure, in the jitter mode of the clock modulation circuit, the change in clock frequency achieved by using the independent jitter current channel is smaller than the change in clock frequency achieved by using the trimming current channel, and the overshoot or undershoot of the spread spectrum clock signal during the frequency jump can be suppressed.

[0086] See also Fig.10 , which shows the measured waveform of the spread spectrum clock signal of the clock modulation circuit according to the embodiment of the present invention. It can be seen that the frequency overshoot or undershoot of the spread spectrum clock signal of the clock modulation circuit is directly related to the change in the clock frequency. As the attached jitter current increases, the frequency change of the spread spectrum clock signal of the clock modulation circuit increases, and the frequency overshoot or undershoot of the spread spectrum clock signal increases. The frequency overshoot or undershoot of the spread spectrum clock signal is directly related to the frequency change. The clock modulation circuit of the embodiment of the present invention adopts a high-precision jitter current channel to achieve a high-precision frequency change relative to the standard clock frequency on the basis of the standard clock frequency, thereby significantly suppressing the overshoot or undershoot of the spread spectrum clock signal during the frequency jump.

[0087] The above-described implementation methods do not constitute a limitation on the protection scope of the technical solution. Any modification, equivalent replacement and improvement made within the spirit and principle of the above-described implementation methods shall be included in the protection scope of the technical solution.

Claims

1. A clock modulation circuit, comprising: a current generator for generating a trimming current of a predetermined value and a modulation current varying with time, and a current-controlled oscillator, for generating a standard clock signal and a spread-spectrum clock signal according to the trimming current and the modulation current, respectively; Wherein, the jitter current accuracy of the modulation current is higher than the trimming current accuracy of the trimming current.

2. The clock modulation circuit according to claim 1, wherein: The current generator comprises a current type digital-to-analog converter, which is used for converting the trimming data into the trimming current, and converting the trimming data and the modulation data into the valley value and the peak value of the modulation current respectively.

3. The clock modulation circuit according to claim 2, further comprising: A multiplexer is connected to the current-type digital-to-analog converter, and is used for periodically selecting the trimming data and the modulation data according to a modulation signal, and providing the trimming data and the modulation data to the current-controlled oscillator to generate the modulation current.

4. The clock modulation circuit according to claim 2, wherein: The high significant bits of the trimming data are effective adjustment data, and the low significant bits of the modulation data are effective adjustment data, so that the high weight current channel and the low weight current channel of the current-type digital-to-analog converter serve as the trimming current channel and the jitter current channel respectively.

5. The clock modulation circuit according to claim 1, wherein: The current generator includes a first current channel and a second current channel, which are respectively used to provide the trimming current and the jittering current. The first current channel and the second current channel are coupled to a common node to obtain the modulation current, and the modulation current is a combined current of the trimming current and the jittering current.

6. The clock modulation circuit according to claim 5, wherein: The first current channel includes a first current-type digital-to-analog converter, and the first current-type digital-to-analog converter performs digital-to-analog conversion on the trimming data to generate the trimming current.

7. The clock modulation circuit according to claim 6, wherein: The second current channel comprises: a second current-type digital-to-analog converter, which performs digital-to-analog conversion on the modulation data to generate a reference current; and The modulation module is used to convert the reference current into a jitter current that varies with time.

8. The clock modulation circuit according to claim 7, wherein: The modulation module selectively couples the reference current into one of a sinking current, a sourcing current, and a zero current of the common node to obtain the jittering current.

9. The clock modulation circuit according to claim 8, wherein: The modulation module comprises: A first transistor and a second transistor are coupled to each other to form a first current mirror; A third transistor and a fourth transistor are coupled to each other to form a second current mirror; and First switch, The first transistor is coupled in series with the second current-type digital-to-analog converter, the second transistor is coupled in series with the third transistor, and the first switch is coupled between the fourth transistor and the common node, thereby mirroring the reference current into a sink current or zero current flowing into the common node.

10. The clock modulation circuit according to claim 9, wherein: The modulation module also includes: a fifth transistor coupled with the first transistor to form a third current mirror; and The second switch, The second switch is coupled between the common node of the fifth transistor, so as to mirror the reference current into a source current or a zero current flowing out of the common node.

11. The clock modulation circuit according to claim 7, wherein: The bit weight of the second current-mode digital-to-analog converter is smaller than the bit weight of the first current-mode digital-to-analog converter, thereby improving the bit accuracy of the jitter current relative to the trimming current.

12. The clock modulation circuit according to claim 7 or 8, wherein: The modulation module scales down the reference current to improve the bit accuracy of the jitter current relative to the trimmed current.

13. The clock modulation circuit according to claim 1, wherein: The current controlled oscillator comprises: The third switch; a capacitor connected in parallel with the third switch, wherein the modulation current is used to charge the capacitor during an off period of the third switch to generate a ramp signal; and a control module, configured to generate the spread spectrum clock signal according to a comparison result between the ramp signal and a reference voltage, The third switch is turned on for a certain period of time in response to the rising edge of the spread spectrum clock signal to reset the voltage of the capacitor, and the third switch is turned off after the voltage of the capacitor is reset.

14. The clock modulation circuit according to claim 1, wherein: The current controlled oscillator comprises: A first current source and a second current source, used to generate a first current and a second current corresponding to the modulation current, respectively; a fourth switch and a fifth switch connected in series between the first current source and the second current source; a capacitor coupled to an intermediate node between the fourth switch and the fifth switch, charged with the first current and discharged with the second current, thereby generating a ramp signal; and a trigger, configured to generate the spread spectrum clock signal according to a comparison result between the ramp signal and a reference voltage, Wherein, in the valid state of the spread spectrum clock signal, the fourth switch is turned on and the fifth switch is turned off, and in the invalid state of the spread spectrum clock signal, the fourth switch is turned off and the fifth switch is turned on, so that the capacitor is alternately charged and discharged in the clock cycle of the spread spectrum clock signal.

15. A clock modulation method, comprising: A current generator is used to generate a trimming current of a predetermined value and a modulation current that varies with time; as well as generating a standard clock signal and a spread spectrum clock signal according to the trimming current and the modulation current, respectively; Wherein, the jitter current accuracy of the modulation current is higher than the trimming current accuracy of the trimming current.

16. The clock modulation method according to claim 15, wherein: The steps of generating a trimmed current of a predetermined value and a modulation current varying with time include: periodically selecting the trimming data and the modulation data according to the modulation signal; and The trimming data and the modulation data are provided to a current controlled oscillator to generate the modulation current.

17. The clock modulation method according to claim 15, wherein: The steps of generating a trimmed current of a predetermined value and a modulation current varying with time include: Generate trimming current and jitter current according to trimming data and jitter data respectively. The modulation current is a combined current of the trimming current and the jitter current.

Images