Load impedance adjusting circuit and radio frequency chip

Abstract

The invention is suitable for the technical field of wireless communication, and particularly relates to a load impedance adjusting circuit and a radio frequency chip. The load impedance adjusting circuit comprises a power amplifier, a load mismatch detection circuit, an adjustable output matching circuit and a directional coupler; the load mismatch detection circuit is used for detecting a coupling end voltage of the directional coupler and an isolation end voltage of the directional coupler in real time, calculating a reflection coefficient of load impedance of the power amplifier according to the coupling end voltage and the isolation end voltage, and judging whether a phase in the reflection coefficient exceeds a preset linearity range or not; if yes, the load mismatch detection circuit outputs a control signal to the adjustable output matching circuit, and the adjustable output matching circuit performs impedance adjustment on the power amplifier according to the control signal. According to the invention, the phase with poor linearity in the reflection coefficient can be adjusted in a targeted manner, so that the sensitivity of the performance of the power amplifier along with the change of load impedance is reduced, and the efficiency of the power amplifier is effectively improved.

Description

Technical Field

[0001] The present invention is applicable to the field of wireless communication technology, and in particular relates to a load impedance adjustment circuit and a radio frequency chip. Background Art

[0002] A power amplifier (PA) is an electronic device used to amplify the power of an input signal to drive a load such as a speaker or antenna.

[0003] Since the linearity of the power amplifier is sensitive to the load impedance, when the load is mismatched, the linearity of the phase of some rear-end reflection coefficients of the power amplifier will improve, while the linearity of some phases will deteriorate. In order to solve the problem of load mismatch, the power amplifier in the prior art mainly uses two methods to ensure that the linearity of the worst performance phase can meet the communication index: the first method is to increase the 50 ohm margin of the load value, leaving enough room for the linearity deterioration of the power amplifier when the load is mismatched, thereby ensuring that the worst performance phase in the power amplifier can meet the index, so that the phase margin of the improved linearity will be further increased. However, for the power amplifier, linearity and current are two contradictory indicators, which will cause the current of the power amplifier to further increase, affecting the battery life and performance of the power amplifier. The second method is to use the output signal of the power amplifier and the reverse signal reflected by the load to the directional coupler as the adjustment coefficient, and adjust the impedance of the power amplifier according to the adjustment coefficient. However, this method does not consider the impact of different phases on the performance of the power amplifier, and only makes uniform adjustments to all phases, and only adjusts after the load impedance at the back end of the power amplifier circuit is mismatched. It cannot always keep the linearity of the power amplifier within the communication indicators, cannot reduce the sensitivity of the linearity of the power amplifier to the load impedance, and has limited effect on improving the linearity of the power amplifier.

[0004] Therefore, there is an urgent need for a new load impedance adjustment circuit and radio frequency chip to solve the above technical problems. Summary of the invention

[0005] The present invention provides a load impedance adjustment circuit and a radio frequency chip, aiming to reduce the sensitivity of a power amplifier to load impedance and improve the efficiency of the power amplifier.

[0006] In a first aspect, the present invention provides a load impedance adjustment circuit, the load impedance adjustment circuit comprising a power amplifier, a load mismatch detection circuit, an adjustable output matching circuit and a directional coupler; The input end of the power amplifier serves as the input end of the load impedance adjustment circuit, and is used to receive an input signal. The output end of the power amplifier is connected to the first input end of the adjustable output matching circuit. The first input end of the load mismatch detection circuit and the second input end of the load mismatch detection circuit are respectively connected to the coupling end of the directional coupler and the isolation end of the directional coupler, and the output end of the load mismatch detection circuit is connected to the second input end of the adjustable output matching circuit; The output end of the adjustable output matching circuit is connected to the input end of the directional coupler, and the adjustable output matching circuit is used to adjust the load impedance of the power amplifier; The output end of the directional coupler is used as the output end of the load impedance adjustment circuit to connect to the back-end components; The load mismatch detection circuit is used to detect the coupling terminal voltage of the directional coupler and the isolation terminal voltage of the directional coupler in real time, and calculate the reflection coefficient of the load impedance of the power amplifier according to the coupling terminal voltage and the isolation terminal voltage, and judge whether the phase in the reflection coefficient exceeds the preset linearity range: if so, the load mismatch detection circuit outputs a control signal to the adjustable output matching circuit, and the adjustable output matching circuit adjusts the impedance of the power amplifier according to the control signal to adjust the phase of the reflection coefficient that exceeds the preset linearity range to within the preset linearity range.

[0007] Preferably, the adjustable output matching circuit includes a transformer, a first inductor, a first capacitor, a second inductor, a second capacitor and a first switch; the input end of the transformer serves as the first input end of the adjustable output matching circuit, the output end of the transformer is connected to the first end of the first inductor, the second end of the first inductor is connected to the first end of the second inductor, the first end of the first capacitor is connected to the second end of the first inductor, the second end of the first capacitor is grounded, the second end of the second inductor serves as the output end of the adjustable output matching circuit, the first end of the second capacitor is connected to the second end of the second inductor, the second end of the second capacitor is connected to the control end of the first switch, and the output end of the first switch is grounded.

[0008] Preferably, the load mismatch detection circuit comprises an amplitude detection unit and a phase detection unit; the first input end of the amplitude detection unit and the first input end of the phase detection unit are connected and used together as the first input end of the load mismatch detection circuit, the second input end of the amplitude detection unit and the second input end of the phase detection unit are connected and used together as the second input end of the load mismatch detection circuit, and the output end of the amplitude detection unit and the output end of the phase detection unit are connected and used together as the output end of the load mismatch detection circuit; the amplitude detection unit is used to detect the amplitude of the load impedance of the power amplifier, and the phase detection unit is used to detect the phase of the load impedance of the power amplifier; The amplitude detection unit includes a first adjustable attenuation network, a second adjustable attenuation network, a first power detection circuit, a second power detection circuit and a first voltage conversion circuit; the input end of the first adjustable attenuation network serves as the first input end of the amplitude detection unit, and the input end of the second adjustable attenuation network serves as the second input end of the amplitude detection unit; the output end of the first adjustable attenuation network is connected to the input end of the first power detection circuit, and the output end of the second adjustable attenuation network is connected to the input end of the second power detection circuit; the output end of the first power detection circuit is connected to the first input end of the first voltage conversion circuit, and the output end of the second power detection circuit is connected to the second input end of the first voltage conversion circuit; the output end of the first voltage conversion circuit serves as the output end of the amplitude detection unit; The phase detection unit includes a third adjustable attenuation network, a fourth adjustable attenuation network, a third power detection circuit, a fourth power detection circuit and a second voltage conversion circuit; the input end of the third adjustable attenuation network serves as the first input end of the phase detection unit, and the input end of the fourth adjustable attenuation network serves as the second input end of the phase detection unit; the output end of the third adjustable attenuation network is connected to the input end of the third power detection circuit, and the output end of the fourth adjustable attenuation network is connected to the input end of the fourth power detection circuit; the output end of the third power detection circuit is connected to the first input end of the second voltage conversion circuit, and the output end of the fourth power detection circuit is connected to the second input end of the second voltage conversion circuit; the output end of the second voltage conversion circuit serves as the output end of the phase detection unit.

[0009] Preferably, the circuit structures of the first power detection circuit, the second power detection circuit, the third power detection circuit and the fourth power detection circuit are the same; the first power detection circuit comprises a third capacitor, a fourth capacitor, a fifth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first transistor, a second transistor and a third transistor; The first end of the third capacitor serves as the input end of the first power detection circuit, the second end of the third capacitor is respectively connected to the first end of the first resistor, the first end of the second resistor and the collector of the first transistor, the second end of the first resistor is connected to the first external power supply voltage, the second end of the second resistor and the base of the first transistor are respectively connected to the first end of the third resistor, the emitter of the first transistor is grounded, and the second end of the third resistor is connected to the base of the second transistor, the first end of the fourth capacitor is connected to the second end of the third resistor, the second end of the fourth capacitor is grounded, the emitter of the second transistor is grounded, the collector of the second transistor is respectively connected to the first end of the fourth resistor and the base of the third transistor, the second end of the fourth resistor is connected to the first external power supply voltage, the collector of the third transistor is connected to the second external power supply voltage, and the emitter of the third transistor serves as the output end of the first power detection circuit, the first end of the fifth resistor and the first end of the fifth capacitor are respectively connected to the emitter of the third transistor, and the second end of the fifth resistor and the second end of the fifth capacitor are connected to each other and then grounded.

[0010] Preferably, the first voltage conversion circuit includes a first voltage-to-current circuit, a second voltage-to-current circuit, a first amplifier circuit, and a first current comparison circuit; The input end of the first voltage-to-current circuit serves as the first input end of the first voltage conversion circuit, the first output end of the first voltage-to-current circuit is connected to the first input end of the first current comparison circuit, and the second output end of the first voltage-to-current circuit is connected to the second input end of the first current comparison circuit; the input end of the second voltage-to-current circuit serves as the second input end of the first voltage conversion circuit, the first output end of the second voltage-to-current circuit is connected to the first input end of the first amplifier circuit, and the second output end of the second voltage-to-current circuit is connected to the second input end of the first amplifier circuit; the output end of the first amplifier circuit is connected to the third input end of the first current comparison circuit; the output end of the first current comparison circuit serves as the output end of the first voltage conversion circuit; The first voltage-to-current circuit includes a first operational amplifier, a first MOS tube and a sixth resistor; the negative input terminal of the first operational amplifier serves as the input terminal of the first voltage-to-current circuit, the positive input terminal of the first operational amplifier is respectively connected to the drain of the first MOS tube and the first terminal of the sixth resistor, the second terminal of the sixth resistor is grounded, the output terminal of the first operational amplifier is connected to the gate of the first MOS tube, the output terminal of the first operational amplifier serves as the first output terminal of the first voltage-to-current circuit, the source of the first MOS tube is used to connect to the second external power supply voltage, and the source of the first MOS tube serves as the second output terminal of the first voltage-to-current circuit; The second voltage-to-current circuit includes a second operational amplifier, a second MOS tube and a seventh resistor; the negative input terminal of the second operational amplifier serves as the input terminal of the second voltage-to-current circuit, the positive input terminal of the second operational amplifier is respectively connected to the drain of the second MOS tube and the first end of the seventh resistor, the second end of the seventh resistor is connected, the output terminal of the second operational amplifier is connected to the gate of the second MOS tube, the output terminal of the second operational amplifier serves as the first output terminal of the second voltage-to-current circuit, the source of the second MOS tube is used to connect the second external power supply voltage, and the source of the second MOS tube serves as the second output terminal of the second voltage-to-current circuit; The first amplifier circuit includes a third MOS tube and a fourth MOS tube; the gate of the third MOS tube serves as the first input end of the first amplifier circuit, the source of the third MOS tube serves as the second input end of the first amplifier circuit, the source of the third MOS tube is used to connect to the second external power supply voltage, the drain of the third MOS tube is respectively connected to the drain of the fourth MOS tube and the gate of the fourth MOS tube, the source of the fourth MOS tube is grounded, and the gate of the fourth MOS tube serves as the output end of the first amplifier circuit; The first current comparison circuit includes a fifth MOS tube, a sixth MOS tube, a first inverter and a second inverter; the gate of the fifth MOS tube serves as the first input end of the first current comparison circuit, the source of the fifth MOS tube serves as the second input end of the first current comparison circuit, the source of the fifth MOS tube is used to connect the second external power supply voltage, and the drain of the fifth MOS tube is connected to the input end of the first inverter; the gate of the sixth MOS tube serves as the third input end of the first current comparison circuit, the source of the sixth MOS tube is grounded, the drain of the sixth MOS tube is connected to the input end of the first inverter, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter serves as the output end of the first current comparison circuit.

[0011] Preferably, the second voltage conversion circuit includes a third voltage-to-current circuit, a fourth voltage-to-current circuit, a second amplification circuit, a current subtraction circuit, and a second current comparison circuit; The input end of the third voltage-to-current circuit serves as the first input end of the second voltage conversion circuit, the first output end of the third voltage-to-current circuit is connected to the first input end of the current subtraction circuit, and the second output end of the third voltage-to-current circuit is connected to the second input end of the current subtraction circuit; the input end of the fourth voltage-to-current circuit serves as the second input end of the second voltage conversion circuit, the first output end of the fourth voltage-to-current circuit is connected to the first input end of the second amplifier circuit, and the second output end of the fourth voltage-to-current circuit is connected to the second input end of the second amplifier circuit; the output end of the second amplifier circuit is connected to the third input end of the current subtraction circuit, the output end of the current subtraction circuit is connected to the input end of the second current comparison circuit, and the output end of the second current comparison circuit serves as the output end of the second voltage conversion circuit; The third voltage-to-current circuit includes a third operational amplifier, a seventh MOS tube and an eighth resistor; the negative input terminal of the third operational amplifier serves as the input terminal of the third voltage-to-current circuit, the positive input terminal of the third operational amplifier is respectively connected to the drain of the seventh MOS tube and the first terminal of the eighth resistor, the second terminal of the eighth resistor is grounded, the output terminal of the third operational amplifier is connected to the gate of the seventh MOS tube, the output terminal of the third operational amplifier serves as the first output terminal of the third voltage-to-current circuit, the source terminal of the seventh MOS tube serves as the second output terminal of the third voltage-to-current circuit, and the source terminal of the seventh MOS tube is used to connect to the second external power supply voltage; The fourth voltage-to-current circuit includes a fourth operational amplifier, an eighth MOS tube and a ninth resistor; the negative input terminal of the fourth operational amplifier serves as the input terminal of the fourth voltage-to-current circuit, the positive input terminal of the fourth operational amplifier is respectively connected to the drain of the eighth MOS tube and the first terminal of the ninth resistor, the second terminal of the ninth resistor is grounded, the output terminal of the fourth operational amplifier is connected to the gate of the eighth MOS tube, the output terminal of the fourth operational amplifier serves as the first output terminal of the fourth voltage-to-current circuit, the source terminal of the eighth MOS tube serves as the second output terminal of the fourth voltage-to-current circuit, and the source terminal of the eighth MOS tube is used to connect to the second external power supply voltage; The second amplifier circuit includes a ninth MOS tube and a tenth MOS tube; the gate of the ninth MOS tube serves as the first input end of the second amplifier circuit, the source of the ninth MOS tube serves as the second input end of the second amplifier circuit, the source of the ninth MOS tube is used to connect to a second external power supply voltage, the drain of the ninth MOS tube is respectively connected to the drain of the tenth MOS tube and the gate of the tenth MOS tube, the source of the tenth MOS tube is grounded, and the gate of the tenth MOS tube serves as the output end of the second amplifier circuit; The current subtraction circuit includes an eleventh MOS tube, a twelfth MOS tube and a thirteenth MOS tube; the gate of the eleventh MOS tube serves as the first input end of the current subtraction circuit, the source of the eleventh MOS tube serves as the second input end of the current subtraction circuit, the source of the eleventh MOS tube is used to connect to the second external power supply voltage, and the drain of the eleventh MOS tube is connected to the drain of the twelfth MOS tube; the gate of the twelfth MOS tube serves as the third input end of the current subtraction circuit, the source of the twelfth MOS tube is grounded, the drain of the twelfth MOS tube is respectively connected to the drain of the thirteenth MOS tube and the gate of the thirteenth MOS tube, the source of the thirteenth MOS tube is grounded, and the gate of the thirteenth MOS tube serves as the output end of the current subtraction circuit; The second current comparison circuit includes a current source, a fourteenth MOS tube, a third inverter and a fourth inverter; the input end of the current source is used to connect to the second external power supply voltage, and the output end of the current source is connected to the input end of the third inverter; the gate of the fourteenth MOS tube serves as the input end of the second current comparison circuit, the source of the fourteenth MOS tube is grounded, the drain of the fourteenth MOS tube is connected to the input end of the third inverter, the output end of the third inverter is connected to the input end of the fourth inverter, and the output end of the fourth inverter serves as the output end of the second current comparator circuit.

[0012] Preferably, the coupling terminal voltage is defined as Vcpl, the isolation terminal voltage is defined as Viso, and the reflection coefficient is defined as ΓL. The coupling terminal voltage and the isolation terminal voltage are combined to calculate the reflection coefficient according to the following rule: .

[0013] Preferably, the preset linearity range is less than -33dBc.

[0014] Preferably, the back-end component is a filter device.

[0015] In a second aspect, the present invention further provides a radio frequency chip, wherein the radio frequency chip comprises the load impedance adjustment circuit as described in any one of the above embodiments.

[0016] Compared with the prior art, the present invention detects the coupling terminal voltage of the directional coupler and the isolation terminal voltage of the directional coupler in real time through a load mismatch detection circuit, and calculates the reflection coefficient of the load impedance of the power amplifier according to the coupling terminal voltage and the isolation terminal voltage, and determines whether the phase in the reflection coefficient exceeds the preset linearity range; if so, the load mismatch detection circuit outputs a control signal to the adjustable output matching circuit, and the adjustable output matching circuit adjusts the impedance of the power amplifier according to the control signal, so as to adjust the phase of the reflection coefficient that exceeds the preset linearity range to within the preset linearity range. In this way, the present invention can specifically adjust the phase of the linearity difference in the reflection coefficient, thereby reducing the sensitivity of the power amplifier performance to changes in load impedance and effectively improving the efficiency of the power amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present invention will be described in detail below in conjunction with the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made in conjunction with the following drawings. In the accompanying drawings: Figure 1 is a circuit structure diagram of a load impedance adjustment circuit provided by an embodiment of the present invention; Figure 2 is a comparison diagram of simulation results of a power amplifier that performs load impedance adjustment in a load impedance adjustment circuit provided in an embodiment of the present invention and does not perform load impedance adjustment in a related art; Figure 3 is a Smith chart of the load impedance adjustment circuit provided by an embodiment of the present invention; Figure 4 1 is a schematic diagram of the load impedance adjustment principle of the load impedance adjustment circuit provided by an embodiment of the present invention; Figure 5 It is a schematic diagram of the load impedance adjustment principle of a power amplifier in the related art; Figure 6 It is a circuit structure schematic diagram of an adjustable output matching circuit of a load impedance adjustment circuit provided in an embodiment of the present invention; Figure 7 It is a circuit structure schematic diagram of an amplitude detection unit of a load mismatch detection circuit of a load impedance adjustment circuit provided by an embodiment of the present invention; Figure 8 1 is a circuit structure diagram of a phase detection unit of a load mismatch detection circuit of a load impedance adjustment circuit provided in an embodiment of the present invention; Fig. 9 is a circuit structure diagram of a first power detection circuit of a load impedance adjustment circuit provided in an embodiment of the present invention; Fig.10 is a circuit structure diagram of a first voltage conversion circuit of a load impedance adjustment circuit provided in an embodiment of the present invention; Fig.11 It is a circuit structure schematic diagram of a second voltage conversion circuit of a load impedance adjustment circuit provided in an embodiment of the present invention.

[0018] In the figure, 100, load impedance adjustment circuit, 1, power amplifier, 2, adjustable output matching circuit, 3, load mismatch detection circuit, 31, amplitude detection unit, 311, first adjustable attenuation network, 312, first power detection circuit, 313, second adjustable attenuation network, 314, second power detection circuit, 315, first voltage conversion circuit, 3151, first voltage to current circuit, 3152, second voltage to current circuit, 3153, first amplifier circuit, 3154, first current comparison circuit, 32, phase detection unit, 321, third adjustable attenuation network, 322, third power detection circuit, 323, fourth adjustable attenuation network, 324, fourth power detection circuit, 325, second voltage conversion circuit, 3251, third voltage to current circuit, 3252, fourth voltage to current circuit, 3253, second amplifier circuit, 3254, current subtraction circuit, 3255, second current comparison circuit, 4, directional coupler, 5, back-end element. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0020] Embodiment 1 Please refer to Figure 1 , Figure 1 The present invention provides a load impedance adjustment circuit 100, which includes a power amplifier 1, a load mismatch detection circuit 3, an adjustable output matching circuit 2 and a directional coupler 4.

[0021] The input end of the power amplifier 1 serves as the input end of the load impedance adjustment circuit 100 for receiving an input signal, and the output end of the power amplifier 1 is connected to the first input end of the adjustable output matching circuit 2 .

[0022] The first input end of the load mismatch detection circuit 3 and the second input end of the load mismatch detection circuit 3 are respectively connected to the coupling end of the directional coupler 4 and the isolation end of the directional coupler 4 , and the output end of the load mismatch detection circuit 3 is connected to the second input end of the adjustable output matching circuit 2 .

[0023] The output end of the adjustable output matching circuit 2 is connected to the input end of the directional coupler 4 , and the adjustable output matching circuit 2 is used to adjust the load impedance of the power amplifier 1 .

[0024] The output end of the directional coupler 4 serves as the output end of the load impedance adjustment circuit 100 and is used to connect to the back-end element 5 .

[0025] The load mismatch detection circuit 3 is used to detect the coupling end voltage of the directional coupler 4 and the isolation end voltage of the directional coupler 4 in real time, and calculate the reflection coefficient of the load impedance of the power amplifier 1 according to the coupling end voltage and the isolation end voltage, and judge whether the phase in the reflection coefficient exceeds the preset linearity range: if so, the load mismatch detection circuit 3 outputs a control signal to the adjustable output matching circuit 2, and the adjustable output matching circuit 2 adjusts the impedance of the power amplifier 1 according to the control signal, so as to adjust the phase of the reflection coefficient that exceeds the preset linearity range to within the preset linearity range.

[0026] Specifically, the reflection coefficient corresponding to the load impedance is detected by the load mismatch detection circuit 3, and a control signal is output to the adjustable output matching circuit 2, and the impedance is adjusted by the adjustable output matching circuit 2, so that the phase of the reflection coefficient can always be kept within the preset linearity range, effectively reducing the sensitivity of the linearity of the power amplifier 1 to the load impedance, and greatly improving the efficiency of the power amplifier 1. In the embodiment of the present invention, the coupling terminal voltage is defined as Vcpl, the isolation terminal voltage is defined as Viso, and the reflection coefficient is defined as ΓL. The coupling terminal voltage and the isolation terminal voltage are combined to calculate the reflection coefficient according to the following rule: .

[0027] Specifically, since the reflection coefficient satisfies ΓL=V- / V+, V+ and V- respectively represent the voltage of the incident wave and the voltage of the reflected wave transmitted to the load. For the directional coupler 4, its coupling end voltage satisfies Vcpl=C*V+, and the isolation end voltage satisfies Viso=C*V-, where C is the coupling coefficient of the directional coupler 4. Therefore, the reflection coefficient can be characterized by the signals at the isolation end of the directional coupler 4 and the coupling end of the directional coupler 4.

[0028] In the embodiment of the present invention, the preset linearity range is less than -33dBc. It should be noted that the preset linearity range can be set according to actual conditions and is not limited to -33dBc, and other values ​​are also feasible.

[0029] For details, please refer to Figure 2, is a comparison diagram of simulation results of a power amplifier that performs load impedance adjustment in a load impedance adjustment circuit provided in an embodiment of the present invention and does not perform load impedance adjustment in a related art. Figure 2 The figure shows a comparison of the simulation results of the power amplifier that does not perform load impedance adjustment using the load impedance adjustment circuit 100 provided by the present invention when the voltage standing wave ratio (VSWR) is 2:1 and the phase changes from 0 to 360°. As can be seen from the figure, when the load impedance is adjusted by the load impedance adjustment circuit 100 provided by the present invention, it can be seen that when the phase is in the 0°-180° region, its linearity, i.e., the adjacent channel power ratio (ACPR), is improved by 7dB, while when the power amplifier in the related art does not perform load impedance adjustment, its phase is in the 0°-180° region and obviously exceeds the preset linearity range. It can be seen that the load impedance adjustment circuit 100 proposed by the present invention can significantly improve the sensitivity of the power amplifier 1 to the load impedance, and effectively improve the efficiency of the power amplifier 1.

[0030] Please refer to Figure 3 , Figure 3 is a Smith chart of the load impedance adjustment circuit provided by the embodiment of the present invention. Figure 3 It can be seen that the performance of the power amplifier 1 will change significantly with the phase when the reflection coefficient is equal. On the circle of equal reflection coefficient, the adjacent channel leakage ratio (ACLR) and the current consumption (ICC) (where the smaller the ACLR value, the larger the ICC value) will change. The present invention can adjust the linearity of different phases when the reflection coefficient modulus is equal. The principle is as follows Figure 4 As shown, Figure 4 It is a schematic diagram of the load impedance adjustment principle of the load impedance adjustment circuit provided in an embodiment of the present invention. Figure 4 Region 1, region 2 and region 3 are marked (the range and size of each region and the number of regions are only for illustration purposes). The reflection coefficients of the outer rings formed by region 2 and region 3 are equal, but the performance of the power amplifier 1 is quite different in the two regions. For example, the performance of the power amplifier 1 in region 2 is better than that in region 3, and the linearity of the power amplifier 1 in region 3 does not meet the preset linearity range (region 3 can be understood as Figure 2 As shown in the figure, the phase in the 0°-180° region exceeds -33dBc), that is, the phase in region 3 belongs to the phase with poor linearity, and impedance adjustment is required to adjust the phase in region 3 to region 1. In the related art, as Figure 5 As shown, Figure 5This is a schematic diagram of the load impedance adjustment principle of the power amplifier in the related art. When performing impedance adjustment, it is necessary to Figure 5 The middle and outer circles (i.e. Figure 5 The large circle formed by the dots in Figure 5 The value of the reflection coefficient represented by the node m1 in the figure, which represents the reflection coefficient S(1,1)=0.67 / 1.80E2 and the impedance impedance=10.00+j2.94E-15, is adjusted to the inner circle (i.e. Figure 5 The small circles made up of dots, such as Figure 5 Point m2 in the figure represents a node with a reflection coefficient of S(1,1)=0.33 / 1.80E2 and an impedance of 24.96+j2.94E-15). This requires adjusting each phase at the same time, but this method cannot effectively distinguish between a phase with poor linearity and a phase with good linearity. The method proposed in the present invention can perform targeted adjustment on the phase with poor linearity in the power amplifier 1, and its adjustment effect is better.

[0031] In the embodiment of the present invention, the back-end component 5 is a filter device. The output end of the back-end component 5 is connected to the antenna, and the load impedance of the power amplifier 1 will change as the position of the antenna changes.

[0032] In the embodiment of the present invention, please refer to Figure 6 , Figure 6 1 is a schematic diagram of the circuit structure of the adjustable output matching circuit of the load impedance adjustment circuit provided by an embodiment of the present invention. The adjustable output matching circuit 2 includes a transformer Transfomer, a first inductor L1, a first capacitor C1, a second inductor L2, a second capacitor C2 and a first switch SW; the input end of the transformer Transfomer serves as the first input end of the adjustable output matching circuit 2, the output end of the transformer Transfomer is connected to the first end of the first inductor L1, the second end of the first inductor L1 is connected to the first end of the second inductor L2, the first end of the first capacitor C1 is connected to the second end of the first inductor L1, the second end of the first capacitor C1 is grounded, the second end of the second inductor L2 serves as the output end of the adjustable output matching circuit 2, the first end of the second capacitor C2 is connected to the second end of the second inductor L2, the second end of the second capacitor C2 is connected to the control end of the first switch SW, and the output end of the first switch SW is grounded. Specifically, the first switch SW is used as the second input end of the adjustable output matching circuit 2, and the first switch SW is turned on or off according to the control signal from the load mismatch detection circuit 3 to achieve the effect of adjusting the load impedance of the power amplifier 1.

[0033] In the embodiment of the present invention, please refer to Figure 7-Figure 8 , Figure 7 It is a circuit structure schematic diagram of an amplitude detection unit of a load mismatch detection circuit of a load impedance adjustment circuit provided by an embodiment of the present invention; Figure 8 It is a circuit structure diagram of the phase detection unit of the load mismatch detection circuit of the load impedance adjustment circuit provided by an embodiment of the present invention. The load mismatch detection circuit 3 includes an amplitude detection unit 31 and a phase detection unit 32; the first input end of the amplitude detection unit 31 and the first input end of the phase detection unit 32 are connected and used together as the first input end of the load mismatch detection circuit 3, the second input end of the amplitude detection unit 31 and the second input end of the phase detection unit 32 are connected and used together as the second input end of the load mismatch detection circuit 3, the output end of the amplitude detection unit 31 and the output end of the phase detection unit 32 are connected and used together as the output end of the load mismatch detection circuit 3; the amplitude detection unit 31 is used to detect the amplitude of the load impedance of the power amplifier 1, and the phase detection unit 32 is used to detect the phase of the load impedance of the power amplifier 1.

[0034] Specifically, when the amplitude detection result of the amplitude detection unit 31 exceeds a preset range, an enable signal is sent to drive the phase detection unit 32 to perform phase detection. When the detection results of the amplitude detection unit 31 and the phase detection unit 32 exceed the preset range at the same time, a control signal (i.e., Vcrtl1 and Vcrtl2) is sent to the first switch SW to close the first switch SW.

[0035] The amplitude detection unit 31 includes a first adjustable attenuation network 311, a second adjustable attenuation network 313, a first power detection circuit 312, a second power detection circuit 314 and a first voltage conversion circuit 315; the input end of the first adjustable attenuation network 311 serves as the first input end of the amplitude detection unit 31, and the input end of the second adjustable attenuation network 313 serves as the second input end of the amplitude detection unit 31; the output end of the first adjustable attenuation network 311 is connected to the input end of the first power detection circuit 312, and the output end of the second adjustable attenuation network 313 is connected to the input end of the second power detection circuit 314; the output end of the first power detection circuit 312 is connected to the first input end of the first voltage conversion circuit 315, and the output end of the second power detection circuit 314 is connected to the second input end of the first voltage conversion circuit 315; the output end of the first voltage conversion circuit 315 serves as the output end of the amplitude detection unit 31; The phase detection unit 32 includes a third adjustable attenuation network 321, a fourth adjustable attenuation network 323, a third power detection circuit 322, a fourth power detection circuit 324 and a second voltage conversion circuit 325; the input end of the third adjustable attenuation network 321 serves as the first input end of the phase detection unit 32, and the input end of the fourth adjustable attenuation network 323 serves as the second input end of the phase detection unit 32; the output end of the third adjustable attenuation network 321 is connected to the input end of the third power detection circuit 322, and the output end of the fourth adjustable attenuation network 323 is connected to the input end of the fourth power detection circuit 324; the output end of the third power detection circuit 322 is connected to the first input end of the second voltage conversion circuit 325, and the output end of the fourth power detection circuit 324 is connected to the second input end of the second voltage conversion circuit 325; the output end of the second voltage conversion circuit 325 serves as the output end of the phase detection unit 32.

[0036] In an embodiment of the present invention, the circuit structures of the first power detection circuit 312, the second power detection circuit 314, the third power detection circuit 322 and the fourth power detection circuit 324 are the same; the circuit structures of the first adjustable attenuation network 311, the second adjustable attenuation network 313, the third adjustable attenuation network 321 and the fourth adjustable attenuation network 323 are the same.

[0037] In the embodiments of the present invention, please refer to Fig. 9 , Fig. 9 : is a circuit structure diagram of the first power detection circuit of the load impedance adjustment circuit provided in an embodiment of the present invention. The first power detection circuit 312 includes a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first transistor T1, a second transistor T2 and a third transistor T3; The first end of the third capacitor C3 serves as the input end of the first power detection circuit 312, the second end of the third capacitor C3 is respectively connected to the first end of the first resistor R1, the first end of the second resistor R2 and the collector of the first transistor T1, the second end of the first resistor R1 is connected to the first external power supply voltage Vbias, the second end of the second resistor R2 and the base of the first transistor T1 are respectively connected to the first end of the third resistor R3, the emitter of the first transistor T1 is grounded, the second end of the third resistor R3 is connected to the base of the second transistor T2, the first end of the fourth capacitor C4 is connected to the second end of the third resistor R3, and the fourth capacitor C4 is connected to the second end of the third resistor R3. The second end of the capacitor C4 is grounded, the emitter of the second transistor T2 is grounded, the collector of the second transistor T2 is respectively connected to the first end of the fourth resistor R4 and the base of the third transistor T3, the second end of the fourth resistor R4 is connected to the first external power supply voltage Vbias, the collector of the third transistor T3 is connected to the second external power supply voltage Vat, the emitter of the third transistor T3 serves as the output end of the first power detection circuit 312, the first end of the fifth resistor R5 and the first end of the fifth capacitor C5 are respectively connected to the emitter of the third transistor T3, the second end of the fifth resistor R5 and the second end of the fifth capacitor C5 are connected to each other and then grounded. It should be noted that the magnitudes of the first external power supply voltage Vbias and the second external power supply voltage Vat can be set according to actual conditions.

[0038] In the embodiments of the present invention, please refer to Fig.10 , Fig.10 315 is a circuit structure diagram of the first voltage conversion circuit of the load impedance adjustment circuit provided in an embodiment of the present invention. The first voltage conversion circuit 315 includes a first voltage-to-current circuit 3151, a second voltage-to-current circuit 3152, a first amplifier circuit 3153 and a first current comparison circuit 3154; wherein the first voltage-to-current circuit 3151 is used to convert the received voltage into a current (such as Fig.10 The second voltage-to-current circuit 3152 is used to convert the received voltage into a current (such as Fig.10 V2 in the figure); the first amplifier circuit 3153 amplifies the current output by the second voltage-to-current circuit 3152; and the first current comparison circuit 3154 is used to determine whether the received current exceeds a preset threshold.

[0039] The input end of the first voltage-to-current circuit 3151 serves as the first input end of the first voltage conversion circuit 315, the first output end of the first voltage-to-current circuit 3151 is connected to the first input end of the first current comparison circuit 3154, and the second output end of the first voltage-to-current circuit 3151 is connected to the second input end of the first current comparison circuit 3154; the input end of the second voltage-to-current circuit 3152 serves as the second input end of the first voltage conversion circuit 3155, the first output end of the second voltage-to-current circuit 3152 is connected to the first input end of the first amplifier circuit 3153, and the second output end of the second voltage-to-current circuit 3152 is connected to the second input end of the first amplifier circuit 3153; the output end of the first amplifier circuit 3153 is connected to the third input end of the first current comparison circuit 3154; the output end of the first current comparison circuit 3154 serves as the output end of the first voltage conversion circuit 315; The first voltage-to-current circuit 3151 includes a first operational amplifier OPA1, a first MOS tube M1 and a sixth resistor R6; the negative input terminal of the first operational amplifier OPA1 serves as the input terminal of the first voltage-to-current circuit 3151, the positive input terminal of the first operational amplifier OPA1 is respectively connected to the drain of the first MOS tube M1 and the first end of the sixth resistor R6, the second end of the sixth resistor R6 is grounded, the output terminal of the first operational amplifier OPA1 is connected to the gate of the first MOS tube M1, the output terminal of the first operational amplifier OPA1 serves as the first output terminal of the first voltage-to-current circuit 3151, the source of the first MOS tube M1 is used to connect to the second external power supply voltage Vbat, and the source of the first MOS tube M1 serves as the second output terminal of the first voltage-to-current circuit 3151; The second voltage-to-current circuit 3152 includes a second operational amplifier OPA2, a second MOS tube M2 and a seventh resistor R7; the negative input terminal of the second operational amplifier OPA2 serves as the input terminal of the second voltage-to-current circuit 3152, the positive input terminal of the second operational amplifier OPA2 is respectively connected to the drain of the second MOS tube M2 and the first end of the seventh resistor R7, the second end of the seventh resistor R7 is connected, the output terminal of the second operational amplifier OPA2 is connected to the gate of the second MOS tube M2, the output terminal of the second operational amplifier OPA2 serves as the first output terminal of the second voltage-to-current circuit 3152, the source of the second MOS tube M2 is used to connect the second external power supply voltage Vbat, and the source of the second MOS tube M2 serves as the second output terminal of the second voltage-to-current circuit 3152; The first amplifier circuit 3153 includes a third MOS tube M3 and a fourth MOS tube M4; the gate of the third MOS tube M3 serves as the first input terminal of the first amplifier circuit 3153, the source of the third MOS tube M3 serves as the second input terminal of the first amplifier circuit 3153, the source of the third MOS tube M3 is used to connect to the second external power supply voltage Vbat, the drain of the third MOS tube M3 is respectively connected to the drain of the fourth MOS tube M4 and the gate of the fourth MOS tube M4, the source of the fourth MOS tube M4 is grounded, and the gate of the fourth MOS tube M4 serves as the output terminal of the first amplifier circuit 3153; The first current comparison circuit 3154 includes a fifth MOS tube M5, a sixth MOS tube M6, a first inverter INV1 and a second inverter INV2; the gate of the fifth MOS tube M5 serves as the first input end of the first current comparison circuit 3154, the source of the fifth MOS tube M5 serves as the second input end of the first current comparison circuit 3154, the source of the fifth MOS tube M5 is used to connect the second external power supply voltage Vbat, and the drain of the fifth MOS tube M5 is connected to the input end of the first inverter INV1; the gate of the sixth MOS tube M6 serves as the third input end of the first current comparison circuit 3154, the source of the sixth MOS tube M6 is grounded, the drain of the sixth MOS tube M6 is connected to the input end of the first inverter INV1, the output end of the first inverter INV1 is connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 serves as the output end of the first current comparison circuit 3154.

[0040] In the embodiments of the present invention, please refer to Fig.11 , Fig.11 3 is a circuit structure diagram of the second voltage conversion circuit 325 of the load impedance adjustment circuit provided in an embodiment of the present invention. The second voltage conversion circuit 325 includes a third voltage-to-current circuit 3251, a fourth voltage-to-current circuit 3252, a second amplifier circuit 3253, a current subtraction circuit 3254 and a second current comparison circuit 3255; wherein the third voltage-to-current circuit 3251 is used to convert the received voltage into a current (such as Fig.11 The fourth voltage-to-current circuit 3252 is used to convert the received voltage into a current (such as Fig.11 V4 in the figure); the second amplifier circuit 3253 amplifies the current output by the third voltage-to-current circuit 3251; the current subtraction circuit 3254 is used to control the magnitude of the received current; and the second current comparison circuit 3255 is used to determine whether the received current exceeds a preset threshold.

[0041] The input end of the third voltage-to-current circuit 3251 serves as the first input end of the second voltage conversion circuit 325, the first output end of the third voltage-to-current circuit 3251 is connected to the first input end of the current subtraction circuit 3254, and the second output end of the third voltage-to-current circuit 3251 is connected to the second input end of the current subtraction circuit 3254; the input end of the fourth voltage-to-current circuit 3252 serves as the second input end of the second voltage conversion circuit 325, the first output end of the fourth voltage-to-current circuit 3252 is connected to the first input end of the second amplifier circuit 3253, and the second output end of the fourth voltage-to-current circuit 3252 is connected to the second input end of the second amplifier circuit 3253; the output end of the second amplifier circuit 3253 is connected to the third input end of the current subtraction circuit 3254, the second output end of the current subtraction circuit 3254 is connected to the input end of the second current comparison circuit 3255, and the output end of the second current comparison circuit 3255 serves as the output end of the second voltage conversion circuit 325; The third voltage-to-current circuit 3251 includes a third operational amplifier OPA3, a seventh MOS tube M7 and an eighth resistor R8; the negative input terminal of the third operational amplifier OPA3 serves as the input terminal of the third voltage-to-current circuit 3251, the positive input terminal of the third operational amplifier OPA3 is respectively connected to the drain of the seventh MOS tube M7 and the first end of the eighth resistor R8, the second end of the eighth resistor R8 is grounded, the output terminal of the third operational amplifier OPA3 is connected to the gate of the seventh MOS tube M7, the output terminal of the third operational amplifier OPA3 serves as the first output terminal of the third voltage-to-current circuit 3251, the source of the seventh MOS tube M7 serves as the second output terminal of the third voltage-to-current circuit 3251, and the source of the seventh MOS tube M7 is used to connect the second external power supply voltage Vbat; The fourth voltage-to-current circuit 3252 includes a fourth operational amplifier OPA4, an eighth MOS tube M8 and a ninth resistor R9; the negative input terminal of the fourth operational amplifier OPA4 serves as the input terminal of the fourth voltage-to-current circuit 3252, the positive input terminal of the fourth operational amplifier OPA4 is respectively connected to the drain of the eighth MOS tube M8 and the first end of the ninth resistor R9, the second end of the ninth resistor R9 is grounded, the output terminal of the fourth operational amplifier OPA4 is connected to the gate of the eighth MOS tube M8, the output terminal of the fourth operational amplifier OPA4 serves as the first output terminal of the fourth voltage-to-current circuit 3252, the source of the eighth MOS tube M8 serves as the second output terminal of the fourth voltage-to-current circuit 3252, and the source of the eighth MOS tube M8 is used to connect the second external power supply voltage Vbat; The second amplifier circuit 3253 includes a ninth MOS tube M9 and a tenth MOS tube M10; the gate of the ninth MOS tube M9 serves as the first input terminal of the second amplifier circuit 3253, the source of the ninth MOS tube M9 serves as the second input terminal of the second amplifier circuit 3253, the source of the ninth MOS tube M9 is used to connect to the second external power supply voltage Vbat, the drain of the ninth MOS tube M9 is respectively connected to the drain of the tenth MOS tube M10 and the gate of the tenth MOS tube M10, the source of the tenth MOS tube M10 is grounded, and the gate of the tenth MOS tube M10 serves as the output terminal of the second amplifier circuit 3253; The current subtraction circuit 3254 includes an eleventh MOS tube M11, a twelfth MOS tube M12 and a thirteenth MOS tube M13; the gate of the eleventh MOS tube M11 serves as the first input end of the current subtraction circuit 3254, the source of the eleventh MOS tube M11 serves as the second input end of the current subtraction circuit 3254, the source of the eleventh MOS tube M11 is used to connect the second external power supply voltage Vbat, and the drain of the eleventh MOS tube M11 is connected to the drain of the twelfth MOS tube M12; the gate of the twelfth MOS tube M12 serves as the third input end of the current subtraction circuit, the source of the twelfth MOS tube M12 is grounded, the drain of the twelfth MOS tube M12 is respectively connected to the drain of the thirteenth MOS tube M13 and the gate of the thirteenth MOS tube M13, the source of the thirteenth MOS tube M13 is grounded, and the gate of the thirteenth MOS tube M13 serves as the output end of the current subtraction circuit 3254; The second current comparison circuit 3255 includes a current source Iref, a fourteenth MOS tube M14, a third inverter INV3 and a fourth inverter INV4; the input end of the current source Iref is used to connect to the second external power supply voltage Vbat, and the output end of the current source Iref is connected to the input end of the third inverter INV3; the gate of the fourteenth MOS tube M14 serves as the input end of the second current comparison circuit 3255, the source of the fourteenth MOS tube M14 is grounded, the drain of the fourteenth MOS tube M14 is connected to the input end of the third inverter INV3, the output end of the third inverter INV3 is connected to the input end of the fourth inverter INV4, and the output end of the fourth inverter INV4 serves as the output end of the second current comparator circuit.

[0042] Compared with the prior art, the present invention detects the coupling terminal voltage of the directional coupler and the isolation terminal voltage of the directional coupler in real time through a load mismatch detection circuit, and calculates the reflection coefficient of the load impedance of the power amplifier according to the coupling terminal voltage and the isolation terminal voltage, and determines whether the phase in the reflection coefficient exceeds the preset linearity range; if so, the load mismatch detection circuit outputs a control signal to the adjustable output matching circuit, and the adjustable output matching circuit adjusts the impedance of the power amplifier according to the control signal, so as to adjust the phase of the reflection coefficient that exceeds the preset linearity range to within the preset linearity range. In this way, the present invention can specifically adjust the phase of the linearity difference in the reflection coefficient, thereby reducing the sensitivity of the power amplifier performance to changes in load impedance and effectively improving the efficiency of the power amplifier.

[0043] Embodiment 2 An embodiment of the present invention further provides a radio frequency chip, which includes the load impedance adjustment circuit 100 as described in the above embodiment and can achieve the same technical effect. Please refer to the description in the above embodiment and will not be repeated here.

[0044] Compared with the prior art, the present invention detects the coupling terminal voltage of the directional coupler and the isolation terminal voltage of the directional coupler in real time through a load mismatch detection circuit, and calculates the reflection coefficient of the load impedance of the power amplifier according to the coupling terminal voltage and the isolation terminal voltage, and determines whether the phase in the reflection coefficient exceeds the preset linearity range; if so, the load mismatch detection circuit outputs a control signal to the adjustable output matching circuit, and the adjustable output matching circuit adjusts the impedance of the power amplifier according to the control signal, so as to adjust the phase of the reflection coefficient that exceeds the preset linearity range to within the preset linearity range. In this way, the present invention can specifically adjust the phase of the linearity difference in the reflection coefficient, thereby reducing the sensitivity of the power amplifier performance to changes in load impedance and effectively improving the efficiency of the power amplifier.

[0045] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0046] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A load impedance adjustment circuit, characterized in that: The load impedance adjustment circuit includes a power amplifier, a load mismatch detection circuit, an adjustable output matching circuit and a directional coupler; The input end of the power amplifier serves as the input end of the load impedance adjustment circuit, and is used to receive an input signal. The output end of the power amplifier is connected to the first input end of the adjustable output matching circuit. The first input end of the load mismatch detection circuit and the second input end of the load mismatch detection circuit are respectively connected to the coupling end of the directional coupler and the isolation end of the directional coupler, and the output end of the load mismatch detection circuit is connected to the second input end of the adjustable output matching circuit; The output end of the adjustable output matching circuit is connected to the input end of the directional coupler, and the adjustable output matching circuit is used to adjust the load impedance of the power amplifier; The output end of the directional coupler is used as the output end of the load impedance adjustment circuit to connect to the back-end components; The load mismatch detection circuit is used to detect the coupling terminal voltage of the directional coupler and the isolation terminal voltage of the directional coupler in real time, and calculate the reflection coefficient of the load impedance of the power amplifier according to the coupling terminal voltage and the isolation terminal voltage, and judge whether the phase in the reflection coefficient exceeds the preset linearity range: if so, the load mismatch detection circuit outputs a control signal to the adjustable output matching circuit, and the adjustable output matching circuit adjusts the impedance of the power amplifier according to the control signal to adjust the phase of the reflection coefficient that exceeds the preset linearity range to within the preset linearity range.

2. The load impedance adjustment circuit according to claim 1, wherein: The adjustable output matching circuit includes a transformer, a first inductor, a first capacitor, a second inductor, a second capacitor and a first switch; the input end of the transformer serves as the first input end of the adjustable output matching circuit, the output end of the transformer is connected to the first end of the first inductor, the second end of the first inductor is connected to the first end of the second inductor, the first end of the first capacitor is connected to the second end of the first inductor, the second end of the first capacitor is grounded, the second end of the second inductor serves as the output end of the adjustable output matching circuit, the first end of the second capacitor is connected to the second end of the second inductor, the second end of the second capacitor is connected to the control end of the first switch, and the output end of the first switch is grounded.

3. The load impedance adjustment circuit according to claim 1, wherein: The load mismatch detection circuit comprises an amplitude detection unit and a phase detection unit; a first input end of the amplitude detection unit and a first input end of the phase detection unit are connected and used together as the first input end of the load mismatch detection circuit, a second input end of the amplitude detection unit and a second input end of the phase detection unit are connected and used together as the second input end of the load mismatch detection circuit, an output end of the amplitude detection unit and an output end of the phase detection unit are connected and used together as the output end of the load mismatch detection circuit; the amplitude detection unit is used to detect the amplitude of the load impedance of the power amplifier, and the phase detection unit is used to detect the phase of the load impedance of the power amplifier; The amplitude detection unit includes a first adjustable attenuation network, a second adjustable attenuation network, a first power detection circuit, a second power detection circuit and a first voltage conversion circuit; the input end of the first adjustable attenuation network serves as the first input end of the amplitude detection unit, and the input end of the second adjustable attenuation network serves as the second input end of the amplitude detection unit; the output end of the first adjustable attenuation network is connected to the input end of the first power detection circuit, and the output end of the second adjustable attenuation network is connected to the input end of the second power detection circuit; the output end of the first power detection circuit is connected to the first input end of the first voltage conversion circuit, and the output end of the second power detection circuit is connected to the second input end of the first voltage conversion circuit; the output end of the first voltage conversion circuit serves as the output end of the amplitude detection unit; The phase detection unit includes a third adjustable attenuation network, a fourth adjustable attenuation network, a third power detection circuit, a fourth power detection circuit and a second voltage conversion circuit; the input end of the third adjustable attenuation network serves as the first input end of the phase detection unit, and the input end of the fourth adjustable attenuation network serves as the second input end of the phase detection unit; the output end of the third adjustable attenuation network is connected to the input end of the third power detection circuit, and the output end of the fourth adjustable attenuation network is connected to the input end of the fourth power detection circuit; the output end of the third power detection circuit is connected to the first input end of the second voltage conversion circuit, and the output end of the fourth power detection circuit is connected to the second input end of the second voltage conversion circuit; the output end of the second voltage conversion circuit serves as the output end of the phase detection unit.

4. The load impedance adjustment circuit according to claim 3, characterized in that: The circuit structures of the first power detection circuit, the second power detection circuit, the third power detection circuit and the fourth power detection circuit are the same; the first power detection circuit includes a third capacitor, a fourth capacitor, a fifth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first transistor, a second transistor and a third transistor; The first end of the third capacitor serves as the input end of the first power detection circuit, the second end of the third capacitor is respectively connected to the first end of the first resistor, the first end of the second resistor and the collector of the first transistor, the second end of the first resistor is connected to the first external power supply voltage, the second end of the second resistor and the base of the first transistor are respectively connected to the first end of the third resistor, the emitter of the first transistor is grounded, and the second end of the third resistor is connected to the base of the second transistor, the first end of the fourth capacitor is connected to the second end of the third resistor, the second end of the fourth capacitor is grounded, the emitter of the second transistor is grounded, the collector of the second transistor is respectively connected to the first end of the fourth resistor and the base of the third transistor, the second end of the fourth resistor is connected to the first external power supply voltage, the collector of the third transistor is connected to the second external power supply voltage, and the emitter of the third transistor serves as the output end of the first power detection circuit, the first end of the fifth resistor and the first end of the fifth capacitor are respectively connected to the emitter of the third transistor, and the second end of the fifth resistor and the second end of the fifth capacitor are connected to each other and then grounded.

5. The load impedance adjustment circuit according to claim 3, characterized in that: The first voltage conversion circuit includes a first voltage-to-current circuit, a second voltage-to-current circuit, a first amplifier circuit, and a first current comparison circuit; The input end of the first voltage-to-current circuit serves as the first input end of the first voltage conversion circuit, the first output end of the first voltage-to-current circuit is connected to the first input end of the first current comparison circuit, and the second output end of the first voltage-to-current circuit is connected to the second input end of the first current comparison circuit; the input end of the second voltage-to-current circuit serves as the second input end of the first voltage conversion circuit, the first output end of the second voltage-to-current circuit is connected to the first input end of the first amplifier circuit, and the second output end of the second voltage-to-current circuit is connected to the second input end of the first amplifier circuit; the output end of the first amplifier circuit is connected to the third input end of the first current comparison circuit; the output end of the first current comparison circuit serves as the output end of the first voltage conversion circuit; The first voltage-to-current circuit includes a first operational amplifier, a first MOS tube and a sixth resistor; the negative input terminal of the first operational amplifier serves as the input terminal of the first voltage-to-current circuit, the positive input terminal of the first operational amplifier is respectively connected to the drain of the first MOS tube and the first terminal of the sixth resistor, the second terminal of the sixth resistor is grounded, the output terminal of the first operational amplifier is connected to the gate of the first MOS tube, the output terminal of the first operational amplifier serves as the first output terminal of the first voltage-to-current circuit, the source of the first MOS tube is used to connect to the second external power supply voltage, and the source of the first MOS tube serves as the second output terminal of the first voltage-to-current circuit; The second voltage-to-current circuit includes a second operational amplifier, a second MOS tube and a seventh resistor; the negative input terminal of the second operational amplifier serves as the input terminal of the second voltage-to-current circuit, the positive input terminal of the second operational amplifier is respectively connected to the drain of the second MOS tube and the first end of the seventh resistor, the second end of the seventh resistor is connected, the output terminal of the second operational amplifier is connected to the gate of the second MOS tube, the output terminal of the second operational amplifier serves as the first output terminal of the second voltage-to-current circuit, the source of the second MOS tube is used to connect the second external power supply voltage, and the source of the second MOS tube serves as the second output terminal of the second voltage-to-current circuit; The first amplifier circuit includes a third MOS tube and a fourth MOS tube; the gate of the third MOS tube serves as the first input end of the first amplifier circuit, the source of the third MOS tube serves as the second input end of the first amplifier circuit, the source of the third MOS tube is used to connect to the second external power supply voltage, the drain of the third MOS tube is respectively connected to the drain of the fourth MOS tube and the gate of the fourth MOS tube, the source of the fourth MOS tube is grounded, and the gate of the fourth MOS tube serves as the output end of the first amplifier circuit; The first current comparison circuit includes a fifth MOS tube, a sixth MOS tube, a first inverter and a second inverter; The gate of the fifth MOS tube serves as the first input end of the first current comparison circuit, the source of the fifth MOS tube serves as the second input end of the first current comparison circuit, the source of the fifth MOS tube is used to connect the second external power supply voltage, and the drain of the fifth MOS tube is connected to the input end of the first inverter; the gate of the sixth MOS tube serves as the third input end of the first current comparison circuit, the source of the sixth MOS tube is grounded, the drain of the sixth MOS tube is connected to the input end of the first inverter, the output end of the first inverter is connected to the input end of the second inverter, and the output end of the second inverter serves as the output end of the first current comparison circuit.

6. The load impedance adjustment circuit according to claim 3, characterized in that: The second voltage conversion circuit includes a third voltage-to-current circuit, a fourth voltage-to-current circuit, a second amplification circuit, a current subtraction circuit, and a second current comparison circuit; The input end of the third voltage-to-current circuit serves as the first input end of the second voltage conversion circuit, the first output end of the third voltage-to-current circuit is connected to the first input end of the current subtraction circuit, and the second output end of the third voltage-to-current circuit is connected to the second input end of the current subtraction circuit; the input end of the fourth voltage-to-current circuit serves as the second input end of the second voltage conversion circuit, the first output end of the fourth voltage-to-current circuit is connected to the first input end of the second amplifier circuit, and the second output end of the fourth voltage-to-current circuit is connected to the second input end of the second amplifier circuit; the output end of the second amplifier circuit is connected to the third input end of the current subtraction circuit, the output end of the current subtraction circuit is connected to the input end of the second current comparison circuit, and the output end of the second current comparison circuit serves as the output end of the second voltage conversion circuit; The third voltage-to-current circuit includes a third operational amplifier, a seventh MOS tube and an eighth resistor; the negative input terminal of the third operational amplifier serves as the input terminal of the third voltage-to-current circuit, the positive input terminal of the third operational amplifier is respectively connected to the drain of the seventh MOS tube and the first terminal of the eighth resistor, the second terminal of the eighth resistor is grounded, the output terminal of the third operational amplifier is connected to the gate of the seventh MOS tube, the output terminal of the third operational amplifier serves as the first output terminal of the third voltage-to-current circuit, the source terminal of the seventh MOS tube serves as the second output terminal of the third voltage-to-current circuit, and the source terminal of the seventh MOS tube is used to connect to the second external power supply voltage; The fourth voltage-to-current circuit includes a fourth operational amplifier, an eighth MOS tube and a ninth resistor; the negative input terminal of the fourth operational amplifier serves as the input terminal of the fourth voltage-to-current circuit, the positive input terminal of the fourth operational amplifier is respectively connected to the drain of the eighth MOS tube and the first terminal of the ninth resistor, the second terminal of the ninth resistor is grounded, the output terminal of the fourth operational amplifier is connected to the gate of the eighth MOS tube, the output terminal of the fourth operational amplifier serves as the first output terminal of the fourth voltage-to-current circuit, the source terminal of the eighth MOS tube serves as the second output terminal of the fourth voltage-to-current circuit, and the source terminal of the eighth MOS tube is used to connect to the second external power supply voltage; The second amplifier circuit includes a ninth MOS tube and a tenth MOS tube; the gate of the ninth MOS tube serves as the first input end of the second amplifier circuit, the source of the ninth MOS tube serves as the second input end of the second amplifier circuit, the source of the ninth MOS tube is used to connect to a second external power supply voltage, the drain of the ninth MOS tube is respectively connected to the drain of the tenth MOS tube and the gate of the tenth MOS tube, the source of the tenth MOS tube is grounded, and the gate of the tenth MOS tube serves as the output end of the second amplifier circuit; The current subtraction circuit includes an eleventh MOS tube, a twelfth MOS tube and a thirteenth MOS tube; the gate of the eleventh MOS tube serves as the first input end of the current subtraction circuit, the source of the eleventh MOS tube serves as the second input end of the current subtraction circuit, the source of the eleventh MOS tube is used to connect to the second external power supply voltage, and the drain of the eleventh MOS tube is connected to the drain of the twelfth MOS tube; the gate of the twelfth MOS tube serves as the third input end of the current subtraction circuit, the source of the twelfth MOS tube is grounded, the drain of the twelfth MOS tube is respectively connected to the drain of the thirteenth MOS tube and the gate of the thirteenth MOS tube, the source of the thirteenth MOS tube is grounded, and the gate of the thirteenth MOS tube serves as the output end of the current subtraction circuit; The second current comparison circuit includes a current source, a fourteenth MOS tube, a third inverter and a fourth inverter; the input end of the current source is used to connect to the second external power supply voltage, and the output end of the current source is connected to the input end of the third inverter; the gate of the fourteenth MOS tube serves as the input end of the second current comparison circuit, the source of the fourteenth MOS tube is grounded, the drain of the fourteenth MOS tube is connected to the input end of the third inverter, the output end of the third inverter is connected to the input end of the fourth inverter, and the output end of the fourth inverter serves as the output end of the second current comparator circuit.

7. The load impedance adjustment circuit according to claim 1, wherein: Define the coupling terminal voltage as Vcpl, the isolation terminal voltage as Viso, and the reflection coefficient as ΓL, and calculate the reflection coefficient by combining the coupling terminal voltage and the isolation terminal voltage according to the following rule: 。 8. The load impedance adjustment circuit according to claim 1, wherein: The preset linearity range is less than -33dBc.

9. The load impedance adjustment circuit according to claim 1, wherein: The back-end component is a filter device.

10. A radio frequency chip, characterized in that: The radio frequency chip includes the load impedance adjustment circuit as described in any one of claims 1-9.

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