A multi-channel signal real-time monitoring and access system with flexible scalability

Abstract

The present invention discloses a multi-channel signal real-time monitoring and access system with flexible scalability, which relates to the field of signal transmission, reception and access technology. The system includes an interconnection calculation matrix and a data access unit, wherein the interconnection calculation matrix is ​​an N1-element interconnection calculation matrix or an N M The meta-extension interconnected computing matrix can be expanded. On the one hand, by expanding the connection relationship between the interconnected computing matrix levels, between the interconnected computing matrix and the interconnected computing matrix, and between the computing units within the interconnected computing matrix, the larger the scale of the computing matrix, the larger the total computing power and storage space, thereby adapting to real-time signal analysis, data recording and data playback with different numbers of channels. On the other hand, by designing decoupled computing units and data access units, it can be flexibly configured according to the channel and capacity requirements of analog signals, digital signals and disk playback, thereby reducing overall costs.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal transmission, reception and access, and in particular relates to a multi-channel signal real-time monitoring and access system with flexible scale expansion. Background Art

[0002] When developing complex RF systems such as communications, radar, or electronic warfare systems, researchers often need to conduct indoor functional verification or performance testing using purely digital or hardware-in-the-loop simulations with RF signal injection before conducting large-scale, real-world testing. This approach reduces testing costs and shortens testing cycles. This type of verification and testing involves interconnecting dozens or even hundreds of RF systems using channel emulators or RF distribution networks for dynamic testing, with each system simultaneously receiving or transmitting RF signals. To deeply analyze the functionality or performance of each RF system, it is ideal to digitally store the RF signals of interest during these tests (e.g., signals from a few dozen channels out of hundreds) for further, more precise analysis. However, because these tests involve numerous connected RF systems, flexible recording of the signals from the channels of interest requires signal storage devices capable of online, real-time monitoring of numerous channels, simultaneous, and on-demand recording of these channels, and subsequent retrieval and playback.

[0003] Although various devices are currently available on the market for signal playback or streaming, they generally cannot meet the requirements for flexible signal monitoring, data recording, and signal playback for the aforementioned large number of channels due to the following reasons:

[0004] (1) The number of supported channels is small. In other words, the recording performance of existing signal playback equipment on the market generally does not exceed 8GB / s. For a 1GHz instantaneous bandwidth RF signal, even if recorded at 12 bits, the data rate generated by the two-channel signal will reach 7.5GB / s. As a result, a single playback device on the market can only support recording of a maximum of two 1GHz instantaneous bandwidth signal channels.

[0005] (2) The signal connection relationship is fixed. That is, the existing signal playback equipment on the market has a fixed signal connection port. The signal connection port needs to be directly connected to the signal channel to be tested to complete the playback. It cannot dynamically switch to different channels during the test, nor can it be used to identify and record the signal characteristics of interest online.

[0006] (3) Lack of multi-channel real-time analysis capabilities. In other words, when accessing data, the existing signal playback equipment on the market takes up a lot of processor computing time, and generally cannot perform synchronous real-time monitoring and analysis of the signal, especially the multi-channel real-time monitoring and analysis capabilities.

[0007] (4) The cost of building a multi-channel system is high. That is, if you want to build a signal playback device that can monitor, for example, hundreds of channels, the cost will be very high because each channel must be connected one-to-one to an independent storage system.

[0008] In summary, the signal playback solutions currently on the market have problems such as a small number of supported channels, fixed signal connection relationships, lack of multi-channel real-time analysis capabilities, and high costs of building multi-channel systems. Summary of the Invention

[0009] The purpose of the present invention is to provide a multi-channel signal real-time monitoring and access system that can be flexibly expanded to solve the problems of existing signal playback solutions, such as a small number of supported channels, fixed signal connection relationships, lack of multi-channel real-time analysis capabilities, and / or high cost of building a multi-channel system.

[0010] In order to achieve the above object, the present invention adopts the following technical solutions:

[0011] The present invention provides a multi-channel signal real-time monitoring and access system with flexible scalability, comprising an interconnection calculation matrix and a data access unit, wherein the interconnection calculation matrix is ​​an N1-element interconnection calculation matrix or Meta-Extended Interconnected Computing Matrix, the The meta-extension interconnection computing matrix includes N M indivual Meta-Extended Interconnected Computing Matrix, the The meta-extension interconnection computing matrix includes N M-1 indivual Meta-extended interconnected computing matrix, and so on The meta-extension interconnection computing matrix includes N M-m indivual Meta-extended interconnected computing matrix until The element-extension interconnection computing matrix includes N2 N1 element-interconnection computing matrices, and the N1 element-interconnection computing matrix includes N1 computing units. N M ×N M-1 ×…×N M-m The abbreviation of ×…×N2×N1, N M 、N M-1 、N M-m, N2 and N1 respectively represent integers greater than or equal to 2, M represents an integer greater than or equal to 2, m exists when M is greater than or equal to 3, and represents an integer greater than or equal to 0 and less than M-2;

[0012] Any two of the N1 computing units are communicatively connected;

[0013] For each of the computing units in any N1-element interconnected computing matrix, the corresponding unit is connected to the computing units in the corresponding positions in N2-1 other N1-element interconnected computing matrices, wherein the any N1-element interconnected computing matrix and the N2-1 other N1-element interconnected computing matrices constitute the Meta-Extended Interconnected Computing Matrix;

[0014] For any Each of the computing units in the N-th element expansion interconnection computing matrix is ​​connected to the corresponding unit. M-m -1 other The computing units in corresponding positions in the meta-extension interconnected computing matrix are connected in communication, wherein any one Meta-extended interconnection computing matrix and the N M-m -1 other The meta-extension interconnected computing matrix is ​​composed of Meta-Extended Interconnected Computing Matrix;

[0015] The data access unit is communicatively connected to the computing unit and establishes a one-to-one connection relationship, a one-to-many connection relationship, or a many-to-one connection relationship with a signal channel on the computing unit, wherein the signal channel is a signal receiving channel, a signal transmitting channel, or a signal transceiver channel;

[0016] The data access unit is used to monitor and store the signal data collected by the signal channel in real time, and / or read local signal data and send it out through the signal channel.

[0017] Based on the above invention, a new multi-channel signal real-time monitoring access solution with flexible scalability is provided, which includes an interconnection calculation matrix and a data access unit, wherein the interconnection calculation matrix is ​​an N1-element interconnection calculation matrix or an N MThe invention provides an interconnected computing matrix with a meta-extension. On the one hand, by expanding the connection relationship between the layers of the interconnected computing matrix, between the extended interconnected computing matrix and the interconnected computing matrix, and between the computing units within the interconnected computing matrix, computing arrays of different topologies and different scales can be constructed. The more array elements in the interconnected computing matrix and the more levels of the extended interconnection, the larger the scale of the computing matrix, the greater the total computing power and storage space, thereby adapting to real-time signal analysis, data recording and data playback with different numbers of channels. On the other hand, by designing decoupled computing units and data access units, it is convenient to flexibly configure according to the channel and capacity requirements of analog signals, digital signals and disk playback, thereby reducing the overall cost. It can further solve the problems of the existing signal disk playback solution, such as the small number of supported channels, fixed signal connection relationship, lack of multi-channel real-time analysis capability and / or high cost of building a multi-channel system, and facilitate practical application and promotion.

[0018] In one possible design, a one-to-one connection relationship, a one-to-many connection relationship, or a many-to-one connection relationship between the data access unit and the signal channel on the computing unit is established as follows:

[0019] Taking the computing unit with the signal channel in the interconnected computing matrix as the central computing unit, the interconnected computing matrix is ​​decomposed layer by layer into at least two-order computing resources in the following manner: the computing resources in the central computing unit are divided into zero-order computing resources, the computing resources in all other computing units in the N1-element interconnected computing matrix where the central computing unit is located are divided into first-order computing resources, and the computing resources in the interconnected computing matrix for the signal channel are divided into first-order computing resources. When the element interconnection calculation matrix is ​​expanded, the N1 element interconnection calculation matrix will also be located at the location of the N1 element interconnection calculation matrix. The computing resources in all other N1 element interconnection computing matrices in the element extension interconnection computing matrix are divided into second-order computing resources, and the Mm-order computing resources, M-1-order computing resources and M-order computing resources are determined by analogy;

[0020] If there are at least two connectable computing units with different computing resource orders in the interconnected computing matrix, the computing resources in the selected unit are divided into low-order computing resources and the connectable computing unit is communicatively connected to the data access unit;

[0021] If there are at least two connectable computing units with the same computing resource order in the interconnected computing matrix, the connectable computing unit is arbitrarily selected to be communicatively connected to the data access unit.

[0022] In a possible design, a control computer is further included, wherein the control computer is communicatively connected to the controlled ends of each of the computing units in the interconnected computing matrix, and is used to read and write parameters and / or data of the computing units.

[0023] In one possible design, the computing unit includes a first FPGA module, a first storage module, and a first high-speed serial interface, wherein the first high-speed serial interface has at least one and is used to communicatively connect to the signal transceiver unit or other computing units;

[0024] The first FPGA module is communicatively connected to the first storage module and the first high-speed serial interface respectively.

[0025] In one possible design, the computing unit is communicatively connected to K signal transceiver units, where K represents a positive integer, and the signal transceiver units are used to provide a signal receiving channel, a signal transmitting channel, or a signal transceiver channel.

[0026] In one possible design, when the signal transceiver unit is used to provide a signal receiving channel and a signal transmitting channel, and the signal receiving channel is used to receive an input analog signal and convert it into an input digital signal, and the signal transmitting channel is used to directly convert an output digital signal into an output analog signal and transmit it, the signal transceiver unit includes an analog receiving front-end module, an analog transmitting front-end module, an ADC module, a DAC module, a second FPGA module, a second storage module, and a second high-speed serial interface, wherein the analog receiving front-end module is used to receive the input analog signal, the analog transmitting front-end module is used to transmit the output analog signal, and the second high-speed serial interface is used to communicatively connect to the computing unit;

[0027] The output end of the analog receiving front-end module is communicatively connected to the input end of the ADC module, the output end of the ADC module is communicatively connected to the input end of the second FPGA module, the input end of the analog transmitting front-end module is communicatively connected to the output end of the DAC module, the input end of the DAC module is communicatively connected to the output end of the second FPGA module, and the second FPGA module is also communicatively connected to the second storage module and the second high-speed serial interface respectively.

[0028] In one possible design, the signal transceiver unit further includes a clock and trigger signal interface, an onboard OCXO module, and a clock generation and distribution circuit module based on a phase-locked loop mechanism, wherein the clock and trigger signal interface is used to receive an external sampling clock signal, a reference clock signal, a GPS second pulse signal, and a trigger signal, and the onboard OCXO module is used to generate a time base signal;

[0029] The trigger signal output end of the clock and trigger signal interface is communicatively connected to the second FPGA module, the non-trigger signal output end of the clock and trigger signal interface and the time base signal output end of the onboard OCXO module are respectively communicatively connected to the input end of the clock generation and distribution circuit module, and the clock signal output end of the clock generation and distribution circuit module is respectively communicatively connected to the analog receiving front-end module, the analog transmitting front-end module, the ADC module, the DAC module and the second FPGA module.

[0030] In one possible design, when the signal transceiver unit includes a second FPGA module and a second storage module and a second high-speed serial interface respectively communicatively connected to the second FPGA, the signal transceiver unit is also used as an extended computing unit relative to the computing unit so as to share the computing tasks of the computing unit.

[0031] In one possible design, the data access unit includes a third FPGA module, a third storage module, a third high-speed serial interface, and a data buffer storage group, wherein the third high-speed serial interface has at least one and is used for communication with the computing unit, and the data buffer storage group includes a dynamic random access memory for data buffering and a solid-state hard disk for data storage;

[0032] The third FPGA module is communicatively connected to the third storage module, the third high-speed serial interface, the dynamic random access memory and the solid state drive respectively.

[0033] In one possible design, the data access unit also includes a PCIe bus control interface or a PCIe-based instrument expansion bus control interface that is communicatively connected to the third FPGA module, wherein the PCIe bus control interface or the instrument expansion bus control interface is used to communicate with the control interface of an external host computer.

[0034] In one possible design, the third storage module uses flash memory to store the firmware program of the third FPGA module, and the third high-speed serial interface uses a Nano-Pitch interface, a MiniSAS HD interface, an SFP interface, an SFP+ interface, a QSFP interface, a QSFP+ interface, a QSFP28 interface or a QSFP56 interface.

[0035] Beneficial effects of the above scheme:

[0036] (1) The present invention provides a new multi-channel signal real-time monitoring access solution that can be flexibly expanded in scale, namely, it includes an interconnection calculation matrix and a data access unit, wherein the interconnection calculation matrix is ​​an N1-element interconnection calculation matrix or an N MThe invention provides an interconnected computing matrix. On the one hand, by expanding the connection relationships between the interconnected computing matrix layers, between the expanded interconnected computing matrix and the interconnected computing matrix, and between the computing units within the interconnected computing matrix, computing arrays of different topologies and different scales can be constructed. The more array elements in the interconnected computing matrix and the more levels of expansion, the larger the scale of the computing matrix, the greater the total computing power and storage space, thereby adapting to real-time signal analysis, data recording, and data playback with different numbers of channels. On the other hand, by designing decoupled computing units and data access units, it is convenient to flexibly configure according to the channel and capacity requirements of analog signals, digital signals, and disk playback, thereby reducing overall costs. This can solve the problems of existing signal disk playback solutions, such as a small number of supported channels, fixed signal connection relationships, lack of multi-channel real-time analysis capabilities, and / or high cost of building multi-channel systems, and facilitate practical application and promotion.

[0037] (2) Flexible expansion and splitting: The computing topology designed by the present invention is applicable to signal monitoring and access systems with a few to several hundred channels. It can easily expand a small-scale signal monitoring and access system into a large-scale system, and can also easily split a large-scale system into several small-scale systems.

[0038] (3) Integrated computing and storage: The access system designed by the present invention integrates storage and computing capabilities, so that signal analysis and processing can be performed on data before data storage or after data reading;

[0039] (4) Diversified access connection relationships: One-to-many, one-to-one, and many-to-one connection relationships can be established between signal channels and data access units. This allows the access system designed by the present invention to adopt different configurations to accommodate various application scenarios such as storage capacity expansion, parallel analysis storage, and multi-channel flexible storage. At the same time, multiple connection relationships can coexist, making the device very flexible.

[0040] (5) Low cost: Due to the standardization of computing units and data access units, the construction and expansion of large-scale signal monitoring and access systems no longer need to be customized, thus achieving low cost. At the same time, the many-to-one access connection relationship can also significantly reduce the number of data access units when multi-channel data acquisition and reading, thereby significantly reducing costs.

[0041] (6) Easy configuration: Since the computing topology designed by the present invention is a completely symmetrical structure, it is only necessary to design the algorithm and program for a single computing unit to complete the algorithm and program design of the entire computing matrix;

[0042] (7) Customizable: The signal transceiver unit provides extended computing power, and the implementation of this computing power is completely decoupled from the computing matrix, so it is easy to provide customized signal processing capabilities for signal monitoring and access port devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 A schematic diagram of the specific structure of a computing unit in a multi-channel signal real-time monitoring and access system provided by an embodiment of the present invention.

[0045] Figure 2 A schematic diagram of the specific structure of a two-element interconnected computing matrix provided in an embodiment of the present invention.

[0046] Figure 3 A schematic diagram of the structure of an N-element interconnected computing matrix provided by an embodiment of the present invention, wherein: Figure 3 (a) shows the schematic diagram of the structure of the 3-element interconnected computing matrix. Figure 3 (b) shows the structural diagram of the 4-element interconnection calculation matrix. Figure 3 (c) shows a schematic diagram of the structure of a 5-element interconnected computing matrix.

[0047] Figure 4 A schematic diagram of the structure of a 3×3 element extended interconnection computing matrix provided in an embodiment of the present invention.

[0048] Figure 5 A schematic diagram of the structure of a 4×3 element extended interconnection computing matrix provided in an embodiment of the present invention.

[0049] Figure 6 A schematic diagram of the structure of a 4×4 element extended interconnection computing matrix provided in an embodiment of the present invention.

[0050] Figure 7 A schematic diagram of the specific structure of a signal transceiver unit in a multi-channel signal real-time monitoring and access system provided by an embodiment of the present invention.

[0051] Figure 8 This is an example diagram of the connection relationship between the 4×3 element interconnection computing matrix and the signal transceiver unit provided in an embodiment of the present invention.

[0052] Figure 9 This is an example diagram of the topological structure of the 4×3 element interconnected computing matrix after computational extension provided in an embodiment of the present invention.

[0053] Figure 10 This is an example diagram of the connection relationship between the 4×3 element interconnection computing matrix and the signal transceiver unit provided in an embodiment of the present invention.

[0054] Figure 11 A schematic diagram of the specific structure of a data access unit in a multi-channel signal real-time monitoring and access system provided by an embodiment of the present invention.

[0055] Figure 12 This is an example diagram of establishing a one-to-one connection relationship based on an extended interconnection computing matrix provided in an embodiment of the present invention.

[0056] Figure 13 This is an example diagram of establishing a many-to-one connection relationship and a one-to-many connection relationship based on an extended interconnection computing matrix provided in an embodiment of the present invention.

[0057] Figure 14 This is an example diagram of establishing multiple many-to-one connection relationships based on an extended interconnection computing matrix provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0058] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the present invention will be briefly introduced below in conjunction with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the structures of the drawings is only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these embodiments without creative work. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention.

[0059] It should be understood that although the terms first, second, etc. may be used herein to describe various objects, these objects should not be limited by these terms. These terms are merely used to distinguish one object from another. For example, a first object can be referred to as a second object, and similarly, a second object can be referred to as a first object without departing from the scope of the exemplary embodiments of the present invention.

[0060] It should be understood that the term "and / or" that may appear in this document is merely a description of the association relationship between associated objects, indicating that there may be three relationships. For example, A and / or B can indicate three situations: A exists alone, B exists alone, or A and B exist at the same time. For another example, A, B and / or C can indicate the existence of any one of A, B and C or any combination of them. The term " / and" that may appear in this document describes another type of association object relationship, indicating that there may be two relationships. For example, A / and B can indicate two situations: A exists alone or A and B exist at the same time. In addition, the character " / " that may appear in this document generally indicates that the previous and next associated objects are in an "or" relationship.

[0061] Example

[0062] like Figures 1 to 14 As shown, the multi-channel signal real-time monitoring and access system provided by this embodiment and capable of flexible expansion includes but is not limited to an interconnection computing matrix and a data access unit, wherein the interconnection computing matrix is ​​an N1-element interconnection computing matrix or Meta-Extended Interconnected Computing Matrix, the The meta-extension interconnection computing matrix includes N M indivual Meta-Extended Interconnected Computing Matrix, the The meta-extension interconnection computing matrix includes N M-1 indivual Meta-extended interconnected computing matrix, and so on The meta-extension interconnection computing matrix includes N M-m indivual Meta-extended interconnected computing matrix until The element-extension interconnection computing matrix includes N2 N1 element-interconnection computing matrices, and the N1 element-interconnection computing matrix includes N1 computing units. N M ×N M-1 ×…×N M-m The abbreviation of ×…×N2×N1, N M 、N M-1 、N M-m , N2 and N1 represent integers greater than or equal to 2, M represents an integer greater than or equal to 2, m exists when M is greater than or equal to 3, and represents an integer greater than or equal to 0 and less than M-2; any two of the N1 computing units are communicatively connected; for each of the computing units in any N1-element interconnected computing matrix, the corresponding unit is communicatively connected with the computing unit in the corresponding position in the N2-1 other N1-element interconnected computing matrices, wherein any N1-element interconnected computing matrix and the N2-1 other N1-element interconnected computing matrices constitute the Meta-extended interconnected computing matrix; for any Each of the computing units in the N-th element expansion interconnection computing matrix is ​​connected to the corresponding unit. M-m -1 other The computing units in corresponding positions in the meta-extension interconnected computing matrix are connected in communication, wherein any one Meta-extended interconnection computing matrix and the N M-m -1 other The meta-extension interconnected computing matrix is ​​composed of Meta-Extended Interconnected Computing Matrix.

[0063] like Figures 1 to 14 As shown, in the specific structure of the multi-channel signal real-time monitoring access system, the interconnection calculation matrix and the data access unit are the main bodies for multi-channel signal real-time monitoring access, and can be based on N M 、N M-1 、N M-m , N2, N1, and M can be used to arbitrarily expand the scale of the computing units, and the number of data access units required can be determined based on the needs of signal monitoring and access (such as single-channel data rate, number of transceiver channels, and / or data access duration, etc.). This allows for changing product features, expanding product functions, and adjusting channel scale based on different user needs, thereby resolving the issues of limited number of supported channels and high cost of building multi-channel systems in existing signal playback solutions on the market. In addition, since the construction of the aforementioned computing matrix is ​​completely symmetrical, when performing real-time monitoring and access of multi-channel signals, designing the embedded computing program for a certain computing unit can complete the embedded computing program for the entire computing matrix.

[0064] like Figure 1As shown, specifically, the computing unit includes but is not limited to a first FPGA module, a first storage module and a first high-speed serial interface, wherein the number of the first high-speed serial interfaces is multiple and is used to communicate and connect the signal transceiver unit or other computing units; the first FPGA module is respectively communicated to the first storage module and the first high-speed serial interface. The first FPGA (Field Programmable Gate Array) module is used for signal data transmission and analysis and calculation, which can be implemented specifically by using existing device products; the number of the first FPGA modules can be one or more, and when there are multiple, the multiple first FPGA modules can be interconnected through a high-speed communication interface, so that a large amount of signal data can be transmitted between the FPGA modules for storage and calculation (at this time, the computing unit composed of multiple first FPGA modules is still logically regarded as a whole computing unit to the outside world, thereby enhancing the computing power, storage capacity and number of high-speed serial interfaces of a single computing unit, and improving the overall computing power and expansion capability of the interconnected computing matrix). The first storage module (i.e. Figure 1 DRAM) is used to temporarily store the data to be calculated by the computing unit, which can be implemented by using dynamic random access memory (DRAM); when there are multiple first FPGA modules, each of the first FPGA modules can be independently connected to the first storage module (that is, there are multiple first storage modules). The first high-speed serial interface (that is, Figure 1The high-speed serial interface (D) is mainly used for the following five purposes: (a) high-speed interconnection with other computing units within the same circuit board; (b) high-speed interconnection with computing units in other circuit boards through high-speed serial interface connectors (such as QSFP28 or QSFP56 high-speed connectors); (c) connection with the high-speed serial interface of the signal transceiver unit; (d) connection with the high-speed serial interface of the data access unit; (e) connection with the high-speed serial interface of other peripherals. To be more specific, the first high-speed serial interface can be, but is not limited to, a Nano-Pitch interface, a MiniSAS HD (Serial Attached Small Computer System Interface, HD is the abbreviation of High Definition in English) interface, an SFP (Small Form Pluggable) interface, an SFP+ interface, a QSFP (Quad Small Form-factor Pluggable) interface, a QSFP+ interface, a QSFP28 interface or a QSFP56 interface, etc., preferably using a Nano-Pitch standard 42-pin (not limited to this standard) connector as a compact and high-speed connection interface, each connector can provide up to 6 bidirectional data transmission links with a unidirectional rate of up to 16 Gbps, a total of 96 Gbps (12 GB / s).

[0065] like Figure 2 As shown, the two computing units can communicate with each other through a high-speed serial interface to form a two-element interconnected computing matrix; the two-element interconnected computing matrix can be connected through a high-speed serial cable, or it can be implemented on the same circuit board. The latter can save high-speed serial connectors and cables, simplify the connection between each other, reduce the interconnection cost, and increase the interconnection data rate; the two computing units can exchange and share data at high speed through high-speed interconnection, and perform parallel calculations on different data at the same time, thereby increasing computing power. Moreover, the two two-element interconnected computing matrices can be further extended and interconnected through a high-speed serial interface to form a two 2 The 2-element interconnected computing matrix (the extended interconnection method is: each computing unit of one 2-element interconnected computing matrix is ​​connected to the computing units at the corresponding position of another 2-element interconnected computing matrix in pairs). 2 Each computing unit in the meta-extension interconnect matrix can exchange high-speed data with any other computing unit through at most one intermediate computing unit, thus ensuring that each computing unit can efficiently obtain the required data from other computing units.

[0066] Based on the above-mentioned construction method of the 2-element interconnected computing matrix, further: N1 computing units are fully interconnected (here fully interconnected means: any computing unit is directly connected to the other N1-1 computing units through high-speed serial connections) to form an N1-element interconnected computing matrix; for example, the 3-element interconnected computing matrix is ​​as follows Figure 3 As shown in (a) in the figure, the 4-element interconnection calculation matrix is ​​as follows Figure 3 As shown in (b), the 5-element interconnection calculation matrix is ​​as follows Figure 3 As shown in (c) in , and so on.

[0067] Based on the above 2 2 The construction method of the element-extension interconnection computing matrix is ​​further: an N1 element-interconnection computing matrix can be extended and interconnected with up to N2-1 other N1 element-interconnection computing matrices through a high-speed serial interface to construct a maximum N2×N1 element-extension interconnection computing matrix (the extension interconnection method is that each computing unit of the N1 element-interconnection computing matrix is ​​connected to the computing units at the corresponding position of other N1 element-interconnection computing matrices in pairs). For example, Figure 4 As shown: 3 3-element interconnection calculation matrices are expanded into 3×3-element extended interconnection calculation matrices; Figure 5 As shown: 4 3-element interconnection calculation matrices are expanded into 4×3-element extended interconnection calculation matrices; Figure 6 As shown: 4 4-element interconnection computing matrices are expanded into a 4×4-element expanded interconnection computing matrix, and so on.

[0068] Based on the above Figures 4-6 It can be seen that the topological structure in the N2×N1 element extended interconnected computing matrix is ​​completely symmetrical; that is, the position and connection relationship of each computing unit in the matrix are completely consistent and symmetrical with respect to other computing units, so each computing unit in the extended interconnected computing matrix is ​​equivalent, which makes the computing matrix very suitable for performing highly parallel and symmetrical computing and data transmission. In addition to the symmetry of the topological structure, each computing unit in the N2×N1 element extended interconnected computing matrix can complete data exchange with any other computing unit through at most one level of intermediate computing unit, thereby ensuring that each computing unit can easily establish a high-speed communication connection with other computing units directly or through different intermediate computing units. Such a data transmission topology is not easily caused by a central data exchange node causing a data transmission bottleneck. Therefore, an N2×N1 element extended interconnected computing matrix can be extended and interconnected with up to N3-1 other N2×N1 element interconnected computing matrices based on the same expansion method as above (where N3 represents an integer greater than or equal to 2), to construct a maximum of N3×N2×N1 element extended interconnected computing matrix (i.e. Meta-interconnection computing matrix), and can be further expanded to N M×N M-1 ×…×N M-m ×…×N2×N1 element extended interconnection calculation matrix (that is, the Meta-Extended Interconnection Computing Matrix). Each computing unit in the meta-extended interconnected computing matrix is ​​also equivalent, and high-speed data exchange between it and any other computing unit only requires passing through M-1 intermediate computing units at most. This decentralized switching topology ensures that there are high-speed transmission paths between computing units, and avoids the data exchange bottleneck caused by the central switching node during parallel data transmission to the greatest extent.

[0069] Based on the aforementioned expansion methods of the interconnected computing matrix, computing arrays of varying topologies and scales can be constructed. The greater the number of elements in the interconnected computing matrix and the greater the number of interconnect levels, the more signal transceivers and data access units the matrix can connect to. This increases the total number of channels, total playback bandwidth, and total storage capacity, thus accommodating larger-scale signal analysis, monitoring, and playback requirements.

[0070] In order to make the computing unit have a signal receiving channel and / or a signal transmitting channel, specifically, the computing unit is communicatively connected with K signal transceiver units, where K represents a positive integer (i.e., it can be a positive integer such as 1, 2 or 3. In addition, under certain conditions, the computing unit may not be connected with the signal transceiver unit), and the signal transceiver unit is used to provide a signal receiving channel, a signal transmitting channel or a signal transceiver channel (i.e., providing a signal receiving channel and a signal transmitting channel). The signal receiving channel is used to receive an input digital signal obtained based on the conversion of the input analog signal or to receive an input analog signal and convert it into an input digital signal. The signal transmitting channel is used to send an output digital signal for conversion into an output analog signal or to directly convert the output digital signal into an output analog signal and send it out. Since the computing input of the aforementioned interconnected computing matrix usually comes from an external radio frequency signal, and the computing output usually also needs to be sent to the outside, the signal transceiver unit is required to collect, acquire, generate and send. In addition to being responsible for the high-speed transmission and reception of digital signals or analog signals, the signal transceiver unit can also perform signal processing according to specific needs. It is mainly composed of an FPGA module and a high-speed serial interface. Specifically, when the signal transceiver unit is used to provide a signal receiving channel and a signal transmitting channel, and the signal receiving channel is used to receive an input analog signal and convert it into an input digital signal, and the signal transmitting channel is used to directly convert an output digital signal into an output analog signal and send it out, the signal transceiver unit includes but is not limited to an analog receiving front-end module, an analog transmitting front-end module, an ADC module, a DAC module, a second FPGA module, a second storage module, and a second high-speed serial interface, etc., wherein the analog receiving front-end module is used to receive the input analog signal, the analog transmitting front-end module is used to send the output analog signal, and the second high-speed serial interface is used to communicatively connect to the computing unit; the output end of the analog receiving front-end module is communicatively connected to the input end of the ADC module, the output end of the ADC module is communicatively connected to the input end of the second FPGA module, the input end of the analog transmitting front-end module is communicatively connected to the output end of the DAC module, the input end of the DAC module is communicatively connected to the output end of the second FPGA module, and the second FPGA module is also communicatively connected to the second storage module and the second high-speed serial interface respectively.

[0071] like Figure 7As shown, in the specific structure of the signal transceiver unit, the analog receiving front-end module and the analog transmitting front-end module respectively correspond to the ADC module and the DAC module, and are used to convert, amplify, condition, filter, receive and transmit analog signals, and realize the conversion between analog signals and digital signals. The second FPGA module has high-speed data throughput capability and is a key component connecting the ADC / DAC and the analog front end. Its characteristics suitable for high-speed parallel fixed-point number calculations can provide real-time signal preprocessing capabilities for the system. On the one hand, it can complete part of the signal processing work, and on the other hand, it can also complete the extraction and compression of effective data, reducing the amount of data transmitted between the back-end signal processor. The second FPGA module can also have a signal processing delay as low as nanoseconds, and realize low-latency signal transmission and reception through the ADC module and the DAC module. The second storage module specifically includes but is not limited to DRAM and FLASH, wherein the former is used for local caching and temporary storage of high-speed signal data, and the latter is used to store firmware programs. The second high-speed serial interface can be specifically implemented as a high-speed serial bus interface using the Aurora communication protocol, that is, preferably using the Aurora 16Gbps x6 or higher high-speed serial transmission protocol, which has a peak data throughput of 11GB / s and a transmission delay as short as microseconds. It can provide a sufficiently large transmission bandwidth and a sufficiently short transmission delay for most real-time signal processing applications, ensure the continuity and timeliness of data transmission, and provide the basic conditions for real-time signal processing; the second high-speed serial interface further preferably uses the Nano-Pitch series connectors produced by Molex, which can provide a maximum data transmission capacity of 25Gbps x8, which is sufficient to meet the full-duplex transmission requirements of two 2GHz instantaneous bandwidth signals.

[0072] Further preferably, the signal transceiver unit further includes but is not limited to a clock and trigger signal interface, an onboard OCXO module, and a clock generation and distribution circuit module based on a phase-locked loop mechanism, wherein the clock and trigger signal interface ( Figure 7 The onboard OCXO module ( Figure 7 The trigger signal output terminal of the clock and trigger signal interface is communicatively connected to the second FPGA module, the non-trigger signal output terminal of the clock and trigger signal interface and the time base signal output terminal of the onboard OCXO module are communicatively connected to the input terminal of the clock generation and distribution circuit module respectively, and the clock generation and distribution circuit module ( Figure 7The clock signal output end of the analog receiving front-end module (represented by PLL in the figure) is respectively communicatively connected to the analog receiving front-end module, the analog transmitting front-end module, the ADC module, the DAC module and the second FPGA module. The connector of the clock and trigger signal interface can be selected according to the specific signal frequency and quantity. The sampling clock signal, the reference clock signal, the GPS second pulse signal and the time base signal are used to provide clock signals to the analog receiving front-end module, the analog transmitting front-end module, the ADC module, the DAC module and the second FPGA module respectively through the clock generation and distribution circuit module based on the phase-locked loop. The trigger signal is connected to the second FPGA module and is used for internal processing logic triggered by external events. In this way, through the aforementioned clock and trigger mechanism, multiple parallel or distributed signal transceiver units can work synchronously to achieve the reception or transmission of coherent signals.

[0073] The interconnection computing matrix can connect the signal transceiver units to transmit and receive analog signals according to the signal monitoring access requirements; the number of signal receiving channels and signal transmitting channels provided by each signal transceiver unit can be different and can also be set according to the signal monitoring access requirements. Since the connection between the complete interconnection computing matrix and the signal transceiver units is also completely symmetrical, for the Meta-extended interconnected computing matrix, if all N M ×N M-1 ×…×N M-m ×…×N2×N1 computing units are connected ( represents a positive integer) the signal transceiver units, and each of the signal transceiver units has J pairs of transceiver channels, then the multi-channel signal real-time monitoring access system has a total of For the transceiver channel, an H-receiver and H-transmitter signal monitoring and access system is formed. This connection method of the interconnected computing matrix and the signal transceiver unit can just meet the needs of multi-channel signal monitoring and access: (1) Each signal transceiver channel has a directly connected computing unit, which can simultaneously complete real-time signal analysis and monitoring; (2) The signal data of multiple channels can use fully interconnected communication connections to realize combined signal processing real-time calculation, and realize multi-channel joint analysis and monitoring; (3) Any data access unit can be connected to any signal transceiver unit for high-speed data storage and playback, so that the data access unit and the signal transceiver unit no longer need to be paired one to one, which is conducive to reducing costs; (4) The number of signal transceiver units and data access units can be increased or decreased as needed, and the connection topology can be expanded or split as needed. At the same time, according to the structure of the signal transceiver unit, it can be seen that the signal transceiver unit actually also includes the structure of the computing unit, that is, the combination of FPGA, DRAM and high-speed serial port. Therefore, when the signal transceiver unit is connected to the interconnected computing matrix, it is actually equivalent to connecting a new computing unit to each node of the interconnected computing matrix. Figure 8 As shown in the figure, in the 4×3 element interconnected computing matrix, each computing unit is connected to two signal transceiver units, and the signal transceiver units receive and send radio frequency signals. Since the signal transceiver units contain computing unit structures, this interconnected computing matrix is ​​equivalent to being expanded as follows: Figure 9The extended interconnected computing matrix topology is shown. Although each computing unit of the extended interconnected computing matrix does not have sufficient computing unit interconnection like the interconnected computing matrix or the extended interconnected computing matrix (that is, each computing unit is interconnected with other computing units by multiple high-speed serial interfaces), the computing power of each computing unit of the original extended interconnected computing matrix has been enhanced, which enables the extended interconnected computing matrix to perform not only completely symmetrical channel simulation calculations, but also further signal processing related to the devices connected to each channel simulation port, that is, further preferably, when the signal transceiver unit includes a second FPGA module and a second storage module and a second high-speed serial interface respectively connected to the second FPGA module for communication, the signal transceiver unit is also used as a relative to the computing unit The extended computing unit can be used to share the computing tasks of the computing unit. In addition, the extended computing unit can also be used to perform any one of the following extended computing tasks (A) to (I) or any combination thereof: (A) increasing the instantaneous bandwidth of the signal using interpolation processing; (B) reducing the instantaneous bandwidth of the signal using decimation processing; (C) changing the center frequency of the signal using digital frequency conversion; (D) calculating the signal spectrum in real time; (E) calculating the target echo or clutter in real time; (F) simulating the phase offset of the signal reaching each port of the multi-channel direction-finding receiver; (G) simulating the signal amplitude and phase of each channel in the radar sum channel and auxiliary channel; (H) transmitting and receiving data via a high-speed serial bus; (I) performing amplitude calibration and phase calibration of the transmitted and received signals. The aforementioned extended computing capability greatly increases the computing and analysis functions of the multi-channel signal real-time monitoring and access system. Figure 9 The topology of the 4×3 element interconnected computing matrix after the calculation is extended is shown. Similarly, all The extended interconnected computing matrix can be formed by connecting the signal transceiver unit to any number of computing units, such as Figure 10 As shown, 3 2 The interconnected computing matrix is ​​extended, and each computing unit is connected to a signal transceiver unit. Furthermore, the computing input of the interconnected computing matrix can also be injected as a digital signal via a high-speed serial interface, and its computing output can also be output as a digital signal via a high-speed serial interface. In this case, the relevant computing units do not need to be connected to the signal transceiver unit.

[0074] The data access unit is used to be responsible for the implementation of signal data transmission, storage and reading, etc. Figure 11Specifically, the data access unit includes, but is not limited to, a third FPGA module, a third storage module, a third high-speed serial interface, and a data buffer storage group. There is at least one third high-speed serial interface for communication with the computing unit. The data buffer storage group includes a dynamic random access memory for data buffering and a solid-state drive for data storage. The third FPGA module is communicatively connected to the third storage module, the third high-speed serial interface, the dynamic random access memory, and the solid-state drive, respectively. The FPGA device in the third FPGA module is also a semi-custom circuit within an application-specific integrated circuit (ASIC). It is a programmable logic array with high-speed data throughput, high-speed logic, and timing control capabilities, making it suitable for implementing functions such as high-speed serial buses, real-time signal processing, sequential logic, and trigger timing. Since high-performance FPGA chips usually have multiple MGTs (Multi-Gigabit Transceivers), that is, high-speed serial transceivers, multiple PCIe (Peripheral component interconnect express, a high-speed serial computer expansion bus standard, its original name was "3GIO", which was proposed by Intel in 2001 to replace the old PCI, PCI-X and AGP bus standards) resources and a large number of digital I / O channels (these MGTs, PCIe resources and digital I / O channels can implement high-speed communication protocols between FPGA and external devices, including Aurora, PCIe, NVMe, SATA, Serial RapidIO, JESD204 and / or USB, etc.), the data access unit can implement the control interface of the PCIe bus or the PCIe-based instrument expansion bus (such as PXIe, CPCIe, VPX, etc.) on the PCIe resources and digital I / O channels on the FPGA chip (because mainstream FPGA manufacturers all provide soft cores and hard cores of the PCIe protocol, the PCIe protocol here preferably adopts PCIe Gen3 x8, and is represented by PCIe in the figure). The IP identifier is used to abstract and manage the data access unit into a standard PCIe disk device. Specifically, the third storage module (in Figure 11 A flash memory is used to store the firmware program of the third FPGA module.

[0075] The third high-speed serial interface preferably uses 4 to 6 MGT (not limited to this number) full-duplex serial links, and preferably uses the Aurora protocol (not limited to this protocol) to achieve data communication, and preferably uses the Nano-Pitch standard 42-pin (not limited to this standard) connector as a compact and high-speed connection interface. Each Nano-Pitch interface can provide up to 6 full-duplex Aurora links with a speed of up to 16Gbps, and can provide a total bidirectional data transmission capacity of 96Gbps or 12GB / s in each direction (not limited to this number of links and total speed); that is, the third high-speed serial interface (in Figure 11 The "Nano-Pitch" designation (indicated by "Nano-Pitch" in this context) preferably utilizes a Nano-Pitch interface. The aforementioned Nano-Pitch connector features a compact size of 5.0 x 15.0 x 9.0 mm and a connector-to-cable assembly height of 12.0 mm. This allows for the arrangement of multiple high-speed data transmission interfaces on a compact panel, while simultaneously offering extremely high data transmission performance and convenient plug-in connectivity. Furthermore, the third high-speed serial interface may also utilize, but is not limited to, a MiniSAS HD interface, SFP interface, SFP+ interface, QSFP interface, QSFP+ interface, QSFP28 interface, or QSFP56 interface.

[0076] The number of the data buffer storage groups can be multiple, so as to achieve parallel data storage and reading through collaborative work. Figure 11 DRAM) and the solid-state drive (in Figure 11 The SATA / NVMe SSD may be connected to the third FPGA module by using, but not limited to, a SATA (Serial ATA) interface or an NVMe (NVM Express, or non-volatile memory host controller interface specification) interface. Figure 11As shown, the IP used to control and communicate with SATA / NVMe SSD (Solid State Disk or Solid State Drive) on the FPGA is identified by IP3; the IP used to control and communicate with DRAM on the FPGA is identified by IP4; the FPGA obtains a high-speed data stream through the MGT IP, splits and encodes the data stream, and writes it in parallel to the SATA / NVMe SSDs of the multiple data buffer storage groups. The writing process uses the DRAM of the same group for data buffering to achieve smooth data writing; the reading process is the same. The FPGA reads data from the SATA / NVMe SSDs of the multiple data buffer storage groups. The reading process uses the DRAM of the same group for data buffering, and then decodes and restores the original data stream, and sends the data stream out through the MGT IP. The data access unit utilizes the FPGA's PCIe (PCI-Express, full name Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) resources and digital I / O channels as well as PCIe IP to build a control interface. The host computer can implement convenient data access and management of multiple SATA / NVMe SSDs according to standard disk objects through the management and scheduling of the FPGA in the data access unit. Figure 11 As shown, the data access unit also includes a PCIe bus control interface or a PCIe-based instrument expansion bus control interface (in communication connection with the third FPGA module) Figure 11 "PCIe" is used in the specification), wherein the PCIe bus control interface or the instrument expansion bus control interface is used to communicate with the control interface of an external host computer, so that the external host computer can read the data in multiple groups of SATA / NVMe SSDs at any time.

[0077] The data access unit is communicatively connected to the computing unit, and establishes a one-to-one connection relationship, a one-to-many connection relationship, or a many-to-one connection relationship with the signal channel on the computing unit, wherein the signal channel is a signal receiving channel, a signal transmitting channel, or a signal transceiver channel. The aforementioned one-to-one connection relationship means that one signal channel corresponds to one data access unit, so as to be applicable to situations where simultaneous data access is required on all signal channels; the aforementioned one-to-many connection relationship means that one signal channel corresponds to multiple data access units, so as to be applicable to situations where the data access time is long and the capacity of one data access unit is insufficient; the aforementioned many-to-one connection relationship means that multiple signal transceiver channels correspond to one data access unit, so as to be applicable to situations where not all signal channels need to access data, in which case the signal channel of interest can be selected for data access. In addition, in the multi-channel signal real-time monitoring and access system, the one-to-one connection relationship, the one-to-many connection relationship and / or the many-to-one connection relationship may exist simultaneously for different multiple signal channels. For example, one signal channel and the data access unit have the one-to-many connection relationship, while the other signal channels and the data access unit have the many-to-one connection relationship.

[0078] Since the position and connection relationship of each computing unit in the interconnected computing matrix are completely consistent and symmetrical, the interconnected computing matrix can be decomposed layer by layer outward with any computing unit as the center into at least two-order computing resources: the computing resources in any computing unit are divided into zero-order computing resources, and the computing resources in all other computing units in the N1-element interconnected computing matrix where any computing unit is located are divided into first-order computing resources. When the element interconnection calculation matrix is ​​expanded, the N1 element interconnection calculation matrix will also be located at the location of the N1 element interconnection calculation matrix. All computing resources within the N1 meta-interconnect computing matrix within the meta-extended interconnect computing matrix are classified as second-order computing resources, and the same logic is used to determine Mm-order computing resources, M-1-order computing resources, and M-order computing resources. Because the aforementioned second-order computing resources require a one-to-one high-speed serial connection with the central computing unit through at most one computing unit, their access speed is slower than that of the first-order computing resources, and their data transmission latency is also lower than that of the first-order computing resources; and so on. Based on the aforementioned computing resource topology, in order to minimize the data transmission delay between the signal channel and the data access unit, preferably, the one-to-one connection relationship, one-to-many connection relationship or many-to-one connection relationship between the data access unit and the signal channel on the computing unit is established in the following manner: taking the computing unit having the signal channel in the interconnected computing matrix as the central computing unit, the interconnected computing matrix is ​​decomposed outward layer by layer into at least two-order computing resources in the following manner: the computing resources in the central computing unit are divided into zero-order computing resources, the computing resources in all other computing units in the N1-element interconnected computing matrix where the central computing unit is located are divided into first-order computing resources, and the computing resources in the interconnected computing matrix are divided into the first-order computing resources. When the element interconnection calculation matrix is ​​expanded, the N1 element interconnection calculation matrix will also be located at the location of the N1 element interconnection calculation matrix. The computing resources in all other N1 meta-interconnected computing matrices in the meta-extended interconnected computing matrix are divided into second-order computing resources, and the Mm-order computing resources, M-1-order computing resources and M-order computing resources are determined by analogy; if there are at least two connectable computing units with different computing resource orders in the interconnected computing matrix, the computing resources in the unit are divided into low-order computing resources and the connectable computing unit is selected to communicate with the data access unit; if there are at least two connectable computing units with the same computing resource order in the interconnected computing matrix, the connectable computing unit is arbitrarily selected to communicate with the data access unit.

[0079] The data access unit is used to monitor and store the signal data collected by the signal channel in real time, and / or read local signal data and send it out through the signal channel.

[0080] Preferably, a control computer is further included, wherein the control computer is communicatively connected to the controlled end of each computing unit in the extended interconnected computing matrix and is used to read and write parameters and / or data of the computing units. Figure 1 and Figure 2 As shown, the controlled end of the computing unit is specifically the control bus interface (ie Figure 1The bus interface circuitry is preferably connected to the bus interface circuitry using the PCIe bus or a PCIe-based instrument expansion bus (such as PXIe, CPCIe, and VPX) as the communication and control bus. The PCIe bus and PCIe-based instrument expansion buses have a mature and comprehensive hardware and software ecosystem, making it easy for users to add a variety of I / O modules based on these bus platforms and utilize sophisticated system and data management software to control and manage the system. These bus platforms also offer a modular architecture, allowing users to easily expand system functionality and capabilities with a variety of modules.

[0081] Here, taking an N2xN1 extended interconnection computing matrix as an example, each computing unit and the signal transceiver channel are numbered: in the computing unit numbering rule U(N2,N1), N1 is the position of each computing unit in each interconnection computing matrix, N2 is the position of each interconnection computing matrix in the extended interconnection computing matrix, the value of N1 is from 0 to N1-1, and the value of N2 is from 0 to N2-1; if the computing unit is connected to the signal transceiver unit, the signal transceiver channels provided by the signal transceiver unit are numbered R(N2,N1,J) receiving channel and T(N2,N1,J) transmitting channel, respectively, where J is the Jth signal transceiver channel connected to this computing unit (the value starts from 0), N1 is the position of each computing unit in each interconnection computing matrix, and N2 is the position of each interconnection computing matrix in the extended interconnection computing matrix.

[0082] Implementation Example 1:

[0083] like Figure 12 (As shown in this example diagram, the connection lines between each computing unit and the signal transceiver unit: solid lines represent utilized high-speed connections, dashed lines represent unused high-speed connections, and dot-dash lines represent high-speed connections between computing units and signal transceiver units) This embodiment establishes a one-to-one connection relationship between the signal channel and the data access unit: each computing unit is connected to a group of signal transceiver channels, namely, the R(N2,N1,0) receiving channel and the T(N2,N1,0) transmitting channel. At the same time, each computing unit is connected to one data access unit, denoted as S(N2,N1,). Each data access unit S(N2,N1,) is responsible for real-time monitoring and storage of data collected by the R(N2,N1,0) receiving channel on the S(N2,N1,) computing unit, as well as reading local signal data and transmitting it through the T(N2,N1,0) transmitting channel.

[0084] Implementation Example 2:

[0085] like Figure 13(In this example diagram, the connection lines between the computing units and the signal transceiver units: solid lines represent utilized high-speed connections, dashed lines represent unused high-speed connections, and dot-dash lines represent high-speed connections between the computing units and the signal transceiver units) As shown, this embodiment establishes a many-to-one connection relationship and a one-to-many connection relationship between the signal channel and the data access unit:

[0086] (A) The nine computing units including the U(0,x) computing unit, the U(2,x) computing unit and the U(3,x) computing unit are used to participate in establishing a many-to-one connection relationship: each computing unit is connected to a set of signal transceiver channels, namely the R(N2,N1,0) receiving channel and the T(N2,N1,0) transmitting channel, and only one data access unit S(0,0) is connected to the U(0,0) computing unit (the U(0,0) computing unit is arbitrarily selected because the computing resources are of the same order); and except for the U(0,0) computing unit, the For the other eight computing units except the U(0,0) computing unit, the data collected by the signal transceiver channel connected to the computing unit needs to be transmitted to the U(0,0) computing unit through the high-speed serial connection relationship between the computing units, and then transmitted to the data access unit S(0,0) for storage; and the data read by the data access unit S(0,0) needs to be transmitted to the other eight computing units except the U(0,0) computing unit through the high-speed serial connection relationship between the computing units, and then transmitted through the signal transceiver channel connected to the other computing units;

[0087] (B) The three computing units including the U(1,x) computing unit are used to participate in establishing a one-to-many connection relationship: the U(1,0) computing unit is connected to a group of signal transceiver channels, namely the R(1,0,0) receiving channel and the T(1,0,0) transmitting channel, and is connected to a data access unit S(1,0), a data access unit S(1,1) and a data access unit S(1,2) on the U(1,0) computing unit, the U(1,1) computing unit and the U(1,2) computing unit respectively (although the computing resource orders of the U(1,0) computing unit, the U(1,1) computing unit and the U(1,2) computing unit are different, they can only be connected to one data access unit); the signal receiving unit connected to the U(1,0) computing unit is the data access unit of the U(1,0) computing unit. The data collected by the transmission channel can be transmitted to the data access unit S(1,0) for storage, or can be transmitted to the data access unit S(1,1) or the data access unit S(1,2) for storage through the high-speed serial connection between the U(1,0) computing unit and the U(1,1) computing unit or the U(1,2) computing unit; and the data read by the data access unit S(0,0) can be transmitted through the signal transceiver channel connected to the U(1,0) computing unit, and at the same time, the data read by the data access unit S(1,1) or the data access unit S(1,2) can first be transmitted to the U(1,0) computing unit through the high-speed serial connection relationship between the computing units, and then transmitted through the signal transceiver channel connected to the U(1,0) computing unit.

[0088] Implementation Example 3:

[0089] like Figure 14 (In this example diagram, the connection lines between each computing unit and the signal transceiver unit: the solid line represents the used high-speed connection, the dotted line represents the unused high-speed connection, and the dot-dash line represents the high-speed connection between the computing unit and the signal transceiver unit) As shown, this embodiment establishes multiple many-to-one connection relationships between the signal channel and the data access unit:

[0090] (C) There are 4 groups of 12 computing units, including the U(x,0) computing unit, the U(x,1) computing unit, and the U(x,2) computing unit, which are used to participate in establishing 4 many-to-one connection relationships: each computing unit is connected to a group of signal transceiver channels, namely the R(N2,N1,0) receiving channel and the T(N2,N1,0) transmitting channel, and only one data access unit S(x,0) is connected to the U(x,0) computing unit. In each many-to-one connection relationship, the signal transceiver channel connected to the U(x,0) computing unit can directly transmit the collected data to the data access unit S(x,0) for storage, and the data read by the data access unit S(x,0) can be directly transmitted to the signal transceiver channel connected to the U(x,0) computing unit for transmission; the other two computing units except the U(x,0) computing unit need to first transmit the data collected by the signal transceiver channel connected to them to the U(x,0) computing unit through the high-speed serial connection relationship between the computing units, and then transmit it to the data access unit S(x,0) for storage; and the data read by the data access unit S(x,0) needs to first be transmitted to the other two computing units except the U(x,0) computing unit through the high-speed serial connection relationship between the computing units, and transmitted through the signal transceiver channel connected to the other computing units.

[0091] In summary, the multi-channel signal real-time monitoring access system provided by this embodiment has the following technical effects:

[0092] (1) This embodiment provides a new solution for real-time monitoring and access of multi-channel signals that can be flexibly expanded in scale, namely, it includes an interconnection computing matrix and a data access unit, wherein the interconnection computing matrix is ​​an N1-element interconnection computing matrix or an N M The invention provides an interconnected computing matrix. On the one hand, by expanding the connection relationships between the interconnected computing matrix layers, between the expanded interconnected computing matrix and the interconnected computing matrix, and between the computing units within the interconnected computing matrix, computing arrays of different topologies and different scales can be constructed. The more array elements in the interconnected computing matrix and the more levels of expansion, the larger the scale of the computing matrix, the greater the total computing power and storage space, thereby adapting to real-time signal analysis, data recording, and data playback with different numbers of channels. On the other hand, by designing decoupled computing units and data access units, it is convenient to flexibly configure according to the channel and capacity requirements of analog signals, digital signals, and disk playback, thereby reducing overall costs. This can solve the problems of existing signal disk playback solutions, such as a small number of supported channels, fixed signal connection relationships, lack of multi-channel real-time analysis capabilities, and / or high cost of building multi-channel systems, and facilitate practical application and promotion.

[0093] (2) Flexible expansion and splitting: The computing topology designed in this embodiment is applicable to signal monitoring and access systems with a few to several hundred channels. It can easily expand a small-scale signal monitoring and access system into a large-scale system, and can also easily split a large-scale system into several small-scale systems.

[0094] (3) Integrated computing and storage: The access system designed in this embodiment integrates storage and computing capabilities, so that signal analysis and processing can be performed on data before storage or after reading.

[0095] (4) Diversified access connection relationships: One-to-many, one-to-one, and many-to-one connection relationships can be established between signal channels and data access units. This allows the access system designed in this embodiment to adopt different configurations to accommodate various application scenarios such as storage capacity expansion, parallel analysis storage, and multi-channel flexible storage. Furthermore, multiple connection relationships can coexist, making the device highly flexible.

[0096] (5) Low cost: Due to the standardization of computing units and data access units, the construction and expansion of large-scale signal monitoring and access systems no longer need to be customized, thus achieving low cost. At the same time, the many-to-one access connection relationship can also significantly reduce the number of data access units when multi-channel data acquisition and reading, thereby significantly reducing costs.

[0097] (6) Easy configuration: Since the computing topology designed in this embodiment is a completely symmetrical structure, it is only necessary to design the algorithm and program for a single computing unit to complete the algorithm and program design for the entire computing matrix;

[0098] (7) Customizable: The signal transceiver unit provides extended computing power, and the implementation of this computing power is completely decoupled from the computing matrix, so it is easy to provide customized signal processing capabilities for signal monitoring and access port devices.

[0099] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of protection of the present invention.

Claims

1. A multi-channel signal real-time monitoring and access system with flexible scalability, characterized by: It includes an interconnection calculation matrix and a data access unit, wherein the interconnection calculation matrix is ​​an N1-element interconnection calculation matrix or Meta-Extended Interconnected Computing Matrix, the The meta-extension interconnection computing matrix includes N M indivual Meta-Extended Interconnected Computing Matrix, the The meta-extension interconnection computing matrix includes N M-1 indivual Meta-extended interconnected computing matrix, and so on The meta-extension interconnection computing matrix includes N M-m indivual Meta-extended interconnected computing matrix until The element-extension interconnection computing matrix includes N2 N1 element-interconnection computing matrices, and the N1 element-interconnection computing matrix includes N1 computing units. N M ×N M-1 ×…×N M-m The abbreviation of ×…×N2×N1, N M 、N M-1 、N M-m , N2 and N1 respectively represent integers greater than or equal to 2, M represents an integer greater than or equal to 2, m exists when M is greater than or equal to 3, and represents an integer greater than or equal to 0 and less than M-2; Any two of the N1 computing units are communicatively connected; For each of the computing units in any N1-element interconnected computing matrix, the corresponding unit is connected to the computing units in the corresponding positions in N2-1 other N1-element interconnected computing matrices, wherein the any N1-element interconnected computing matrix and the N2-1 other N1-element interconnected computing matrices constitute the Meta-Extended Interconnected Computing Matrix; For any Each of the computing units in the N-th element expansion interconnection computing matrix is ​​connected to the corresponding unit. M-m -1 other The computing units in corresponding positions in the meta-extension interconnected computing matrix are connected in communication, wherein any one Meta-extended interconnection computing matrix and the N M-m -1 other The meta-extension interconnected computing matrix is ​​composed of Meta-Extended Interconnected Computing Matrix; The data access unit is communicatively connected to the computing unit and establishes a one-to-one connection relationship, a one-to-many connection relationship, or a many-to-one connection relationship with a signal channel on the computing unit, wherein the signal channel is a signal receiving channel, a signal transmitting channel, or a signal transceiver channel; The data access unit is used to monitor and store the signal data collected by the signal channel in real time, and / or read local signal data and send it out through the signal channel.

2. The multi-channel signal real-time monitoring and access system according to claim 1, wherein: A one-to-one connection relationship, a one-to-many connection relationship, or a many-to-one connection relationship between the data access unit and the signal path on the computing unit is established in the following manner: Taking the computing unit with the signal channel in the interconnected computing matrix as the central computing unit, the interconnected computing matrix is ​​decomposed layer by layer into at least two-order computing resources in the following manner: the computing resources in the central computing unit are divided into zero-order computing resources, the computing resources in all other computing units in the N1-element interconnected computing matrix where the central computing unit is located are divided into first-order computing resources, and the computing resources in the interconnected computing matrix for the signal channel are divided into first-order computing resources. When the element interconnection calculation matrix is ​​expanded, the N1 element interconnection calculation matrix will also be located at the location of the N1 element interconnection calculation matrix. The computing resources in all other N1 element interconnection computing matrices in the element extension interconnection computing matrix are divided into second-order computing resources, and the Mm-order computing resources, M-1-order computing resources and M-order computing resources are determined by analogy; If there are at least two connectable computing units with different computing resource orders in the interconnected computing matrix, the computing resources in the selected unit are divided into low-order computing resources and the connectable computing unit is communicatively connected to the data access unit; If there are at least two connectable computing units with the same computing resource order in the interconnected computing matrix, the connectable computing unit is arbitrarily selected to be communicatively connected to the data access unit.

3. The multi-channel signal real-time monitoring and access system according to claim 1, wherein: It also includes a control computer, wherein the control computer is communicatively connected to the controlled ends of the various computing units in the interconnected computing matrix, and is used to perform read and write operations on the parameters and / or data of the computing units.

4. The multi-channel signal real-time monitoring and access system according to claim 1, wherein: The computing unit includes a first FPGA module, a first storage module and a first high-speed serial interface, wherein the first high-speed serial interface has at least one and is used for communication connection with a signal transceiver unit or other computing units; The first FPGA module is communicatively connected to the first storage module and the first high-speed serial interface respectively.

5. The multi-channel signal real-time monitoring and access system according to claim 1, wherein: The computing unit is communicatively connected to K signal transceiver units, where K represents a positive integer, and the signal transceiver units are used to provide a signal receiving channel, a signal transmitting channel, or a signal transceiver channel.

6. The multi-channel signal real-time monitoring and access system according to claim 5, wherein: When the signal transceiver unit is used to provide a signal receiving channel and a signal transmitting channel, and the signal receiving channel is used to receive an input analog signal and convert it into an input digital signal, and the signal transmitting channel is used to directly convert an output digital signal into an output analog signal and send it out, the signal transceiver unit includes an analog receiving front-end module, an analog transmitting front-end module, an ADC module, a DAC module, a second FPGA module, a second storage module, and a second high-speed serial interface, wherein the analog receiving front-end module is used to receive the input analog signal, the analog transmitting front-end module is used to send the output analog signal, and the second high-speed serial interface is used to communicate with the computing unit; The output end of the analog receiving front-end module is communicatively connected to the input end of the ADC module, the output end of the ADC module is communicatively connected to the input end of the second FPGA module, the input end of the analog transmitting front-end module is communicatively connected to the output end of the DAC module, the input end of the DAC module is communicatively connected to the output end of the second FPGA module, and the second FPGA module is also communicatively connected to the second storage module and the second high-speed serial interface respectively.

7. The multi-channel signal real-time monitoring and access system according to claim 5, wherein: When the signal transceiver unit includes a second FPGA module and a second storage module and a second high-speed serial interface respectively connected to the second FPGA for communication, the signal transceiver unit is also used as an extended computing unit relative to the computing unit to share the computing tasks of the computing unit.

8. The multi-channel signal real-time monitoring and access system according to claim 1, wherein: The data access unit includes a third FPGA module, a third storage module, a third high-speed serial interface, and a data buffer storage group, wherein the third high-speed serial interface has at least one and is used for communication connection with the computing unit, and the data buffer storage group includes a dynamic random access memory for data buffering and a solid-state hard disk for data storage; The third FPGA module is communicatively connected to the third storage module, the third high-speed serial interface, the dynamic random access memory and the solid state drive respectively.

9. The multi-channel signal real-time monitoring and access system according to claim 8, wherein: The data access unit also includes a PCIe bus control interface or a PCIe-based instrument extension bus control interface that is communicatively connected to the third FPGA module, wherein the PCIe bus control interface or the instrument extension bus control interface is used to communicate with the control interface of an external host computer.

10. The multi-channel signal real-time monitoring and access system according to claim 8, wherein: The third storage module uses flash memory to store the firmware program of the third FPGA module, and the third high-speed serial interface uses a Nano-Pitch interface, a MiniSAS HD interface, an SFP interface, an SFP+ interface, a QSFP interface, a QSFP+ interface, a QSFP28 interface or a QSFP56 interface.

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