Multi-hop time synchronization precision test system and method

Abstract

The invention provides a multi-hop time synchronization precision test system and method, a simulation device module comprises a plurality of test boards with multi-domain switching chips, and each multi-domain switching chip is provided with a time synchronization domain to form a cascade network; the tester sends a time synchronization message to the simulation equipment module, and a sending timestamp is stamped in the time synchronization message; the simulation equipment module receives the time synchronization message and transmits the time synchronization message in the cascade network; the input port bound with each time synchronization domain receives the time synchronization message, carries out time synchronization and prints a receiving timestamp, and the output port bound with each time synchronization domain prints a sending timestamp when sending the time synchronization message; the tester also receives a time synchronization message sent by the last time synchronization domain in the cascade network, and calculates the time synchronization precision. Through the multi-domain function of the multi-domain switching chip, one domain simulates one intermediate node device, so that the test cost is reduced, and the occupation of hardware resources is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of network communication and time synchronization, and in particular to a system and method for testing the accuracy of time synchronization with multiple hops. Background Art

[0002] According to the requirements of 802.3AS2020, after completing synchronization, devices that support gPTP (Generalized Precision Time Protocol) need to meet the end-to-end time difference within 7 hops (number of hops) within 1 microsecond. The traditional test method requires 6 boards to be cascaded for testing, such as Figure 1 The traditional testing method requires at least 6 intermediate node devices, bridges, to perform networking tests. Especially for FPGA testing before chip production, at least 6 FPGA boards need to be cascaded for performance testing, which takes up a lot of hardware resources and is costly. Summary of the invention

[0003] Based on the above problems, the present invention provides a multi-hop time synchronization accuracy test system and method, which aims to solve the technical problems of high cost of multiple time synchronization accuracy test equipment in the prior art.

[0004] A multi-hop time synchronization accuracy test system, comprising a simulation device module and a tester;

[0005] The simulation device module includes multiple test boards, and a multi-domain switching chip is arranged on each test board;

[0006] Each multi-domain switch chip sets a time synchronization domain, and the test board binds a unique input port and output port to each time synchronization domain;

[0007] The time synchronization domains in the multi-domain switching chips on each test board are networked and cascaded to form a cascade network;

[0008] The tester is used to: form a time synchronization message, send the time synchronization message to the simulation device module, and put a sending timestamp in the time synchronization message;

[0009] The analog device module is used to: receive time synchronization messages and transmit time synchronization messages in the cascade network;

[0010] Each input port bound to a time synchronization domain receives a time synchronization message and performs time synchronization and adds a receiving timestamp. Each output port bound to a time synchronization domain adds a sending timestamp when sending a time synchronization message.

[0011] The tester is also used to: receive the time synchronization message sent by the last time synchronization domain in the cascade network, add a receiving timestamp, and calculate the time synchronization accuracy based on the sending timestamp and receiving timestamp added by itself to the time synchronization message.

[0012] Furthermore, in a cascade network, the two time synchronization domains for network communication are not in the same multi-domain switching chip.

[0013] Furthermore, each time synchronization domain in the same multi-domain switch chip has a unique domain number;

[0014] In the cascade network, a test mode is added to the output port bound to each time synchronization domain. In the test mode, the domain code carried by the time synchronization message is modified to the domain code of the next time synchronization domain in the cascade network, and then the time synchronization message is sent to the next time synchronization domain.

[0015] Further, the hop count is 7;

[0016] The simulation device module includes two test boards, each of which has a multi-domain switch chip, and each multi-domain switch chip has three time synchronization domains; the cascade network formed is:

[0017] An input port bound to a first time synchronization domain of a first multi-domain switch chip communicates with an output port of a tester;

[0018] The output port bound to the first time synchronization domain of the first multi-domain switch chip communicates with the input port bound to the first time synchronization domain of the second multi-domain switch chip;

[0019] The output port bound to the first time synchronization domain of the second multi-domain switch chip communicates with the input port bound to the second time synchronization domain of the first multi-domain switch chip;

[0020] The output port bound to the second time synchronization domain of the first multi-domain switch chip communicates with the input port bound to the second time synchronization domain of the second multi-domain switch chip;

[0021] The output port bound to the second time synchronization domain of the second multi-domain switch chip communicates with the input port bound to the third time synchronization domain of the first multi-domain switch chip;

[0022] The output port bound to the third time synchronization domain of the first multi-domain switch chip communicates with the input port bound to the third time synchronization domain of the second multi-domain switch chip;

[0023] The output port bound to the third time synchronization domain of the second multi-domain switch chip communicates with the input port of the tester.

[0024] Further, the test system further includes an oscilloscope;

[0025] The multi-domain switching chip is connected to the oscilloscope through the PPS interface. The multi-domain switching chip binds a time synchronization domain to the PPS interface, and the PPS interface sends the PPS synchronization signal of the bound time synchronization domain to the oscilloscope;

[0026] The oscilloscope checks the time synchronization accuracy between different time synchronization domains according to the PPS synchronization signal.

[0027] A method for testing the time synchronization accuracy of multiple hops uses the aforementioned test system for the time synchronization accuracy of multiple hops. The simulation device module includes multiple test boards, and a multi-domain switching chip is arranged on each test board. Each multi-domain switching chip sets a time synchronization domain. The test board binds a unique input port and output port to each time synchronization domain. The time synchronization domains in the multi-domain switching chips on each test board are networked in a cascade to form a cascade network; the method includes the following steps:

[0028] Step A1, the tester forms a time synchronization message, sends the time synchronization message to the simulation device module, and stamps the sending timestamp in the time synchronization message;

[0029] Step A2, the simulation device module receives the time synchronization message and transmits the time synchronization message in the cascade network. The input port bound to each time synchronization domain receives the time synchronization message for time synchronization and stamps the receiving timestamp. When the output port bound to each time synchronization domain sends the time synchronization message, it stamps the sending timestamp;

[0030] Step A3, the tester receives the time synchronization message sent by the last time synchronization domain in the cascade network, stamps the receiving timestamp, and calculates the time synchronization accuracy according to the sending timestamp and receiving timestamp stamped by itself for the time synchronization message.

[0031] Further, in Step A2, the two consecutive time synchronization domains for network communication are not in the same multi-domain switching chip.

[0032] Further, each time synchronization domain in the same multi-domain switching chip has a unique domain number;

[0033] In Step A2, the output port bound to each time synchronization domain adds a test mode. In the test mode, the domain code carried in the time synchronization message is modified to the domain code of the next time synchronization domain in the cascade network, and then the time synchronization message is sent to the next time synchronization domain.

[0034] Further, the number of hops is 7;

[0035] The simulation device module includes two test boards, each of which has a multi-domain switch chip, and each multi-domain switch chip has three time synchronization domains; the cascade network formed is:

[0036] An input port bound to a first time synchronization domain of a first multi-domain switch chip communicates with an output port of a tester;

[0037] The output port bound to the first time synchronization domain of the first multi-domain switch chip communicates with the input port bound to the first time synchronization domain of the second multi-domain switch chip;

[0038] The output port bound to the first time synchronization domain of the second multi-domain switch chip communicates with the input port bound to the second time synchronization domain of the first multi-domain switch chip;

[0039] The output port bound to the second time synchronization domain of the first multi-domain switch chip communicates with the input port bound to the second time synchronization domain of the second multi-domain switch chip;

[0040] The output port bound to the second time synchronization domain of the second multi-domain switch chip communicates with the input port bound to the third time synchronization domain of the first multi-domain switch chip;

[0041] The output port bound to the third time synchronization domain of the first multi-domain switch chip communicates with the input port bound to the third time synchronization domain of the second multi-domain switch chip;

[0042] The output port bound to the third time synchronization domain of the second multi-domain switch chip communicates with the input port of the tester.

[0043] Further, before step A1, the PPS interface of the multi-domain switch chip is connected to the oscilloscope, and the multi-domain switch chip binds a time synchronization domain to the PPS interface;

[0044] In step A2, the PPS interface sends a PPS synchronization signal of the bound time synchronization domain to the oscilloscope, and the oscilloscope checks the time synchronization accuracy between different time synchronization domains according to the PPS synchronization signal.

[0045] The beneficial technical effect of the present invention is that: through the multi-domain function of the multi-domain switching chip, one domain simulates an intermediate node device, reducing the test cost and reducing the occupation of hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 This is a networking diagram for testing the 7-hop time synchronization accuracy in the prior art;

[0047] Figure 2 A 7-hop networking diagram of a multi-hop time synchronization accuracy test system of the present invention;

[0048] Figure 3 The present invention is a flowchart of the steps of a method for testing the time synchronization accuracy of multiple hops. DETAILED DESCRIPTION

[0049] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0051] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0052] The present invention provides a multi-hop time synchronization accuracy test system, comprising a simulation device module and a tester;

[0053] The simulation device module includes multiple test boards, and a multi-domain switching chip is arranged on each test board;

[0054] Each multi-domain switch chip sets a time synchronization domain, and the test board binds a unique input port and output port to each time synchronization domain;

[0055] The time synchronization domains in the multi-domain switching chips on each test board are networked and cascaded to form a cascade network;

[0056] The tester is used to: form a time synchronization message, send the time synchronization message to the simulation device module, and put a sending timestamp in the time synchronization message;

[0057] The analog device module is used to: receive time synchronization messages and transmit time synchronization messages in the cascade network;

[0058] Each input port bound to a time synchronization domain receives a time synchronization message and performs time synchronization and adds a receiving timestamp. Each output port bound to a time synchronization domain adds a sending timestamp when sending a time synchronization message.

[0059] The tester is also used to: receive the time synchronization message sent by the last time synchronization domain in the cascade network, add a receiving timestamp, and calculate the time synchronization accuracy based on the sending timestamp and receiving timestamp added by itself to the time synchronization message.

[0060] Specifically, the time synchronization message is a gPTP (Generalized Precision Time Protocol) message. Through the multi-domain function of the multi-domain switching chip, each time synchronization domain forms an independent clock domain (RTC, Real-Time CLOCK), simulating an intermediate node device, reducing testing costs and reducing hardware resource usage.

[0061] The output port and the receiving port of the tester are also in the same domain. Furthermore, in the cascade network, the two time synchronization domains for network communication are not in the same multi-domain switching chip.

[0062] For example, if the previous time synchronization domain is in the first multi-domain switching chip and the next time synchronization domain is in the second multi-domain switching chip, the data transmission and reception between the two time synchronization domains is like the data transmission and reception between two intermediate node devices, and a hop is formed between the two time synchronization domains.

[0063] Specifically, in order to minimize the test cost and reduce the occupation of hardware resources, each multi-domain switching chip has at least three synchronous time domains.

[0064] The two time synchronization domains for network communication are not in the same multi-domain switching chip, forming a snake-like network.

[0065] Furthermore, each time synchronization domain in the same multi-domain switch chip has a unique domain number;

[0066] In the cascade network, a test mode is added to the output port bound to each time synchronization domain. In the test mode, the domain code carried by the time synchronization message is modified to the domain code of the next time synchronization domain in the cascade network, and then the time synchronization message is sent to the next time synchronization domain.

[0067] The domain number is in the domain number field. Because the two time synchronization domains that communicate on the network are not in the same multi-domain switching chip, the domain number identifies the specific logical or physical area, network partition or management boundary to which the data packet belongs, that is, the identifier of the domain. If the domain number is not modified, the domain number may be inconsistent with the domain number of the next time synchronization domain, so the next time synchronization domain may not be able to process the time synchronization message received. Therefore, by modifying the domain number and the domain number of the next time synchronization domain in the network, the next time synchronization domain recognizes that the domain number in the message matches its own domain number and processes it.

[0068] like Figure 2 As shown, further, the number of hops is 7;

[0069] The simulation device module includes two test boards, each of which has a multi-domain switch chip, and each multi-domain switch chip has three time synchronization domains; the cascade network formed is:

[0070] An input port bound to a first time synchronization domain of a first multi-domain switch chip communicates with an output port of a tester;

[0071] The output port bound to the first time synchronization domain of the first multi-domain switch chip communicates with the input port bound to the first time synchronization domain of the second multi-domain switch chip;

[0072] The output port bound to the first time synchronization domain of the second multi-domain switch chip communicates with the input port bound to the second time synchronization domain of the first multi-domain switch chip;

[0073] The output port bound to the second time synchronization domain of the first multi-domain switch chip communicates with the input port bound to the second time synchronization domain of the second multi-domain switch chip;

[0074] The output port bound to the second time synchronization domain of the second multi-domain switch chip communicates with the input port bound to the third time synchronization domain of the first multi-domain switch chip;

[0075] The output port bound to the third time synchronization domain of the first multi-domain switch chip communicates with the input port bound to the third time synchronization domain of the second multi-domain switch chip;

[0076] The output port bound to the third time synchronization domain of the second multi-domain switch chip communicates with the input port of the tester.

[0077] By cascading two test boards, you can complete 7 Hop performance tests, reducing test costs and hardware resource usage.

[0078] When the hop count is 7, follow Figure 2As shown in the figure, the switch chip test board 1 and the switch chip test board 2 are cascaded, where the input port port0 (0S) and the output port port1 (1M) are bound to instance0 (the first time synchronization domain), the input port port2 (2S) and the output port port3 (3M) are bound to instance1 (the second time synchronization domain), and the input port port4 (4S) and the output port port5 (5M) are bound to instance2 (the third time synchronization domain). Instance0 corresponds to the message with the gPTP domain number fielded as 0, instance1 corresponds to the message with the gPTP domain number fielded as 1, and instance2 corresponds to the message with the gPTP domain number fielded as 2. According to Figure 2 As shown in the figure, snake networking is performed. After the networking is completed, each gPTP instance can simulate an intermediate node device (switching device), and the synchronization between different gPTP instances is completed by modifying the domain number of the output port. As shown in the figure above, the gPTP message output by the output port port1 (1M) of the test board 2 modifies the domain number filed to 1 when it is output, and then sends it to the input port port2 (2S) of the test board 1; the gPTP message sent by the output port port3 (3M) of the test board 2 modifies the domain number filed to 2 when it is output, and then sends it to the input port port4 (4S) of the test board 1; the gPTP message sent by the output port port5 (5M) of the test board 2 modifies the domain number filed to 0 when it is output, and then sends it to the tester. The message sent by the tester and the message received are in the same domain. After the networking is completed, the system performance test is performed. The end-to-end time error can be detected by the tester, and the time error between each device (each instance simulates an intermediate node device) can also be checked through PPS out.

[0079] According to the above method, the design and networking test are carried out. The three gPTP instances (that is, three time synchronization domains) of the two switching devices can simulate the networking scenario of 6 intermediate switching devices, and then test the 7-hop time synchronization accuracy test of the gPTP device.

[0080] Specifically, the tester is an IXIA tester.

[0081] Specifically, there may be more hop numbers, such as 8, 9, etc. When performing precision testing with more hop numbers, the problem may be solved by increasing the number of time synchronization domains of each multi-domain switch chip or increasing the number of multi-domain switch chips.

[0082] Further, the test system also includes an oscilloscope;

[0083] The multi-domain switching chip is connected to the oscilloscope through the PPS interface. The multi-domain switching chip binds a time synchronization domain to the PPS interface. The PPS interface sends a PPS synchronization signal of the bound time synchronization domain to the oscilloscope.

[0084] The oscilloscope checks the time synchronization accuracy between different time synchronization domains based on the PPS synchronization signal.

[0085] PPS (Pulse Per Second) is a time synchronization signal. The cross-CROSS check function of the oscilloscope allows users to simultaneously view and analyze the pulse alignment between two or more PPS signals, and analyze the relative time relationship, that is, the time synchronization accuracy. Specifically, if the number of time synchronization domains on the multi-domain switching chip is greater than the number of PPS interfaces, the multi-domain switching chip selects a time synchronization domain for the PPS interface to be bound to the time synchronization accuracy check.

[0086] If the number of time synchronization domains on the multi-domain switch chip is equal to or smaller than the number of PPS interfaces, each time synchronization domain may be bound to a PPS interface.

[0087] See also Figure 3 The present invention also provides a method for testing the time synchronization accuracy of multiple hops, using the aforementioned time synchronization accuracy testing system of multiple hops, wherein the simulation device module comprises multiple test boards, each test board is provided with a multi-domain switching chip, each multi-domain switching chip is provided with a time synchronization domain, the test board binds a unique input port and an output port for each time synchronization domain, and the time synchronization domains in the multi-domain switching chips on each test board are networked and cascaded to form a cascade network; the method comprises the following steps:

[0088] Step A1, the tester forms a time synchronization message, sends the time synchronization message to the simulation device module, and puts a sending timestamp in the time synchronization message;

[0089] Step A2, the simulation device module receives the time synchronization message and transmits the time synchronization message in the cascade network, each input port bound to the time synchronization domain receives the time synchronization message for time synchronization and marks the receiving timestamp, and each output port bound to the time synchronization domain sends the time synchronization message and marks the sending timestamp;

[0090] Step A3: the tester receives the time synchronization message sent by the last time synchronization domain in the cascade network, adds a receiving timestamp, and calculates the time synchronization accuracy based on the sending timestamp and receiving timestamp added by the tester to the time synchronization message.

[0091] Specifically, the time synchronization message is a gPTP (Generalized Precision Time Protocol) message. Through the multi-domain function of the multi-domain switching chip, each time synchronization domain forms an independent clock domain (RTC, Real-Time CLOCK), simulating an intermediate node device, reducing testing costs and reducing hardware resource usage.

[0092] The tester's output ports and receiving ports are also in the same domain.

[0093] Furthermore, in step A2, the two time synchronization domains for network communication are not in the same multi-domain switching chip.

[0094] For example, if the previous time synchronization domain is in the first multi-domain switching chip and the next time synchronization domain is in the second multi-domain switching chip, the data transmission and reception between the two time synchronization domains is like the data transmission and reception between two intermediate node devices, and a hop is formed between the two time synchronization domains.

[0095] Specifically, in order to minimize the test cost and reduce the occupation of hardware resources, each multi-domain switching chip has at least three synchronous time domains.

[0096] The two time synchronization domains for network communication are not in the same multi-domain switching chip, forming a snake-like network.

[0097] Furthermore, each time synchronization domain in the same multi-domain switch chip has a unique domain number;

[0098] In step A2, a test mode is added to the output port bound to each time synchronization domain, and the domain code carried by the time synchronization message is modified in the test mode to the domain code of the next time synchronization domain in the cascade network, and then the time synchronization message is sent to the next time synchronization domain.

[0099] The domain number is in the domain number field. Because the two time synchronization domains that communicate on the network are not in the same multi-domain switching chip, the domain number identifies the specific logical or physical area, network partition or management boundary to which the data packet belongs, that is, the identifier of the domain. If the domain number is not modified, the domain number may be inconsistent with the domain number of the next time synchronization domain, so the next time synchronization domain may not be able to process the time synchronization message received. Therefore, by modifying the domain number and the domain number of the next time synchronization domain in the network, the next time synchronization domain recognizes that the domain number in the message matches its own domain number and processes it.

[0100] Further, the hop count is 7;

[0101] The simulation device module includes two test boards, each of which has a multi-domain switch chip, and each multi-domain switch chip has three time synchronization domains; the cascade network formed is:

[0102] An input port bound to a first time synchronization domain of a first multi-domain switch chip communicates with an output port of a tester;

[0103] The output port bound to the first time synchronization domain of the first multi-domain switch chip communicates with the input port bound to the first time synchronization domain of the second multi-domain switch chip;

[0104] The output port bound to the first time synchronization domain of the second multi-domain switch chip communicates with the input port bound to the second time synchronization domain of the first multi-domain switch chip;

[0105] The output port bound to the second time synchronization domain of the first multi-domain switch chip communicates with the input port bound to the second time synchronization domain of the second multi-domain switch chip;

[0106] The output port bound to the second time synchronization domain of the second multi-domain switch chip communicates with the input port bound to the third time synchronization domain of the first multi-domain switch chip;

[0107] The output port bound to the third time synchronization domain of the first multi-domain switch chip communicates with the input port bound to the third time synchronization domain of the second multi-domain switch chip;

[0108] The output port bound to the third time synchronization domain of the second multi-domain switch chip communicates with the input port of the tester.

[0109] Specifically, the tester is an IXIA tester. The three gPTP instances (that is, three time synchronization domains) of two switching devices can simulate the networking scenario of six intermediate switching devices, and then test the 7-hop time synchronization accuracy test of the gPTP device.

[0110] Further, before step A1, the PPS interface of the multi-domain switch chip is connected to the oscilloscope, and the multi-domain switch chip binds a time synchronization domain to the PPS interface;

[0111] In step A2, the PPS interface sends a PPS synchronization signal of the bound time synchronization domain to the oscilloscope, and the oscilloscope checks the time synchronization accuracy between different time synchronization domains according to the PPS synchronization signal.

[0112] PPS (Pulse Per Second) is a time synchronization signal. The cross-CROSS check function of the oscilloscope allows users to simultaneously view and analyze the pulse alignment between two or more PPS signals, and analyze the relative time relationship, that is, the time synchronization accuracy. Specifically, if the number of time synchronization domains on the multi-domain switching chip is greater than the number of PPS interfaces, the multi-domain switching chip selects a time synchronization domain for the PPS interface to be bound to the time synchronization accuracy check.

[0113] If the number of time synchronization domains on the multi-domain switch chip is equal to or smaller than the number of PPS interfaces, each time synchronization domain may be bound to a PPS interface.

[0114] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-hop time synchronization accuracy test system, characterized in that: Includes analog device modules and testers; The simulation device module includes a plurality of test boards, each of which is provided with a multi-domain switching chip; Each multi-domain switch chip sets a time synchronization domain, and the test board binds a unique input port and output port to each time synchronization domain; The time synchronization domains in the multi-domain switching chips on each of the test boards are networked and cascaded to form a cascade network; The tester is used to: form a time synchronization message, send the time synchronization message to the simulation device module, and put a sending timestamp in the time synchronization message; The analog device module is used to: receive the time synchronization message and transmit the time synchronization message in the cascade network; Each input port bound to the time synchronization domain receives the time synchronization message, performs time synchronization and adds a receiving timestamp, and each output port bound to the time synchronization domain adds a sending timestamp when sending the time synchronization message; The tester is also used to: receive the time synchronization message sent by the last time synchronization domain in the cascade network, add a receiving timestamp, and calculate the time synchronization accuracy based on the sending timestamp and the receiving timestamp added by itself to the time synchronization message.

2. A multi-hop time synchronization accuracy test system as claimed in claim 1, characterized in that: In the cascade network, the two time synchronization domains for network communication are not in the same multi-domain switching chip.

3. A multi-hop time synchronization accuracy test system as claimed in claim 1, characterized in that: Each of the time synchronization domains in the same multi-domain switching chip has a unique domain number; In the cascade network, a test mode is added to the output port bound to each time synchronization domain. In the test mode, the domain code carried by the time synchronization message is modified to the domain code of the next time synchronization domain in the cascade network, and then the time synchronization message is sent to the next time synchronization domain.

4. A multi-hop time synchronization accuracy test system as claimed in claim 1, characterized in that: The number of hops is 7; The simulation device module includes two test boards, each of which has one multi-domain switching chip, and each of which has three time synchronization domains; the cascade network formed is: An input port bound to a first time synchronization domain of the first multi-domain switch chip communicates with an output port of the tester; An output port bound to the first time synchronization domain of the first multi-domain switch chip communicates with an input port bound to the first time synchronization domain of the second multi-domain switch chip; The output port bound to the first time synchronization domain of the second multi-domain switch chip communicates with the input port bound to the second time synchronization domain of the first multi-domain switch chip; The output port bound to the second time synchronization domain of the first multi-domain switch chip communicates with the input port bound to the second time synchronization domain of the second multi-domain switch chip; The output port bound to the second time synchronization domain of the second multi-domain switch chip communicates with the input port bound to the third time synchronization domain of the first multi-domain switch chip; The output port bound to the third time synchronization domain of the first multi-domain switch chip communicates with the input port bound to the third time synchronization domain of the second multi-domain switch chip; The output port bound to the third time synchronization domain of the second multi-domain switching chip communicates with the input port of the tester.

5. A multi-hop time synchronization accuracy test system as claimed in claim 1, characterized in that: The test system also includes an oscilloscope; The multi-domain switching chip is connected to the oscilloscope via a PPS interface, the multi-domain switching chip binds one of the time synchronization domains to the PPS interface, and the PPS interface sends a PPS synchronization signal of the bound time synchronization domain to the oscilloscope; The oscilloscope checks the time synchronization accuracy between different time synchronization domains according to the PPS synchronization signal.

6. A method for testing the time synchronization accuracy of multiple hops, characterized in that: Using a multi-hop time synchronization accuracy test system as described in any one of claims 1 to 5, the simulation device module includes multiple test boards, each test board is arranged with a multi-domain switching chip, each multi-domain switching chip is set with a time synchronization domain, the test board binds a unique input port and output port for each time synchronization domain, and the time synchronization domains in the multi-domain switching chips on each of the test boards are networked and cascaded to form a cascade network; comprising the following steps: Step A1, the tester forms a time synchronization message, sends the time synchronization message to the simulation device module, and puts a sending timestamp in the time synchronization message; Step A2, the analog device module receives the time synchronization message and transmits the time synchronization message in the cascade network, each input port bound to the time synchronization domain receives the time synchronization message for time synchronization and marks a receiving timestamp, and each output port bound to the time synchronization domain sends the time synchronization message and marks a sending timestamp; In step A3, the tester receives the time synchronization message sent by the last time synchronization domain in the cascade network, adds a receiving timestamp, and calculates the time synchronization accuracy based on the sending timestamp and the receiving timestamp added by itself to the time synchronization message.

7. A method for testing the time synchronization accuracy of multiple hops as claimed in claim 6, characterized in that: In the step A2, the two time synchronization domains for network communication are not in the same multi-domain switching chip.

8. A method for testing the time synchronization accuracy of multiple hops as claimed in claim 6, characterized in that: Each of the time synchronization domains in the same multi-domain switching chip has a unique domain number; In step A2, a test mode is added to the output port bound to each time synchronization domain, and the domain code carried by the time synchronization message is modified in the test mode to the domain code of the next time synchronization domain in the cascade network, and then the time synchronization message is sent to the next time synchronization domain.

9. A method for testing the time synchronization accuracy of multiple hops as claimed in claim 6, characterized in that: The number of hops is 7; The simulation device module includes two test boards, each of which has one multi-domain switching chip, and each of which has three time synchronization domains; the cascade network formed is: An input port bound to a first time synchronization domain of the first multi-domain switch chip communicates with an output port of the tester; An output port bound to the first time synchronization domain of the first multi-domain switch chip communicates with an input port bound to the first time synchronization domain of the second multi-domain switch chip; The output port bound to the first time synchronization domain of the second multi-domain switch chip communicates with the input port bound to the second time synchronization domain of the first multi-domain switch chip; The output port bound to the second time synchronization domain of the first multi-domain switch chip communicates with the input port bound to the second time synchronization domain of the second multi-domain switch chip; The output port bound to the second time synchronization domain of the second multi-domain switch chip communicates with the input port bound to the third time synchronization domain of the first multi-domain switch chip; The output port bound to the third time synchronization domain of the first multi-domain switch chip communicates with the input port bound to the third time synchronization domain of the second multi-domain switch chip; The output port bound to the third time synchronization domain of the second multi-domain switching chip communicates with the input port of the tester.

10. A method for testing the time synchronization accuracy of multiple hops as claimed in claim 6, characterized in that: Before step A1, the PPS interface of the multi-domain switching chip is connected to an oscilloscope, and the multi-domain switching chip binds one of the time synchronization domains to the PPS interface; In the step A2, the PPS interface sends a PPS synchronization signal of the bound time synchronization domain to the oscilloscope, and the oscilloscope checks the time synchronization accuracy between different time synchronization domains according to the PPS synchronization signal.

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