Interpolation Position Calculation Method, Device and Equipment for Parallel Time Synchronizer

Abstract

The present application discloses an interpolation position calculation method, device and equipment for a parallel time synchronizer, relating to the technical field of wireless communication. The method includes: determining output data at the current moment based on the interpolation position and input data at the current moment; determining the sampling period at the current moment based on the output data and output valid flag at the current moment; performing arithmetic processing on the sampling period at the current moment to obtain the initial interpolation position at the target moment, and the arithmetic processing at least includes multiplication arithmetic processing, subtraction arithmetic processing and division arithmetic processing based on a fixed constant; performing overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment. By the above method, a fixed constant value is used to calculate the interpolation position, which simplifies the calculation complexity, reduces the calculation time of the interpolation position, reduces the feedback delay, and updates the interpolation position in real time, and can avoid introducing additional feedback delay due to a serial chain structure.

Description

Technical Field

[0001] This application relates to the field of wireless communication technologies, and in particular, to an interpolation position calculation method, apparatus, and device for a parallel time synchronizer. Background Art

[0002] The Gardner algorithm is a commonly used time synchronization algorithm in wireless communication. It can compensate for the sampling point deviation caused by the sampling rate error and find the optimal sampling point. In specific implementation, it uses an interpolation filter to perform resampling of the signal, and at the same time, uses the "early-late gate" algorithm to detect the sampling point error of the signal. According to the output of the loop filter based on the error value, the interpolation position is calculated, and the interpolation position is fed back to the interpolation filter, thereby realizing real-time adjustment of the interpolation position and finding the optimal sampling point.

[0003] In a traditional parallel time synchronizer (Gardner time synchronizer) using the Gardner algorithm, its interpolation position is calculated by dividing the current value of the numerically controlled oscillator by the estimated sampling period. Since both the current value of the numerically controlled oscillator and the estimated sampling period are variables, involving high-precision variable division, it consumes a large amount of time in calculation, resulting in a certain delay in the feedback of the interpolation position. Moreover, when calculating the interpolation position, the interpolation position is updated only when the valid signal is high, otherwise the value calculated last time is maintained. It can be seen that the calculation input of each path depends on the calculation output of the previous path, which will introduce a serial chain structure and cause additional feedback delay.

[0004] The above content is only used to assist in understanding the technical solution of the present invention, and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main purpose of this application is to provide an interpolation position calculation method, apparatus, and device for a parallel time synchronizer, aiming to solve the technical problem that the parallel time synchronizer in the prior art consumes a long time in calculating the interpolation position and has a high feedback delay.

[0006] To achieve the above purpose, this application provides an interpolation position calculation method for a parallel time synchronizer. The method includes:

[0007] Determine the output data at the current moment based on the interpolation position and input data at the current moment;

[0008] Determine the sampling period at the current moment based on the output data and output valid flag at the current moment;

[0009] Perform arithmetic processing on the sampling period at the current moment to obtain the initial interpolation position at the target moment. The arithmetic processing includes at least multiplication arithmetic processing, subtraction arithmetic processing, and division arithmetic processing based on a fixed constant;

[0010] Perform an overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment.

[0011] In one embodiment, the step of determining the output data at the current moment based on the interpolation position and input data at the current moment includes:

[0012] Input the input data at the current moment into a plurality of parallel filters with different coefficients respectively to obtain the initial output data of the parallel filters at the current moment;

[0013] Obtain a first correspondence relationship among the initial output data at the current moment, the interpolation position at the current moment, the filtering weight, and the output data at the current moment;

[0014] Based on the initial output data of the parallel filters at the current moment, the interpolation position at the current moment, the filtering weight, and the first correspondence relationship, obtain the output data at the current moment.

[0015] In one embodiment, the step of determining the sampling period at the current moment based on the output data and the output valid flag at the current moment includes:

[0016] Determine a parallel error amount based on the output data and the output valid flag at the current moment;

[0017] Determine an average error amount based on the parallel error amount;

[0018] Input the average error amount into a loop filter for filtering to obtain loop-filtered data;

[0019] Determine the sampling period at the current moment based on the loop-filtered data.

[0020] In one embodiment, the step of determining the parallel error amount based on the output data and the output valid flag at the current moment includes:

[0021] When the output valid flag at the current moment is a first value, use the first value as the parallel error amount;

[0022] When the output valid flag at the current moment is a second value, obtain a second correspondence relationship between the output data at the current moment and the parallel error amount, and based on the output data at the current moment and the second correspondence relationship, obtain the parallel error amount.

[0023] In one embodiment, the step of performing arithmetic processing on the sampling period at the current moment to obtain the initial interpolation position at the target moment includes:

[0024] Perform a multiplication operation on the sampling period at the current moment based on a preset constant sequence to obtain a multiplication operation result;

[0025] Perform a subtraction operation on the multiplication operation result and the stored value at the current moment to obtain a subtraction operation result, and update the stored value at the target moment based on the subtraction operation result;

[0026] Perform a division operation on the subtraction operation result based on the fixed constant to obtain the initial interpolation position at the target moment.

[0027] In one embodiment, before the step of performing overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment, the following steps are further included:

[0028] Determine the adjacent path subtraction operation result based on the subtraction operation result at the target moment, the adjacent path subtraction operation result;

[0029] Determine the output valid flag at the target moment based on the adjacent path subtraction operation result.

[0030] In one embodiment, the adjacent path subtraction operation result includes the subtraction operation result of the current path and the subtraction operation result of the previous path, and the step of determining the output valid flag at the target moment based on the adjacent path subtraction operation result includes:

[0031] When the subtraction operation result of the current path is less than or equal to the subtraction operation result of the previous path, use the first value as the output valid flag corresponding to the current path;

[0032] When the subtraction operation result of the current path is greater than the subtraction operation result of the previous path, use the second value as the output valid flag corresponding to the current path.

[0033] In one embodiment, the step of performing overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment includes:

[0034] Obtain the third corresponding relationship among the initial interpolation position at the target moment, the output valid flag at the target moment, and the interpolation position at the target moment;

[0035] Obtain the interpolation position at the target moment based on the initial interpolation position at the target moment, the output valid flag at the target moment, and the third corresponding relationship.

[0036] In addition, to achieve the above object, the present application also proposes an interpolation position calculation device for a parallel time synchronizer, and the interpolation position calculation device for a parallel time synchronizer includes:

[0037] A parallel filtering module, configured to determine the output data at the current moment based on the interpolation position and the input data at the current moment;

[0038] A sampling period estimation module, configured to determine the sampling period at the current moment based on the output data and the output valid flag at the current moment;

[0039] A numerically controlled oscillator module, configured to perform arithmetic processing on the sampling period at the current moment to obtain an initial interpolation position at a target moment, where the arithmetic processing at least includes multiplication arithmetic processing, subtraction arithmetic processing, and division arithmetic processing based on a fixed constant;

[0040] The numerically controlled oscillator module is further configured to perform overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment.

[0041] In addition, to achieve the above object, the present application further provides an interpolation position calculation device for a parallel time synchronizer. The interpolation position calculation device for a parallel time synchronizer includes: a memory, a processor, and a computer program stored on the memory and executable on the processor. The computer program is configured to implement the steps of the interpolation position calculation method for a parallel time synchronizer as described above.

[0042] In addition, to achieve the above object, the present invention further provides a storage medium. The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the interpolation position calculation method for a parallel time synchronizer as described above are implemented.

[0043] In addition, to achieve the above object, the present application further provides a computer program product. The computer program product includes a computer program. When the computer program is executed by a processor, the steps of the interpolation position calculation method for a parallel time synchronizer as described above are implemented.

[0044] The present application provides an interpolation position calculation method for a parallel time synchronizer, which determines the output data at the current moment based on the interpolation position and input data at the current moment; determines the sampling period at the current moment based on the output data and output valid flag at the current moment; performs arithmetic processing on the sampling period at the current moment to obtain the initial interpolation position at the target moment, and the arithmetic processing at least includes multiplication arithmetic processing, subtraction arithmetic processing, and division arithmetic processing based on a fixed constant; performs overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment. The present application uses fixed constant values to calculate the interpolation position, which can simplify the complexity of the calculation, reduce the calculation time of the interpolation position, reduce the feedback delay, and update the interpolation position in real time. Whether the valid signal is high or not, the interpolation position will be updated, which can avoid introducing additional feedback delay due to the serial chain structure. In addition, the process of overflow correction is added to avoid errors caused by the overflow of the interpolation position and ensure the accuracy of the calculated interpolation position, solving the technical problems that the parallel time synchronizer consumes a long time in calculating the interpolation position and has a high feedback delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0047] Figure 1 It is a schematic flowchart of the first embodiment of the interpolation position calculation method for the parallel time synchronizer of the present application;

[0048] Figure 2 It is a schematic diagram of the overall structure of the parallel time synchronizer for the interpolation position calculation method provided in the first embodiment of the present application;

[0049] Figure 3 It is a schematic flowchart of the second embodiment of the interpolation position calculation method for the parallel time synchronizer of the present application;

[0050] Figure 4 It is a schematic diagram of the numerically controlled oscillator structure for the interpolation position calculation method of the parallel time synchronizer provided in the second embodiment of the present application;

[0051] Figure 5 It is a schematic flowchart of the third embodiment of the interpolation position calculation method for the parallel time synchronizer of the present application;

[0052] Figure 6 This is a schematic flowchart of the interpolation position calculation method for the parallel time synchronizer provided in the third embodiment of this application;

[0053] Figure 7 This is a schematic module structure diagram of the interpolation position calculation device for the parallel time synchronizer in the embodiment of this application;

[0054] Figure 8 This is a schematic device structure diagram of the hardware operating environment involved in the interpolation position calculation method for the parallel time synchronizer in the embodiment of this application.

[0055] The realization, functional features, and advantages of the purpose of this application will be further described in combination with the embodiments with reference to the accompanying drawings. Detailed implementation manners

[0056] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of this application and are not used to limit this application.

[0057] To better understand the technical solutions of this application, the following will be described in detail in combination with the accompanying drawings of the specification and specific implementation manners.

[0058] The main solution of the embodiment of this application is: determining the output data at the current moment based on the interpolation position and input data at the current moment; determining the sampling period at the current moment based on the output data and output valid flag at the current moment; performing arithmetic processing on the sampling period at the current moment to obtain the initial interpolation position at the target moment, and the arithmetic processing at least includes multiplication arithmetic processing, subtraction arithmetic processing, and division arithmetic processing based on a fixed constant; performing overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment.

[0059] Currently, in the traditional parallel time synchronizer (Gardner time synchronizer) using the Gardner algorithm, its interpolation position is calculated by dividing the current value of the numerically controlled oscillator by the estimated sampling period. Since both the current value of the numerically controlled oscillator and the estimated sampling period are variables, involving high-precision variable division, it consumes a lot of time in calculation, resulting in a certain delay in the feedback of the interpolation position. Moreover, when calculating the interpolation position, the interpolation position is only updated when the valid signal is high, otherwise the value calculated last time is maintained. It can be seen that the calculation input of each path depends on the calculation output of the previous path, which will introduce a serial chain structure and cause additional feedback delay.

[0060] The present application provides a solution. By using fixed constant values to calculate the interpolation position, the complexity of the calculation can be simplified, the calculation time of the interpolation position can be reduced, the feedback delay can be decreased, and the interpolation position can be updated in real time. Whether the valid signal is high or not, the interpolation position will be updated, which can avoid introducing additional feedback delay due to the serial chain structure. In addition, an overflow correction process is added to avoid large errors caused by the overflow of the interpolation position, ensuring the accuracy of the calculated interpolation position, and solving the technical problems that the parallel time synchronizer consumes a long time in calculating the interpolation position and has a high feedback delay.

[0061] It should be noted that the execution subject of this embodiment can be a parallel time synchronizer, or an electronic device capable of implementing the above functions, an interpolation position calculation device of the parallel time synchronizer, etc. This embodiment does not make specific limitations in this regard. Hereinafter, taking the parallel time synchronizer as an example, this embodiment and the following embodiments will be described.

[0062] The embodiment of the present application provides a method for calculating the interpolation position of a parallel time synchronizer. Refer to Figure 1 , Figure 1 which is a schematic flowchart of the first embodiment of the method for calculating the interpolation position of the parallel time synchronizer of the present application.

[0063] In this embodiment, the method for calculating the interpolation position of the parallel time synchronizer includes steps S10 to S40:

[0064] Step S10, based on the interpolation position and input data at the current moment, determine the output data at the current moment;

[0065] It should be noted that the parallel time synchronizer can be a Gardner time synchronizer. In this embodiment, refer to Figure 2 , the parallel time synchronizer includes a parallel filtering module, a sampling period estimation module, and a numerically controlled oscillator module. Among them, the parallel filtering module usually includes multiple parallel filters, and the numerically controlled oscillator module usually includes a numerically controlled oscillator. The parallel filtering module can calculate the output data according to the input data and the interpolation position fed back by the numerically controlled oscillator module. The sampling period estimation module can estimate the sampling period according to the output valid flag and output data fed back by the numerically controlled oscillator. The numerically controlled oscillator module can calculate the interpolation position at the next moment and feed it back to the parallel filtering module according to the estimated sampling period, and calculate the output valid flag at the next moment and feed it back to the sampling period estimation module.

[0066] In addition, it should be noted that the current moment is the current time, usually denoted as time . The input data is the data input to the input parallel time synchronizer, and the output data is the data output by the parallel time synchronizer. The output valid flag is usually used to represent the high and low levels of the valid signal level, and includes two states, namely "0" and "1". Generally speaking, "0" represents that the valid signal is at a low level, and "1" represents that the valid signal is at a high level. The interpolation position is the position corresponding to the interpolation, and the sampling period is the estimated sampling period.

[0067] It can be understood that assuming that the number of parallel paths (greater than 2) of the parallel time synchronizer is , then the parallel time synchronizer receives at time parallel input data, generates parallel output data, parallel output valid flags, parallel interpolation positions, and the sampling period. In a specific implementation, at time , parallel input data can be denoted as , parallel output data can be denoted as , parallel output valid flags can be denoted as , parallel interpolation positions can be denoted as , and the sampling period can be denoted as . Exemplarily, for time , the input data of the 16-channel parallel time synchronizer can be denoted as , the output data of the 16-channel parallel time synchronizer can be denoted as , the output valid flag of the 16-channel parallel time synchronizer can be denoted as , and the interpolation position of the 16-channel parallel time synchronizer can be denoted as .

[0068] It should be understood that in the initialization stage, the parallel time synchronizer initializes the time to 0, initializes all the interpolation positions at time to 0, and initializes all the output valid flags at time to 0.

[0069] In a feasible implementation manner, step S10 may include steps S101 to S103:

[0070] Step S101, input the input data at the current moment into a plurality of parallel filters with different coefficients respectively, and obtain the initial output data of the parallel filters at the current moment;

[0071] It should be noted that in this embodiment, multiple parallel filters are provided, and the coefficients of these parallel filters are all different. The number of parallel filters is usually set to 3, and the number of parallel paths of each parallel filter is the same as that of the parallel time synchronizer, both being . The data obtained after inputting the input data at the current moment into the parallel filters is the initial output data, and further processing is required to obtain the output data at the current moment. Exemplarily, the coefficient of parallel filter one is , the coefficient of parallel filter two is , and the coefficient of parallel filter three is .

[0072] It can be understood that the input data at time is sent to 3 parallel filters with different coefficients. Assuming that the coefficient of parallel filter one is , then the initial output data of the -th path of parallel filter one at time can be expressed as:

[0073]

[0074] In the formula, represents the initial output data of the -th path of parallel filter one at time , represents the number of parallel paths, represents the floor function, represents the remainder function.

[0075] Correspondingly, assuming that the coefficient of parallel filter two is , then the initial output data of the -th path of parallel filter two at time can be expressed as:

[0076]

[0077] In the formula, represents the initial output data of the -th path of parallel filter two at time , represents the number of parallel paths, represents the floor function, represents the remainder function.

[0078] Correspondingly, assuming that the coefficient of parallel filter three is , then the initial output data of the -th path of parallel filter three at time ​The initial output data can be expressed as:

[0079]

[0080] Wherein, represents the th path of the parallel filter three at the moment of the initial output data, represents the number of parallel paths, represents the floor function, represents the remainder function.

[0081] Step S102, obtain the first correspondence relationship between the initial output data at the current moment, the interpolation position at the current moment, the filtering weight, and the output data at the current moment;

[0082] It can be understood that after obtaining the initial output data of each parallel filter at the current moment, weighted accumulation is performed to obtain the final output data. The filtering weight is the weight coefficient set when calculating the output data. The first correspondence relationship between the initial output data at the current moment, the interpolation position at the current moment, the filtering weight, and the output data at the current moment, that is, the calculation formula of the output data at the current moment, is as follows:

[0083]

[0084] Wherein, , , represent the th path of each parallel filter at the moment of the initial output data, , , represent the filtering weights of each parallel filter, represents the interpolation position at the moment , represents the moment of the output data, represents the number of parallel paths of the parallel filter.

[0085] Step S103, based on the initial output data of the parallel filter at the current moment, the interpolation position at the current moment, the filtering weight, and the first correspondence relationship, obtain the output data at the current moment.

[0086] It can be understood that substituting the initial output data of each parallel filter at the moment , the interpolation position at the moment , and the filtering weights of each parallel filter into the above first correspondence relationship, calculate the output data at the moment .

[0087] Step S20, determine the sampling period at the current moment based on the output data and the output valid flag at the current moment;

[0088] In a feasible implementation manner, step S20 may include steps S201 to S204:

[0089] Step S201, determine the parallel error amount based on the output data and the output valid flag at the current moment;

[0090] It should be noted that each path of output data has a corresponding output valid flag, so that the corresponding parallel error amount can be calculated. The parallel error amount is the error of the parallel output data of paths. At time , according to paths of parallel output data and paths of parallel output valid flags, the paths of parallel error amount is calculated.

[0091] In a feasible implementation manner, step S201 may include: when the output valid flag at the current moment is the first value, use the first value as the parallel error amount; when the output valid flag at the current moment is the second value, obtain the second corresponding relationship between the output data at the current moment and the parallel error amount, and based on the output data at the current moment and the second corresponding relationship, obtain the parallel error amount.

[0092] It can be understood that the first value is 0 and the second value is 1. If the output valid flag of the th path , then the corresponding parallel error amount is 0. The second corresponding relationship between the output data at the current moment and the parallel error amount, that is, the calculation formula of the parallel error amount when the output valid flag . If the output valid flag of the th path , then calculate the parallel error amount according to the following formula:

[0093]

[0094] In the formula, represents the parallel error amount of the th path at time , , represents the number of parallel paths, represents the output data at time , represents the floor function, represents the remainder function. At time Substitute the output data into the above second corresponding relationship, and calculate the moment The parallel error amount corresponding to each path of output data, and obtain The parallel error amounts of

[0095] Step S202, based on the parallel error amounts, determine the average error amount;

[0096] It can be understood that the average error amount is The average value of the parallel error amounts of After obtaining the parallel error amounts of

[0097] Step S203, input the average error amount into a loop filter for filtering to obtain loop filter data;

[0098] It should be noted that by inputting the average error amount into a loop filter for filtering, two loop filter outputs can be obtained, that is, two loop filter data, as follows:

[0099]

[0100]

[0101] In the formula, and are respectively the two loop filter data at the moment , represents the parallel error amount of the th path at the moment , represents the average error amount at the moment , represents the loop filter data corresponding to the moment , represents the number of parallel paths.

[0102] Step S204, based on the loop filter data, determine the sampling period at the current moment.

[0103] It can be understood that according to the two loop filter data, calculate the sampling period at the current moment, and the calculation relationship is as follows:

[0104]

[0105] In the formula, represents the sampling period at the moment , and are respectively the two loop filter data at the moment . Substitute the two loop filter data at the moment into the above calculation relationship, and obtain the moment The sampling period of

[0106] Step S30: Perform arithmetic processing on the sampling period at the current moment to obtain the initial interpolation position at the target moment. The arithmetic processing includes at least multiplication arithmetic processing, subtraction arithmetic processing, and division arithmetic processing based on a fixed constant.

[0107] It should be noted that the target moment is the next moment, denoted as moment . According to the estimated sampling period Calculate the of moment parallel output valid flags and parallel interpolation positions.

[0108] It can be understood that during the process of calculating the interpolation position at the target moment, an intermediate process value will be calculated first, that is, the initial interpolation position at the target moment. Through a series of arithmetic processing on the sampling period at the current moment, the corresponding initial interpolation position is obtained. The entire arithmetic processing includes at least multiplication arithmetic processing, subtraction arithmetic processing, and division arithmetic processing based on a fixed constant. The fixed constant is a set fixed constant value, and the division arithmetic processing based on a fixed constant means using the fixed constant value for division arithmetic.

[0109] It should be understood that in the traditional method, the interpolation position is calculated by dividing the current stored value of the numerically controlled oscillator by the estimated sampling period, which involves high-precision variable division, consumes a lot of time, and there is a certain feedback delay. Therefore, in this embodiment, constant division is used instead of variable division to simplify the calculation process, which can reduce the time spent on calculation and reduce the feedback delay.

[0110] Step S40: Perform overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment.

[0111] It should be noted that since this embodiment uses a fixed constant for division arithmetic processing, the initial interpolation position is approximately calculated finally, introducing a certain error, which may cause data overflow and cannot be directly used as the final interpolation position. An overflow correction operation needs to be performed to prevent the interpolation position from overflowing.

[0112] It can be understood that by performing overflow correction on the initial interpolation position at moment , the accurate interpolation position at moment is obtained.

[0113] It should be understood that the interpolation position can be calculated according to the process of steps S10 - S40 at each moment.

[0114] This embodiment provides an interpolation position calculation method for a parallel time synchronizer, which determines the output data at the current moment based on the interpolation position and input data at the current moment; determines the sampling period at the current moment based on the output data and output valid flag at the current moment; performs arithmetic processing on the sampling period at the current moment to obtain the initial interpolation position at the target moment, and the arithmetic processing at least includes multiplication arithmetic processing, subtraction arithmetic processing, and division arithmetic processing based on a fixed constant; performs overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment. This embodiment uses a fixed constant value to calculate the interpolation position, which can simplify the calculation complexity, reduce the calculation time of the interpolation position, reduce the feedback delay, and update the interpolation position in real time. Whether the valid signal is high or not, the interpolation position will be updated, which can avoid introducing additional feedback delay due to the serial chain structure. In addition, an overflow correction process is added to avoid the huge error caused by the overflow of the interpolation position and ensure the accuracy of the calculated interpolation position.

[0115] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar content as that in the above-mentioned first embodiment can be referred to the above introduction and will not be repeated hereinafter. On this basis, please refer to Figure 3 , step S30 may include steps S301 to S303:

[0116] Step S301, perform multiplication arithmetic processing on the sampling period at the current moment based on a preset constant sequence to obtain a multiplication arithmetic result;

[0117] It should be noted that the numerically controlled oscillator calculates the moment based on the estimated sampling period of the Figure 4 parallel initial interpolation positions. Refer to , in this embodiment, the numerically controlled oscillator maintains a memory to record the state, and the value of the memory is the stored value, and the stored value at the moment is denoted as . The numerically controlled oscillator also includes

[0118] parallel multipliers, subtractors, and constant dividers, and each path includes a multiplier, a subtractor, and a constant divider. The multiplier is used for multiplication arithmetic processing, the subtractor is used for subtraction arithmetic processing, and the constant divider is used for division arithmetic processing based on a fixed constant.

[0118] Additionally, it should be noted that the preset constant sequence is the sequence composed of the constants used in each path during the multiplication arithmetic processing, that is, the values of the parallel multipliers need to be set according to the preset constant sequence. Exemplarily, assuming the preset constant sequence is , then the values of the .

[0119] It can be understood that the sampling period at time is input to parallel multipliers, and multiplied by the constant values in the preset constant sequence respectively. The multiplication results obtained are the multiplication operation results. .

[0120] Step S302: Perform a subtraction operation on the multiplication operation result and the stored value at the current time to obtain a subtraction operation result, and update the stored value at the target time based on the subtraction operation result;

[0121] It should be noted that the stored value at the current time is the stored value at time . Using a subtractor, perform a subtraction operation on the multiplication operation result and the stored value at time . The results obtained are the subtraction operation results, as shown below:

[0122]

[0123] In the formula, represents the subtraction operation result of the th path at time , , represents the number of parallel paths, represents the stored value at time , represents the sampling period at time , represents the floor function.

[0124] It can be understood that after obtaining the subtraction operation results of the paths, the subtraction operation result obtained by the last subtractor is fed back to the memory as the value of the memory at the next time, that is, the stored value at the target time, which is the stored value at time , as shown below:

[0125]

[0126] In the formula, represents the stored value at time , represents the subtraction operation result of the subtractor of the th path, represents the number of parallel paths.

[0127] Step S303: Perform a division operation on the subtraction operation result based on the fixed constant to obtain the initial interpolation position at the target moment.

[0128] It should be noted that the value of the fixed constant can be flexibly adjusted according to actual needs, and no specific limitation is made here. In this embodiment, the fixed constant can be set to 0.5. At this time, the calculation formula for the constant divider to perform a division operation using the fixed constant is as follows:

[0129]

[0130] In the formula, represents the initial interpolation position of the th path at time , represents the subtraction operation result of the th path at time , represents the subtraction operation result of the th path at time .

[0131] It can be understood that by comparing the subtraction operation results of adjacent paths, if the subtraction operation result of the th path at time is greater than the subtraction operation result of the th path at time , then divide the subtraction operation result of the th path at time by the fixed constant 0.5 to calculate the initial interpolation position of the th path at time ; if the subtraction operation result of the th path at time is less than or equal to the subtraction operation result of the th path at time , then divide the subtraction operation result of the th path at time by the fixed constant 0.5 and subtract 1 to calculate the initial interpolation position of the th path at time .

[0132] Furthermore, in a feasible implementation manner, based on the subtraction operation result at the target moment, determine the subtraction operation results of adjacent paths, and based on the subtraction operation results of adjacent paths, determine the output valid flag at the target moment.

[0133] It should be noted that the adjacent-path subtraction operation result is the subtraction operation result of the subtractors of two adjacent paths. The subtraction operation results of the subtractors of two adjacent paths are compared to obtain the output valid flag for the next moment. The adjacent-path subtraction operation result includes the subtraction operation result of the current path and the subtraction operation result of the previous path. The subtraction operation result of the current path is the subtraction operation result of the path at the moment , and the subtraction operation result of the previous path is the subtraction operation result of the path at the moment .

[0134] It can be understood that when the subtraction operation result of the current path is less than or equal to the subtraction operation result of the previous path, the first value is used as the output valid flag for the corresponding current path; when the subtraction operation result of the current path is greater than the subtraction operation result of the previous path, the second value is used as the output valid flag for the corresponding current path. The calculation formula is as follows:

[0135]

[0136] In the formula, represents the output valid flag of the path at the moment , represents the subtraction operation result of the path at the moment , represents the subtraction operation result of the path at the moment , represents the number of parallel paths.

[0137] It should be understood that if the subtraction operation result of the path at the moment is greater than the subtraction operation result of the path at the moment , then the output valid flag of the path at the moment is set to 1; if the subtraction operation result of the path at the moment is less than or equal to the subtraction operation result of the path at the moment , then the output valid flag of the path at the moment is set to 0.

[0138] This embodiment provides an interpolation position calculation method for a parallel time synchronizer. Based on a preset constant sequence, a multiplication operation is performed on the sampling period at the current moment to obtain a multiplication operation result; a subtraction operation is performed on the multiplication operation result and the stored value at the current moment to obtain a subtraction operation result, and based on the subtraction operation result, the stored value at the target moment is updated; based on a fixed constant, a division operation is performed on the subtraction operation result to obtain the initial interpolation position at the target moment. This embodiment uses fixed constant values to calculate the interpolation position, which can simplify the calculation complexity, reduce the calculation time of the interpolation position, reduce the feedback delay, and update the interpolation position in real time. Regardless of whether the valid signal is high or not, the interpolation position will be updated, which can avoid introducing additional feedback delay due to the serial chain structure.

[0139] Based on the above embodiments of the present application, in the third embodiment of the present application, the same or similar content as the above embodiments can be referred to the above introduction and will not be repeated hereinafter. On this basis, please refer to Figure 5 , step S40 may include steps S401 to S402:

[0140] Step S401, obtain a third correspondence relationship between the initial interpolation position at the target moment, the output valid flag at the target moment, and the interpolation position at the target moment;

[0141] It should be noted that using a constant divider to approximately calculate the interpolation position will introduce certain errors and may cause data overflow. To prevent overflow, this embodiment combines the initial interpolation position and the output valid flag at the target moment to perform an overflow correction operation to obtain the interpolation position at the next moment. The third correspondence relationship between the initial interpolation position at the target moment, the output valid flag at the target moment, and the interpolation position at the target moment, that is, the calculation formula for the interpolation position at the target moment, is as follows:

[0142]

[0143] In the formula, represents the interpolation position of the th path at time , represents the output valid flag of the th path at time , represents the initial interpolation position of the th path at time , represents the number of parallel paths.

[0144] Step S402, based on the initial interpolation position at the target moment, the output valid flag at the target moment, and the third correspondence relationship, obtain the interpolation position at the target moment.

[0145] It is understandable that if the output valid flag of the th path at time is 1 and the initial interpolation position of the th path at time is greater than 1, then the interpolation position at time is 1; if the output valid flag of the th path at time is 0 and the initial interpolation position of the th path at time is less than 0, then the interpolation position at time is 0; in other cases, the interpolation position at time is equal to the initial interpolation position of the th path at time .

[0146] This embodiment provides a method for calculating the interpolation position of a parallel time synchronizer, obtaining a third correspondence relationship between the initial interpolation position of the target time, the output valid flag of the target time, and the interpolation position of the target time; based on the initial interpolation position of the target time, the output valid flag of the target time, and the third correspondence relationship, obtaining the interpolation position of the target time. This embodiment adds an overflow correction process, which can avoid the huge error caused by the overflow of the interpolation position and ensure the accuracy of the calculated interpolation position.

[0147] Exemplarily, to help understand the implementation process of the method for calculating the interpolation position of the parallel time synchronizer obtained by combining this embodiment with the above Embodiment 3, please refer to Figure 6 , Figure 6 which provides a schematic diagram of the brief process of the method for calculating the interpolation position of a parallel time synchronizer. Specifically:

[0148] In the initialization stage, the parallel time synchronizer initializes the time to 0, initializes all the interpolation positions of the time to 0, and initializes all the output valid flags of the time to 0.

[0149] In the operation stage, for each time , the parallel filter calculates the output data of the time according to the interpolation position of the time and the input data of the time ; the sampling period estimation module calculates the sampling period of the time according to the output data of the time and the output valid flag of the time ; the numerically controlled oscillator calculates the time according to the sampling period of the time Interpolation position and moment Output valid flag. After completion, the moment is incremented by 1, and the above steps are executed again in a loop until the machine stops.

[0150] It should be noted that the above example is only for understanding this application and does not constitute a limitation on the interpolation position calculation method of the parallel time synchronizer in this application. Based on this technical concept, more forms of simple transformations are within the protection scope of this application.

[0151] This application also provides an interpolation position calculation device for a parallel time synchronizer. Please refer to Figure 7 The interpolation position calculation device of the parallel time synchronizer includes:

[0152] A parallel filtering module 10, configured to determine the output data at the current moment based on the interpolation position and input data at the current moment;

[0153] A sampling period estimation module 20, configured to determine the sampling period at the current moment based on the output data and output valid flag at the current moment;

[0154] A numerically controlled oscillator module 30, configured to perform arithmetic processing on the sampling period at the current moment to obtain an initial interpolation position at the target moment, and the arithmetic processing at least includes multiplication arithmetic processing, subtraction arithmetic processing, and division arithmetic processing based on a fixed constant;

[0155] The numerically controlled oscillator module 30 is further configured to perform overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment.

[0156] In a feasible implementation manner, the parallel filtering module 10 is further configured to respectively input the input data at the current moment into a plurality of parallel filters with different coefficients to obtain initial output data of the parallel filters at the current moment;

[0157] Obtain a first correspondence relationship between the initial output data at the current moment, the interpolation position at the current moment, the filtering weight, and the output data at the current moment;

[0158] Based on the initial output data of the parallel filters at the current moment, the interpolation position at the current moment, the filtering weight, and the first correspondence relationship, obtain the output data at the current moment.

[0159] In a feasible implementation manner, the sampling period estimation module 20 is further configured to determine a parallel error amount based on the output data and output valid flag at the current moment;

[0160] Determine an average error amount based on the parallel error amount;

[0161] Input the average error amount into a loop filter for filtering to obtain loop-filtered data;

[0162] Determine the sampling period at the current moment based on the loop-filtered data.

[0163] In a feasible implementation manner, the sampling period estimation module 20 is further configured to use the first numerical value as the parallel error amount when the output valid flag at the current moment is the first numerical value;

[0164] When the output valid flag at the current moment is the second numerical value, obtain a second correspondence relationship between the output data at the current moment and the parallel error amount, and obtain the parallel error amount based on the output data at the current moment and the second correspondence relationship.

[0165] In a feasible implementation manner, the numerically controlled oscillator module 30 is further configured to perform a multiplication operation on the sampling period at the current moment based on a preset constant sequence to obtain a multiplication operation result;

[0166] Perform a subtraction operation on the multiplication operation result and the stored value at the current moment to obtain a subtraction operation result, and update the stored value at the target moment based on the subtraction operation result;

[0167] Perform a division operation on the subtraction operation result based on the fixed constant to obtain the initial interpolation position at the target moment.

[0168] In a feasible implementation manner, the numerically controlled oscillator module 30 is further configured to determine an adjacent-path subtraction operation result based on the subtraction operation result at the target moment, the adjacent-path subtraction operation result;

[0169] Determine the output valid flag at the target moment based on the adjacent-path subtraction operation result.

[0170] In a feasible implementation manner, the numerically controlled oscillator module 30 is further configured to use the first numerical value as the output valid flag for the corresponding current path when the subtraction operation result of the current path is less than or equal to the subtraction operation result of the previous path;

[0171] When the subtraction operation result of the current path is greater than the subtraction operation result of the previous path, use the second numerical value as the output valid flag for the corresponding current path.

[0172] In a feasible implementation manner, the numerically controlled oscillator module 30 is further configured to obtain a third correspondence relationship between the initial interpolation position at the target moment, the output valid flag at the target moment, and the interpolation position at the target moment;

[0173] Obtain the interpolation position at the target moment based on the initial interpolation position at the target moment, the output valid flag at the target moment, and the third corresponding relationship.

[0174] The interpolation position calculation device of the parallel time synchronizer provided in this application adopts the interpolation position calculation method of the parallel time synchronizer in the above-mentioned embodiment, and can solve the technical problems that the parallel time synchronizer consumes a long time when calculating the interpolation position and has a high feedback delay. Compared with the prior art, the beneficial effects of the interpolation position calculation device of the parallel time synchronizer provided in this application are the same as those of the interpolation position calculation method of the parallel time synchronizer provided in the above-mentioned embodiment, and other technical features in the interpolation position calculation device of the parallel time synchronizer are the same as the features disclosed in the above-mentioned embodiment method, and will not be elaborated here.

[0175] This application provides an interpolation position calculation device for a parallel time synchronizer. The interpolation position calculation device for the parallel time synchronizer includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the interpolation position calculation method of the parallel time synchronizer in the first embodiment above.

[0176] Next, refer to Figure 8 , which shows a schematic structural diagram of an interpolation position calculation device for a parallel time synchronizer suitable for implementing the embodiments of this application. The interpolation position calculation device for the parallel time synchronizer in the embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistant), PADs (Portable Application Description: tablet computers), PMPs (Portable Media Players), in-vehicle terminals (such as in-vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 8 The interpolation position calculation device of the parallel time synchronizer shown is only an example and should not impose any limitation on the functions and usage scope of the embodiments of this application.

[0177] As Figure 8As shown, the interpolation position calculation device of the parallel time synchronizer may include a processing device 1001 (such as a central processing unit, a graphics processing unit, etc.), which may perform various appropriate actions and processes according to a program stored in a ROM (Read Only Memory) 1002 or a program loaded from a storage device 1003 into a RAM (Random Access Memory) 1004. In the RAM 1004, various programs and data required for the operation of the interpolation position calculation device of the parallel time synchronizer are also stored. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other through a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Generally, the following systems may be connected to the I / O interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 may allow the interpolation position calculation device of the parallel time synchronizer to communicate with other devices wirelessly or wiredly to exchange data. Although the figure shows an interpolation position calculation device of the parallel time synchronizer having various systems, it should be understood that it is not required to implement or have all the shown systems. More or fewer systems may be alternatively implemented or had.

[0178] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts may be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program codes for performing the methods shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network through the communication device, or installed from the storage device 1003, or installed from the ROM 1002. When the computer program is executed by the processing device 1001, the above functions defined in the methods of the embodiments disclosed in the present application are executed.

[0179] The interpolation position calculation device of the parallel time synchronizer provided by this application, adopting the interpolation position calculation method of the parallel time synchronizer in the above embodiment, can solve the technical problems that the parallel time synchronizer consumes a long time in calculating the interpolation position and has a high feedback delay. Compared with the prior art, the beneficial effects of the interpolation position calculation device of the parallel time synchronizer provided by this application are the same as those of the interpolation position calculation method of the parallel time synchronizer provided by the above embodiment, and other technical features in the interpolation position calculation device of the parallel time synchronizer are the same as the features disclosed in the method of the previous embodiment, which will not be elaborated here.

[0180] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0181] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed in this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

[0182] This application provides a computer-readable storage medium, having computer-readable program instructions (i.e., computer programs) stored thereon, and the computer-readable program instructions are used to execute the interpolation position calculation method of the parallel time synchronizer in the above embodiment.

[0183] The computer-readable storage medium provided by this application can be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or components, or any combination of the above. More specific examples of computer-readable storage media can include, but are not limited to: electrical connections with one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) or flash memory, optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this embodiment, the computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or component. The program code contained on the computer-readable storage medium can be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination of the above.

[0184] The above computer-readable storage medium can be included in the interpolation position calculation device of the parallel time synchronizer; or it can exist separately and not be assembled into the interpolation position calculation device of the parallel time synchronizer.

[0185] The above computer-readable storage medium carries one or more programs. When the one or more programs are executed by the interpolation position calculation device of the parallel time synchronizer, the interpolation position calculation device of the parallel time synchronizer is caused to: determine the output data at the current moment based on the interpolation position and input data at the current moment; determine the sampling period at the current moment based on the output data and output valid flag at the current moment; perform arithmetic processing on the sampling period at the current moment to obtain the initial interpolation position at the target moment, where the arithmetic processing includes at least multiplication arithmetic processing, subtraction arithmetic processing, and division arithmetic processing based on a fixed constant; and perform overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment.

[0186] Computer program code for performing the operations of this application can be written in one or more programming languages or combinations thereof. The above-mentioned programming languages include object-oriented programming languages such as Java, Smalltalk, C++, and also include conventional procedural programming languages such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, executed as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user's computer through any kind of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (for example, by connecting through the Internet using an Internet service provider).

[0187] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of the code, and this module, program segment, or part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0188] The modules described in the embodiments of this application can be implemented in software or in hardware. Among them, the name of the module does not constitute a limitation to the unit itself in some cases.

[0189] The readable storage medium provided in this application is a computer-readable storage medium, and the computer-readable storage medium stores computer-readable program instructions (i.e., computer programs) for performing the interpolation position calculation method of the above-mentioned parallel time synchronizer, which can solve the technical problems that the parallel time synchronizer consumes a long time in calculating the interpolation position and has a high feedback delay. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the interpolation position calculation method of the parallel time synchronizer provided in the above embodiments, and will not be elaborated here.

[0190] The present application also provides a computer program product, including a computer program which, when executed by a processor, implements the steps of the interpolation position calculation method of the parallel time synchronizer as described above.

[0191] The computer program product provided by the present application can solve the technical problems that the parallel time synchronizer consumes a long time in calculating the interpolation position and has a high feedback delay. Compared with the prior art, the beneficial effects of the computer program product provided by the present application are the same as those of the interpolation position calculation method of the parallel time synchronizer provided in the above embodiments, and will not be elaborated herein.

[0192] The above are only partial embodiments of the present application, and thus do not limit the patent scope of the present application. Any equivalent structural transformation made under the technical concept of the present application by using the content of the specification and drawings of the present application, or any direct / indirect application in other related technical fields, is included in the patent protection scope of the present application.

Claims

1. A method for calculating the interpolation position of a parallel time synchronizer, characterized in that, The method described above includes: Determining the output data at the current moment based on the interpolation position and input data at the current moment; Determining the sampling period at the current moment based on the output data and output valid flag at the current moment; Performing arithmetic processing on the sampling period at the current moment to obtain the initial interpolation position at the target moment, where the arithmetic processing includes at least multiplication arithmetic processing, subtraction arithmetic processing, and division arithmetic processing based on a fixed constant; Performing overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment; The step of performing arithmetic processing on the sampling period at the current moment to obtain the initial interpolation position at the target moment includes: Performing multiplication arithmetic processing on the sampling period at the current moment based on a preset constant sequence to obtain a multiplication result; Performing subtraction arithmetic processing on the multiplication result and the stored value at the current moment to obtain a subtraction result, and updating the stored value at the target moment based on the subtraction result; Performing division arithmetic processing on the subtraction result based on the fixed constant to obtain the initial interpolation position at the target moment, specifically including: comparing the subtraction result of the current path with the subtraction result of the previous path. If the subtraction result of the current path is greater than the subtraction result of the previous path, then dividing the subtraction result of the current path by the fixed constant to calculate the initial interpolation position of the current path at the target moment. If the subtraction result of the current path is less than or equal to the subtraction result of the previous path, then dividing the subtraction result of the previous path by the fixed constant and subtracting 1 to calculate the initial interpolation position of the current path at the target moment.

2. The method according to claim 1, wherein The step of determining the output data at the current moment based on the interpolation position and input data at the current moment includes: Inputting the input data at the current moment into multiple parallel filters with different coefficients respectively to obtain the initial output data of the parallel filters at the current moment; Obtaining the first correspondence relationship among the initial output data at the current moment, the interpolation position at the current moment, the filtering weight, and the output data at the current moment; Obtaining the output data at the current moment based on the initial output data of the parallel filters at the current moment, the interpolation position at the current moment, the filtering weight, and the first correspondence relationship.

3. The method according to claim 1, wherein The step of determining the sampling period at the current moment based on the output data and output valid flag at the current moment includes: Determining the parallel error amount based on the output data and output valid flag at the current moment; Determining the average error amount based on the parallel error amount; Inputting the average error amount into a loop filter for filtering to obtain loop-filtered data; Determining the sampling period at the current moment based on the loop-filtered data.

4. The method according to claim 3, characterized in that, The step of determining the parallel error amount based on the output data and output valid flag at the current moment includes: When the output valid flag at the current moment is the first value, taking the first value as the parallel error amount; When the output valid flag at the current moment is the second value, obtain the second correspondence between the output data at the current moment and the parallel error amount, and based on the output data at the current moment and the second correspondence, obtain the parallel error amount.

5. The method according to claim 1, wherein Before the step of performing overflow correction on the initial interpolation position of the target moment to obtain the interpolation position of the target moment, it further includes: Based on the subtraction operation result of the target moment, determine the adjacent path subtraction operation result, the adjacent path subtraction operation result; Based on the adjacent path subtraction operation result, determine the output valid flag of the target moment.

6. The method according to claim 5, characterized in that The adjacent path subtraction operation result includes the subtraction operation result of the current path and the subtraction operation result of the previous path. The step of determining the output valid flag of the target moment based on the adjacent path subtraction operation result includes: When the subtraction operation result of the current path is less than or equal to the subtraction operation result of the previous path, use the first value as the output valid flag of the corresponding current path; When the subtraction operation result of the current path is greater than the subtraction operation result of the previous path, use the second value as the output valid flag of the corresponding current path.

7. An interpolation position calculation device for a parallel time synchronizer, characterized in that, The device includes: A parallel filtering module for determining the output data at the current moment based on the interpolation position at the current moment and the input data; A sampling period estimation module for determining the sampling period at the current moment based on the output data at the current moment and the output valid flag; A numerically controlled oscillator module for performing arithmetic processing on the sampling period at the current moment to obtain the initial interpolation position of the target moment. The arithmetic processing includes at least multiplication arithmetic processing, subtraction arithmetic processing, and division arithmetic processing based on a fixed constant; The numerically controlled oscillator module is further configured to perform overflow correction on the initial interpolation position of the target moment to obtain the interpolation position of the target moment; The numerically controlled oscillator module is further configured to perform multiplication arithmetic processing on the sampling period at the current moment based on a preset constant sequence to obtain a multiplication arithmetic result; Perform subtraction arithmetic processing on the multiplication arithmetic result and the stored value at the current moment to obtain a subtraction arithmetic result, and update the stored value of the target moment based on the subtraction arithmetic result; Perform division arithmetic processing on the subtraction arithmetic result based on the fixed constant to obtain the initial interpolation position of the target moment; The numerically controlled oscillator module is further configured to compare the subtraction operation result of the current path with the subtraction operation result of the previous path. If the subtraction operation result of the current path is greater than the subtraction operation result of the previous path, divide the subtraction operation result of the current path by the fixed constant to calculate the initial interpolation position of the current path at the target moment. If the subtraction operation result of the current path is less than or equal to the subtraction operation result of the previous path, divide the subtraction operation result of the previous path by the fixed constant and subtract 1 to calculate the initial interpolation position of the current path at the target moment.

8. An interpolation position calculation device for a parallel time synchronizer, characterized in that, The device includes: a memory, a processor, and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the interpolation position calculation method of the parallel time synchronizer according to any one of claims 1 to 6.

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