Audio processing chip, audio processing method, digital power amplifier tuning system and digital power amplifier tuning method

Abstract

The invention discloses an audio processing chip, an audio processing method, a digital power amplifier tuning system and a digital power amplifier tuning method, the digital power amplifier tuning system comprises a user configuration unit, an upper computer tool, a firmware processing unit and the audio processing chip, and high-speed transmission and real-time processing of static tuning parameters and dynamic tuning parameters can be realized. Tone tuning instructions and parameters are packaged by a PC tool and then transmitted to firmware, a protocol stack analyzes and completes protocol conversion, and tone tuning data are written into an audio chip register or an SRAM in real time to be directly read and processed by a DSP. The system adopts the DMA and FIFO design, improves the data transmission efficiency and real-time performance, supports the real-time tuning in the audio playing process, meets the high-performance debugging requirements in a complex audio scene, and has the advantages of high response speed, high tuning precision, simplicity and convenience in operation, and flexibility and expandability of the system.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and in particular to an audio processing chip, a processing method, a digital power amplifier tuning system and a tuning method. Background Art

[0002] With the development of audio technology, digital amplifiers are widely used in various audio devices. Compared with traditional analog amplifiers, digital amplifiers have obvious advantages in performance, energy efficiency and controllability. However, there are still many technical challenges in the actual application and debugging of digital amplifiers, especially in dynamic tuning and real-time debugging.

[0003] First, digital power amplifier systems involve a lot of digital signal processing (DSP) and complex control logic, and the debugging process is more complicated and difficult than that of analog power amplifiers. Developers not only need to be proficient in algorithm design, but also need to be familiar with hardware architecture and low-level communication protocols, which invisibly increases the difficulty and cycle of development and debugging.

[0004] Secondly, digital amplifiers have extremely high requirements for real-time performance during audio signal processing. In order to ensure the continuity and synchronization of audio playback, the processing of tuning parameters and audio signals needs to meet strict low-latency requirements. However, complex DSP algorithms and data transmission processes often increase processing delays, affect the real-time performance of the system, and even cause sound distortion or freezes during dynamic tuning.

[0005] In addition, digital power amplifier chips are usually limited by hardware resources, such as processing power, memory capacity, and data bandwidth, which further limits the ability of real-time tuning and dynamic parameter optimization. Especially when faced with highly complex sound effect algorithms or frequent dynamic adjustment needs, the existing architecture makes it difficult to ensure stable and smooth operation of the system.

[0006] The existing tuning architecture also has deficiencies in performance analysis and debugging. DSP software development itself is a multi-dimensional project, involving algorithm selection, programming language optimization, resource management, performance tuning and other links. The lack of a systematic tuning parameter management and debugging mechanism leads to inefficient tuning process and difficulty in balancing real-time and stability. Summary of the invention

[0007] The purpose of the present invention is to provide an audio processing chip, a processing method, a digital power amplifier tuning system and a tuning method to improve the efficiency and real-time performance of tuning data processing.

[0008] The present invention discloses an audio processing chip, the chip comprising: a storage unit and a DMA control unit integrated in an SRAM, a first communication interface and a digital signal processing unit; The storage unit is configured to store tuning parameters; wherein the tuning parameters include dynamic tuning parameters; The first communication interface is configured to receive the dynamic tuning parameters and transmit the dynamic tuning parameters to the DMA control unit; The DMA control unit is configured to receive the dynamic tuning parameters in real time and input the dynamic tuning parameters into the storage unit for storage; The digital signal processing unit is configured to read the tuning parameters from the storage unit and perform signal processing on the tuning parameters.

[0009] Furthermore, the tuning parameters also include static tuning parameters; The first communication interface is further configured to receive the static tuning parameters; and transmit the static tuning parameters to the storage unit for storage.

[0010] Furthermore, the storage unit includes: A running configuration area, configured to store the dynamic tuning parameters and the static tuning parameters; The running status area is configured to store the state variables during the tuning process.

[0011] Furthermore, the chip further comprises: The second communication interface is configured to receive at least one signal of the static tuning parameter, the dynamic tuning parameter and the state variable transmitted from the storage unit.

[0012] Furthermore, the chip further comprises: The main control unit is configured to exchange data with the SRAM through the first communication interface or the second communication interface.

[0013] Furthermore, the chip further comprises: The register unit is configured to be connected to the main control unit through a control port, and to receive and store the tuning instructions and static tuning parameters transmitted by the main control unit in real time.

[0014] Furthermore, the chip further includes: a FIFO buffer unit integrated in the SRAM, The FIFO buffer unit is configured to buffer data and transmit the dynamic tuning parameters to the DMA control unit in sequence.

[0015] The present invention also discloses an audio processing method, which comprises: After receiving the write instruction, the dynamic tuning parameters are transmitted from the first communication interface to the FIFO buffer unit in real time, and the FIFO buffer unit transmits the dynamic tuning parameters to the DMA control unit in sequence; the static tuning parameters are transmitted from the first communication interface to the storage unit for storage; The DMA control unit transmits the dynamic tuning parameters to the storage unit in real time for storage; The digital signal processing unit reads the dynamic tuning parameters from the storage unit in real time and performs signal processing on the dynamic tuning parameters.

[0016] Furthermore, the method further comprises: After receiving the read instruction, the second communication interface initiates a storage unit access request to read at least one signal of the static tuning parameters, dynamic tuning parameters and state variables stored in the storage unit.

[0017] Furthermore, the method further comprises: When the digital signal processing unit detects that the tuning process needs to be initialized or an abnormality occurs, the digital signal processing unit actively initiates a reset operation to reset the information stored in the working configuration area and the running status area in the storage unit.

[0018] The present invention also discloses a digital power amplifier tuning system, comprising: A user configuration unit configured to generate tuning configuration parameters; A host computer tool is configured to receive the tuning configuration parameters and generate register operation instructions and DSP configuration parameters according to the tuning configuration parameters; A firmware processing unit is configured to receive and parse the register operation instruction and DSP configuration parameters, and generate tuning instructions and tuning parameters according to the register operation instruction and DSP configuration parameters; an audio processing chip, configured to receive the tuning instruction and the tuning parameters transmitted by the firmware processing unit, and perform real-time processing on the audio signal according to the tuning instruction and the tuning parameters; The tuning parameters include dynamic tuning parameters and static tuning parameters, and the tuning instructions include tuning instructions corresponding to the dynamic tuning parameters and tuning instructions corresponding to the static tuning parameters.

[0019] Furthermore, the host computer tool includes: A register control unit configured to generate static tuning parameters and tuning instructions according to the tuning configuration parameters, and parse and map the static tuning parameters and tuning instructions into corresponding register operation instructions, which are sent by the register control unit to the firmware processing unit for processing; The DSP configuration unit is configured to generate DSP configuration parameters according to default tuning parameters or / the tuning configuration parameters, and send the DSP configuration parameters to the firmware processing unit for processing.

[0020] Furthermore, the firmware processing unit includes: A flash memory configured to receive and update the DSP configuration parameters; A protocol stack configured to parse the DSP configuration parameters and the register operation instructions in real time, perform protocol conversion on the parsed DSP configuration parameters and the parsed register operation instructions, and update the DSP configuration parameters in the flash memory in real time; The storage unit is configured to store the tuning instructions and the tuning parameters obtained after the protocol conversion, and update the tuning instructions and the tuning parameters to the audio processing chip in real time.

[0021] The present invention also discloses a real-time debugging digital power amplifier tuning method, the method comprising: The user configuration unit generates tuning configuration parameters; The upper computer tool receives the tuning configuration parameters, and generates tuning instructions and tuning parameters according to the tuning configuration parameters; The firmware processing unit receives and analyzes the tuning instruction and the tuning parameter transmitted by the parameter management and debugging unit; The audio processing chip receives the tuning instruction and the tuning parameters transmitted by the firmware processing unit, and processes the audio signal in real time according to the tuning instruction and the tuning parameters; The tuning parameters include dynamic tuning parameters and static tuning parameters, and the tuning instructions include tuning instructions corresponding to the dynamic tuning parameters and tuning instructions corresponding to the static tuning parameters.

[0022] Compared with the prior art, the present invention has at least the following technical effects: The present invention realizes high-speed transmission and real-time storage of dynamic tuning parameters by introducing a DMA control unit in the audio processing chip, thereby improving the efficiency and real-time performance of tuning data processing. The digital signal processing unit can directly read the latest dynamic tuning parameters from the storage unit in real time, thereby realizing precise adjustment and dynamic optimization of sound effects and meeting high-performance tuning requirements in complex audio application scenarios.

[0023] Furthermore, the real-time debugging digital power amplifier tuning system provided by the present invention has good user-friendliness and flexible scalability. Users can directly input tuning parameters through the PC tool interface, and the system automatically completes data processing and distribution, thereby avoiding user interaction with the underlying hardware and simplifying the operation process. In addition, due to the use of hardware abstraction design, the firmware and chip collaborate to perform underlying operations, further reducing the difficulty of development and use. Through the efficient collaboration of PC tools and firmware, tuning parameters can be accurately parsed, quickly converted and distributed in real time, making the tuning process efficient and reliable, and comprehensively improving the real-time and flexibility of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a simplified structural diagram of an audio processing chip in Embodiment 1 of the present invention; Figure 2 This is a flow chart of the method of the audio processing chip in the second embodiment of the present invention; Figure 3 This is a structural diagram of a digital power amplifier tuning system in Embodiment 3 of the present invention; Figure 4 This is a flow chart of a method for a digital power amplifier tuning system in Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0025] The following is a description of an audio processing chip, a processing method, a digital amplifier tuning system and a tuning method of the present invention in conjunction with schematic diagrams, wherein preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as being widely known to those skilled in the art and not as a limitation of the present invention.

[0026] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to facilitate and clearly assist in illustrating the purpose of the embodiments of the present invention.

[0027] Embodiment 1 Please refer to Figure 1 This embodiment discloses an audio processing chip, the chip comprising: A storage unit and a DMA (direct memory access control unit) integrated in an SRAM (static random access memory), a first communication interface, and a digital signal processing unit.

[0028] The storage unit is configured to store tuning parameters; wherein the tuning parameters include dynamic tuning parameters.

[0029] The first communication interface is configured to receive the dynamic tuning parameters and transmit the dynamic tuning parameters to a DMA control unit.

[0030] The DMA control unit is configured to receive the dynamic tuning parameters in real time, and input the dynamic tuning parameters into the storage unit for storage.

[0031] The digital signal processing unit is configured to read the tuning parameters from the storage unit and perform signal processing on the tuning parameters.

[0032] It is understandable that the dynamic tuning parameters are tuning data that need to be frequently adjusted according to real-time changing audio signals or external control instructions during the audio processing process, usually including real-time equalizer adjustment, dynamic gain control, compression parameters or sound effect detail adjustment in specific scenarios. Dynamic tuning parameters are used to achieve real-time optimization of audio processing and can be updated instantly as audio content or user operations change. SRAM is a high-speed, volatile memory that can continuously save data when powered on and data will be lost after power failure. It supports frequent and fast read and write operations and is very suitable for use as a cache or temporary storage area in the system. It is widely used in scenarios that require real-time response, such as tuning parameters and state variable storage in audio processing chips.

[0033] In this embodiment, a DMA control unit is introduced in the audio processing chip to realize the movement of dynamic tuning parameters between the SRAM and the first communication interface (that is, the real-time debugging data synchronization process). The DMA control unit can automatically initiate the transfer and update process of the tuning parameters, and store the data directly in the SRAM for the digital signal processing unit to read in real time without the need for CPU (central processing unit) intervention, thereby improving the efficiency and real-time performance of tuning data processing. The digital signal processing unit can directly read the latest dynamic tuning parameters from the storage unit in real time, thereby realizing precise adjustment and dynamic optimization of sound effects, and meeting the high-performance tuning requirements in complex audio application scenarios.

[0034] In a specific embodiment, the DMA control unit includes a DMA controller, which can automatically initiate the transfer and update process of the tuning parameters and directly store the data in the SRAM for the digital signal processing unit to read in real time.

[0035] In another specific embodiment, the digital signal processing unit includes a DSP (digital signal processor), which is responsible for processing audio signals and realizing various audio processing functions including equalization, filtering, dynamic gain control, etc. The DSP interacts with the SRAM, and can not only read the latest dynamic tuning parameters and static tuning parameters in real time, but also write back the state variables or intermediate data generated during the processing to the SRAM.

[0036] Furthermore, in this embodiment, the first communication interface is further configured to receive the static tuning parameters; and transmit the static tuning parameters to the storage unit for storage.

[0037] It is understandable that the static tuning parameters are relatively fixed tuning configuration information that is updated with low periodicity during the audio processing process, and usually include basic tuning parameters such as filter coefficients, gain values, sound effect mode selection, equalizer parameters, and limiter settings. These parameters are mainly used to set the basic working state of the audio processing chip so that the audio effect is stable and consistent. Static tuning parameters are generally set when the device leaves the factory, user configuration, or in a specific scenario, and are only adjusted when necessary. They can be flexibly configured according to actual needs to adapt to different audio application scenarios.

[0038] In this embodiment, the first communication interface is further configured to receive static tuning parameters and transmit them to a storage unit for storage. This design enables the static tuning parameters to be managed and stored in a unified manner with the dynamic tuning parameters, making it convenient for the digital signal processing unit to call them on demand during the audio processing process, avoiding repeated communications with the external master control, reducing communication load and processing delays, and improving the tuning flexibility and real-time performance of the system. At the same time, it facilitates the subsequent reading, verification and updating of static parameters, thereby enhancing the maintainability and expandability of the system.

[0039] Furthermore, the audio processing chip disclosed in this embodiment also includes: a second communication interface.

[0040] Specifically, the second communication interface is configured to read at least one signal of a static tuning parameter, a dynamic tuning parameter and a state variable from the SRAM storage unit.

[0041] In a specific embodiment, the state variables include but are not limited to the loading status of tuning parameters, update progress, execution status of the current tuning task, anomaly detection flag and DSP processing state variables. It can be understood that those skilled in the art can flexibly configure and adjust the state variables according to actual application requirements.

[0042] It can be seen that the audio processing chip disclosed in this embodiment has the ability to read and write tuning parameters in parallel. While the digital signal processing unit reads the tuning parameters or state variables, it can support writing new tuning parameters into the storage unit in real time through the communication interface or DMA control unit, thereby realizing high-speed two-way flow and real-time update of tuning data.

[0043] In a specific embodiment, the first communication interface and the second communication interface are I2C (Inter-Integrated Circuit Communication) interfaces, which are used to communicate with external devices, such as PC (Personal Host) debugging tools, host computers or other terminal devices. It can be understood by those skilled in the art that in a specific implementation, the first communication interface and the second communication interface can select I2C, SPI (Serial Peripheral Interface), UART (Universal Asynchronous Receiver / Transmitter) or other communication interfaces supporting data transmission according to actual application requirements, so as to adapt to the communication methods of different external devices and system design requirements, and ensure the efficient transmission of tuning parameters and the flexible compatibility of the system.

[0044] Furthermore, the audio processing chip disclosed in this embodiment also includes a FIFO (First In First Out) buffer unit integrated in the SRAM.

[0045] Specifically, the FIFO buffer unit is configured to buffer data and transmit the dynamic tuning parameters to the DMA control unit in sequence.

[0046] In this embodiment, the introduction of the FIFO buffer unit can effectively improve the stability and orderliness of the tuning data transmission, and avoid data loss, congestion or disorder problems caused by communication rate mismatch or data burst.

[0047] Furthermore, in this embodiment, the audio processing chip also includes: a main control unit.

[0048] The main control unit is configured to exchange data with the SRAM through the first communication interface or the second communication interface.

[0049] Specifically, when the main control unit receives the write instruction from the external input, it sends the tuning instruction and the tuning signal to the first communication interface, and writes the tuning parameters, the tuning instruction and other information into the storage unit of the SRAM through the first communication interface.

[0050] When the main control unit receives the read instruction input from the outside, it retrieves the tuning parameters and status parameters and other information from the SRAM to the second communication interface, and the main control unit can read the information through the second communication interface.

[0051] In a specific embodiment, the main control unit may be a highly integrated microcontroller (MCU) or a central processing unit (CPU), and those skilled in the art may select the main control unit according to actual conditions.

[0052] Furthermore, in this embodiment, the audio processing chip also includes a register unit and a control module.

[0053] Specifically, the register unit is configured to be connected to the main control unit via a control port, and to receive and store the tuning instructions and tuning parameters transmitted by the main control unit in real time.

[0054] In this embodiment, through the control port, the main control unit can write the tuning parameters into the control port and transmit them to the register through a direct write operation, and can also receive information transmitted by the second communication interface through the communication protocol.

[0055] In a specific embodiment, the register address range of the control port can be 0x00 to 0x40. This means that the main control unit can perform read and write operations within this address range to configure and control the functions of the audio processing chip. Of course, those skilled in the art can select different address ranges according to actual conditions.

[0056] In summary, in this embodiment, the storage, transmission and processing of tuning data are realized by the coordinated work of multiple components including the digital signal processing unit, the storage unit, the FIFO buffer unit, the DMA control unit, the first communication interface, the second communication interface, the main control unit and the control port. With this design, the digital power amplifier can operate in an asynchronous static tuning mode, while supporting active tuning and synchronous operation.

[0057] It is understandable that the configurations described in the present invention are all controlled by a hardware state machine integrated inside the chip. The state machine is preset by the manufacturer during the chip design phase and automatically implements scheduling and control between various functional units through hardware logic.

[0058] Embodiment 2 Please refer to Figure 2 Based on the same inventive concept, this embodiment discloses an audio processing method, the method comprising: S1. After receiving the write instruction, the dynamic tuning parameters are transmitted from the first communication interface to the FIFO buffer unit in real time, and the FIFO buffer unit transmits the dynamic tuning parameters to the DMA control unit in sequence; the static tuning parameters are transmitted from the second communication interface to the storage unit for storage; S2. The DMA control unit transmits the dynamic tuning parameters in real time to the storage unit for storage; S3. The digital signal processing unit reads the dynamic tuning parameters from the storage unit in real time and performs signal processing on the dynamic tuning parameters.

[0059] In this embodiment, the system can achieve high-speed transmission and real-time storage of dynamic tuning parameters, significantly improving the efficiency and real-time performance of tuning data processing. The collaboration between the FIFO buffer unit and the DMA control unit avoids frequent intervention of the main control chip, reduces the system load, and improves the continuity and stability of data transmission. The separate storage of dynamic tuning parameters and static tuning parameters enables the digital signal processing unit (DSP) to quickly and accurately access the tuning data and perform audio processing in real time.

[0060] Furthermore, in this embodiment, the method also includes: after receiving the read instruction, the communication interface initiates an SRAM storage unit access request to read at least one signal among the static tuning parameters, dynamic tuning parameters and state variables stored in the SRAM storage unit.

[0061] Furthermore, in this embodiment, the method further includes: when the digital signal processing unit (DSP) detects that the tuning process needs to be reinitialized or an abnormality occurs, a reset operation can be initiated actively. In response to the reset signal, the working configuration area and the operating status area in the SRAM storage unit will be cleared and restored to the initial state, thereby ensuring that the system is in a stable and controllable working state during the subsequent tuning process, and avoiding the influence of parameter residue or abnormal state on the audio processing effect.

[0062] In summary, through the audio processing method disclosed in this embodiment, the system can achieve high-speed transmission, real-time storage and efficient processing of tuning parameters, significantly improving the real-time and flexibility of tuning. The dynamic tuning parameters are automatically transferred to SRAM via FIFO buffering and DMA, reducing the intervention of the main control and improving data processing efficiency. Static and dynamic tuning parameters are stored in a unified manner, which facilitates the DSP to quickly read and process audio signals in real time. The method supports the main control to access SRAM in real time, obtain tuning parameters and state variables, and enhance the controllability and maintainability of the system. At the same time, the design introduces a working configuration area and a status area to support DSP abnormality detection and active reset, thereby improving system stability and the reliability of sound effect processing.

[0063] Embodiment 3 Please refer to Figure 3 Based on the same inventive concept, this embodiment further discloses a digital power amplifier tuning system, the system comprising the audio processing chip disclosed in the first and second embodiments. Specifically, the architecture of the system comprises: The user configuration unit is configured to generate tuning configuration parameters.

[0064] The host computer tool is configured to receive the tuning configuration parameters and generate register operation instructions and DSP configuration parameters according to the tuning configuration parameters.

[0065] The firmware processing unit is configured to receive and parse the register operation instruction and DSP configuration parameters, and generate tuning instructions and tuning parameters according to the register operation instruction and DSP configuration parameters.

[0066] The audio processing chip is configured to receive the tuning instruction and the tuning parameters transmitted by the firmware processing unit, and to process the audio signal in real time according to the tuning instruction and the tuning parameters.

[0067] The tuning parameters include dynamic tuning parameters and static tuning parameters, and the tuning instructions include tuning instructions corresponding to the dynamic tuning parameters and tuning instructions corresponding to the static tuning parameters.

[0068] In this embodiment, the real-time debugging digital power amplifier tuning system has good user-friendliness and flexible scalability. Users can directly input tuning parameters through the PC tool interface, and the system automatically completes data processing and distribution, thereby avoiding user interaction with the underlying hardware and simplifying the operation process. In addition, due to the use of hardware abstraction design, the firmware and chip collaborate to perform underlying operations, which can further reduce the difficulty of development and use. Furthermore, through the efficient collaboration of PC tools and firmware, the tuning parameters can be accurately parsed, quickly converted and distributed in real time, making the tuning process efficient and reliable, and comprehensively improving the real-time and flexibility of the system.

[0069] In this embodiment, in the user interface (UI) configuration module, the user can input various tuning configuration parameters through the graphical UI interface. The input tuning configuration parameters can be of floating point (double) type, supporting higher precision audio adjustment, such as frequency points, gain values, filter coefficients, etc.

[0070] Furthermore, in this embodiment, the graphical UI interface can provide a variety of human-computer interaction methods such as a slider, a value input box, and a curve drawing area, and supports users to adjust and visualize audio processing modules such as multi-band equalizer (EQ), low-pass filter (LPF), high-pass filter (HPF), band-pass filter (BPF), and dynamic range control (DRC) in real time. Users can intuitively adjust the center frequency, gain, filter slope, and bandwidth of each frequency band, and the system will automatically convert the floating-point parameters entered by the user into corresponding tuning configuration parameters.

[0071] Furthermore, in this embodiment, the host computer tool has parameter parsing, format conversion and data packaging functions, and can convert the original parameter data input by the user into a standardized data format recognizable by the system, such as fixed-point numbers, integers or DSP configuration parameters encapsulated in a specific protocol. This data can be directly sent to the firmware processing unit to achieve automatic loading and real-time adjustment of subsequent tuning parameters, thereby improving the convenience of user operation and the accuracy of system tuning. This design effectively reduces the complexity of user interaction with the underlying hardware and enhances the flexibility and scalability of the system.

[0072] In this embodiment, the host computer tool includes: a register control unit and a DSP configuration unit.

[0073] The register control unit is a key hardware component in an embedded system. It is mainly responsible for converting the configuration parameters passed by the software layer (such as firmware or operating system) into register operation instructions that can be recognized by the hardware, thereby realizing the control and configuration of hardware functions.

[0074] In this embodiment, the register control unit is configured to generate the static tuning parameters and the tuning instructions according to the tuning configuration parameters, and map the tuning instructions and the static tuning parameters into corresponding register operation instructions and send them to the firmware processing unit.

[0075] In a digital signal processing (DSP) system, the DSP configuration unit is mainly responsible for managing and configuring the hardware resources inside the DSP to optimize signal processing performance.

[0076] In this embodiment, the DSP configuration unit is configured to generate DSP configuration parameters according to the default tuning parameters and / or the tuning configuration parameters, and send the DSP configuration parameters to the firmware processing unit for processing.

[0077] In another specific embodiment, the DSP configuration parameter includes parameter type identification, storage location indication information, check code, timestamp or version information, etc. Preferably, the size of the DSP configuration parameter is 4 bytes (Int32) to meet the data processing and transmission efficiency requirements of the system. Of course, those skilled in the art can appropriately adjust the format and size of the DSP configuration parameter according to actual application requirements, parameter complexity or system resource conditions.

[0078] In another specific embodiment, the host computer tool further includes a second control port.

[0079] Specifically, the second control port is configured to receive the tuning configuration parameters configured by the user, and transmit the tuning configuration parameters to the register control unit and the DSP configuration unit.

[0080] It can be understood that the firmware processing unit is a key component in an embedded system and is primarily responsible for executing instructions stored in the firmware to control hardware operations and system functions.

[0081] In this embodiment, the firmware processing unit is used to receive the register operation instruction issued by the register control unit, and complete the write operation of the internal register unit of the audio processing chip according to the instruction content, so as to realize the loading and configuration of the static tuning parameters. At the same time, the firmware processing unit can also receive the dynamic tuning parameters DSP configuration parameters issued by the DSP configuration module, and store the dynamic tuning parameters in the SRAM storage unit after parsing, so as to be read and called by the digital signal processing unit (DSP) in real time.

[0082] In a specific embodiment, the firmware processing unit includes: The flash memory is configured to receive and update the DSP configuration parameters.

[0083] The protocol stack is configured to parse in real time and perform protocol conversion on the parsed DSP configuration parameters and the register operation instructions, and update the DSP configuration parameters in the flash memory in real time.

[0084] The storage unit is configured to store the tuning instructions and the tuning parameters obtained after the protocol conversion, and update the tuning instructions and the tuning parameters to the audio processing chip in real time.

[0085] In another specific embodiment, the configuration storage unit includes: An initialization hardware driver unit is configured to initialize the audio processing chip and its peripheral hardware. A current tuning parameter writing module is configured to write static tuning parameters and tuning instructions into the register and synchronize them into the SRAM. An active tuning synchronization unit is used to input the dynamic tuning parameters and tuning instructions stored in the flash memory into the SRAM in the audio processing chip.

[0086] Through the above digital amplifier tuning system, the tuning instructions and tuning parameters can be configured by the user in real time through a friendly interface, and encapsulated as DSP configuration parameters via PC tools and transmitted to the firmware processing unit. The protocol stack in the firmware can parse and convert the received DSP configuration parameters, so that subsequent tuning instructions and parameters can be accurately sent to the audio processing chip. The system design supports synchronizing dynamic tuning parameters to the SRAM inside the chip for real-time call processing by the DSP, thereby achieving real-time tuning without delay during audio playback, improving the system's response speed, tuning accuracy, and overall tuning flexibility and reliability.

[0087] It can be understood that the audio processing chip disclosed in this embodiment is substantially the same as the audio processing chip disclosed in Embodiment 1 and Embodiment 2. The technical features and technical effects it possesses have been described in detail in Embodiment 1 and Embodiment 2, and will not be repeated here.

[0088] Embodiment 4 Please refer to Figure 4 Based on the same inventive concept, this embodiment further discloses a real-time debugging digital power amplifier tuning method, which is implemented by the real-time debugging digital power amplifier tuning system disclosed in the third embodiment, and the method includes: S1. The user configuration unit generates tuning configuration parameters; S2. The host computer tool receives the tuning configuration parameters and generates register operation instructions and DSP configuration parameters according to the tuning configuration parameters; S3. The firmware processing unit receives and parses the register operation instruction and DSP configuration parameters; and generates register operation instructions and DSP configuration parameters according to the register operation instruction and DSP configuration parameters; S4. The audio processing chip receives the tuning instruction and the tuning parameters transmitted by the firmware processing unit, and processes the audio signal in real time according to the tuning instruction and the tuning parameters; The tuning parameters include dynamic tuning parameters and static tuning parameters, and the tuning instructions include tuning instructions corresponding to the dynamic tuning parameters and tuning instructions corresponding to the static tuning parameters.

[0089] It is understandable that the specific implementation method and the technical effects that can be achieved by the method have been described in Example 3 and will not be repeated here.

[0090] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. An audio processing chip, characterized in that: The chip includes: a storage unit and a DMA control unit integrated in the SRAM, a first communication interface and a digital signal processing unit; The storage unit is configured to store tuning parameters; wherein the tuning parameters include dynamic tuning parameters; The first communication interface is configured to receive the dynamic tuning parameters and transmit the dynamic tuning parameters to the DMA control unit; The DMA control unit is configured to receive the dynamic tuning parameters in real time and input the dynamic tuning parameters into the storage unit for storage; The digital signal processing unit is configured to read the tuning parameters from the storage unit and perform signal processing on the tuning parameters.

2. The audio processing chip according to claim 1, characterized in that: The tuning parameters also include static tuning parameters; The first communication interface is further configured to receive the static tuning parameters; and transmit the static tuning parameters to the storage unit for storage.

3. The audio processing chip as claimed in claim 2, characterized in that: The storage unit comprises: A running configuration area, configured to store the dynamic tuning parameters and the static tuning parameters; The running status area is configured to store the state variables during the tuning process.

4. The audio processing chip as claimed in claim 3, characterized in that: The chip further comprises: The second communication interface is configured to receive at least one signal of the static tuning parameter, the dynamic tuning parameter and the state variable transmitted from the storage unit.

5. The audio processing chip as claimed in claim 4, characterized in that: The chip further comprises: The main control unit is configured to exchange data with the SRAM through the first communication interface or the second communication interface.

6. The audio processing chip as claimed in claim 5, characterized in that: The chip further comprises: The register unit is configured to be connected to the main control unit through a control port, and to receive and store the tuning instructions and static tuning parameters transmitted by the main control unit in real time.

7. The audio processing chip according to claim 1, characterized in that: The chip further comprises: a FIFO buffer unit integrated in the SRAM, The FIFO buffer unit is configured to buffer data and transmit the dynamic tuning parameters to the DMA control unit in sequence.

8. An audio processing method, characterized in that: The method is implemented by using an audio processing chip as described in any one of claims 1 to 7, and comprises: After receiving the write instruction, the dynamic tuning parameters are transmitted from the first communication interface to the FIFO buffer unit in real time, and the FIFO buffer unit transmits the dynamic tuning parameters to the DMA control unit in sequence; the static tuning parameters are transmitted from the first communication interface to the storage unit for storage; The DMA control unit transmits the dynamic tuning parameters to the storage unit in real time for storage; The digital signal processing unit reads the dynamic tuning parameters from the storage unit in real time and performs signal processing on the dynamic tuning parameters.

9. The audio processing method according to claim 8, characterized in that: The method further comprises: After receiving the read instruction, the second communication interface initiates a storage unit access request to read at least one signal of the static tuning parameters, dynamic tuning parameters and state variables stored in the storage unit.

10. The audio processing method according to claim 8, characterized in that: The method further comprises: When the digital signal processing unit detects that the tuning process needs to be initialized or an abnormality occurs, the digital signal processing unit actively initiates a reset operation to reset the information stored in the working configuration area and the running status area in the storage unit.

11. A digital power amplifier tuning system, characterized in that: The system comprises an audio processing chip as claimed in any one of claims 1 to 7, wherein: A user configuration unit configured to generate tuning configuration parameters; A host computer tool is configured to receive the tuning configuration parameters and generate register operation instructions and DSP configuration parameters according to the tuning configuration parameters; A firmware processing unit is configured to receive and parse the register operation instruction and DSP configuration parameters, and generate tuning instructions and tuning parameters according to the register operation instruction and DSP configuration parameters; an audio processing chip, configured to receive the tuning instruction and the tuning parameters transmitted by the firmware processing unit, and perform real-time processing on the audio signal according to the tuning instruction and the tuning parameters; The tuning parameters include dynamic tuning parameters and static tuning parameters, and the tuning instructions include tuning instructions corresponding to the dynamic tuning parameters and tuning instructions corresponding to the static tuning parameters.

12. The digital power amplifier tuning system according to claim 11, characterized in that: The host computer tool includes: A register control unit configured to generate static tuning parameters and tuning instructions according to the tuning configuration parameters, and parse and map the static tuning parameters and tuning instructions into corresponding register operation instructions, which are sent by the register control unit to the firmware processing unit for processing; The DSP configuration unit is configured to generate DSP configuration parameters according to default tuning parameters or / the tuning configuration parameters, and send the DSP configuration parameters to the firmware processing unit for processing.

13. The digital power amplifier tuning system according to claim 12, characterized in that: The firmware processing unit comprises: A flash memory configured to receive and update the DSP configuration parameters; A protocol stack configured to parse the DSP configuration parameters and the register operation instructions in real time, perform protocol conversion on the parsed DSP configuration parameters and the parsed register operation instructions, and update the DSP configuration parameters in the flash memory in real time; A storage unit is configured to store the tuning instructions and the tuning parameters obtained after the protocol conversion, and update the tuning instructions and the tuning parameters to the audio processing chip in real time.

14. A digital power amplifier tuning method, characterized in that: The method is implemented by using the digital power amplifier tuning system according to any one of claims 11 to 13, and comprises: The user configuration unit generates tuning configuration parameters; The host computer tool receives the tuning configuration parameters, and generates register operation instructions and DSP configuration parameters according to the tuning configuration parameters; The firmware processing unit receives and parses the register operation instruction and the DSP configuration parameter, and generates the tuning instruction and the tuning parameter according to the register operation instruction and the DSP configuration parameter; The audio processing chip receives the tuning instruction and the tuning parameters transmitted by the firmware processing unit, and processes the audio signal in real time according to the tuning instruction and the tuning parameters; The tuning parameters include dynamic tuning parameters and static tuning parameters, and the tuning instructions include tuning instructions corresponding to the dynamic tuning parameters and tuning instructions corresponding to the static tuning parameters.

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