Audio processing chip, processing method, digital power amplifier tuning system and tuning method

Abstract

The present invention discloses an audio processing chip, a processing method, a digital power amplifier tuning system and a tuning method. The system includes a user configuration unit, a host computer tool, a firmware processing unit and an audio processing chip, and can realize high-speed transmission and real-time processing of static tuning parameters and dynamic tuning parameters. Tuning instructions and parameters are encapsulated by the PC tool and then transmitted to the firmware. The protocol stack parses and completes protocol conversion, and the tuning data is written into the audio chip register or SRAM in real time for direct reading and processing by the DSP. The system adopts DMA and FIFO designs to improve data transmission efficiency and real-time performance, supports real-time tuning during audio playback, meets the high-performance debugging requirements in complex audio scenarios, and has the advantages of fast response speed, high tuning accuracy, simple operation and flexible system scalability.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and in particular to an audio processing chip, a processing method, a digital power amplifier tuning system and a tuning method. Background Art

[0002] With the development of audio technology, digital amplifiers are widely used in various audio devices. Compared with traditional analog amplifiers, digital amplifiers have obvious advantages in performance, energy efficiency and controllability. However, there are still many technical challenges in the actual application and debugging of digital amplifiers, especially in dynamic tuning and real-time debugging.

[0003] First, digital power amplifier systems involve a lot of digital signal processing (DSP) and complex control logic, and the debugging process is more complicated and difficult than that of analog power amplifiers. Developers not only need to be proficient in algorithm design, but also need to be familiar with hardware architecture and low-level communication protocols, which invisibly increases the difficulty and cycle of development and debugging.

[0004] Secondly, digital amplifiers have extremely high requirements for real-time performance during audio signal processing. In order to ensure the continuity and synchronization of audio playback, the processing of tuning parameters and audio signals needs to meet strict low-latency requirements. However, complex DSP algorithms and data transmission processes often increase processing delays, affect the real-time performance of the system, and even cause sound distortion or freezes during dynamic tuning.

[0005] In addition, digital power amplifier chips are usually limited by hardware resources, such as processing power, memory capacity, and data bandwidth, which further limits the ability of real-time tuning and dynamic parameter optimization. Especially when faced with highly complex sound effect algorithms or frequent dynamic adjustment needs, the existing architecture makes it difficult to ensure stable and smooth operation of the system.

[0006] The existing tuning architecture also has deficiencies in performance analysis and debugging. DSP software development itself is a multi-dimensional project, involving algorithm selection, programming language optimization, resource management, performance tuning and other links. The lack of a systematic tuning parameter management and debugging mechanism leads to inefficient tuning process and difficulty in balancing real-time and stability. Summary of the invention

[0007] The purpose of the present invention is to provide an audio processing chip, a processing method, a digital power amplifier tuning system and a tuning method to improve the efficiency and real-time performance of tuning data processing.

[0008] The present invention discloses an audio processing chip, the chip comprising: a storage unit and a DMA control unit integrated in an SRAM, a first communication interface and a digital signal processing unit;

[0009] The storage unit is configured to store tuning parameters; wherein, the tuning parameters include dynamic tuning parameters;

[0010] The first communication interface is configured to receive the dynamic tuning parameters and transmit the dynamic tuning parameters into the DMA control unit;

[0011] The DMA control unit is configured to receive the dynamic tuning parameters in real time and input the dynamic tuning parameters into the storage unit for storage;

[0012] The digital signal processing unit is configured to read the tuning parameters from the storage unit and perform signal processing on the tuning parameters.

[0013] Further, the tuning parameters further include static tuning parameters;

[0014] The first communication interface is further configured to receive the static tuning parameters; and transmit the static tuning parameters into the storage unit for storage.

[0015] Further, the storage unit includes:

[0016] An operation configuration area, configured to store the dynamic tuning parameters and the static tuning parameters;

[0017] An operation status area, configured to store status variables during the tuning process.

[0018] Further, the chip further includes:

[0019] A second communication interface, configured to receive at least one of the signals of the static tuning parameters, the dynamic tuning parameters, and the status variables transmitted from the storage unit.

[0020] Further, the chip further includes:

[0021] A main control unit, configured to perform data exchange with the SRAM through the first communication interface or the second communication interface.

[0022] Further, the chip further includes:

[0023] A register unit, configured to be connected to the main control unit through a control port, and receive and store in real time the tuning instructions and the static tuning parameters transmitted by the main control unit.

[0024] Further, the chip further includes: a FIFO buffer unit integrated in the SRAM,

[0025] The FIFO buffer unit is configured to buffer data and sequentially transmit the dynamic tuning parameters to the DMA control unit in order.

[0026] The present invention also discloses an audio processing method, which includes:

[0027] After receiving a write instruction, the dynamic tuning parameters are real-time transmitted from the first communication interface to the FIFO buffer unit, and the FIFO buffer unit sequentially transmits the dynamic tuning parameters to the DMA control unit in order; the static tuning parameters are transmitted from the first communication interface to the storage unit for storage;

[0028] The DMA control unit real-time transmits the dynamic tuning parameters to the storage unit for storage;

[0029] The digital signal processing unit reads the dynamic tuning parameters from the storage unit in real-time and performs signal processing on the dynamic tuning parameters.

[0030] Further, the method further includes:

[0031] After receiving a read instruction, the second communication interface initiates a storage unit access request to read at least one of the static tuning parameters, dynamic tuning parameters, and status variables stored in the storage unit.

[0032] Further, the method further includes:

[0033] When the digital signal processing unit detects that the tuning process needs to be initialized or an abnormality occurs, the digital signal processing unit actively initiates a reset operation to reset the information stored in the working configuration area and the running status area of the storage unit.

[0034] The present invention also discloses a digital power amplifier tuning system, including:

[0035] A user configuration unit, configured to generate tuning configuration parameters;

[0036] An upper computer tool, configured to receive the tuning configuration parameters and generate register operation instructions and DSP configuration parameters according to the tuning configuration parameters;

[0037] A firmware processing unit, configured to receive and parse the register operation instructions and DSP configuration parameters, and generate tuning instructions and tuning parameters according to the register operation instructions and DSP configuration parameters;

[0038] An audio processing chip, configured to receive the tuning instructions and the tuning parameters transmitted by the firmware processing unit, and perform real-time processing on the audio signal according to the tuning instructions and the tuning parameters;

[0039] Among them, the tuning parameters include dynamic tuning parameters and static tuning parameters, and the tuning instructions include the tuning instructions corresponding to the dynamic tuning parameters and the tuning instructions corresponding to the static tuning parameters.

[0040] Furthermore, the host computer tool includes:

[0041] A register control unit, configured to generate static tuning parameters and tuning instructions according to the tuning configuration parameters, and parse and map the static tuning parameters and tuning instructions into corresponding register operation instructions, and the register operation instructions are sent by the register control unit to the firmware processing unit for processing;

[0042] A DSP configuration unit, configured to generate DSP configuration parameters according to default tuning parameters or / and the tuning configuration parameters, and send the DSP configuration parameters to the firmware processing unit for processing.

[0043] Furthermore, the firmware processing unit includes:

[0044] A flash memory, configured to receive and update the DSP configuration parameters;

[0045] A protocol stack, configured to parse the DSP configuration parameters and the register operation instructions in real time, perform protocol conversion on the parsed DSP configuration parameters and the parsed register operation instructions, and update the DSP configuration parameters in the flash memory in real time;

[0046] A configuration storage unit, configured to store the tuning instructions and the tuning parameters obtained after protocol conversion, and update the tuning instructions and the tuning parameters to the audio processing chip in real time.

[0047] The present invention also discloses a method for tuning a digital power amplifier in real-time debugging, and the method includes:

[0048] A user configuration unit generates tuning configuration parameters;

[0049] The host computer tool receives the tuning configuration parameters, and generates tuning instructions and tuning parameters according to the tuning configuration parameters;

[0050] The firmware processing unit receives and parses the tuning instructions and the tuning parameters transmitted by the parameter management and debugging unit;

[0051] The audio processing chip receives the tuning instructions and the tuning parameters transmitted by the firmware processing unit, and performs real-time processing on the audio signal according to the tuning instructions and the tuning parameters;

[0052] Among them, the tuning parameters include dynamic tuning parameters and static tuning parameters, and the tuning instructions include the tuning instructions corresponding to the dynamic tuning parameters and the tuning instructions corresponding to the static tuning parameters.

[0053] Compared with the prior art, the present invention has at least the following technical effects:

[0054] The present invention realizes the high-speed transmission and real-time storage of dynamic tuning parameters by introducing a DMA control unit into the audio processing chip, improving the efficiency and real-time performance of tuning data processing. The digital signal processing unit can directly read the latest dynamic tuning parameters from the storage unit in real time, so as to realize the precise adjustment and dynamic optimization of the sound effect, and meet the high-performance tuning requirements in complex audio application scenarios.

[0055] Furthermore, the real-time debugging digital power amplifier tuning system provided by the present invention has good user-friendliness and flexible scalability. Users can directly input tuning parameters through the PC tool interface, and the system automatically completes data processing and distribution, thus avoiding users' interaction with the underlying hardware and simplifying the operation process. In addition, due to the adoption of hardware abstraction design, the firmware and the chip cooperate to execute the underlying operations, further reducing the development and use difficulty. Through the efficient cooperation of the PC tool and the firmware, the tuning parameters can be accurately parsed, quickly converted and distributed in real time, making the tuning process efficient and reliable, and comprehensively improving the real-time performance and flexibility of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 It is a schematic structural diagram of an audio processing chip in Embodiment 1 of the present invention;

[0057] Figure 2 It is a method flow chart of an audio processing chip in Embodiment 2 of the present invention;

[0058] Figure 3 It is a schematic structural diagram of a digital power amplifier tuning system in Embodiment 3 of the present invention;

[0059] Figure 4 It is a method flow chart of a digital power amplifier tuning system in Embodiment 4 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0060] The following will describe an audio processing chip, a processing method, a digital power amplifier tuning system and a tuning method of the present invention with reference to the schematic diagrams, in which the preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as a broad guidance for those skilled in the art and not as a limitation to the present invention.

[0061] The present invention will be described more specifically by way of example with reference to the accompanying drawings in the following paragraphs. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are in very simplified forms and use non-precise scales, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0062] Embodiment 1

[0063] Please refer to Figure 1 , this embodiment discloses an audio processing chip, and the chip includes:

[0064] A storage unit integrated in SRAM (Static Random Access Memory), a DMA (Direct Memory Access Control Unit), a first communication interface, and a digital signal processing unit.

[0065] The storage unit is configured to store tuning parameters; wherein, the tuning parameters include dynamic tuning parameters.

[0066] The first communication interface is configured to receive the dynamic tuning parameters and transmit the dynamic tuning parameters into the DMA control unit.

[0067] The DMA control unit is configured to receive the dynamic tuning parameters in real time and input the dynamic tuning parameters into the storage unit for storage.

[0068] The digital signal processing unit is configured to read the tuning parameters from the storage unit and perform signal processing on the tuning parameters.

[0069] It can be understood that the dynamic tuning parameters are tuning data that need to be frequently adjusted according to the real-time changing audio signals or external control instructions during the audio processing process, and generally include real-time equalizer adjustment, dynamic gain control, compression limit parameters, or sound effect detail adjustment in specific scenarios. The dynamic tuning parameters are used to achieve real-time optimization of audio processing and can be instantaneously updated as the audio content or user operations change. SRAM is a high-speed and volatile memory that can continuously store data when powered on and the data will be lost after power off. It supports frequent and fast read and write operations and is very suitable for use as a high-speed cache or temporary storage area in the system and is widely used in scenarios that require real-time response, such as storing tuning parameters and status variables in an audio processing chip.

[0070] In this embodiment, by introducing a DMA control unit in the audio processing chip, data is moved between the SRAM and the first communication interface for dynamic tuning parameters (i.e., the real-time debugging data synchronization process). The DMA control unit can automatically initiate the process of transporting and updating the tuning parameters, directly storing the data in the SRAM for the digital signal processing unit to read in real time, without the intervention of the CPU (Central Processing Unit), improving the efficiency and real-time performance of tuning data processing. The digital signal processing unit can directly read the latest dynamic tuning parameters from the storage unit in real time, thereby achieving precise adjustment and dynamic optimization of the sound effects, meeting the high-performance tuning requirements in complex audio application scenarios.

[0071] In a specific embodiment, the DMA control unit includes a DMA controller, which can automatically initiate the process of transporting and updating the tuning parameters, directly storing the data in the SRAM for the digital signal processing unit to read in real time.

[0072] In another specific embodiment, the digital signal processing unit includes a DSP (Digital Signal Processor), which is responsible for processing audio signals and implementing various sound effect processing functions, including equalization, filtering, dynamic gain control, etc. The DSP interacts with the SRAM, not only being able to read the latest dynamic tuning parameters and static tuning parameters in real time, but also writing back the state variables or intermediate data generated during the processing to the SRAM.

[0073] Furthermore, in this embodiment, the first communication interface is also configured to receive the static tuning parameters; and transmit the static tuning parameters to the storage unit for storage.

[0074] It can be understood that the static tuning parameters are tuning configuration information that is relatively fixed and has a low periodic update rate during audio processing, usually including basic tuning parameters such as filter coefficients, gain values, sound effect mode selection, equalizer parameters, and limiter settings. These parameters are mainly used to set the basic working state of the audio processing chip, making the audio effects stable and consistent. The static tuning parameters are generally set during device factory settings, user configuration, or specific scenarios, and are only adjusted when necessary, and can be flexibly configured according to actual needs to adapt to different audio application scenarios.

[0075] In this embodiment, the first communication interface is also configured to receive the static tuning parameters and transmit them to the storage unit for storage. This design enables the unified management and storage of static tuning parameters and dynamic tuning parameters, facilitating the digital signal processing unit to call them as needed during audio processing, avoiding repeated communication with the external main control, reducing the communication load and processing delay, improving the tuning flexibility and real-time performance of the system, and at the same time providing convenience for subsequent reading, verification, and update of the static parameters, enhancing the maintainability and expandability of the system.

[0076] Further, the audio processing chip disclosed in this embodiment further includes: a second communication interface.

[0077] Specifically, the second communication interface is configured to read at least one of the static tuning parameters, dynamic tuning parameters, and status variables from the SRAM storage unit.

[0078] In a specific embodiment, the status variables include, but are not limited to, the loading status of the tuning parameters, the update progress, the execution status of the current tuning task, the anomaly detection flag, and the processing status variables of the DSP. It can be understood that those skilled in the art can flexibly configure and adjust the status variables according to actual application requirements.

[0079] It can be seen that the audio processing chip disclosed in this embodiment has the parallel processing ability of reading and writing tuning parameters, and can support real-time writing of new tuning parameters into the storage unit through the communication interface or the DMA control unit while the digital signal processing unit reads the tuning parameters or status variables, realizing high-speed bidirectional transfer and real-time update of the tuning data.

[0080] In a specific embodiment, the first communication interface and the second communication interface are I2C (Inter-Integrated Circuit) interfaces for communicating with external devices, such as a PC (Personal Computer) debugging tool, a host computer, or other terminal devices. Those skilled in the art can understand that in specific implementations, the first communication interface and the second communication interface can be selected as I2C, SPI (Serial Peripheral Interface), UART (Universal Asynchronous Receiver-Transmitter), or other communication interfaces supporting data transmission according to actual application requirements to adapt to the communication methods of different external devices and the system design requirements, ensuring the efficient transmission of tuning parameters and the flexible compatibility of the system.

[0081] Further, the audio processing chip disclosed in this embodiment further includes a FIFO (First In First Out) buffer unit integrated in the SRAM.

[0082] Specifically, the FIFO buffer unit is configured to buffer data and sequentially transmit the dynamic tuning parameters to the DMA control unit.

[0083] In this embodiment, introducing the FIFO buffer unit can effectively improve the stability and orderliness of the tuning data transmission, and avoid problems such as data loss, congestion, or disorder caused by mismatched communication rates or data bursts.

[0084] Further, in this embodiment, the audio processing chip further includes: a main control unit.

[0085] The main control unit is configured to perform data exchange with the SRAM through the first communication interface or the second communication interface.

[0086] Specifically, when the main control unit receives a write instruction input from the outside, it sends a tuning instruction and a tuning signal to the first communication interface, and writes information such as tuning parameters and tuning instructions into the storage unit of the SRAM through the first communication interface.

[0087] When the main control unit receives a read instruction input from the outside, it retrieves information such as tuning parameters and status parameters from the SRAM to the second communication interface, and the main control unit can read the information through the second communication interface.

[0088] In a specific embodiment, the main control unit can be a highly integrated microcontroller (MCU) or a central processing unit (CPU), and those skilled in the art can select the main control unit according to the actual situation.

[0089] Furthermore, in this embodiment, the audio processing chip further includes a register unit and a control module.

[0090] Specifically, the register unit is configured to be connected to the main control unit through a control port, and receive and store in real time the tuning instructions and tuning parameters transmitted by the main control unit.

[0091] In this embodiment, through the control port, the main control unit can write the tuning parameters into the control port and transfer them to the register through a direct write operation, and can also receive the information transmitted by the second communication interface through a communication protocol.

[0092] In a specific embodiment, the register address range of the control port can be from 0x00 to 0x40. This means that the main control unit can perform read and write operations within this address range to configure and control the functions of the audio processing chip. Of course, those skilled in the art can select different address ranges according to the actual situation.

[0093] In summary, in this embodiment, through the cooperation of multiple components such as a digital signal processing unit, a storage unit, a FIFO buffer unit, a DMA control unit, a first communication interface, a second communication interface, a main control unit, and a control port, the storage, transmission, and processing of tuning data are realized. Through this design, the digital power amplifier can operate in an asynchronous static tuning mode, and at the same time support active tuning and synchronous operation.

[0094] It can be understood that the configurations described in the present invention are all controlled and completed by a hardware state machine integrated inside the chip. The state machine is preset by the manufacturer during the chip design stage, and the scheduling and control between each functional unit are automatically realized through hardware logic.

[0095] Embodiment 2

[0096] Please refer to Figure 2 , based on the same inventive concept, this embodiment discloses an audio processing method, and the method includes:

[0097] S1. After receiving a write instruction, the dynamic tuning parameters are transmitted in real time from the first communication interface to the FIFO buffer unit, and the FIFO buffer unit sequentially transmits the dynamic tuning parameters to the DMA control unit in sequence; the static tuning parameters are transmitted from the second communication interface to the storage unit for storage;

[0098] S2. The DMA control unit transmits the dynamic tuning parameters to the storage unit in real time for storage;

[0099] S3. The digital signal processing unit reads the dynamic tuning parameters from the storage unit in real time and performs signal processing on the dynamic tuning parameters.

[0100] In this embodiment, the system can achieve high-speed transmission and real-time storage of dynamic tuning parameters, significantly improving the efficiency and real-time performance of tuning data processing. The cooperation of the FIFO buffer unit and the DMA control unit avoids frequent intervention of the main control chip, reduces the system load, and improves the continuity and stability of data transmission. The separate storage of dynamic tuning parameters and static tuning parameters enables the digital signal processing unit (DSP) to quickly and accurately access the tuning data and perform audio processing in real time.

[0101] Further, in this embodiment, the method further includes: after receiving a read instruction, the communication interface initiates an SRAM storage unit access request to read at least one of the static tuning parameters, dynamic tuning parameters, and status variables stored in the SRAM storage unit.

[0102] Further, in this embodiment, the method further includes: when the digital signal processing unit (DSP) detects that the tuning process needs to be re-initialized or an exception occurs, it can actively initiate a reset operation. In response to this reset signal, the working configuration area and the running status area in the SRAM storage unit will be cleared and restored to the initial state, so as to ensure that the system is in a stable and controllable working state during subsequent tuning, and avoid the influence of parameter residue or status exception on the audio processing effect.

[0103] In summary, through the audio processing method disclosed in this embodiment, the system can achieve high-speed transmission, real-time storage, and efficient processing of tuning parameters, significantly improving the real-time performance and flexibility of tuning. The dynamic tuning parameters are buffered by the FIFO and automatically transmitted to the SRAM via DMA, reducing the intervention of the main controller and improving the data processing efficiency. The static and dynamic tuning parameters are stored uniformly, facilitating the DSP to quickly read and process the audio signal in real time. The method supports the main controller to access the SRAM in real time to obtain the tuning parameters and status variables, enhancing the controllability and maintainability of the system. At the same time, a working configuration area and a status area are introduced in the design to support DSP exception detection and active reset, improving the stability of the system and the reliability of sound effect processing.

[0104] Embodiment III

[0105] Please refer to Figure 3 , based on the same inventive concept, this embodiment also discloses a digital power amplifier tuning system, which includes the audio processing chip disclosed in Embodiment 1 and Embodiment 2. Specifically, the architecture of the system includes:

[0106] A user configuration unit, configured to generate tuning configuration parameters.

[0107] An upper computer tool, configured to receive the tuning configuration parameters and generate register operation instructions and DSP configuration parameters according to the tuning configuration parameters.

[0108] A firmware processing unit, configured to receive and parse the register operation instructions and DSP configuration parameters, and generate tuning instructions and tuning parameters according to the register operation instructions and DSP configuration parameters.

[0109] An audio processing chip, configured to receive the tuning instructions and the tuning parameters transmitted by the firmware processing unit, and perform real-time processing on the audio signal according to the tuning instructions and the tuning parameters.

[0110] Among them, the tuning parameters include dynamic tuning parameters and static tuning parameters, and the tuning instructions include the tuning instructions corresponding to the dynamic tuning parameters and the tuning instructions corresponding to the static tuning parameters.

[0111] In this embodiment, the real-time debugging digital power amplifier tuning system has good user-friendliness and flexible scalability. The user can directly input the tuning parameters through the PC tool interface, and the system automatically completes data processing and distribution, thus avoiding the user's interaction with the underlying hardware and simplifying the operation process. In addition, due to the use of hardware abstraction design, the firmware and the chip cooperate to execute the underlying operations, which can further reduce the development and use difficulty. Further, through the efficient cooperation between the PC tool and the firmware, the tuning parameters can be accurately parsed, quickly converted, and distributed in real time, making the tuning process efficient and reliable, and comprehensively improving the real-time performance and flexibility of the system.

[0112] In this embodiment, within the user interface (UI) configuration module, the user can input various tuning configuration parameters through a graphical UI interface. The input tuning configuration parameters can be of the floating-point number (double) type, supporting higher-precision audio adjustment, such as frequency points, gain values, filter coefficients, etc.

[0113] Furthermore, in this embodiment, the graphical UI interface can provide various human-computer interaction methods such as sliders, numeric input boxes, curve drawing areas, etc., supporting real-time adjustment and visualization operations of audio processing modules such as multi-band equalizer (EQ), low-pass filter (LPF), high-pass filter (HPF), band-pass filter (BPF), and dynamic range control (DRC). The user can intuitively adjust the center frequency, gain, filter slope, and bandwidth of each frequency band, and the system will automatically convert the floating-point number parameters input by the user into corresponding tuning configuration parameters.

[0114] Furthermore, in this embodiment, the host computer tool has functions of parameter parsing, format conversion, and data packing, and can convert the original parameter data input by the user into a standardized data format recognizable by the system, such as fixed-point numbers, integers, or DSP configuration parameters encapsulated by a specific protocol. This data can be directly sent to the firmware processing unit to achieve automatic loading and real-time adjustment of subsequent tuning parameters, improving the convenience of user operation and the accuracy of system tuning. This design effectively reduces the complexity of the interaction between the user and the underlying hardware, and enhances the flexibility and scalability of the system.

[0115] In this embodiment, the host computer tool includes: a register control unit and a DSP configuration unit.

[0116] The register control unit is a key hardware component in an embedded system, mainly responsible for converting the configuration parameters passed by the software layer (such as firmware or operating system) into register operation instructions recognizable by the hardware, so as to achieve the control and configuration of hardware functions.

[0117] In this embodiment, the register control unit is configured to generate the static tuning parameters and the tuning instructions according to the tuning configuration parameters, and map the tuning instructions and the static tuning parameters into corresponding register operation instructions and send them to the firmware processing unit.

[0118] In a digital signal processing (DSP) system, the DSP configuration unit is mainly responsible for managing and configuring the internal hardware resources of the DSP to optimize the signal processing performance.

[0119] In this embodiment, the DSP configuration unit is configured to generate DSP configuration parameters according to the default tuning parameters or / and the tuning configuration parameters, and send the DSP configuration parameters to the firmware processing unit for processing.

[0120] In another specific embodiment, the DSP configuration parameters include parameter type identification, storage location indication information, check code, timestamp, version information, etc. Preferably, the size of the DSP configuration parameters is 4 bytes (Int32) to meet the data processing and transmission efficiency requirements of the system. Of course, those skilled in the art can appropriately adjust the format and size of the DSP configuration parameters according to actual application requirements, parameter complexity, or system resource conditions.

[0121] In another specific embodiment, the host computer tool further includes a second control port.

[0122] Specifically, the second control port is configured to receive the tuning configuration parameters configured by the user and transfer the tuning configuration parameters to the register control unit and the DSP configuration unit.

[0123] It can be understood that the firmware processing unit is a key component in the embedded system, mainly responsible for executing the instructions stored in the firmware to control the hardware operations and system functions.

[0124] In this embodiment, the firmware processing unit is used to receive the register operation instructions sent by the register control unit, and complete the write operation to the internal register unit of the audio processing chip according to the instruction content, so as to realize the loading and configuration of the static tuning parameters. At the same time, the firmware processing unit can also receive the dynamic tuning parameter DSP configuration parameters sent by the DSP configuration module, and store the dynamic tuning parameters in the SRAM storage unit after parsing for the digital signal processing unit (DSP) to read and call in real time.

[0125] In a specific embodiment, the firmware processing unit includes:

[0126] Flash memory, configured to receive and update the DSP configuration parameters.

[0127] Protocol stack, configured to parse in real time and perform protocol conversion on the parsed DSP configuration parameters and the register operation instructions, and update the DSP configuration parameters in the flash memory in real time.

[0128] Configuration storage unit, configured to store the tuning instructions and the tuning parameters obtained after protocol conversion, and update the tuning instructions and the tuning parameters to the audio processing chip in real time.

[0129] In another specific embodiment, the configuration storage unit includes:

[0130] Initialize the hardware driver unit, which is configured to initialize the audio processing chip and its peripheral hardware. A current tuning parameter writing module, which is configured to write static tuning parameters and tuning instructions into registers and synchronize them to the SRAM. An active tuning synchronization unit is used to input the dynamic tuning parameters and tuning instructions stored in the flash memory into the SRAM in the audio processing chip.

[0131] Through the above digital power amplifier tuning system, the tuning instructions and tuning parameters can be configured by the user in real time through a friendly interface, and are encapsulated as DSP configuration parameters by the PC tool and transmitted to the firmware processing unit. The protocol stack in the firmware can parse and perform protocol conversion on the received DSP configuration parameters, so that the subsequent tuning instructions and parameters are accurately sent to the audio processing chip. The system design supports synchronizing the dynamic tuning parameters to the SRAM inside the chip for real-time calling and processing by the DSP, so as to achieve delay-free real-time tuning during the audio playback process, improving the system's response speed, tuning accuracy, and overall tuning flexibility and reliability.

[0132] It can be understood that the audio processing chip disclosed in this embodiment is substantially the same as the audio processing chips disclosed in Embodiment 1 and Embodiment 2. The technical features and technical effects it possesses have been described in detail in Embodiment 1 and Embodiment 2, and will not be elaborated here.

[0133] Embodiment 4

[0134] Please refer to Figure 4 , based on the same inventive concept, this embodiment also discloses a digital power amplifier tuning method for real-time debugging, implemented using the real-time debugging digital power amplifier tuning system disclosed in Embodiment 3. The method includes:

[0135] S1. The user configuration unit generates tuning configuration parameters;

[0136] S2. The host computer tool receives the tuning configuration parameters and generates register operation instructions and DSP configuration parameters according to the tuning configuration parameters;

[0137] S3. The firmware processing unit receives and parses the register operation instructions and DSP configuration parameters; and generates register operation instructions and DSP configuration parameters according to the register operation instructions and DSP configuration parameters;

[0138] S4. The audio processing chip receives the tuning instructions and the tuning parameters transmitted by the firmware processing unit, and performs real-time processing on the audio signal according to the tuning instructions and the tuning parameters;

[0139] Among them, the tuning parameters include dynamic tuning parameters and static tuning parameters, and the tuning instructions include the tuning instructions corresponding to the dynamic tuning parameters and the tuning instructions corresponding to the static tuning parameters.

[0140] It can be understood that the specific implementation method and the technical effects that can be achieved by the method have been described in Embodiment 3, and will not be elaborated here.

[0141] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims

1. An audio processing chip, characterized in that, The chip includes: a storage unit and a DMA control unit integrated in the SRAM, a first communication interface, and a digital signal processing unit; The storage unit is configured to store tuning parameters; wherein, the tuning parameters include dynamic tuning parameters; The first communication interface is configured to receive the dynamic tuning parameters and transmit the dynamic tuning parameters into the DMA control unit; The DMA control unit is configured to receive the dynamic tuning parameters in real time and input the dynamic tuning parameters into the storage unit for storage; The digital signal processing unit is configured to read the tuning parameters from the storage unit and perform signal processing on the tuning parameters.

2. The audio processing chip according to claim 1, wherein The tuning parameters further include static tuning parameters; The first communication interface is further configured to receive the static tuning parameters; and transmit the static tuning parameters into the storage unit for storage.

3. The audio processing chip according to claim 2, wherein The storage unit includes: An operation configuration area, configured to store the dynamic tuning parameters and the static tuning parameters; An operation status area, configured to store status variables during the tuning process.

4. The audio processing chip according to claim 3, characterized in that, The chip further includes: A second communication interface, configured to receive at least one of the static tuning parameters, the dynamic tuning parameters, and the status variables transmitted from the storage unit.

5. The audio processing chip according to claim 4, characterized in that, The chip further includes: A main control unit, configured to perform data exchange with the SRAM through the first communication interface or the second communication interface.

6. The audio processing chip according to claim 5, wherein The chip further includes: A register unit, configured to be connected to the main control unit through a control port, and receive and store in real time the tuning instructions and static tuning parameters transmitted by the main control unit.

7. The audio processing chip according to claim 1, wherein, The chip further includes: a FIFO buffer unit integrated in the SRAM, The FIFO buffer unit is configured to buffer data and transmit the dynamic tuning parameters to the DMA control unit in sequence.

8. An audio processing method, characterized in that Implemented by using the audio processing chip according to any one of claims 1-7, the method includes: After receiving a write instruction, the dynamic tuning parameters are transmitted from the first communication interface to the FIFO buffer unit in real time, and the FIFO buffer unit transmits the dynamic tuning parameters to the DMA control unit in sequence; the static tuning parameters are transmitted from the first communication interface to the storage unit for storage; The DMA control unit transmits the dynamic tuning parameters to the storage unit for storage in real time; The digital signal processing unit reads the dynamic tuning parameters from the storage unit in real time and performs signal processing on the dynamic tuning parameters.

9. The audio processing method according to claim 8, wherein The method further includes: After receiving a read instruction, the second communication interface initiates a storage unit access request to read at least one of the static tuning parameters, the dynamic tuning parameters, and the status variables stored in the storage unit.

10. The audio processing method according to claim 8, wherein The method further includes: When the digital signal processing unit detects that the tuning process needs to be initialized or an exception occurs, the digital signal processing unit actively initiates a reset operation to reset the information stored in the working configuration area and the operation status area of the storage unit.

11. A digital power amplifier tuning system, characterized in that, Including the audio processing chip as described in any one of claims 1-7, the system includes: A user configuration unit configured to generate tuning configuration parameters; A host computer tool configured to receive the tuning configuration parameters and generate register operation instructions and DSP configuration parameters according to the tuning configuration parameters; A firmware processing unit configured to receive and parse the register operation instructions and DSP configuration parameters, and generate tuning instructions and tuning parameters according to the register operation instructions and DSP configuration parameters; An audio processing chip configured to receive the tuning instructions and the tuning parameters transmitted by the firmware processing unit, and perform real-time processing on the audio signal according to the tuning instructions and the tuning parameters; Wherein, the tuning parameters include dynamic tuning parameters and static tuning parameters, and the tuning instructions include tuning instructions corresponding to the dynamic tuning parameters and tuning instructions corresponding to the static tuning parameters.

12. The digital power amplifier tuning system according to claim 11, wherein The host computer tool includes: A register control unit configured to generate static tuning parameters and tuning instructions according to the tuning configuration parameters, and parse and map the static tuning parameters and tuning instructions into corresponding register operation instructions, and the register operation instructions are sent by the register control unit to the firmware processing unit for processing; A DSP configuration unit configured to generate DSP configuration parameters according to default tuning parameters or / and the tuning configuration parameters, and send the DSP configuration parameters to the firmware processing unit for processing.

13. The digital power amplifier tuning system according to claim 12, characterized in that, The firmware processing unit includes: A flash memory configured to receive and update the DSP configuration parameters; A protocol stack configured to parse the DSP configuration parameters and the register operation instructions in real time, perform protocol conversion on the parsed DSP configuration parameters and the parsed register operation instructions, and update the DSP configuration parameters in the flash memory in real time; A configuration storage unit configured to store the tuning instructions and the tuning parameters obtained after protocol conversion, and update the tuning instructions and the tuning parameters to the audio processing chip in real time.

14. A digital power amplifier tuning method, characterized in that, Implemented using the digital power amplifier tuning system as described in any one of claims 11-13, the method includes: The user configuration unit generates tuning configuration parameters; The host computer tool receives the tuning configuration parameters and generates register operation instructions and DSP configuration parameters according to the tuning configuration parameters; The firmware processing unit receives and parses the register operation instructions and DSP configuration parameters, and generates the tuning instructions and the tuning parameters according to the register operation instructions and DSP configuration parameters; The audio processing chip receives the tuning instructions and the tuning parameters transmitted by the firmware processing unit, and performs real-time processing on the audio signal according to the tuning instructions and the tuning parameters; Wherein, the tuning parameters include dynamic tuning parameters and static tuning parameters, and the tuning instructions include tuning instructions corresponding to the dynamic tuning parameters and tuning instructions corresponding to the static tuning parameters.

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