Method of making air gap between bit line structure and capacitor contact

Abstract

The present disclosure provides a semiconductor device having an air gap between a bit line structure and a capacitor contact, and a method of fabricating the same. The method includes defining an active region in a substrate, forming a bit line structure and a capacitor contact disposed over and electrically connected to the active region, forming a first spacer structure sandwiched between the bit line structure and the capacitor contact, and forming a second spacer structure disposed over the first spacer structure. The first spacer structure includes an air gap structure, and the air gap structure is covered by the second spacer structure.

Description

Technical Field

[0001] This application claims priority to U.S. patent application No. 18 / 518,545 (i.e., the priority date is "November 23, 2023"), the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor element and a method for manufacturing the same, and more particularly to a method for manufacturing a semiconductor element having an air gap between a bit line structure and a capacitor contact. Background Art

[0003] Semiconductor components are essential to many modern applications. As electronic technology advances, semiconductor components are becoming smaller in size while providing more functionality and including a larger number of integrated circuits. Due to the miniaturization of semiconductor components, various types and sizes of semiconductor components providing different functions are integrated and packaged into a single module. In addition, many manufacturing operations are performed to integrate different types of semiconductor components.

[0004] However, the manufacturing and integration of semiconductor devices involve many complex steps and operations. The integration in semiconductor devices is becoming more and more complex. The increase in the complexity of semiconductor devices in manufacturing and integration may cause defects. Therefore, it is necessary to continuously improve the manufacturing process of semiconductor devices to solve the above defects.

[0005] The above “prior art” description is only to provide background technology, and does not admit that the above “prior art” description reveals the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0006] In one embodiment of the present disclosure, a method for preparing a semiconductor element is provided. The method includes: defining multiple active regions by forming an element isolation layer in a substrate; forming a semiconductor layer and a metal layer on the active regions; forming a first mask on the metal layer intersecting the active regions; etching the semiconductor layer and the metal layer using the first mask as an etching mask to form multiple bit line structures; forming multiple lower spacer structures having an energy removable material; forming a second mask on the metal layer; forming multiple first spacer structures by forming multiple higher spacer structures, wherein each higher spacer structure is disposed on a corresponding lower spacer structure; forming a dielectric layer surrounding the higher spacer structures and covering the metal layer; forming multiple capacitor contacts by forming a barrier layer and a conductive layer within the capacitor contacts; and performing a heat treatment process to transform the first spacer structures into multiple air gap structures.

[0007] In one embodiment, forming the lower spacer structures with an energy removable material includes: depositing the energy removable material on the metal layer; and planarizing the energy removable material until the metal layer is exposed.

[0008] In one embodiment, forming the taller spacer structures includes: conformally depositing the energy removable material overlying the first mask and the metal layer; and etching the energy removable material by an anisotropic etching process.

[0009] In one embodiment, forming the dielectric layer surrounding the upper spacer structures and covering the metal layer includes: depositing a dielectric material overlying and covering the upper spacer structures and the metal layer; and planarizing the dielectric material until the first mask is exposed.

[0010] In one embodiment, the barrier layer is fabricated using an anisotropic deposition process.

[0011] In one embodiment, the fabrication technique of the conductive layer includes a deposition process.

[0012] In one embodiment, the method further includes forming the barrier layer with a first thickness on the sidewall of the corresponding conductive layer and with a second thickness below the bottom surface of the corresponding conductive layer.

[0013] In one embodiment, performing a thermal treatment process to transform the first spacer structures into a plurality of air gap structures further includes: forming an air gap enclosed by a liner in each of the air gap structures.

[0014] In another embodiment of the present disclosure, a method for preparing a semiconductor device includes: forming a first source / drain region and a second source / drain region in a semiconductor substrate; forming a bit line structure on the first source / drain region and electrically connected to the first source / drain region; forming a capacitor contact on the second source / drain region and electrically connected to the second source / drain region; forming a first spacer structure sandwiched between the bit line structure and the capacitor contact, wherein the first spacer structure includes an air gap; and forming a second spacer structure on the first spacer structure, wherein the air gap is covered by the second spacer structure.

[0015] In one embodiment, forming the bit line structure includes: forming a semiconductor layer on the semiconductor substrate; forming a metal layer on the semiconductor layer; and performing an etching process on the semiconductor layer and the metal layer.

[0016] In one embodiment, a patterned mask is further formed on the bit line structure.

[0017] In one embodiment, a dielectric layer is further formed on the second spacer structure and the patterned mask.

[0018] In one embodiment, a conductive pad is further formed, which covers the second spacer structure and extends to cover a portion of the patterned mask.

[0019] In one embodiment, the conductive pad is disposed on the capacitor contact and is electrically connected to the capacitor contact.

[0020] In one embodiment, a thermal treatment process is further performed to transform the first spacer structure into an air gap structure, wherein the air gap structure includes an air gap enclosed by a liner layer.

[0021] In one embodiment, the air gap structure and the air gap of the first spacer structure extend into the semiconductor substrate.

[0022] In one embodiment, the capacitor contact includes a barrier layer and a conductive layer lining the barrier layer.

[0023] In one embodiment, the barrier layer has a first thickness on the sidewall of the corresponding conductive layer, and has a second thickness below the bottom surface of the corresponding conductive layer.

[0024] In yet another embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device includes: a first source / drain region and a second source / drain region, disposed in a semiconductor substrate; a bit line structure, disposed on the first source / drain region and electrically connected to the first source / drain region; a capacitor contact, disposed on the second source / drain region and electrically connected to the second source / drain region; a first spacer structure, sandwiched between the bit line structure and the capacitor contact, wherein the first spacer structure includes an air gap; and a second spacer structure, disposed on the first spacer structure, wherein the air gap is covered by the second spacer structure.

[0025] In one embodiment, the first spacer structure includes an air gap structure in contact with the bit line structure.

[0026] In one embodiment, the air gap structure includes an air gap enclosed by a liner.

[0027] In one embodiment, the air gap of the first spacer structure extends into the semiconductor substrate.

[0028] In one embodiment, the method further includes a patterned mask disposed on the bit line structure.

[0029] In one embodiment, the device further includes a conductive pad disposed on the capacitor contact and electrically connected to the capacitor contact, wherein the conductive pad extends over the second spacer structure and the patterned mask.

[0030] In one embodiment, the bit line structure includes a semiconductor layer located on the semiconductor substrate and a metal layer located on the semiconductor layer.

[0031] In one embodiment, the barrier layer has a first thickness on the sidewall of the corresponding conductive layer, and has a second thickness below the bottom surface of the corresponding conductive layer.

[0032] The above has been a fairly broad overview of the technical features and advantages of the present disclosure, so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that form the subject of the claims of the present disclosure will be described below. It should be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those with ordinary knowledge in the technical field to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The various aspects of the present disclosure can be read in conjunction with the following drawings and detailed descriptions for easy understanding. It is emphasized that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily enlarged or reduced for the sake of clarity of discussion.

[0034] Figure 1 A flow chart of a method for manufacturing a semiconductor device is shown according to some embodiments.

[0035] Figure 2 A top view illustrating an intermediate stage of forming an isolation structure in a semiconductor substrate during fabrication of the semiconductor device according to some embodiments.

[0036] Figure 3 According to some embodiments, displaying Figure 2 A cross-sectional view taken along the line AA' at an intermediate stage during the preparation of the semiconductor device.

[0037] Figure 4 A top view showing an intermediate stage of etching the semiconductor substrate to form a plurality of openings during fabrication of the semiconductor device according to some embodiments.

[0038] Figure 5 According to some embodiments, display along Figure 4A cross-sectional view taken along the line AA' at an intermediate stage during the preparation of the semiconductor device.

[0039] Figure 6 A top view is shown of an intermediate stage of sequentially forming a semiconductor layer, a metal layer, and a patterned mask on the semiconductor substrate during fabrication of the semiconductor device according to some embodiments.

[0040] Figure 7 According to some embodiments, display along Figure 6 A cross-sectional view taken along the line AA' at an intermediate stage during the preparation of the semiconductor device.

[0041] Figure 8 A top view showing an intermediate stage of etching the semiconductor layer and the metal layer to form a plurality of bit line structures during fabrication of the semiconductor device according to some embodiments.

[0042] Fig. 9 According to some embodiments, display along Figure 8 A cross-sectional view taken along the line AA' at an intermediate stage during the preparation of the semiconductor device.

[0043] Fig.10 A top view showing an intermediate stage of forming a plurality of first spacer structures on sidewalls of the bit line structures during fabrication of the semiconductor device according to some embodiments.

[0044] Fig.11 According to some embodiments, display along Fig.10 A cross-sectional view taken along the line AA' at an intermediate stage during the preparation of the semiconductor device.

[0045] Fig.12 A top view illustrating an intermediate stage of forming a plurality of capacitor contacts adjacent to the first spacer structures during fabrication of the semiconductor device according to some embodiments.

[0046] Fig.13 According to some embodiments, display along Fig.12 A cross-sectional view taken along the line AA' at an intermediate stage during the preparation of the semiconductor device.

[0047] Fig.14 A top view illustrating an intermediate stage of forming a plurality of second spacer structures on the first spacer structures during fabrication of the semiconductor device according to some embodiments.

[0048] Fig.15 According to some embodiments, display along Fig.14 A cross-sectional view taken along the line AA' at an intermediate stage during the preparation of the semiconductor device.

[0049] Fig.16 A top view illustrating an intermediate stage of forming a plurality of conductive pads above the capacitor contacts during fabrication of the semiconductor device according to some embodiments.

[0050] Fig.17 According to some embodiments, display along Fig.16 A cross-sectional view taken along the line AA' at an intermediate stage during the preparation of the semiconductor device.

[0051] Fig.18 A top view showing an intermediate stage of transforming a portion of the first spacer structures into a plurality of air gaps during fabrication of the semiconductor device according to some embodiments.

[0052] Fig.19 A cross-sectional view showing an intermediate stage during the fabrication of the semiconductor device according to some embodiments.

[0053] Fig. 20 A cross-sectional view showing an intermediate stage during the fabrication of the semiconductor device according to some embodiments.

[0054] Fig.21 A cross-sectional view showing an intermediate stage during the fabrication of the semiconductor device according to some embodiments.

[0055] Fig.22A , Fig. 22B , Fig. 22C , Fig.22D , Fig.22E , Fig.22F , Figure 22G A cross-sectional view showing an intermediate stage during the fabrication of the semiconductor device according to some embodiments.

[0056] The reference numerals are described as follows:

[0057] 10: Methods

[0058] 100a: Semiconductor components

[0059] 100b: Semiconductor components

[0060] 100c: Semiconductor components

[0061] 100d: semiconductor components

[0062] 101: Substrate

[0063] 103: Isolation Structure

[0064] 105: Doping area

[0065] 105a: Source / drain region

[0066] 105b: Source / drain region

[0067] 107: Character Line Structure

[0068] 109: Buffer layer

[0069] 112: Opening

[0070] 115: Semiconductor layer

[0071] 115': Semiconductor pattern

[0072] 115c: Bit line contact

[0073] 117: Metal layer

[0074] 117': Metal pattern

[0075] 119: Bit Line Structure

[0076] 121: Patterned Mask

[0077] 121-1: Patterned mask

[0078] 121-3: Patterned Mask

[0079] 124: Gap

[0080] 131: Internal spacer

[0081] 133: Intermediate spacer

[0082] 133B: Lower part

[0083] 133U: Higher part

[0084] 135: External spacer

[0085] 137: First spacer structure

[0086] 137': First spacer structure

[0087] 137”: First spacer structure

[0088] 139: Dielectric layer

[0089] 141: Dielectric layer

[0090] 143: Capacitor contact

[0091] 149: Second spacer structure

[0092] 151: Dielectric layer

[0093] 153: Conductive pad

[0094] 156: Air Gap

[0095] 173: Barrier layer

[0096] 175: Conductive layer

[0097] 175B: Bottom surface

[0098] 175S: Sidewall

[0099] 179: Composite Contact

[0100] 211A: Block

[0101] 211B: Lining

[0102] 211C: Air Gap

[0103] 213: Air Gap Structure

[0104] OP: Opening

[0105] OP1: Opening

[0106] S1: Sidewall

[0107] S2: Sidewall

[0108] S3: Sidewall

[0109] S11: Steps

[0110] S13: Steps

[0111] S15: Steps

[0112] S17: Steps

[0113] S19: Steps

[0114] S21: Steps

[0115] S23: Steps

[0116] T1: Top surface

[0117] T2: Top surface

[0118] T3: Top surface

[0119] T11: First thickness

[0120] T21: Second thickness DETAILED DESCRIPTION

[0121] The following disclosure provides many different embodiments or examples to implement different components of the embodiments of the present disclosure. The following describes specific examples of components and their arrangements to simplify the embodiments of the present disclosure. Of course, these are only examples and should not be used to limit the scope of the embodiments of the present disclosure. For example, when the description mentions that a first component is formed "on" or "on" a second component, it may include an embodiment in which the first component is in direct contact with the second component, and it may also include an embodiment in which there are other components formed between the two without direct contact. In addition, the present disclosure may repeat reference symbols and / or marks in different embodiments. These repetitions are for the purpose of simplicity and clarity, and are not used to limit the relationship between the different embodiments and / or structures discussed.

[0122] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like are used herein to facilitate describing the relationship between one element or component and another element or component as shown in the drawings. These spatially relative terms are intended to encompass different orientations of the element in use or operation other than the orientation depicted in the drawings. The device may be oriented differently (rotated 90 degrees or at other orientations) and the spatially relative adjectives used therein may be interpreted similarly.

[0123] Figure 1 According to some embodiments, a semiconductor device (such as Fig.18 The semiconductor device 100a shown in FIG. Fig.19 The semiconductor device 100b shown in FIG. Fig. 20 1 is a flow chart of a method 10 for preparing a semiconductor element 100 c). According to some embodiments, the method 10 includes steps S11, S13, S15, S17, S19, S21, and S23.

[0124] First, steps S11 to S23 are briefly introduced, and then explained in detail with reference to the following figures. Figure 1 As shown, the method 10 begins with step S11, forming a plurality of source / drain regions in a semiconductor substrate. In some embodiments, an isolation structure is formed in the semiconductor substrate to define a plurality of active regions, and a plurality of source / drain regions are formed in the active regions. In step S13, a plurality of bit line structures are formed on the semiconductor substrate. In some embodiments, material layers of the bit line structures are sequentially formed on the semiconductor substrate, and the material layers are etched using an overlying patterned mask as a mask.

[0125] In step S15, a plurality of first spacer structures are formed on the sidewalls of the bit line structures. In some embodiments, each of the first spacer structures is a three-layer structure, including an inner spacer contacting the bit line structure, an intermediate spacer, and an outer spacer separated from the inner spacer by the intermediate spacer. In some embodiments, each of the first spacer structures is a single-layer structure (e.g., an intermediate spacer) in contact with the bit line structure and the patterned mask. In addition, in some embodiments, the intermediate spacer of the first spacer structure includes an energy removable material. In step S17, a plurality of capacitor contacts (also referred to as CC contacts) are formed on the semiconductor substrate and adjacent to the first spacer structures. In some embodiments, each capacitor contact is a single contact. In some embodiments, each capacitor contact is a composite contact. In some embodiments, after forming the first spacer structure, a first dielectric layer is formed on the semiconductor substrate, and a capacitor contact is formed through the first dielectric layer to be physically and electrically connected to the source / drain region below. In addition, in some embodiments, the first spacer structure is partially etched during the formation of the capacitor contact.

[0126] In step S19, a plurality of second spacer structures are formed on the first spacer structures. In some embodiments, the second spacer structures extend to cover a portion of the capacitor contacts.

[0127] In step S21, a conductive pad is formed on the capacitor contact and covers the second spacer structure. In some embodiments, a second dielectric layer is formed on the capacitor contact and the second spacer structure, and a plurality of conductive pads are formed through the second dielectric layer to be physically and electrically connected to the capacitor contact. In some embodiments, the second spacer structure is covered by the conductive pad. In step S23, a thermal treatment process is performed to convert a portion of the first spacer structures into a plurality of air gaps. In some embodiments, the middle spacer of the first spacer structure includes an energy removable material, which can be converted into an air gap by a thermal treatment process. In some embodiments, after the thermal treatment process, the air gap is sandwiched between the inner spacer and the outer spacer of the first spacer structure. In some embodiments, after the thermal treatment process, the air gap is closed by a liner.

[0128] It should be noted that if the first spacer structure of step S15 is a single layer (eg, an intermediate spacer), then Fig.19 If the capacitor contact in step S17 is a composite contact, then Fig. 20In other words, the semiconductor element 100a includes a first spacer structure of a three-layer structure and a capacitor contact of a single contact, the semiconductor element 100b includes a first spacer structure of a single-layer structure and a capacitor contact of a single contact, and the semiconductor element 100c includes a first spacer structure of a three-layer structure and a capacitor contact of a composite contact. Any combination of the first spacer structure and its capacitor contact is possible. In some other embodiments, the semiconductor element includes a first spacer structure of a single-layer structure and a capacitor contact of a composite contact, such as Fig.21 In some embodiments, the semiconductor devices 100a, 100b, 100c, and 100d are part of a dynamic random access memory (DRAM). Figure 1 Steps S11 to S23 are described in detail.

[0129] According to some embodiments, Figure 2 , Figure 4 , Figure 6 , Figure 8 , Fig.10 , Fig.12 , Fig.14 ,and Fig.16 A top view showing an intermediate stage of forming a semiconductor device 100a is shown. Figure 3 , Figure 5 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.17 ,and Fig.18 A cross-sectional view showing an intermediate stage of forming a semiconductor element 100a. It should be noted that Figure 3 , Figure 5 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 ,and Fig.17 Along the Figure 2 , Figure 4 , Figure 6 , Figure 8 , Fig.10 , Fig.12 , Fig.14 ,and Fig.16 A cross-sectional view drawn along the section line A-A'.

[0130] Reference Figure 2 and Figure 3, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Optionally or additionally, the semiconductor substrate 101 may include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0131] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator substrate, which may include a substrate, a buried oxide layer on the substrate, and a semiconductor layer on the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate may be prepared using separation by implantationoxygen (SIMOX), wafer bonding, and / or other applicable methods.

[0132] Still refer to Figure 2 and Figure 3 According to some embodiments, an isolation structure 103 is formed in the semiconductor substrate 101 to define a plurality of active regions, and the isolation structure 103 is a shallow trench isolation (STI) structure. The isolation structure 103 may include silicon oxide, silicon nitride, silicon oxynitride, or another applicable dielectric material, and the formation of the isolation structure 103 may include forming a patterned mask (not shown) on the semiconductor substrate 101, etching the semiconductor substrate 101 using the patterned mask as a mask to form an opening (not shown), depositing a dielectric material in the opening and on the semiconductor substrate 101, and planarizing the dielectric material until the semiconductor substrate 101 is exposed.

[0133] In addition, a doped region 105 is formed in the active region defined by the isolation structure 103. In some embodiments, the fabrication techniques of the doped region 105 include one or more ion implantation processes, and depending on the conductivity type of the semiconductor device 100a, a P-type dopant such as boron (B), gallium (Ga), or indium (In), or an N-type dopant such as phosphorus (P) or arsenic (As) may be implanted into the active region to form the doped region 105. In addition, the doped region 105 will become the source / drain region of the semiconductor device 100a in subsequent processes.

[0134] According to some embodiments, after forming the doped region 105, a word line structure 107 is formed through the doped region 105 to form source / drain regions 105a and 105b, such as Figure 4 and Figure 5 The corresponding steps are Figure 1 This is shown as step S11 in the method 10. In some embodiments, the word line structures 107 are embedded in the semiconductor substrate 101 and are arranged in parallel with each other.

[0135] Each word line structure 107 may include a gate dielectric layer (not shown) and a gate electrode (not shown) on the gate dielectric layer. The gate dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, or a combination thereof, and the gate electrode may include a conductive material such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or a multilayer structure including any combination of the above materials. The formation of the word line structure 107 may include etching the semiconductor substrate 101 to form a trench, and performing one or more deposition and etching processes to form the word line structure 107 in the trench.

[0136] In addition, in this embodiment, each active region is penetrated by two parallel word line structures 107, such as Figure 4 In some embodiments, the source / drain regions 105b are located at opposite ends of the active region, and the source / drain region 105a is located at a central portion of the active region. Figure 4 and Figure 5 According to some embodiments, after forming the source / drain regions 105a, 105b and the word line structure 107, a buffer layer 109 is formed on the semiconductor substrate 101, and a plurality of openings 112 (i.e., bit line contact openings) are formed in the semiconductor substrate 101 and on the source / drain region 105a.

[0137] The buffer layer 109 may include one or more insulating layers. For example, the buffer layer 109 may include at least one or two of a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The formation of the opening 112 may include forming a patterned mask (not shown) on the buffer layer 109 and etching the buffer layer 109 and the semiconductor substrate 101 using the patterned mask as a mask. More specifically, the upper portion of the source / drain region 105a is etched to form the opening 112.

[0138] Next, according to some embodiments, Figure 6 and Figure 7 As shown, a semiconductor layer 115 is formed on the buffer layer 109, a metal layer 117 is formed on the semiconductor layer 115, and a patterned mask 121 is formed on the metal layer 117. In some embodiments, the semiconductor layer 115 fills the opening 112. In some embodiments, the semiconductor layer 115 includes doped polysilicon. In some other embodiments, the semiconductor layer 115 includes a metal, a metal silicide, a metal compound, or a combination thereof. The manufacturing technology of the semiconductor layer 115 may include a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. In some embodiments, the metal layer 117 includes one or more metals, such as tungsten (W). In addition, the manufacturing technology of the metal layer 117 may include a CVD process, a PVD process, an ALD process, a metal organic CVD (MOCVD) process, a sputtering process, an electroplating process, or a combination thereof.

[0139] Then, according to some embodiments, Figure 8 and Fig. 9 As shown, the patterned mask 121 is used as a mask to etch the metal layer 117 and the semiconductor layer 115 to form a bit line structure 119 on the semiconductor substrate 101. The corresponding steps are as follows: Figure 1 This is shown as step S13 in the method 10. Each bit line structure 119 includes a semiconductor pattern 115' and a metal pattern 117'. The etching process may include a dry etching process, a wet etching process, or a combination thereof.

[0140] In some embodiments, the semiconductor layer 115 is filled in the opening 112 (see Figure 4 and Figure 5) is etched to form a plurality of gaps 124 along the bit line structure 119, and the portion of the semiconductor pattern 115' left in the opening 112 (below the top surface T1 of the buffer layer 109) is referred to as a bit line contact 115c. A dotted line is used to indicate the boundary between the bit line contact 115c and the bit line structure 119 to clarify the present disclosure. No obvious interface exists between the bit line contact 115c and the bit line structure 119.

[0141] In some embodiments, the gap 124 partially exposes the source / drain region 105a, and the gap 124 is located within the opening 112. In addition, after the etching process, the sidewall S1 of the semiconductor pattern 115', the sidewall S2 of the metal pattern 117', and the sidewall S3 of the patterned mask 121 are substantially aligned. In the context of the present disclosure, the term "substantially" means preferably at least 90%, more preferably 95%, further preferably 98%, and most preferably 99%.

[0142] Then, according to some embodiments, Fig.10 and Fig.11 As shown, a plurality of first spacer structures 137 are formed on the sidewalls of the bit line structure 119 (including the sidewalls S1 of the semiconductor pattern 115' and the sidewalls S2 of the metal pattern 117') and the sidewalls S3 of the patterned mask 121. The corresponding steps are as follows: Figure 1 In the method 10 shown in FIG. 1 , the first spacer structure 137 fills the gap 124 (see FIG. 1 ). Figure 8 and Fig. 9 ).

[0143] In some embodiments, each first spacer structure 137 includes an inner spacer 131 in contact with the bit line structure 119 and the patterned mask 121, an intermediate spacer 133, and an outer spacer 135 separated from the inner spacer 131 by the intermediate spacer 133. In some embodiments, the inner spacer 131 and the outer spacer 135 include high-density carbon, silicon carbide (SiC), silicon carbonitride (SiCN), doped oxide, or another applicable dielectric material, but any other material may be used instead. In some embodiments, the intermediate spacer 133 includes an energy-removable material.

[0144] In some embodiments, the energy-removable material of the intermediate spacer 133 includes a substrate and a decomposable porogen material that is substantially removed upon exposure to an energy source (e.g., heat). In some embodiments, the substrate may include hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous silicon dioxide (SiO 2 ), and the decomposable porogen material may include a consistent porogen organic compound, which can provide porosity to the space initially occupied by the intermediate spacer 133 in subsequent processing.

[0145] In some embodiments, the formation of the inner spacer 131 includes conformally depositing an inner spacer material (not shown) on the inner spacer. Figure 8 and Fig. 9 The deposition process may include a CVD process, a PVD process, an ALD process, a spin coating process, or another applicable process. The inner spacer material may then be etched by an anisotropic etching process that vertically removes an equal amount of spacer material at all locations, leaving the inner spacer 131 on the sidewalls S1, S2 of the bit line structure 119 and on the sidewall S3 of the patterned mask 121. In some embodiments, the etching process is a dry etching process. Some processes for forming the intermediate spacers 133 and the outer spacers 135 are similar or identical to the processes for forming the inner spacers 131, and their details are not repeated here.

[0146] According to some embodiments, Fig.10 and Fig.11As shown, after forming the first spacer structure 137, a first dielectric layer 141 is formed to fill the space between the first spacer structure 137 and above the source / drain region 105b. The first dielectric layer 141 may include a low-k dielectric material. In some embodiments, the low-k dielectric material has a dielectric constant (k value) of less than about 4. Examples of low-k dielectric materials include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, polyparaxylene, bis-benzocyclobutenes (BCB), or polyimide. The manufacturing technology of the dielectric layer 141 may include a deposition process. After depositing the dielectric layer 141, a planarization process may be performed until the patterned mask 121 is exposed. The planarization process may be a chemical mechanical polishing (CMP) process.

[0147] Next, according to some embodiments, Fig.12 and Fig.13 As shown, a plurality of openings (not shown) are formed through the first dielectric layer 141 and the buffer layer 109, thereby exposing the source / drain regions 105b, and forming a plurality of capacitor contacts 143 in the openings. Figure 1 This is shown as step S17 in the method 10. In some embodiments, the fabrication technique for exposing the opening of the source / drain region 105b includes a dry etching process. In some embodiments, the fabrication technique for the capacitor contact 143 includes a deposition process and a subsequent etch-back process.

[0148] Specifically, the formation of the capacitor contact 143 includes depositing a conductive material (not shown) in the opening exposing the source / drain region 105b, and performing an etch-back process on the conductive material to form the capacitor contact 143. In some embodiments, during the etch-back process for forming the capacitor contact 143, the first spacer structure 137 is partially etched so that the top surface T2 of the etched first spacer structure 137' is substantially coplanar with the top surface T3 of the capacitor contact 143. In addition, in some embodiments, the etched first spacer structure 137' is in direct contact with the capacitor contact 143. The capacitor contact 143 may include copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), a combination of the foregoing, or another applicable conductive material.

[0149] Then, according to some embodiments, Fig.14 and Fig.15 As shown, a plurality of second spacer structures 149 are formed on the etched first spacer structures 137'. The corresponding steps are as follows: Figure 1 In the method 10 shown in FIG. 1 , the second spacer structure 149 is formed on the sidewall S3 of the patterned mask 121 (see FIG. 1 ). Fig.13 ). Specifically, according to some embodiments, the second spacer structure 149 is in direct contact with the top surface T2 of the first spacer structure 137', the top surface T3 of the capacitor contact 143, and the sidewall S3 of the patterned mask 121. Some materials and processes used to form the second spacer structure 149 are similar or identical to the materials and processes used to form the inner spacer 131 of the first spacer structure 137, and the details thereof will not be repeated here.

[0150] Then, according to some embodiments, Fig.16 and Fig.17 As shown, a second dielectric layer 151 is formed on Fig.14 and Fig.15 After forming the second dielectric layer 151, a plurality of openings (not shown) are formed through the second dielectric layer 151 to expose the capacitor contacts 143, and a plurality of conductive pads 153 are formed in the openings. Figure 1 This is shown as step S21 in the method 10 shown in FIG. 1 . In some embodiments, the conductive pad 153 covers the second spacer structure 149 . In some embodiments, the second spacer structure 149 extends to cover a portion of the patterned mask 121 .

[0151] Some of the materials and processes used to form the second dielectric layer 151 are similar to those used to form the first dielectric layer 141 (see Fig.10 and Fig.11 ) are similar or identical in material and process, and the details thereof will not be repeated here. In some embodiments, the manufacturing technique of the opening exposing the capacitor contact 143 includes a dry etching process, and the manufacturing technique of the conductive pad 153 includes a deposition process and a subsequent planarization process. The conductive pad 153 may include copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag), a combination of the foregoing, or another applicable conductive material.

[0152] According to some embodiments, after forming the conductive pad 153, a thermal treatment process is performed to transform the intermediate spacers 133 of the first spacer structure 137' into a plurality of air gaps 156, such as Fig.18 shown. Fig.18 is along with Fig.17 The corresponding steps are in Figure 1This is shown as step S23 in the method 10 . After the heat treatment process, a processed first spacer structure 137 ″ is obtained, which has an air gap 156 sandwiched between the inner spacer 131 and the outer spacer 135 .

[0153] In some other embodiments, the thermal treatment process may be replaced by a phototreatment process, an electron beam treatment process, a combination thereof, or another applicable energy treatment process. In some embodiments, the second spacer structure 149 seals the top of the air gap 156. After the air gap 156 is formed in the first spacer structure 137" between the bit line structure 119 and the capacitor contact 143, the semiconductor device 100a is obtained. In some embodiments, the semiconductor device 100a is part of a dynamic random access memory (DRAM).

[0154] Fig.19 A cross-sectional view showing an intermediate stage during the fabrication of semiconductor device 100b according to some embodiments. Some materials and processes used to form semiconductor device 100b are similar or identical to those used to form semiconductor device 100a, and the details thereof will not be repeated herein.

[0155] like Fig.19 As shown, in step S15, each of the first spacer structures 137 formed on the sidewalls of the bit line structure 119 has a single-layer structure (i.e., the middle spacer 133) including a material composed of an energy-removable material. In some embodiments, the single-layer structure (i.e., the first spacer structure 137) fills the gap 124 (see Figure 8 and Fig. 9 ). In step S17, in some embodiments, the etched first spacer structure 137' (also referred to as the energy removable block 211A (not shown)) has a trapezoidal shape. And, in step S23, after performing a heat treatment process, the energy removable block 211A (i.e., the etched first spacer structure 137') is transformed into an air gap structure 213 (i.e., the treated first spacer structure 137"), which includes an air gap 211C enclosed by the liner 211B. In some embodiments, the semiconductor device 100b is part of a DRAM.

[0156] Fig. 20 A cross-sectional view showing an intermediate stage during the fabrication of semiconductor device 100c according to some embodiments. Some materials and processes used to form semiconductor device 100c are similar or identical to those used to form semiconductor device 100a, and the details thereof will not be repeated herein.

[0157] like Fig. 20As shown, in step S17, each capacitor contact 143 formed in the opening (not shown) has a composite contact 179. Fig.18 Compared with the capacitor contact 143 in Fig. 20 The composite contact 179 in the embodiment includes a barrier layer 173 and a conductive layer 175 disposed on and surrounded by the barrier layer 173. In some embodiments, the barrier layer 173 includes titanium (Ti), titanium nitride (TiN), or a combination thereof, and the conductive layer 175 includes tungsten (W). In some embodiments, the conductive layer 175 is separated from the processed first spacer structure 137" (or the etched first spacer structure 137'), the source / drain region 105b, and the semiconductor substrate 101 by the barrier layer 173.

[0158] It should be noted that each barrier layer 173 has a first thickness T11 on the sidewall 175S of the corresponding conductive layer 175, and each barrier layer 173 has a second thickness T21 below the bottom surface 175B of the corresponding conductive layer 175. In some embodiments, the manufacturing technology of the barrier layer 173 includes an anisotropic deposition process, so that the first thickness is less than the second thickness. In some embodiments, the anisotropic deposition process for forming the barrier layer 173 includes a physical vapor deposition (PVD) process. In some embodiments, the semiconductor device 100c is part of a DRAM.

[0159] Fig.21 , Fig.22A , Fig. 22B , Fig. 22C , Fig.22D , Fig.22E , Fig.22F , Figure 22G A cross-sectional view is shown at an intermediate stage during the fabrication of a semiconductor device 100 d according to some embodiments. Fig.21 An intermediate stage is shown after forming the capacitor contact 143 and the air gap structure 213 (ie, the first spacer structure 137 ). Fig.22A , Fig. 22B , Fig. 22C , Fig.22D , Fig.22E , Fig.22F , Figure 22G A cross-sectional view showing an intermediate stage of forming a capacitor contact 143 during fabrication of a semiconductor device 100d according to some embodiments. Fig.21 As shown, in some other embodiments, each first spacer structure 137 of the semiconductor device 100d is a single-layer structure, and each capacitor contact 143 is a composite structure. Some materials and processes used to form the semiconductor device 100d are similar or identical to those used to form the semiconductor device 100a, and their details are not repeated here.

[0160] In step S13, according to some embodiments, Fig.22A and Fig. 22B As shown, the lower portion 133B of the first spacer structure 137 is formed along the bit line structure 119. The formation of the lower portion 133B of the first spacer structure 137 may include forming a patterned mask 121-1 on the metal layer 117, etching the metal layer 117 and the semiconductor layer 115 by using the patterned mask 121-1 as a mask, thereby forming an opening OP after removing the patterned mask 121-1, as shown in FIG. Fig.22A Then, according to some embodiments, an energy removable material is deposited in the opening OP and on the metal layer 117, and the energy removable material is planarized until the metal layer 117 is exposed, as shown in FIG. Fig. 22B shown.

[0161] In step S15, if Fig. 22C As shown, a patterned mask 121 and a higher portion 133U of the first spacer structure 137 are formed. The patterned mask 121 and the higher portion 133U of the first spacer structure 137 are formed similarly to the patterned mask 121 and the intermediate spacer 133 of the semiconductor device 100a, and the details thereof are not repeated here.

[0162] Then, according to some embodiments, Fig.22D As shown, a dielectric layer 139 is formed to fill the space between the higher portions 133U of the first spacer structure 137, and the dielectric layer 139 is formed on the metal layer 117. The dielectric layer 139 may include a low-k dielectric material. In some embodiments, the low-k dielectric material has a dielectric constant (k value) of less than about 4. Examples of low-k dielectric materials include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), fluorosilicone glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, polyparaxylene, biphenylcyclobutene (BCB), or polyimide. The manufacturing technology of the dielectric layer 139 may include a deposition process. After the dielectric layer 139 is deposited, a planarization process may be performed until the patterned mask 121 is exposed. The planarization process may be a chemical mechanical polishing (CMP) process.

[0163] Next, an opening OP1 is formed through the dielectric layer 139, the metal layer 117, the semiconductor layer 115, and the buffer layer 109, thereby exposing the source / drain region 105b. The formation of the opening includes forming a patterned mask 121-3, etching the dielectric layer 139, the metal layer 117, the semiconductor layer 115, and the buffer layer 109. In some embodiments, the manufacturing technology of the opening OP1 that exposes the source / drain region 105b includes a dry etching process. Then, according to some embodiments, after forming the opening OP1 and removing the patterned mask 121-3, a first spacer structure 137 is formed, such as Fig.22E shown.

[0164] In step S17, according to some embodiments, Fig.22F As shown, a barrier layer 173 is formed to cover the sidewalls and bottom surface of the opening OP1. In some embodiments, the barrier layer 173 includes titanium (Ti), titanium nitride (TiN), or a combination thereof. In some embodiments, an anisotropic deposition process is performed to form the barrier layer 173.

[0165] Then, according to some embodiments, Figure 22G As shown, a conductive layer 175 is formed on the barrier layer 173 and fills the opening OP1. In some embodiments, the conductive layer 175 includes tungsten (W). In some embodiments, the manufacturing technology of the conductive layer 175 includes a deposition process. After the conductive layer 175 is formed, a subsequent back etching process is performed to obtain a capacitor contact 143 with a composite contact 179.

[0166] In step S23, a heat treatment process is performed to transform a portion of the first spacer structure 137 into an air gap structure 213, which includes an air gap 211C (eg, Fig.21 After the air gap structure 213 is formed, the semiconductor device 100d is obtained. In some embodiments, the semiconductor device 100d is a part of a DRAM.

[0167] The present disclosure provides an embodiment of a semiconductor element and a method for preparing the same. The method includes forming a first spacer structure on the sidewall of a bit line structure, and forming a capacitor contact adjacent to the first spacer structure. In some embodiments, the method also includes forming a second spacer structure on the first spacer structure, and performing a heat treatment process to convert a portion of the first spacer structure (e.g., the middle spacer 133) into an air gap. Therefore, the parasitic capacitance between the bit line structure and the capacitor contact can be reduced, and the remaining portion of the first spacer structure (e.g., the inner spacer 131 and the outer spacer 135) can provide additional structural support for the semiconductor element. In addition, the second spacer structure can prevent an undesired short circuit between the bit line structure and a conductive pad subsequently formed on the capacitor contact. As a result, the overall element performance can be improved, and the yield of the semiconductor element can be increased.

[0168] In one embodiment of the present disclosure, a method for preparing a semiconductor element is provided. The method includes: forming a first source / drain region and a second source / drain region in a semiconductor substrate and forming a bit line structure on the first source / drain region and electrically connected to the first source / drain region. The method also includes forming a first spacer structure on the sidewall of the bit line structure, and forming a capacitor contact on the second source / drain region and electrically connected to the second source / drain region. The capacitor contact is adjacent to the first spacer structure, and the first spacer structure is etched during the formation of the capacitor contact. The method further includes forming a second spacer structure on the etched first spacer structure, and performing a heat treatment process after the second spacer structure is formed to convert a portion of the first spacer structure into an air gap.

[0169] In another embodiment of the present disclosure, a method for preparing a semiconductor element is provided. The method includes: forming a first source / drain region and a second source / drain region in a semiconductor substrate and forming a semiconductor layer on the semiconductor substrate. The method also includes forming a metal layer on the semiconductor layer and forming a patterned mask on the metal layer. The method further includes using the patterned mask as a mask to etch the semiconductor layer and the metal layer to form a bit line structure. The bit line structure is formed on the first source / drain region and is electrically connected to the first source / drain region. In addition, the method includes forming a first spacer structure on a side wall of the bit line structure and a side wall of the patterned mask, and forming a capacitor contact on the second source / drain region and electrically connected to the second source / drain region, wherein the first spacer structure is sandwiched between the bit line structure and the capacitor contact. The method also includes forming a second spacer structure on the first spacer structure and performing a thermal treatment process after the second spacer structure is formed to form an air gap in the first spacer structure.

[0170] In yet another embodiment of the present disclosure, a semiconductor element is provided. The semiconductor element includes: a first source / drain region and a second source / drain region, disposed in a semiconductor substrate; and a bit line structure, disposed on the first source / drain region and electrically connected to the first source / drain region. The semiconductor element also includes a capacitor contact, disposed on the second source / drain region and electrically connected to the second source / drain region, and a first spacer structure is sandwiched between the bit line structure and the capacitor contact. The first spacer structure includes an air gap. The semiconductor element further includes a second spacer structure, disposed on the first spacer structure. The air gap is covered by the second spacer structure.

[0171] Embodiments of the present disclosure have several advantageous features. By performing a thermal treatment process to convert a portion of the first spacer structure into an air gap, parasitic capacitance between conductive components on opposite sides of the first spacer structure can be reduced, and the remaining portion of the first spacer structure can provide additional structural support for the semiconductor device. In addition, by forming a second spacer structure on top of the first spacer structure, undesirable short circuits can be prevented. As a result, overall device performance can be improved and the yield of the semiconductor device can be increased.

[0172] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and many of the above processes may be replaced by other processes and combinations thereof.

[0173] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A method for preparing an air gap between a bit line structure and a capacitor contact, comprising: A plurality of active regions are defined by forming a device isolation layer in a substrate; forming a semiconductor layer and a metal layer on the plurality of active regions; forming a first mask intersecting the plurality of active regions on the metal layer; etching the semiconductor layer and the metal layer using the first mask as an etching mask to form a plurality of bit line structures; forming a plurality of lower spacer structures having an energy removable material, wherein the energy removable material is located on sidewalls of the plurality of bit line structures; forming a second mask on the metal layer; forming a plurality of upper spacer structures over the plurality of lower spacer structures; forming a dielectric layer surrounding the plurality of taller spacer structures and covering the metal layer; forming a plurality of capacitor contacts including a barrier layer and a conductive layer; as well as A thermal treatment process is performed to transform the plurality of lower spacer structures into a plurality of air gap structures.

2. The method of claim 1 , wherein forming the plurality of lower spacer structures having an energy removable material comprises: depositing the energy removable material on the metal layer; as well as Planarizing the energy removes material until the metal layer is exposed.

3. The method of claim 1 , wherein forming the plurality of taller spacer structures comprises: conformally depositing the energy removable material overlying the first mask and the metal layer; as well as The energy removable material is etched by an anisotropic etching process.

4. The method of claim 1 , wherein forming the dielectric layer surrounding the plurality of taller spacer structures and covering the metal layer comprises: depositing a dielectric material overlying and covering the plurality of taller spacer structures and the metal layer; as well as The dielectric material is planarized until the first mask is exposed. 5 . The method for fabricating an air gap between a bit line structure and a capacitor contact as claimed in claim 1 , wherein the barrier layer is fabricated using an anisotropic deposition process. 6 . The method for fabricating an air gap between a bit line structure and a capacitor contact as claimed in claim 1 , wherein the fabrication technique of the conductive layer comprises a deposition process.

7. The method for preparing an air gap between a bit line structure and a capacitor contact as claimed in claim 6, wherein the barrier layer has a first thickness on the sidewall of the corresponding conductive layer and has a second thickness below the bottom surface of the corresponding conductive layer.

8. The method for forming an air gap between a bit line structure and a capacitor contact as claimed in claim 1, wherein a heat treatment process is performed to form an air gap sealed by a liner.

9. A method for preparing a semiconductor element, comprising: forming a first source / drain region and a second source / drain region in a semiconductor substrate; forming a bit line structure on the first source / drain region and electrically connected to the first source / drain region; forming a capacitor contact on the second source / drain region and electrically connected to the second source / drain region; forming a first spacer structure between the bit line structure and the capacitor contact, wherein the first spacer structure includes an air gap; as well as A second spacer structure is formed on the first spacer structure, wherein the air gap is covered by the second spacer structure.

10. The method for manufacturing a semiconductor device as claimed in claim 9, wherein forming the bit line structure comprises: forming a semiconductor layer on the semiconductor substrate; forming a metal layer on the semiconductor layer; as well as An etching process is performed on the semiconductor layer and the metal layer. 11 . The method for manufacturing a semiconductor device as claimed in claim 9 , further comprising forming a patterned mask on the bit line structure. 12 . The method for manufacturing a semiconductor device as claimed in claim 11 , further comprising forming a dielectric layer on the second spacer structure and the patterned mask. 13 . The method for manufacturing a semiconductor device as claimed in claim 12 , further comprising forming a conductive pad covering the second spacer structure and a portion of the patterned mask. 14 . The method for manufacturing a semiconductor device as claimed in claim 13 , wherein the conductive pad is disposed on the capacitor contact and electrically connected to the capacitor contact. 15 . The method for manufacturing a semiconductor device as claimed in claim 9 , further comprising performing a thermal treatment process to transform the first spacer structure into an air gap structure, wherein the air gap structure comprises an air gap sealed by a liner. 16 . The method for fabricating a semiconductor device as claimed in claim 15 , wherein the air gap structure and the air gap extend into the semiconductor substrate. 17 . The method for manufacturing a semiconductor device as claimed in claim 9 , wherein the capacitor contact comprises a barrier layer and a conductive layer lining the barrier layer. 18 . The method for manufacturing a semiconductor device as claimed in claim 17 , wherein the barrier layer has a first thickness on the corresponding sidewall of the conductive layer, and has a second thickness below the corresponding bottom surface of the conductive layer.

Images