Preparation method of memory element

Abstract

The invention provides a preparation method of a memory element. The method includes forming a bit line structure over a semiconductor substrate; forming a first nitride spacer, a second nitride spacer, and a first oxide spacer on a sidewall of the bit line structure, where the first nitride spacer is in direct contact with the bit line structure, and the first oxide spacer is located between the first nitride spacer and the second nitride spacer; forming a lower capacitor contact adjacent to the second nitride spacer; forming an upper capacitor contact material over the lower capacitor contact; etching the upper capacitor contact material, the first nitride spacer, the second nitride spacer, and the first oxide spacer to form a capacitor opening; the first oxide spacer is removed through the capacitor opening to form a first gap between the first nitride spacer and the second nitride spacer.

Description

Technical Field

[0001] This application is a divisional application of the invention patent application with application number 202410145847.2, application date February 1, 2024, and invention name “memory element”. The invention patent application with application number 202410145847.2 claims priority and benefits of U.S. formal application No. 18 / 518,543 filed on November 23, 2023, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a memory element and a method for manufacturing the same, and more particularly to a memory element with an air gap and a method for manufacturing the same. Background Art

[0003] Due to its simple structure, dynamic random access memory (DRAM) can provide more memory cells per unit chip area than other types of memory, such as static random access memory (SRAM). A dynamic random access memory is composed of multiple dynamic random access memory cells, each of which includes a capacitor for storing information and a transistor coupled to the capacitor to regulate when the capacitor is charged or discharged. During a read operation, a word line (WL) is asserted, thereby turning on the transistor. The enabled transistor allows a sense amplifier to read the voltage across the capacitor via a bit line (BL). During a write operation, the data to be written is provided on the BL while the WL is asserted.

[0004] In order to meet the demand for greater memory capacity, the size of DRAM memory cells continues to shrink, resulting in a significant increase in the packaging density of these DRAMs. However, the manufacture and integration of memory components involves many complex steps and operations. The integration of memory components is becoming increasingly complex. The increased complexity of the manufacture and integration of memory components may lead to defects. Therefore, there is a need to continuously improve the structure and manufacturing process of memory components to address their defects and improve performance.

[0005] The above “prior art” description only provides background technology, does not admit that the above “prior art” description discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of the present invention. Summary of the invention

[0006] The purpose of the present disclosure is to provide a method for manufacturing a memory element to solve at least one of the above problems.

[0007] One embodiment of the present disclosure provides a memory element. The memory element includes a bit line structure disposed above a semiconductor substrate; and a lower capacitor contact disposed above the semiconductor substrate and adjacent to the bit line structure. The memory element also includes a first nitride spacer and a second nitride spacer disposed between the bit line structure and the lower capacitor contact. The memory element also includes a capacitor disposed above the first nitride spacer and the second nitride spacer. In addition, the memory element includes a first oxide liner and a second oxide liner disposed between the first nitride spacer and the second nitride spacer. An air gap is located between the first oxide liner and the second oxide liner.

[0008] In one embodiment, the first oxide liner is separated from the second oxide liner. In one embodiment, the air gap is surrounded by the semiconductor substrate, the first oxide liner, the second oxide liner and the capacitor. In one embodiment, the first nitride spacer is separated from the air gap by the first oxide liner, and the second nitride spacer is separated from the air gap by the second oxide liner. In one embodiment, the first oxide liner is in direct contact with the first nitride spacer, and the second oxide liner is in direct contact with the second nitride spacer. In addition, the first oxide liner also extends between the first nitride spacer and the capacitor, and the second oxide liner also extends between the second nitride spacer and the capacitor.

[0009] In one embodiment, the memory element further comprises an upper capacitor contact disposed above the lower capacitor contact; and a third nitride spacer disposed between the bit line structure and the upper capacitor contact, wherein the second nitride spacer is disposed between the first nitride spacer and the third nitride spacer, and the third nitride spacer is in direct contact with the upper capacitor contact. In one embodiment, the second oxide liner also extends between the second nitride spacer and the third nitride spacer. In one embodiment, the second oxide liner also extends between the third nitride spacer and the capacitor. In one embodiment, the second oxide liner also extends between the third nitride spacer and the lower capacitor contact. In one embodiment, the memory element further comprises a silicide layer disposed between the lower capacitor contact and the upper capacitor contact, wherein the second oxide liner is in direct contact with the silicide layer.

[0010] Another embodiment of the present disclosure provides a memory element. The memory element includes a bit line structure and a lower capacitor contact, which are arranged above a semiconductor substrate. The lower capacitor contact extends into the semiconductor substrate. The memory element also includes a first nitride spacer and a second nitride spacer, which are arranged above the semiconductor substrate and between the bit line structure and the lower capacitor contact. The first nitride spacer is in direct contact with the bit line structure, and the second nitride spacer is in direct contact with the lower capacitor contact. The memory element also includes a first oxide liner and a second oxide liner, which are arranged between the first nitride spacer and the second nitride spacer. The first oxide liner is in direct contact with the first nitride spacer, and the second oxide liner is in direct contact with the second nitride spacer. The first oxide liner is separated from the second oxide liner by an air gap.

[0011] In one embodiment, the first oxide liner and the second oxide liner are in direct contact with the semiconductor substrate. In one embodiment, the memory element further includes an upper capacitor contact disposed above the lower capacitor contact; and a third nitride spacer disposed between the second nitride spacer and the upper capacitor contact; wherein the third nitride spacer is in direct contact with the upper capacitor contact. In one embodiment, the third nitride spacer is separated from the second nitride spacer by the second oxide liner. In one embodiment, the memory element further includes a silicide layer disposed between the lower capacitor contact and the upper capacitor contact.

[0012] In one embodiment, the silicide layer is in direct contact with the third nitride spacer and the second oxide liner. In one embodiment, the memory element further comprises a capacitor disposed above the first nitride spacer, the second nitride spacer, and the third nitride spacer, wherein the air gap is sealed by the capacitor. In one embodiment, the first oxide liner and the second oxide liner are in direct contact with the capacitor. In one embodiment, the first nitride spacer is separated from the capacitor by the first oxide liner. In one embodiment, the second nitride spacer and the third nitride spacer are separated from the capacitor by the second oxide liner.

[0013] Another embodiment of the present disclosure provides a method for preparing a memory element. The preparation method includes forming a bit line structure above a semiconductor substrate; and forming a first nitride spacer, a second nitride spacer and a first oxide spacer on a side wall of the bit line structure. The first nitride spacer is in direct contact with the bit line structure, and the first oxide spacer is located between the first nitride spacer and the second nitride spacer. The preparation method also includes forming a lower capacitor contact adjacent to the second nitride spacer; and forming an upper capacitor contact material above the lower capacitor contact. The preparation method also includes etching the upper capacitor contact material, the first nitride spacer, the second nitride spacer and the first oxide spacer to form a capacitor opening; and removing the first oxide spacer through the capacitor opening to form a first gap between the first nitride spacer and the second nitride spacer. In addition, the preparation method includes performing an oxidation process to form a first oxide liner and a second oxide liner in the first gap; and forming a capacitor in the capacitor opening to seal the first gap so that an air gap is surrounded by the capacitor, the first oxide liner, the second oxide liner and the semiconductor substrate.

[0014] In one embodiment, an upper surface and a side wall of the first nitride spacer are covered by the first oxide liner, and an upper surface and a side wall of the second nitride spacer are covered by the second oxide liner. In one embodiment, the preparation method also includes forming a first native oxide layer between the first nitride spacer and the first oxide spacer; and forming a second native oxide layer between the second nitride spacer and the first oxide spacer; wherein the first native oxide layer and the second native oxide layer are etched to form the capacitor opening. In one embodiment, the preparation method also includes removing the first native oxide layer and the second native oxide layer through the capacitor opening to form the first gap. In one embodiment, the preparation method also includes forming a third nitride spacer above the lower capacitor contact and adjacent to the second nitride spacer before forming the upper capacitor contact material.

[0015] In one embodiment, after performing the oxidation process, an upper surface of the third nitride spacer is covered by the second oxide liner. In one embodiment, the preparation method further includes forming a third native oxide layer between the second nitride spacer and the third nitride spacer before forming the upper capacitor contact material, wherein the third nitride spacer is separated from the lower capacitor contact and the second nitride spacer by the third native oxide layer. In one embodiment, the preparation method further includes removing the third native oxide layer to form a second gap, wherein after performing the oxidation process, the second gap is filled by the second oxide liner. In one embodiment, the preparation method further includes forming a silicide layer above the lower capacitor contact after forming the third nitride spacer and the third native oxide layer, wherein the upper capacitor contact material is formed above the silicide layer. In one embodiment, after performing the oxidation process, the silicide layer is in direct contact with the second oxide liner.

[0016] The present disclosure provides an embodiment of a memory element and a method for preparing the same. In some embodiments, the memory element includes a bit line structure and a lower capacitor contact disposed above a semiconductor substrate. The memory element also includes a first nitride spacer and a second nitride spacer disposed between the bit line structure and the lower capacitor contact. In some embodiments, the memory element includes a first oxide liner and a second oxide liner disposed between the first nitride spacer and the second nitride spacer, and an air gap is located between the first oxide liner and the second oxide liner. The air gap can reduce parasitic capacitance and improve component performance accordingly (for example, by reducing signal noise). In addition, the first oxide liner and the second oxide liner help prevent etching through the first nitride spacer and the second nitride spacer during the formation of the air gap. As a result, a short circuit problem from the bit line structure to the lower capacitor contact can be prevented.

[0017] The above has been a fairly broad overview of the technical features and advantages of the present disclosure so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the claims of the present disclosure will be described below. It should be understood by those skilled in the art to which the present disclosure belongs that the concepts and specific embodiments disclosed below can be used quite easily to modify or design other structures or processes to achieve the same purpose as the present disclosure. It should also be understood by those skilled in the art to which the present disclosure belongs that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] When with Figure 1When read together, various aspects of the present disclosure can be best understood from the following detailed description. It should be understood that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the size of various features can be arbitrarily increased or reduced for clarity of discussion.

[0019] Figure 1 is a cross-sectional schematic diagram illustrating memory elements of some embodiments of the present disclosure.

[0020] Figure 2 is an enlarged schematic diagram illustrating some embodiments of the present disclosure Figure 1 Area A in .

[0021] Figure 3 is a flow chart illustrating a method for preparing a memory element according to some embodiments of the present disclosure.

[0022] Figure 4 is a schematic cross-sectional view illustrating an intermediate stage of forming an isolation structure and a doped region in a semiconductor substrate during formation of a memory element according to some embodiments of the present disclosure.

[0023] Figure 5 is a schematic cross-sectional view illustrating an intermediate stage of forming a bit line contact in a semiconductor substrate during formation of a memory device according to some embodiments of the present disclosure.

[0024] Figure 6 is a schematic cross-sectional view illustrating an intermediate stage of forming a bit line material over a semiconductor substrate during formation of a memory device according to some embodiments of the present disclosure.

[0025] Figure 7 is a schematic cross-sectional view illustrating an intermediate stage of etching a bit line material to form a bit line structure during formation of a memory element according to some embodiments of the present disclosure.

[0026] Figure 8 is a schematic cross-sectional view illustrating an intermediate stage of forming nitride and oxide spacers on the sidewalls of a bit line structure during formation of a memory device according to some embodiments of the present disclosure.

[0027] Fig. 9 is a schematic cross-sectional view illustrating an intermediate stage of forming an opening adjacent to a bit line structure during formation of a memory element according to some embodiments of the present disclosure.

[0028] Fig.10 is a schematic cross-sectional view illustrating an intermediate stage of filling an opening with a lower capacitor contact material during formation of a memory element according to some embodiments of the present disclosure.

[0029] Fig.11is a schematic cross-sectional view illustrating an intermediate stage of etching a lower capacitor contact material to form a lower capacitor contact during formation of a memory element according to some embodiments of the present disclosure.

[0030] Fig.12 is an enlarged schematic diagram illustrating some embodiments of the present disclosure Fig.11 Area A in .

[0031] Fig.13 is a schematic cross-sectional view illustrating an intermediate stage of depositing a nitride spacer material over a bit line structure and a lower capacitor contact during formation of a memory element according to some embodiments of the present disclosure.

[0032] Fig.14 is a schematic cross-sectional view illustrating an intermediate stage of etching a nitride spacer material to form a nitride spacer during formation of a memory device according to some embodiments of the present disclosure.

[0033] Fig.15 is a schematic cross-sectional view illustrating an intermediate stage of forming a silicide layer over a lower capacitor contact during formation of a memory element according to some embodiments of the present disclosure.

[0034] Fig.16 is an enlarged schematic diagram illustrating some embodiments of the present disclosure Fig.15 Area A in .

[0035] Fig.17 is a schematic cross-sectional view illustrating an intermediate stage of forming an upper capacitor contact material over a silicide layer and a bit line structure during formation of a memory element according to some embodiments of the present disclosure.

[0036] Fig.18 is a schematic cross-sectional view illustrating an intermediate stage of forming a capacitor opening above a nitride and oxide spacer according to some embodiments of the present disclosure.

[0037] Fig.19 is a schematic cross-sectional view illustrating an intermediate stage of etching oxide spacers through a capacitor opening to form a gap in some embodiments of the present disclosure.

[0038] Fig. 20 is a schematic cross-sectional view illustrating an intermediate stage of a post-etch cleaning process performed in accordance with some embodiments of the present disclosure.

[0039] Fig.21 is a schematic cross-sectional view illustrating an intermediate stage of performing an oxidation process to form an oxide liner in a gap according to some embodiments of the present disclosure.

[0040] The reference numerals are as follows:

[0041] 10: Preparation method

[0042] 100: memory element

[0043] 101:Semiconductor substrate

[0044] 103: Isolation Structure

[0045] 105a: doping region

[0046] 105b: doped region

[0047] 105c: doping region

[0048] 107: Bit line contact

[0049] 109: Lower bit line material

[0050] 109a: lower bit line layer

[0051] 109b: Lower bit line layer

[0052] 111: Upper bit line material

[0053] 111a: upper bit line layer

[0054] 111b: Upper bit line layer

[0055] 112a: Bit line structure

[0056] 112b: Bit line structure

[0057] 113: Bit line mask material

[0058] 113a: bit line mask layer

[0059] 113b: bit line mask layer

[0060] 115: Patterned mask

[0061] 118: Opening

[0062] 120: Opening

[0063] 121a: Nitride interstitial

[0064] 121b: Nitride interstitial

[0065] 121c: Nitride interstitial

[0066] 121d: Nitride interstitial

[0067] 123a: Native oxide layer

[0068] 123b: Native oxide layer

[0069] 123c: Native oxide layer

[0070] 123d: Native oxide layer

[0071] 125a: oxide interstitial

[0072] 125b: oxide interstitial

[0073] 125c: oxide interstitial

[0074] 125d: oxide interstitial

[0075] 127a: Native oxide layer

[0076] 127b: Native oxide layer

[0077] 127c: Native oxide layer

[0078] 127d: Native oxide layer

[0079] 129: Nitride interstitial material

[0080] 129a: Nitride interstitial

[0081] 129b: Nitride interstitial

[0082] 131: Nitride interstitial material

[0083] 131a: Nitride interstitial

[0084] 131b: Nitride interstitial

[0085] 134: Opening

[0086] 137: Lower capacitor contact material

[0087] 137a: Lower capacitor contact

[0088] 137b: Lower capacitor contact

[0089] 137c: Lower capacitor contact

[0090] 139: Native oxide materials

[0091] 139a': Native oxide layer

[0092] 139b: Native oxide layer

[0093] 139c': Native oxide layer

[0094] 139d: Native oxide layer

[0095] 141: Nitride interstitial

[0096] 141a: Nitride interstitial

[0097] 141b: Nitride interstitial

[0098] 141c: Nitride interstitial

[0099] 141d: Nitride interstitial

[0100] 143a: Silicide layer

[0101] 143b: Silicide layer

[0102] 143c: Silicide layer

[0103] 145: Upper capacitor contact material

[0104] 145a: Upper capacitor contact

[0105] 145b: Upper capacitor contact

[0106] 145c: Upper capacitor contact

[0107] 148: Capacitor opening

[0108] 150a: Gap

[0109] 150b: Gap

[0110] 150c: Clearance

[0111] 150d: Gap

[0112] 152a: Gap

[0113] 152a': Gap

[0114] 152b: Gap

[0115] 152b': Gap

[0116] 155a: Oxide liner

[0117] 155b: Oxide liner

[0118] 155c: Oxide liner

[0119] 155d: Oxide liner

[0120] 155e: Oxide liner

[0121] 155f: Oxide liner

[0122] 155g: Oxide liner

[0123] 155h: Oxide liner

[0124] 158a: Gap

[0125] 158b: Gap

[0126] 158c: Gap

[0127] 158d: Gap

[0128] 160a: Air gap

[0129] 160b: Air gap

[0130] 160c: Air gap

[0131] 160d: Air gap

[0132] 161a: Lower electrode

[0133] 161b: Lower electrode

[0134] 163a: Capacitor dielectric layer

[0135] 163b: Capacitor dielectric layer

[0136] 165a: Upper electrode

[0137] 165b: Upper electrode

[0138] 167a: Capacitor

[0139] 167b:Capacitor

[0140] A: Area

[0141] S1: Sidewall

[0142] S11: Steps

[0143] S13: Steps

[0144] S15: Steps

[0145] S17: Steps

[0146] S19: Steps

[0147] S2: Sidewall

[0148] S21: Steps

[0149] S23: Steps

[0150] S25: Steps

[0151] S27: Steps

[0152] S29: Steps

[0153] S3: Sidewall

[0154] S4: Sidewall

[0155] S5: Sidewall

[0156] S6: Sidewall

[0157] T1: Upper surface

[0158] T2: Upper surface

[0159] T3: Upper surface

[0160] T4: Upper surface

[0161] T5: Upper surface

[0162] T6: Upper surface

[0163] W1: Width

[0164] W2: Width

[0165] W3: Width

[0166] W4: Width DETAILED DESCRIPTION

[0167] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, in the description, the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which additional components are formed between the first and second components so that the first and second components are not in direct contact. In addition, the embodiments of the present disclosure may repeat reference numbers and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0168] Additionally, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

[0169] Figure 1 is a schematic cross-sectional view illustrating a memory element 100 according to some embodiments of the present disclosure. Figure 2 is an enlarged schematic diagram illustrating some embodiments of the present disclosure Figure 1 Area A in .

[0170] like Figure 1 and Figure 2As shown, the memory device 100 includes a semiconductor substrate 101, a plurality of isolation structures 103, and doped regions 105a, 105b, and 105c disposed in the semiconductor substrate 101. In some embodiments, the doped regions 105a, 105b, and 105c are a plurality of active regions electrically isolated from each other by the isolation structures 103. In addition, the memory device 100 includes a bit line contact 107 disposed in the doped region 105a.

[0171] In addition, the memory device 100 includes bit line structures 112a and 112b disposed above the semiconductor substrate 101. In some embodiments, the bit line structure 112a includes a lower bit line layer 109a and an upper bit line layer 111a disposed above the lower bit line layer 109a. In some embodiments, the bit line structure 112b includes a lower bit line layer 109b and an upper bit line layer 111b disposed above the lower bit line layer 109b. In addition, bit line mask layers 113a and 113b are disposed above the bit line structures 112a and 112b, respectively.

[0172] In some embodiments, lower capacitor contacts 137a, 137b, and 137c are disposed adjacent to bit line structures 112a and 112b. For example, lower capacitor contact 137a is disposed adjacent to bit line structure 112a, lower capacitor contact 137b is disposed between bit line structures 112a and 112b and adjacent to bit line structures 112a and 112b, and lower capacitor contact 137c is disposed adjacent to bit line structure 112b. In some embodiments, silicide layers 143a, 143b, and 143c are disposed over lower capacitor contacts 137a, 137b, and 137c, respectively. In some embodiments, upper capacitor contacts 145a, 145b, and 145c are disposed over silicide layers 143a, 143b, and 143c, respectively, and are in direct contact with silicide layers 143a, 143b, and 143c. In some embodiments, upper capacitor contact 145b extends over bit line mask layer 113a, and upper capacitor contact 145c extends over bit line mask layer 113b.

[0173] In some embodiments, nitride spacers 121a and 121b are disposed on and in direct contact with opposite sidewalls of bit line structure 112a, and nitride spacers 121c and 121d are disposed on and in direct contact with opposite sidewalls of bit line structure 112b. In addition, according to some embodiments, nitride spacers 121a and 121b extend to cover opposite sidewalls of bit line mask layer 113a, and nitride spacers 121c and 121d extend to cover opposite sidewalls of bit line mask layer 113b.

[0174] In some embodiments, a nitride spacer 129a is disposed between the bit line structure 112a and the lower capacitor contact 137a, a nitride spacer 129b is disposed between the bit line structure 112a and the lower capacitor contact 137b, a nitride spacer 131a is disposed between the bit line structure 112b and the lower capacitor contact 137b, and a nitride spacer 131b is disposed between the bit line structure 112b and the lower capacitor contact 137c.

[0175] In some embodiments, oxide liners 155a and 155b are disposed between nitride spacers 121a and 129a, and an air gap 160a is located between oxide liners 155a and 155b. In some embodiments, oxide liner 155a is separated from oxide liner 155b by air gap 160a. In some embodiments, oxide liners 155c and 155d are disposed between nitride spacers 121b and 129b, and an air gap 160b is located between oxide liners 155c and 155d. In some embodiments, oxide liner 155c is separated from oxide liner 155d by air gap 160b.

[0176] In some embodiments, oxide liners 155e and 155f are disposed between nitride spacers 121c and 131a, and an air gap 160c is disposed between oxide liners 155e and 155f. In some embodiments, oxide liner 155e is separated from oxide liner 155f by air gap 160c. In some embodiments, oxide liners 155g and 155h are disposed between nitride spacers 121d and 131b, and an air gap 160d is disposed between oxide liners 155g and 155h. In some embodiments, oxide liner 155g is separated from oxide liner 155h by air gap 160d.

[0177] In some embodiments, a nitride spacer 141a is disposed between the nitride spacer 129a and the upper capacitor contact 145a, and an oxide liner 155a extends between the nitride spacers 129a and 141a. In some embodiments, the lower surface of the nitride spacer 141a is higher than the lower surface of the nitride spacer 121a and the lower surface of the nitride spacer 129a. In some embodiments, the nitride spacers 121a and 129a are in direct contact with the semiconductor substrate 101. In some embodiments, the nitride spacer 141a is disposed above the lower capacitor contact 137a, and the nitride spacer 141a is separated from the lower capacitor contact 137a by the oxide liner 155a. In some embodiments, the oxide liner 155a is in direct contact with the silicide layer 143a.

[0178] In some embodiments, nitride spacer 141b is disposed between nitride spacer 129b and upper capacitor contact 145b, and a native oxide layer 139b is disposed between nitride spacer 129b and nitride spacer 141b. In some embodiments, the lower surface of nitride spacer 141b is higher than the lower surface of nitride spacer 121b and the lower surface of nitride spacer 129b. In some embodiments, nitride spacers 121b and 129b are in direct contact with semiconductor substrate 101. In some embodiments, nitride spacer 141b is disposed above lower capacitor contact 137b, and nitride spacer 141b is separated from lower capacitor contact 137b by native oxide layer 139b. In some embodiments, native oxide layer 139b is in direct contact with silicide layer 143b.

[0179] In addition, in some embodiments, nitride spacer 141c is disposed between nitride spacer 131a and upper capacitor contact 145b, and oxide liner 155e extends between nitride spacers 131a and 141c. In some embodiments, the lower surface of nitride spacer 141c is higher than the lower surface of nitride spacer 121c and the lower surface of nitride spacer 131a. In some embodiments, nitride spacers 121c and 131a are in direct contact with semiconductor substrate 101. In some embodiments, nitride spacer 141c is disposed above lower capacitor contact 137b, and nitride spacer 141c is separated from lower capacitor contact 137b by oxide liner 155e. In some embodiments, oxide In some embodiments, nitride spacer 141d is disposed between nitride spacer 131b and upper capacitor contact 145c, and native oxide layer 139d is disposed between nitride spacer 131b and nitride spacer 141d. In some embodiments, the lower surface of the nitride spacer 141d is higher than the lower surface of the nitride spacer 121d and the lower surface of the nitride spacer 131b. In some embodiments, the nitride spacers 121d and 131b are in direct contact with the semiconductor substrate 101. In some embodiments, the nitride spacer 141d is disposed above the lower capacitor contact 137c, and the nitride spacer 141d is separated from the lower capacitor contact 137c by the native oxide layer 139d. In some embodiments, the native oxide layer 139d is in direct contact with the silicide layer 143c.

[0180] In addition, the memory device 100 includes a capacitor 167a disposed above the nitride spacers 121a, 129a, and 141a and a capacitor 167b disposed above the nitride spacers 121c, 131a, and 141c. In some embodiments, the capacitor 167a includes a lower electrode 161a, an upper electrode 165a disposed above and surrounded by the lower electrode 161a, and a capacitor dielectric layer 163a interposed between the lower electrode 161a and the upper electrode 165a. In some embodiments, the nitride spacers 129a and 141a are separated from the capacitor 167a by the oxide liner 155a, and the nitride spacer 121a is separated from the capacitor 167a by the oxide liner 155b.

[0181] In some embodiments, capacitor 167b includes a lower electrode 161b, an upper electrode 165b disposed above and surrounded by lower electrode 161b, and a capacitor dielectric layer 163b interposed between lower electrode 161b and upper electrode 165b. In some embodiments, nitride spacers 131a and 141c are separated from capacitor 167b by oxide liner 155e, and nitride spacer 121c is separated from capacitor 167b by oxide liner 155f.

[0182] like Figure 2 As shown, a top surface T1 and a side wall S1 of the nitride spacer 121c are covered by and in direct contact with the oxide liner 155f, and a top surface T2 and a side wall S2 of the nitride spacer 131a are covered by and in direct contact with the oxide liner 155e. In some embodiments, according to some embodiments, a top surface T3 of the nitride spacer 141c is covered by and in direct contact with the oxide liner 155e. Similar features also exist in the nitride spacers 121a, 129a, 141a and the oxide liners 155a and 155b, and are not repeated here.

[0183] The present disclosure provides an embodiment of a memory element 100 and a method for making the same. In some embodiments, air gaps 160a, 160b, 160c, and 160d are disposed between oxide pads 155a, 155b, 155c, 155d, 155e, 155f, 155g, and 155h, which can reduce parasitic capacitance and correspondingly improve element performance (e.g., by reducing signal noise). In addition, oxide pads 155a, 155b, 155e, and 155f help prevent etching through nitride spacers 121a, 129a, 121c, and 131a during the formation of air gaps 160a, 160b, 160c, and 160d. As a result, short circuit problems from bit line structures 112a and 112b to lower capacitor contacts 137a and 137b can be prevented.

[0184] Figure 3 1 is a flow chart illustrating a method 10 for preparing a memory element according to some embodiments of the present disclosure, and the method 10 includes steps S11, S13, S15, S17, S19, S21, S23, S25, S27 and S29. Figure 3 Steps S11 to S29 are described in detail.

[0185] Figure 4-Figure 11 , Figure 13-Figure 15 and Figure 17-Figure 21 is a schematic cross-sectional view illustrating an intermediate stage in the formation of a memory element 100 according to some embodiments. According to some embodiments, Fig.12 yes Fig.11 is an enlarged view of region A in FIG. Fig.16 yes Fig.15 Magnified view of area A in FIG.

[0186] like Figure 4 As shown, a semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the semiconductor substrate 101 may include elemental semiconductor materials, compound semiconductor materials and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP.

[0187] In some embodiments, the semiconductor substrate 101 includes an epitaxial layer. For example, the semiconductor substrate 101 has an epitaxial layer covering a bulk semiconductor. In some embodiments, the semiconductor substrate 101 is a semiconductor-on-insulator substrate, which may include a substrate, a buried oxide layer above the substrate, and a semiconductor layer above the buried oxide layer, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate may be manufactured using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other applicable methods.

[0188] Please still refer to Figure 4 According to some embodiments, the isolation structure 103 is formed in the semiconductor substrate 101, and the isolation structure 103 is a shallow trench isolation (STI) structure. In addition, the isolation structure 103 may include silicon oxide, silicon nitride, silicon oxynitride, or other applicable dielectric materials, and the formation of the isolation structure 103 may include forming a patterned mask (not shown) above the semiconductor substrate 101, etching the semiconductor substrate 101 to form a plurality of openings (not shown) using the patterned mask as a mask, depositing a dielectric material in the plurality of openings and above the semiconductor substrate 101, and planarizing the dielectric material until the semiconductor substrate 101 is exposed.

[0189] In addition, doped regions 105a, 105b, and 105c are formed in a plurality of active regions defined by the isolation structure 103. In some embodiments, the fabrication techniques of the doped regions 105a, 105b, and 105c include one or more ion implantation processes, and P-type dopants, such as boron (B), gallium (Ga), or indium (In), or N-type dopants, such as phosphorus (P) or arsenic (As), may be implanted in the active regions to form the doped regions 105a, 105b, and 105c, depending on the conductivity type of the memory device 100. In addition, the doped regions 105a, 105b, and 105c will become source / drain regions of the memory device 100 in subsequent processes.

[0190] According to some embodiments, Figure 5As shown, after forming the isolation structure 103 and the doped regions 105a, 105b and 105c, a bit line contact 107 is formed in the semiconductor substrate 101. In some embodiments, the bit line contact 107 is formed in the doped region 105a. In some embodiments, the bit line contact 107 may include doped polysilicon, metal, metal silicide or other applicable conductive materials, and the formation of the bit line contact 107 may include forming a patterned mask (not shown) above the semiconductor substrate 101, etching the semiconductor substrate 101 using the patterned mask as a mask to form a plurality of openings (not shown), depositing a conductive material in the plurality of openings and above the semiconductor substrate 101, and planarizing the conductive material until the semiconductor substrate 101 is exposed.

[0191] Next, according to some embodiments, Figure 6 As shown, a lower bit line material 109, an upper bit line material 111, a bit line mask material 113, and a patterned mask 115 are sequentially formed over the semiconductor substrate 101. In some embodiments, the patterned mask 115 has a plurality of openings 118 exposing the bit line mask material 113. In some embodiments, the lower bit line material 109 includes titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium carbide (TiC), or other suitable conductive materials.

[0192] In some embodiments, the upper bit line material 111 includes tungsten (W), titanium (Ti), nickel (Ni), cobalt (Co), or a combination thereof. In some embodiments, the bit line mask material 113 includes silicon nitride. However, this material is merely exemplary. Any other suitable material may alternatively be used to form the bit line mask material 113. In some embodiments, the bit line mask material 113 and the patterned mask 115 include different materials so that the etching selectivity may be different in a subsequent etching process.

[0193] In addition, according to some embodiments, the manufacturing technology of the lower bit line material 109 includes a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, and a spin coating process. Some processes used to form the upper bit line material 111 and the bit line mask material 113 are similar or the same as the processes used to form the lower bit line material 109, and are not repeated here.

[0194] Subsequently, according to some embodiments, an etching process is performed using the patterned mask 115 as an etching mask, thereby forming the bit line structures 112a and 112b, such as Figure 7 The individual steps are shown as Figure 2Step S11 of the manufacturing method 10 is shown. In some embodiments, an opening 120 is formed through the bit line mask material 113, the upper bit line material 111 and the lower bit line material 109, and the bit line structures 112a and 112b are separated from each other.

[0195] In some embodiments, the bit line structure 112a includes a lower bit line layer 109a and an upper bit line layer 111a, and the bit line structure 112a is covered by a bit line mask layer 113a. In some embodiments, the bit line structure 112b includes a lower bit line layer 109b and an upper bit line layer 111b, and the bit line structure 112b is covered by a bit line mask layer 113b. In addition, according to some embodiments, the opposite sidewalls S3 and S4 of the bit line structure 112a and the opposite sidewalls S5 and S6 of the bit line structure 112b are exposed through the opening 120. In some embodiments, the etching process for forming the bit line structures 112a and 112b includes a wet etching process, a dry etching process, or a combination thereof. After forming the bit line structures 112a and 112b, the patterned mask 115 may be removed. The material pad 155e is in direct contact with the silicide layer 143b.

[0196] Then, in some embodiments, Figure 8 As shown, nitride spacers 121a and 121b, native oxide layers 123a and 123b, oxide spacers 125a and 125b, and native oxide layers 127a and 127b are formed on opposite sidewalls S3 and S4 of the bit line structure 112a, and nitride spacers 121c and 121d, native oxide layers 123c and 123d, oxide spacers 125c and 125d, and native oxide layers 127c and 127d are formed on opposite sidewalls S5 and S6 of the bit line structure 112b. In some embodiments, opposite sidewalls of the bit line mask layer 113a are covered by nitride spacers 121a and 121b, native oxide layers 123a and 123b, oxide spacers 125a and 125b, and native oxide layers 127a and 127b, and opposite sidewalls of the bit line mask layer 113b are covered by nitride spacers 121c and 121d, native oxide layers 123c and 123d, oxide spacers 125c and 125d, and native oxide layers 127c and 127d.

[0197] In some embodiments, the nitride spacers 121a, 121b, 121c, and 121d include silicon nitride, and the oxide spacers 125a, 125b, 125c, and 125d include silicon oxide. In some embodiments, the native oxide layers 123a, 123b, 123c, 123d, 127a, 127b, 127c, and 127d include silicon oxide. In some embodiments, the fabrication techniques of the nitride spacers 121a, 121b, 121c, and 121d include a deposition process (e.g., a CVD process or an ALD process) and a subsequent etching process. In some embodiments, the etching process used to form the nitride spacers 121a, 121b, 121c, and 121d is an anisotropic etching process that vertically removes the same amount of spacer material at all locations and leaves the nitride spacers 121a, 121b, 121c, and 121d on the sidewalls S3, S4, S5, and S6 of the bit line structures 112a and 112b. In some embodiments, the fabrication technique for the oxide spacers 125a, 125b, 125c, and 125d includes an ALD process. Some processes used to form oxide spacers 125a, 125b, 125c and 125d and native oxide layers 123a, 123b, 123c, 123d, 127a, 127b, 127c and 127d are similar or identical to those used to form nitride spacers 121a, 121b, 121c and 121d, and their details are not repeated here.

[0198] Please still refer to Figure 8 According to some embodiments, a nitride spacer material 129 is formed to cover the native oxide layers 127a and 127b and the upper surface T4 of the bit line structure 112a (see Figure 7 ), and forming a nitride spacer material 131 to cover the native oxide layers 127c and 127d and the upper surface T5 of the bit line structure 112b (see Figure 7 ). In some embodiments, the nitride spacer materials 129 and 131 include silicon nitride. In some embodiments, the manufacturing technique of the nitride spacer materials 129 and 131 includes a deposition process and a subsequent etching process. The nitride spacer materials 129 and 131 may also be referred to as nitride spacers. The steps are shown as Figure 1 Step S13 in the preparation method 10 shown.

[0199] Next, according to some embodiments, Fig. 9As shown, an etching process is performed on the semiconductor substrate 101 so that a plurality of openings 134 are formed adjacent to the bit line structures 112a and 112b. In some embodiments, the nitride spacer materials 129 and 131 are used as an etching process to form the openings 134. In some embodiments, the openings 134 are adjacent to the nitride spacer materials 129 and 131. In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof.

[0200] Then, according to some embodiments, Fig.10 As shown, a capacitor contact material 137 is formed on Fig. 9 In some embodiments, the opening 134 is filled with a lower capacitor contact material 137. In some embodiments, the lower capacitor contact material 137 includes a conductive material, such as copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag). The manufacturing technology of the lower capacitor contact material 137 may include a deposition process, such as a CVD process, a PVD process, a sputtering process, an electroplating process, or other suitable processes.

[0201] Then, according to some embodiments, Fig.11 As shown, an etching process is performed on the lower capacitor contact material 137 so that lower capacitor contacts 137a, 137b, and 137c are formed adjacent to the bit line structures 112a and 112b. In some embodiments, the lower capacitor contact 137a is disposed adjacent to the nitride spacer material 129. In some embodiments, the lower capacitor contact 137b is disposed between and adjacent to the nitride spacer materials 129 and 131. In some embodiments, the lower capacitor contact 137c is disposed adjacent to the nitride spacer material 131. The various steps are shown as follows: Figure 3 Step S15 in the manufacturing method 10 is shown. In some embodiments, the etching process includes a wet etching process, a dry etching process or a combination thereof.

[0202] Additionally, according to some embodiments, during the etching process used to form the lower capacitor contacts 137a, 137b, and 137c, the nitride spacer materials 129 and 131 are partially etched. Fig.12 As shown, the nitride spacer material 129 has a width W1 that is lower than the upper surface T6 of the lower capacitor contact 137b, and a width W2 that is higher than the upper surface T6 of the lower capacitor contact 137b. In some embodiments, the width W1 is greater than the width W2. Similarly, the nitride spacer material 131 has a width W3 that is lower than the upper surface T6 of the lower capacitor contact 137b, and a width W4 that is higher than the upper surface T6 of the lower capacitor contact 137b. According to some embodiments, as Fig.12As shown, width W3 is greater than width W4.

[0203] Next, according to some embodiments, Fig.13 As shown, a native oxide material 139 and a nitride spacer 141 are sequentially formed on Fig.11 In some embodiments, the lower capacitor contacts 137 a , 137 b , and 137 c and the nitride spacer materials 129 and 131 are covered by the native oxide material 139 , and the native oxide material 139 is covered by the nitride spacer 141 .

[0204] In some embodiments, the native oxide material 139 includes silicon oxide. In some embodiments, the nitride spacer 141 includes silicon nitride. In addition, the fabrication techniques of the native oxide material 139 and the nitride spacer 141 may include a plurality of deposition processes, such as a CVD process, a PVD process, an ALD process, and a spin coating process.

[0205] Then, according to some embodiments, Fig.14 As shown, an etching process is performed to expose the lower capacitor contacts 137a, 137b, and 137c and to expose the bit line mask layers 113a and 113b. In some embodiments, portions of the native oxide material 139 and the nitride spacers 141 covering the upper surfaces of the lower capacitor contacts 137a, 137b, and 137c and portions of the native oxide material 139 and the nitride spacers 141 covering the upper surfaces of the bit line mask layers 113a and 113b are removed. As a result, nitride spacers 141a, 141b, 141c, and 141d (i.e., the remaining portions of the nitride spacer material 141) and native oxide layers 139a', 139b, 139c', and 139d (i.e., the remaining portions of the native oxide material 139) are obtained. The various steps are shown as Figure 3 Step S17 in the preparation method 10 shown.

[0206] In addition, according to some embodiments, portions of the nitride spacer materials 129 and 131 covering the upper surfaces of the bit line mask layers 113a and 113b are removed. As a result, nitride spacers 129a and 129b (i.e., the remaining portions of the nitride spacer material 129) and nitride spacers 131a and 131b (i.e., the remaining portions of the nitride spacer material 131) are obtained. In some embodiments, the etching process for exposing the lower capacitor contacts 137a, 137b, and 137c includes a wet etching process, a dry etching process, or a combination thereof.

[0207] Then, according to some embodiments, Fig.15As shown, silicide layers 143a, 143b and 143c are formed over the respective exposed surfaces of the lower capacitor contacts 137a, 137b and 137c. The various steps are shown as follows: Figure 3 Step S19 in the preparation method 10 shown. In some embodiments, the manufacturing technology of the silicide layers 143a, 143b and 143c includes a silicide process, which includes a metal material deposition process and an annealing process performed in sequence. In some embodiments, the deposition process of the silicide process includes a CVD process, a PVD process, an ALD process or other suitable processes. In some embodiments, the annealing process of the silicide process is performed at a temperature in the range of about 300°C to about 800°C. After the annealing process, the unreacted metal material is removed.

[0208] In some embodiments, the silicide layers 143a, 143b, and 143c are in direct contact with the native oxide layers 139a', 139b, 139c', and 139d. In some embodiments, the silicide layers 143a, 143b, and 143c are in direct contact with the nitride spacers 141a, 141b, 141c, and 141d. For example, according to some embodiments, Fig.16 As shown, the silicide layer 143b is in direct contact with the native oxide layers 139b and 139c' and the nitride spacers 141b and 141c.

[0209] Next, according to some embodiments, Fig.17 As shown, an upper capacitor contact material 145 is formed on Fig.15 The individual steps are shown as Figure 3 In step S21 of the preparation method 10 shown in FIG. Fig.15 ) is filled with the upper capacitor contact material 145. In some embodiments, the upper capacitor contact material 145 includes a conductive material, such as copper (Cu), tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), gold (Au), silver (Ag). The manufacturing technology of the upper capacitor contact material 145 may include a deposition process, such as a CVD process, a PVD process, a sputtering process, an electroplating process or other suitable processes.

[0210] Then, according to some embodiments, Fig.18As shown, an etching process is performed to form a plurality of capacitor openings 148. In some embodiments, remaining portions of the upper capacitor contact material 145 are separated from each other by the capacitor openings 148, and upper capacitor contacts 145a, 145b, and 145c are obtained. In some embodiments, the upper capacitor contact material 145, the nitride spacers 141a, 141b, 141c, 141d, the native oxide layers 139a', 139b, 139c', 139d, the nitride spacers 129a, 129b, 131a, 131b, the native oxide layers 127a, 127b, 127c, 127d, the oxide spacers 125a, 125b, 125c, 125d, the native oxide layers 123a, 123b, 123c, 123d, the nitride spacers 121a, 121b, 121c, 121d, and the bit line mask layers 113a, 113b are partially removed to form the capacitor opening 148. In some embodiments, the etching process includes a wet etching process, a dry etching process, or a combination thereof. The various steps are shown as follows: Figure 3 Step S23 in the preparation method 10 shown.

[0211] Then, according to some gap examples, such as Fig.19 As shown, an etching process is performed to remove oxide spacers 125a, 125b, 125c, 125d and native oxide layers 123a, 123b, 123c, 123d, 127a, 127b, 127c, and 127d through capacitor opening 148 to form gaps 150a, 150b, 150c, and 150d. In some embodiments, native oxide layers 139a' and 139c' are partially removed by the etching process so that a gap 152a is formed over a remaining portion of native oxide layer 139a' and a gap 152b is formed over a remaining portion of native oxide layer 139c'. In some embodiments, the fabrication technique of gaps 150a, 150b, 150c, 150d, 152a, and 152b includes a dry etching process. In some embodiments, hydrofluoric acid (HF) and ammonia (NH ) are used during the etching process. 3 ) as etching gas.

[0212] Next, according to some embodiments, Fig. 20As shown, a post-etch cleaning process is performed to remove the remaining portions of the native oxide layers 139a' and 139c' so as to obtain gaps 152a' and 152b'. In some embodiments, the semiconductor substrate 101 is partially exposed through the gaps 150a, 150b, 150c, and 150d. In some embodiments, the silicide layer 143a is partially exposed through the gap 152a', and the silicide layer 143b is partially exposed through the gap 152b'. In some embodiments, dilute hydrofluoric acid (DHF) is used as an etchant during the post-etch cleaning process. The various steps are shown as follows: Figure 3 Step S25 in the preparation method 10 shown.

[0213] Then, according to some embodiments, Fig.21 As shown, an oxidation process is performed to form oxide liners 155a, 155b, 155c, 155d, 155e, 155f, 155g, and 155h in gaps 150a, 150b, 150c, 150d, 152a', and 152b'. In some embodiments, oxide liners 155a and 155b are formed in gap 150a and separated from each other by gap 158a, and oxide liner 155b extends to fill gap 152a'. In some embodiments, oxide liners 155c and 155d are formed in gap 150b and separated from each other by gap 158b. In some embodiments, oxide liners 155e and 155f are formed in gap 150c and separated from each other by gap 158c, and oxide liner 155e extends to fill gap 152b'. In some embodiments, oxide liners 155g and 155h are formed in gap 150d and are separated from each other by gap 158d.

[0214] In some embodiments, the oxidation process used to form the oxide liners 155a, 155b, 155c, 155d, 155e, 155f, 155g, and 155h is also referred to as O 2 Plasma ashing process. According to some embodiments, during the oxidation process, nitride spacers 121a, 121b, 121c, 121d, 129a, 129b, 131a, 131b, 141a, and 141c are oxidized. The various steps are shown as Figure 3 Step S27 in the preparation method 10 shown.

[0215] Then, refer back to Figure 1 and Figure 2According to some embodiments, capacitors 167a and 167b are formed in capacitor opening 148. In some embodiments, gaps 158a and 158b are sealed by capacitor 167a to form air gaps 160a and 160b, and gaps 158c and 158d are sealed by capacitor 167b to form air gaps 160c and 160d. The various steps are shown as Figure 3 Step S29 in the preparation method 10 shown.

[0216] As described above, capacitor 167a includes a lower electrode 161a, an upper electrode 165a, and a capacitor dielectric layer 163a disposed between the lower electrode 161a and the upper electrode 165a, and capacitor 167b includes a lower electrode 161b, an upper electrode 165b, and a capacitor dielectric layer 163b disposed between the lower electrode 161b and the upper electrode 165b. The formation of capacitors 167a and 167b may include depositing a conductive material, a dielectric material, and another conductive material in sequence in the capacitor opening 148 (see Fig.21 ) and extending over the upper capacitor contacts 145a, 145b, and 145c; and performing a planarization process (e.g., a chemical mechanical polishing (CMP) process) to remove excess portions of the two conductive materials and the dielectric material. In some embodiments, the lower electrodes 161a and 161b include titanium nitride (TiN), and the capacitor dielectric layers 163a and 163b include a dielectric material, such as silicon dioxide (SiO 2 ), hafnium dioxide (HfO 2 ), aluminum oxide (Al 2 O 3 )、ZrO 2 ), or a combination thereof, and the upper electrodes 165a and 165b include titanium nitride (TiN), low stress silicon germanium (SiGe), or a combination thereof.

[0217] After forming capacitors 167a and 167b, memory element 100 having air gaps 160a, 160b, 160c, and 160d is obtained. In some embodiments, memory element 100 is part of a dynamic random access memory (DRAM).

[0218] The present disclosure provides an embodiment of a memory element with an air gap and a method for preparing the same. In some embodiments, the memory element includes a bit line structure (e.g., bit line structure 112b) and a lower capacitor contact (e.g., lower capacitor contact 137b) disposed above a semiconductor substrate (e.g., semiconductor substrate 101). The memory element also includes a first nitride spacer (e.g., nitride spacer 121c) and a second nitride spacer (e.g., nitride spacer 131a) disposed between the bit line structure and the lower capacitor contact. In some embodiments, the memory element includes a first oxide liner (e.g., oxide liner 155f) and a second oxide liner (e.g., oxide liner 155e) disposed between the first nitride spacer and the second nitride spacer, and an air gap (e.g., air gap 160c) located between the first oxide liner and the second oxide liner. The air gap can reduce parasitic capacitance and correspondingly improve element performance (e.g., by reducing signal noise). In addition, the first oxide liner and the second oxide liner help prevent etching through the first nitride spacer and the second nitride spacer during the air gap formation. As a result, a short circuit problem from the bit line structure to the lower capacitor contact can be prevented.

[0219] One embodiment of the present disclosure provides a memory element. The memory element includes a bit line structure disposed above a semiconductor substrate; and a lower capacitor contact disposed above the semiconductor substrate and adjacent to the bit line structure. The memory element also includes a first nitride spacer and a second nitride spacer disposed between the bit line structure and the lower capacitor contact. The memory element also includes a capacitor disposed above the first nitride spacer and the second nitride spacer. In addition, the memory element includes a first oxide liner and a second oxide liner disposed between the first nitride spacer and the second nitride spacer. An air gap is located between the first oxide liner and the second oxide liner.

[0220] Another embodiment of the present disclosure provides a memory element. The memory element includes a bit line structure and a lower capacitor contact, which are arranged above a semiconductor substrate. The lower capacitor contact extends into the semiconductor substrate. The memory element also includes a first nitride spacer and a second nitride spacer, which are arranged above the semiconductor substrate and between the bit line structure and the lower capacitor contact. The first nitride spacer is in direct contact with the bit line structure, and the second nitride spacer is in direct contact with the lower capacitor contact. The memory element also includes a first oxide liner and a second oxide liner, which are arranged between the first nitride spacer and the second nitride spacer. The first oxide liner is in direct contact with the first nitride spacer, and the second oxide liner is in direct contact with the second nitride spacer. The first oxide liner is separated from the second oxide liner by an air gap.

[0221] Another embodiment of the present disclosure provides a method for preparing a memory element. The preparation method includes forming a bit line structure above a semiconductor substrate; and forming a first nitride spacer, a second nitride spacer and a first oxide spacer on a side wall of the bit line structure. The first nitride spacer is in direct contact with the bit line structure, and the first oxide spacer is located between the first nitride spacer and the second nitride spacer. The preparation method also includes forming a lower capacitor contact adjacent to the second nitride spacer; and forming an upper capacitor contact material above the lower capacitor contact. The preparation method also includes etching the upper capacitor contact material, the first nitride spacer, the second nitride spacer and the first oxide spacer to form a capacitor opening; and removing the first oxide spacer through the capacitor opening to form a first gap between the first nitride spacer and the second nitride spacer. In addition, the preparation method includes performing an oxidation process to form a first oxide liner and a second oxide liner in the first gap; and forming a capacitor in the capacitor opening to seal the first gap so that an air gap is surrounded by the capacitor, the first oxide liner, the second oxide liner and the semiconductor substrate.

[0222] Embodiments of the present disclosure have some advantageous features. By forming a plurality of oxide liners between a plurality of nitride spacers and forming a plurality of air gaps between a plurality of oxide liners, parasitic capacitance can be reduced while preventing etching through the plurality of nitride spacers. As a result, short circuit problems from a plurality of bit line structures to a plurality of capacitor contacts can be prevented, and overall device performance can be improved.

[0223] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements can be made without departing from the spirit and scope of the present disclosure defined in the claims. For example, many of the above processes can be implemented in different ways, and other processes or combinations thereof can be used to replace many of the above processes.

[0224] Furthermore, the scope of the present invention is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, compositions of matter, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present invention.

Claims

1. A method for preparing a memory element, comprising: forming a bit line structure on a semiconductor substrate; forming a first nitride spacer, a second nitride spacer, and a first oxide spacer on a sidewall of the bit line structure, wherein the first nitride spacer is in direct contact with the bit line structure, and the first oxide spacer is located between the first nitride spacer and the second nitride spacer; forming a lower capacitor contact adjacent to the second nitride spacer; forming an upper capacitor contact material over the lower capacitor contact; etching the upper capacitor contact material, the first nitride spacer, the second nitride spacer, and the first oxide spacer to form a capacitor opening; removing the first oxide spacer through the capacitor opening to form a first gap between the first nitride spacer and the second nitride spacer; performing an oxidation process to form a first oxide liner and a second oxide liner in the first gap; as well as A capacitor is formed in the capacitor opening to seal the first gap so that an air gap is surrounded by the capacitor, the first oxide liner, the second oxide liner and the semiconductor substrate.

2. The method for fabricating a memory element as claimed in claim 1, wherein an upper surface and a side wall of the first nitride spacer are covered by the first oxide liner, and an upper surface and a side wall of the second nitride spacer are covered by the second oxide liner.

3. The method for preparing a memory element according to claim 1, further comprising: forming a first native oxide layer between the first nitride spacer and the first oxide spacer; as well as A second native oxide layer is formed between the second nitride spacer and the first oxide spacer, wherein the first native oxide layer and the second native oxide layer are etched to form the capacitor opening.

4. The method for preparing a memory element according to claim 3, further comprising: The first native oxide layer and the second native oxide layer are removed through the capacitor opening to form the first gap.

5. The method for preparing a memory element according to claim 1, further comprising: Prior to forming the upper capacitor contact material, a third nitride spacer is formed over the lower capacitor contact and adjacent to the second nitride spacer. 6 . The method for fabricating a memory device as claimed in claim 5 , wherein after performing the oxidation process, an upper surface of the third nitride spacer is covered by the second oxide liner.

7. The method for preparing a memory element according to claim 5, further comprising: Before forming the upper capacitor contact material, a third native oxide layer is formed between the second nitride spacer and the third nitride spacer, wherein the third nitride spacer is separated from the lower capacitor contact and the second nitride spacer by the third native oxide layer.

8. The method for preparing a memory element according to claim 7, further comprising: The third native oxide layer is removed to form a second gap, wherein after performing the oxidation process, the second gap is filled with the second oxide liner.

9. The method for preparing a memory element according to claim 7, further comprising: After forming the third nitride spacer and the third native oxide layer, a silicide layer is formed over the lower capacitor contact, wherein the upper capacitor contact material is formed over the silicide layer. 10 . The method for fabricating a memory device as claimed in claim 9 , wherein after performing the oxidation process, the silicide layer is in direct contact with the second oxide liner.

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