Semiconductor device

Abstract

The invention relates to a semiconductor device. Provided is a semiconductor device capable of suppressing a drop in withstand voltage. According to one embodiment, a semiconductor device includes a support having a first surface, first to fourth conductive portions, and a semiconductor layer. The direction from the first surface to the first conductive portion is along the first direction. The second conductive portion is separated from the first conductive portion in the second direction. The semiconductor layer is located between the first conductive portion and the second conductive portion. The semiconductor layer includes an opposing region and a first semiconductor region. The third conductive portion is separated from a portion of the second conductive portion and the opposing region in the third direction. The fourth conductive portion is separated from the first semiconductor region in the third direction. The first semiconductor region includes a first upper end region, a first lower end region, and a first intermediate region. The impurity concentration of the first conductivity type in the first upper end region is higher than the impurity concentration of the first conductivity type in the first intermediate region. The impurity concentration of the first conductivity type in the first lower end region is higher than the impurity concentration of the first conductivity type in the first intermediate region.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device. Background Art

[0002] In semiconductor devices, it is desired to suppress a decrease in breakdown voltage.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2001-274398 Summary of the invention

[0006] An embodiment of the present invention provides a semiconductor device capable of suppressing a decrease in breakdown voltage.

[0007] According to an embodiment of the present invention, a semiconductor device includes a support having a first surface, a first conductive portion, a second conductive portion, a semiconductor layer, a third conductive portion, and a fourth conductive portion. The direction from the first surface toward the first conductive portion is along a first direction perpendicular to the first surface. The second conductive portion is separated from the first conductive portion in a second direction along the first surface. The semiconductor layer is located between the first conductive portion and the second conductive portion. The semiconductor layer has a first end surface and a second end surface located between the first end surface and the support. The semiconductor layer includes an opposing region and a first semiconductor region of a first conductivity type. The opposing region is located between the second conductive portion and the first semiconductor region and is opposed to a portion of the second conductive portion. The third conductive portion is away from a portion of the second conductive portion and the opposing region in a third direction intersecting the second direction and along the first surface. The fourth conductive portion is separated from the first semiconductor region in the third direction. The first semiconductor region includes a first upper region including a portion of the first end face, a first lower region including a portion of the second end face, and a first intermediate region located between the first upper region and the first lower region. The concentration of the first conductivity type impurity in the first upper region is higher than the concentration of the first conductivity type impurity in the first intermediate region. The concentration of the first conductivity type impurity in the first lower region is higher than the concentration of the first conductivity type impurity in the first intermediate region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic perspective view of a semiconductor device according to an exemplary embodiment.

[0009] Figure 2 is a schematic top view of a semiconductor device according to an exemplary embodiment.

[0010] Figure 3 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0011] Figure 4 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0012] Figure 5 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0013] Figure 6 It is a schematic diagram showing the impurity concentration in the semiconductor device according to the embodiment.

[0014] Figure 7 is a schematic perspective view of a semiconductor device according to an exemplary embodiment.

[0015] Figure 8 is a schematic top view of a semiconductor device according to an exemplary embodiment.

[0016] Fig. 9 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0017] Fig.10 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0018] Fig.11 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0019] Fig.12 (a) and Fig.12 (b) is a schematic top view of a semiconductor device according to an exemplary embodiment.

[0020] (Explanation of symbols)

[0021] 10: support body; 10a: first surface; 11: first semiconductor region; 21: first insulating layer; 22: second insulating layer; 22a: upper surface; 30: semiconductor layer; 30t: first end surface; 30u: second end surface; 31: first semiconductor region; 31c: first intermediate region; 31f: upper surface; 31g: lower surface; 31t: first upper region; 31u: first lower region; 32: second semiconductor region; 32c: second intermediate region; 32t: second upper region; 32u: second lower region; 33: third semiconductor region; 33c: third intermediate region; 33t: third upper region; 33u: third lower region; 36: source region; 37: drain region; 38: opposing region; 38a: first portion; 38b: second portion 38c: middle opposing region; 38t: upper opposing region; 38u: lower opposing region; 51: first conductive portion; 52: second conductive portion; 52a, 52b: a portion; 53: third conductive portion; 53f: upper end; 53g: lower end; 54: fourth conductive portion; 54L: wiring; 54f: upper end; 54g: lower end; 61: first conductive layer; 62: second conductive layer; 70: insulating portion; 70f: upper end; 70g: lower end; 71: first insulating region; 72: second insulating region; 73, 74: insulating region; 100~104: semiconductor device; C1, C2: capacitor; C31t, C31u: maximum concentration; Cn1: concentration; F1: opposing surface; S1, S2: substrate; T1, T2, T3: thickness; pZ: position. DETAILED DESCRIPTION

[0022] Hereinafter, various embodiments of the present invention will be described with reference to the drawings.

[0023] The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc. are not necessarily the same as the actual ones. Even when showing the same part, the size and ratio may be different from each other depending on the drawings.

[0024] In the present specification and each drawing, regarding the drawings already shown, the same reference numerals are attached to the same elements as those described above, and the detailed description is appropriately omitted.

[0025] Figure 1 is a schematic perspective view of a semiconductor device according to an exemplary embodiment.

[0026] Figure 2 is a schematic top view of a semiconductor device according to an exemplary embodiment. Figure 2 Indicates observation from above Figure 1 situation.

[0027] Figure 3 and Figure 4is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0028] Figure 3 express Figure 2 The cross section along the line A1-A2 is shown. Figure 4 express Figure 2 The cross section at line A3-A4 is shown.

[0029] like Figure 1 As shown, the semiconductor device 100 of the embodiment includes a support body 10, a semiconductor layer 30, a first conductive portion 51, a second conductive portion 52, a third conductive portion 53, and a fourth conductive portion 54. The semiconductor device 100 further includes an insulating portion 70, a first conductive layer 61, a first insulating layer 21 (see Figure 3 ) and the second insulating layer 22. In addition, Figure 1 and Figure 2 In the figure, for convenience of explanation, the first insulating layer 21 is omitted.

[0030] like Figure 1 As shown, the support body 10 has a first surface 10a. The element portion including the semiconductor layer 30, the first to fourth conductive portions (51 to 54), the first conductive layer 61, the first insulating layer 21 and the second insulating layer 22 is provided on the first surface 10a and supported by the support body 10. The support body 10 is, for example, a substrate.

[0031] In the description of the embodiment, the direction perpendicular to the first surface 10a is set as the Z direction (first direction). A direction along the first surface 10a is set as the X direction. The direction along the first surface 10a and intersecting the X direction is set as the Y direction. The X direction (third direction) and the Y direction (second direction) can be directions perpendicular to the Z direction, respectively. The X direction (third direction) and the Y direction (second direction) can be directions orthogonal to each other. Sometimes the direction perpendicular to the first surface 10a and from the support 10 toward the semiconductor layer 30 is referred to as "up", and the opposite direction is referred to as "down". "Up" and "down" are based on the relative positional relationship between the support 10 and the semiconductor layer 30, and have nothing to do with the direction of gravity.

[0032] The first conductive portion 51, the second conductive portion 52, and the semiconductor layer 30 are provided above the first surface 10a. That is, the direction from the first surface 10a toward the first conductive portion 51, the direction from the first surface 10a toward the second conductive portion 52, and the direction from the first surface 10a toward the semiconductor layer 30 are along the Z direction.

[0033] The second conductive portion 52 is separated from the first conductive portion 51 in the Y direction. That is, the direction from the first conductive portion 51 toward the second conductive portion 52 is along the Y direction.

[0034] The semiconductor layer 30 is located between the first conductive portion 51 and the second conductive portion 52. That is, the first conductive portion 51, the semiconductor layer 30 and the second conductive portion 52 are arranged in parallel in the Y direction. The semiconductor layer 30 is in contact with the first conductive portion 51 and the second conductive portion 52, respectively, and is electrically connected to the first conductive portion 51 and the second conductive portion 52, respectively. The semiconductor layer 30 has a first end face 30t (upper surface) and a second end face 30u (lower surface). The second end face 30u is located between the first end face 30t and the support body 10.

[0035] For example, Figure 2 As shown, the semiconductor layer 30 includes an opposing region 38 that is opposed to a portion 52a of the second conductive portion 52. The opposing region 38 includes an opposing surface F1 that is opposed to a portion 52a of the second conductive portion 52. In this example, the opposing region 38 is of the first conductivity type (n-type), and the opposing region 38 makes Schottky contact with the second conductive portion 52 (portion 52a). For example, the opposing surface F1 forms a Schottky junction with the portion 52a of the second conductive portion 52.

[0036] Furthermore, if Figure 2 As shown, the semiconductor layer 30 includes a first semiconductor region 31, a second semiconductor region 32, and a third semiconductor region 33. The first semiconductor region 31, the second semiconductor region 32, and the third semiconductor region 33 are each of the first conductivity type.

[0037] The first semiconductor region 31 is located between the first conductive portion 51 and the second conductive portion 52. The opposing region 38 is located between the first semiconductor region 31 and the second conductive portion 52 (a portion 52a). The direction from the first semiconductor region 31 to the opposing region 38 is along the Y direction. The first semiconductor region 31 and the opposing region 38 are continuous.

[0038] The second semiconductor region 32 is located between the first conductive portion 51 and the fourth conductive portion 54 in the Y direction. The second semiconductor region 32 is electrically connected to the first conductive portion 51. A portion of the insulating portion 70 (insulating region 73) is provided between the second semiconductor region 32 and the fourth conductive portion 54. The second semiconductor region 32 is away from the third conductive portion 53 and the fourth conductive portion 54 in the Y direction. The direction from the second semiconductor region 32 toward the fourth conductive portion 54 (or the insulating region 73) is along the Y direction.

[0039] The third semiconductor region 33 is located between the first conductive portion 51 and the first semiconductor region 31 in the Y direction. The third semiconductor region 33 is electrically connected to the first conductive portion 51. The third semiconductor region 33 is juxtaposed with the first semiconductor region 31 in the Y direction and is juxtaposed with the second semiconductor region 32 in the X direction. That is, the direction from the third semiconductor region 33 to the first semiconductor region 31 is along the Y direction, and the direction from the third semiconductor region 33 to the second semiconductor region 32 is along the X direction. The third semiconductor region 33 is continuous with the first semiconductor region 31 and the second semiconductor region 32.

[0040] The third conductive portion 53 is away from a part 52a of the second conductive portion 52 and the opposed region 38 in the X direction. The direction from the opposed region 38 (opposed surface F1) to the third conductive portion 53 is along the X direction.

[0041] The fourth conductive portion 54 is away from the first semiconductor region 31 in the X direction. That is, the direction from the first semiconductor region 31 to the fourth conductive portion 54 is along the X direction. For example, the fourth conductive portion 54 is located between the third conductive portion 53 and the first conductive portion 51 in the Y direction.

[0042] For example, an insulating portion 70 is provided in the channel of the semiconductor layer 30, and the third conductive portion 53 and the fourth conductive portion 54 are provided in the insulating portion 70. Through the insulating portion 70, insulation is provided between the third conductive portion 53 and the semiconductor layer 30, between the fourth conductive portion 54 and the semiconductor layer 30, and between the third conductive portion 53 and the fourth conductive portion 54. More specifically, the insulating portion 70 includes a first insulating region 71 provided between the third conductive portion 53 and the opposed region 38 and a second insulating region 72 provided between the fourth conductive portion 54 and the first semiconductor region 31. Further, the insulating portion 70 includes an insulating region 73 provided between the fourth conductive portion 54 and the second semiconductor region 32 and an insulating region 74 provided between the third conductive portion 53 and the fourth conductive portion 54. The first insulating region 71 is in contact with the third conductive portion 53 and the opposed region 38 respectively. The second insulating region 72 is in contact with the fourth conductive portion 54 and the first semiconductor region 31 respectively. The insulating region 73 is in contact with the fourth conductive portion 54 and the second semiconductor region 32 respectively. The insulating region 74 is in contact with the third conductive portion 53 and the fourth conductive portion 54 respectively.

[0043] In the support 10, a silicon substrate can be used, for example.

[0044] The semiconductor layer 30 includes, for example, at least one selected from the group consisting of silicon (Si), nitride semiconductors (such as GaN, etc.), silicon carbide (SiC), and oxide semiconductors (such as GaO). When the first semiconductor region 11 contains silicon, the impurity of the first conductivity type includes, for example, at least one selected from the group consisting of phosphorus, arsenic, and antimony.

[0045] The first conductive portion 51 includes, for example, at least one selected from the group consisting of Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt.

[0046] The second conductive portion 52 includes, for example, at least one selected from the group consisting of Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt. When the opposing region 38 includes silicon, a portion 52a of the second conductive portion 52 may include at least one selected from the group consisting of Ti, W, Mo, Ta, Zr, Al, Sn, V, Re, Os, Ir, Pt, Pd, Rh, Ru, Nb, Sr, and Hf.

[0047] The first conductive layer 61 includes, for example, at least one selected from the group consisting of Al, Cu, Mo, W, Ta, Co, Ru, Ti, and Pt.

[0048] The third conductive portion 53 and the fourth conductive portion 54 include at least one of, for example, polysilicon and metal.

[0049] The first insulating layer 21 and the second insulating layer 22 are, for example, silicon oxide layers (eg, thermal oxide films).

[0050] The insulating portion 70 includes, for example, silicon oxide.

[0051] For example, by controlling the potential of the third conductive portion 53, the current flowing between the first conductive portion 51 and the second conductive portion 52 is controlled. The first conductive portion 51 functions as a drain electrode, for example. The second conductive portion 52 functions as a source electrode, for example. The third conductive portion 53 functions as a gate electrode, for example. The first insulating region 71 functions as a gate insulating film, for example. The semiconductor device 100 is, for example, a MOSFET (metal-oxide-semiconductor field-effect transistor).

[0052] In the semiconductor device 100, a Schottky barrier is formed at the interface between the opposing region 38 and the second conductive portion 52. The thickness of the Schottky barrier (for example, the distance in the Y-axis direction) can be controlled by the potential of the third conductive portion 53. When the Schottky barrier is thick, substantially no current flows. Thus, an off state is obtained. By controlling the potential of the third conductive portion 53, the Schottky barrier becomes thinner, and current (for example, tunnel current) flows. By flowing current, an on state is obtained.

[0053] For example, when the transistor is in the on state, a positive voltage relative to the second conductive portion 52 is applied to the first conductive portion 51, and carriers (electrons) flow from the second conductive portion 52 to the first conductive portion 51 via the opposing region 38, the first semiconductor region 31, the third semiconductor region 33 (and the second semiconductor region 32).

[0054] In this example, the third conductive portion 53 only needs to be opposed to the interface (e.g., the opposing surface F1) between the opposing region 38 and the second conductive portion 52. Therefore, compared to the transistor of the reference example in which, for example, the gate electrode is opposed to the npn structure, the gate length is short. As a result, the total gate charge (Qg) is small. The gate capacitance is small. As a result, high-speed switching is obtained. The loss is small. For example, the gate capacitance (Cg) and the capacitance between the gate and the drain (Cgd) become smaller. As a result, the total gate charge (Qg) and the charge between the gate and the drain (Qgd) are reduced. As a result, the loss of the gate driver can be reduced. For example, the switching speed can be increased. For example, the turn-on loss and the turn-off loss can be suppressed.

[0055] In addition, for example, a region including the facing region 38 and the second conductive portion 52 (region including the Schottky contact) becomes a body diode. Since the body diode is a Schottky barrier diode, it is possible to speed up recovery.

[0056] For example, the fourth conductive portion 54 is electrically connected to the second conductive portion 52. Alternatively, the fourth conductive portion 54 may be electrically connected to the second conductive portion 52. For example, the semiconductor device 100 may also include a wiring 54L that electrically connects the fourth conductive portion 54 to the second conductive portion 52. The fourth conductive portion 54 may be electrically connected to the second conductive portion 52 via wiring or terminals outside the semiconductor device 100.

[0057] The potential of the fourth conductive portion 54 is set to the potential of the second conductive portion 52 (for example, the source potential). By providing the fourth conductive portion 54, the electric field in the semiconductor layer 30 can be controlled. For example, local electric field concentration can be suppressed. For example, high reliability can be easily obtained. The fourth conductive portion 54 functions as a field plate, for example.

[0058] In one example, the semiconductor device 100 can be configured by Figure 1 The two substrates shown (substrate S1 and substrate S2) are bonded together. Substrate S1 is a substrate in which a first conductive layer 61 and a second insulating layer 22 are stacked on a support body 10. Substrate S2 is a substrate in which an insulating portion 70 and first to fourth conductive portions (51 to 54) are formed at the semiconductor layer 30. Substrate S1 and substrate S2 are stacked in a manner that the upper surface of substrate S1 (upper surface 22a of the second insulating layer 22) and the lower surface of substrate S2 (second end face 30u) face each other. The Z direction can be a direction perpendicular to the upper surface of substrate S1.

[0059] like Figure 3 As shown in FIG. 1 , the first conductive portion 51 extends along the Z direction on the first conductive layer 61. The second conductive portion 52 extends along the Z direction on the upper surface 22a of the second insulating layer 22. Figure 4 As shown, on the upper surface 22a of the second insulating layer 22, the third conductive portion 53 extends along the Z direction. With such a structure, transistors can be arranged at a high density on the support body 10 (such as a substrate). The groove area per unit area can be increased. Thus, for example, the on-resistance can be reduced. Large currents can be switched.

[0060] In the embodiment, high-concentration impurity layers (high-concentration n-type layers in this example) having a high concentration of first conductivity type impurities are provided on the upper and lower surfaces of the semiconductor layer 30. More specifically, the following is described.

[0061] like Figure 3 As shown, the first semiconductor region 31 includes a first lower end region 31u, a first intermediate region 31c, and a first upper end region 31t. The upper surface of the first upper end region 31t is a portion of the first end face 30t (upper surface) of the semiconductor layer 30. The lower surface of the first lower end region 31u is a portion of the second end face 30u (lower surface) of the semiconductor layer 30. The first intermediate region 31c is a region between the first upper end region 31t and the first lower end region 31u. The first intermediate region 31c is a region from the first upper end region 31t to the first lower end region 31u in the Z direction. The concentration (atoms / cm 3 ) is greater than the concentration (atoms / cm 3 The concentration of the first conductivity type impurity in the first lower end region 31u (atoms / cm 3 ) is higher than the concentration of the first conductivity type impurities in the first intermediate region 31c.

[0062] like Figure 3 As shown, the third semiconductor region 33 includes a third lower region 33u, a third intermediate region 33c and a third upper region 33t. The upper surface of the third upper region 33t is a part of the first end face 30t (upper surface) of the semiconductor layer 30. The lower surface of the third lower region 33u is a part of the second end face 30u (lower surface) of the semiconductor layer 30. The third intermediate region 33c is a region between the third upper region 33t and the third lower region 33u. The third intermediate region 33c is a region from the third upper region 33t to the third lower region 33u in the Z direction. The concentration of the first conductive type impurity in the third upper region 33t (atoms / cm 3) is greater than the concentration (atoms / cm 3 The concentration of the first conductivity type impurity in the third lower end region 33u (atoms / cm 3 ) is higher than the concentration of the first conductivity type impurities in the third intermediate region 33c.

[0063] like Figure 4 As shown, the second semiconductor region 32 includes a second lower end region 32u, a second intermediate region 32c, and a second upper end region 32t. The upper surface of the second upper end region 32t is a portion of the first end face 30t (upper surface) of the semiconductor layer 30. The lower surface of the second lower end region 32u is a portion of the second end face 30u (lower surface) of the semiconductor layer 30. The second intermediate region 32c is a region between the second upper end region 32t and the second lower end region 32u. The second intermediate region 32c is a region from the second upper end region 32t to the second lower end region 32u in the Z direction. The concentration (atoms / cm 3 ) is greater than the concentration (atoms / cm 3 The concentration of the first conductivity type impurity in the second lower end region 32u (atoms / cm 3 ) is higher than the concentration of the first conductivity type impurities in the second intermediate region 32c.

[0064] The first upper region 31t, the second upper region 32t, and the third upper region 33t are continuous and provided as one high-concentration impurity layer. The concentration of the first conductive type impurity in the high-concentration impurity layer is higher than the concentration of the first conductive type impurity in the first intermediate region 31c. The concentration of the first conductive type impurity in the first upper region 31t may be substantially the same as the concentration of the first conductive type impurity in the second upper region 32t, or substantially the same as the concentration of the first conductive type impurity in the third upper region 33t. The thickness (length along the Z direction) of the first upper region 31t may be substantially the same as the thickness of the second upper region 32t, or substantially the same as the thickness of the third upper region 33t.

[0065] Similarly, the first lower end region 31u, the second lower end region 32u, and the third lower end region 33u are continuous and provided as one high-concentration impurity layer. The concentration of the first conductive type impurity in the first lower end region 31u may be substantially the same as the concentration of the first conductive type impurity in the second lower end region 32u, or substantially the same as the concentration of the first conductive type impurity in the third lower end region 33u. The thickness of the first lower end region 31u may be substantially the same as the thickness of the second lower end region 32u, or substantially the same as the thickness of the third lower end region 33u.

[0066] The first intermediate region 31c, the second intermediate region 32c, and the third intermediate region 33c are continuous and provided as one low-concentration impurity layer. The concentration of the first conductive type impurity in the first intermediate region 31c may be substantially the same as the concentration of the first conductive type impurity in the second intermediate region 32c, or substantially the same as the concentration of the first conductive type impurity in the third intermediate region 33c. The thickness of the first intermediate region 31c may be substantially the same as the thickness of the second intermediate region 32c, or substantially the same as the thickness of the third intermediate region 33c.

[0067] As described above, in this example, the opposing region 38 is of the first conductivity type. Figure 3 As shown, the opposing region 38 includes, for example, a lower opposing region 38u, an intermediate opposing region 38c, and an upper opposing region 38t. The upper opposing region 38t includes a portion of the first end face 30t (upper surface) of the semiconductor layer 30. The first end face 30t is formed by the upper opposing region 38t, the first upper end region 31t, the second upper end region 32t, and the third upper end region 33t. The lower opposing region 38u includes a portion of the second end face 30u (lower surface) of the semiconductor layer 30. The second end face 30u is formed by the lower opposing region 38u, the first lower end region 31u, the second lower end region 32u, and the third lower end region 33u. The intermediate opposing region 38c is between the upper opposing region 38t and the lower opposing region 38u.

[0068] For example, the concentration (atoms / cm2) of the first conductivity type impurity in the upper opposing region 38t is 3 ) may be greater than the concentration (atoms / cm 3 The upper opposing region 38t may be a part of the high concentration impurity layer including the first upper end region 31t. That is, the high concentration impurity layer may be formed on the entire upper end side of the semiconductor layer 30.

[0069] Without limitation to this, the concentration of the first conductivity type impurity in the upper opposing region 38t may be equal to the concentration of the first conductivity type impurity in the middle opposing region 38c. That is, at the upper end side of the semiconductor layer 30, the high concentration impurity layer may be formed on the entire semiconductor layer 30 except for the opposing region 38.

[0070] The concentration of the first conductivity type impurity in the lower opposing region 38u (atoms / cm 3 ) may be greater than the concentration (atoms / cm 3The lower opposing region 38u may be a part of the high concentration impurity layer including the first lower end region 31u. That is, the high concentration impurity layer may be formed on the entire lower end side of the semiconductor layer 30.

[0071] Without limitation to this, the concentration of the first conductivity type impurity in the lower opposing region 38u may be equal to the concentration of the first conductivity type impurity in the middle opposing region 38c. That is, at the lower end side of the semiconductor layer 30, the high concentration impurity layer may be formed on the entire semiconductor layer 30 except for the opposing region 38. When the high concentration impurity layer is formed except for the opposing region 38, for example, the influence of the high concentration impurity layer on the threshold voltage of the transistor can be suppressed.

[0072] Figure 5 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0073] Figure 5 Corresponds to Figure 2 A portion of the cross section taken along line A5-A6 is shown.

[0074] For example, if the impurity concentration of the first conductive type in the entire semiconductor layer 30 is increased, the on-resistance is reduced, but the withstand voltage may be reduced. Here, in the structure with the field plate, for example, the charge balance in the semiconductor layer 30 is achieved so that the electric field concentration can be easily suppressed. According to the impurity concentration of the semiconductor layer 30 (for example, the first semiconductor region 31), the extension of the depletion layer changes and the electric field distribution is adjusted. For example, the electric field concentration is suppressed by balancing the impurity concentration and the electric field.

[0075] On the other hand, for example Figure 5 As shown, a capacitor C1 is formed between the upper end 54f (upper surface) of the fourth conductive portion 54 and the upper surface 31f (a portion of the first end surface 30t) of the first semiconductor region 31. Therefore, the upper end side of the first semiconductor region 31 is easily depleted, and sometimes the charge balance collapses. There is a possibility of electric field concentration and a decrease in withstand voltage. Similarly, a capacitor C2 is formed between the lower end 54g (lower surface) of the fourth conductive portion 54 and the lower surface 31g (a portion of the second end surface 30u) of the first semiconductor region 31. Therefore, the lower end side of the first semiconductor region 31 is easily depleted, and sometimes the charge balance collapses. There is a possibility of electric field concentration and a decrease in withstand voltage.

[0076] In contrast, in the embodiment, as described above, the concentration of the impurity of the first conductivity type in the first upper region 31t is higher than the concentration of the impurity of the first conductivity type in the first middle region 31c. The concentration of the impurity of the first conductivity type in the first lower region 31u is higher than the concentration of the impurity of the first conductivity type in the first middle region 31c. Thus, depletion in the first upper region 31t and the first lower region 31u can be suppressed. A decrease in withstand voltage can be suppressed. In addition, for example, since the concentration of the impurity of the first conductivity type is high, the on-resistance can be reduced. According to the embodiment, for example, the on-resistance can be reduced without impairing the withstand voltage.

[0077] In addition, for example, as described above, the concentration of the first conductivity type impurity in the second upper region 32t may be higher than the concentration of the first conductivity type impurity in the second intermediate region 32c, and the concentration of the first conductivity type impurity in the second lower region 32u may be higher than the concentration of the first conductivity type impurity in the second intermediate region 32c. The concentration of the first conductivity type impurity in the third upper region 33t may be higher than the concentration of the first conductivity type impurity in the third intermediate region 33c, and the concentration of the first conductivity type impurity in the third lower region 33u may be higher than the concentration of the first conductivity type impurity in the third intermediate region 33c. Thus, the decrease in the withstand voltage can be further suppressed.

[0078] like Figure 5 As shown, the semiconductor layer 30 (the first upper region 31t and the first lower region 31u) is located between the first insulating layer 21 and the second insulating layer 22. The first upper region 31t is located between the first lower region 31u and the first insulating layer 21.

[0079] For example, the first insulating layer 21 is in contact with the first end surface 30t of the semiconductor layer 30. The first insulating layer 21 is in contact with the upper surface 31f of the first semiconductor region 31 (and the upper surface of the second semiconductor region 32 and the upper surface of the third semiconductor region 33). In addition, the first insulating layer 21 is in contact with the upper end 54f of the fourth conductive portion 54 (one end of the fourth conductive portion 54 in the Z direction). In addition, as Figure 4 As shown, the first insulating layer 21 is in contact with the upper end 53f (upper surface) of the third conductive portion 53 and the upper end 70f (upper surface) of the insulating portion 70. The first end surface 30t, the upper end 54f, the upper end 53f and the upper end 70f may be on the same plane.

[0080] like Figure 5As shown, the second insulating layer 22 is in contact with the second end surface 30u of the semiconductor layer 30. The second insulating layer 22 is in contact with the lower surface 31g of the first semiconductor region 31 (and the lower surface of the second semiconductor region 32 and the lower surface of the third semiconductor region 33). The second insulating layer 22 is in contact with the lower end 54g of the fourth conductive portion 54 (the other end of the fourth conductive portion 54 in the Z direction). In addition, as shown in FIG. Figure 4 As shown, the second insulating layer 22 is in contact with the lower end 53g (lower surface) of the third conductive portion 53 and the lower end 70g (lower surface) of the insulating portion 70. The second end surface 30u, the lower end 54g, the lower end 53g and the lower end 70g may be on the same plane.

[0081] For example, the thickness (length along the Z direction) of the first insulating layer 21 is greater than or equal to 250 nanometers (nm) and less than or equal to 1250 nm. For example, the thickness (length along the Z direction) of the second insulating layer 22 is greater than or equal to 250 nm and less than or equal to 1250 nm.

[0082] The upper end side of the semiconductor layer 30 may be easily depleted due to the first insulating layer 21. The lower end side of the semiconductor layer 30 may be easily depleted due to the second insulating layer 22. Even in such a case, by providing a high-concentration impurity layer on the upper end side and the lower end side of the semiconductor layer 30, it is easy to suppress the depletion of the upper end side and the lower end side of the semiconductor layer 30. Thus, for example, a decrease in the withstand voltage can be suppressed.

[0083] The first conductive layer 61 is electrically connected to the first conductive portion 51 (see Figure 3 ). For example, in the on state of the transistor, carriers flow from the second conductive portion 52 to the first conductive layer 61 via the semiconductor layer 30 and the first conductive portion 51 .

[0084] In this example, the first conductive layer 61 is connected to the lower part of the first conductive portion 51. The first conductive layer 61 extends along the XY plane below the semiconductor layer 30 (and the third conductive portion 53, the fourth conductive portion 54, and the insulating portion 70). The second insulating layer 22 is arranged between the first conductive layer 61 and the semiconductor layer 30 (and the third conductive portion 53, the fourth conductive portion 54, and the insulating portion 70). The first conductive layer 61 is in contact with the second insulating layer 22.

[0085] Thus, the first conductive layer 61 is below the semiconductor layer 30 and the second insulating layer 22. That is, the first lower end region 31u is between the first upper end region 31t and the first conductive layer 61. In other words, the second end face 30u is between the first end face 30t and the first conductive layer 61.

[0086] The present invention is not limited thereto, and in the embodiment, the first conductive layer 61 (drain) may be provided above the semiconductor layer 30 and the first insulating layer 21 . That is, the first upper end region 31 t may be between the first lower end region 31 u and the first conductive layer 61 .

[0087] The concentration of the impurity of the first conductivity type in one of the first upper region 31t and the first lower region 31u may be higher than the concentration of the impurity of the first conductivity type in the other of the first upper region 31t and the first lower region 31u. Thus, depletion in the one of the first upper region 31t and the first lower region 31u can be further suppressed. For example, the first conductive layer 61 (drain) is arranged on one side of the other of the first upper region 31t and the first lower region 31u. In other words, the other of the first upper region 31t and the first lower region 31u is between the one of the first upper region 31t and the first lower region 31u and the first conductive layer 61. Here, when the semiconductor device 100 is in operation, a voltage different from that of the second conductive portion 52 is applied to the first conductive portion 51 and the first conductive layer 61. Therefore, the end of the semiconductor layer 30 on the side opposite to the first conductive layer 61 (the one of the first upper end region 31t and the first lower end region 31u) is sometimes more susceptible to depletion than the end of the semiconductor layer 30 on the first conductive layer 61 side (the other of the first upper end region 31t and the first lower end region 31u).

[0088] On the other hand, for example, the concentration of the first conductive type impurity at the end portion of the semiconductor layer 30 on the side opposite to the first conductive layer 61 (the one of the first upper end region 31t and the first lower end region 31u) is higher than the concentration of the first conductive type impurity at the end portion of the semiconductor layer 30 on the side opposite to the first conductive layer 61 (the other of the first upper end region 31t and the first lower end region 31u). Thus, for example, depletion of the end portion of the semiconductor layer 30 on the side opposite to the first conductive layer 61 can be further suppressed. However, in the embodiment, the concentration of the first conductive type impurity at the end portion of the semiconductor layer 30 on the side opposite to the first conductive layer 61 may be higher than the concentration of the first conductive type impurity at the end portion of the semiconductor layer 30 on the side opposite to the first conductive layer 61.

[0089] For example, if the first insulating layer 21 is thick, the upper end side (first upper end region 31t) of the semiconductor layer 30 may be easily depleted. For example, if the second insulating layer 22 is thick, the lower end side (first lower end region 31u) of the semiconductor layer 30 may be easily depleted.

[0090] The thickness of one of the first insulating layer 21 and the second insulating layer 22 may be thinner than the thickness of the other of the first insulating layer 21 and the second insulating layer 22. Thus, for example, on the side of the one of the first insulating layer 21 and the second insulating layer 22, the depletion of the semiconductor layer 30 can be further suppressed. For example, the first conductive layer 61 (drain) is arranged on the side of the other of the first insulating layer 21 and the second insulating layer. In other words, the other of the first insulating layer 21 and the second insulating layer 22 is located between the one of the first insulating layer 21 and the second insulating layer 22 and the first conductive layer 61. Here, as described above, the end of the semiconductor layer 30 on the opposite side to the first conductive layer 61 is sometimes more susceptible to depletion.

[0091] Therefore, for example, the insulating layer on the side opposite to the first conductive layer 61 (the one of the first insulating layer 21 and the second insulating layer 22) may be thinner than the insulating layer on the side of the first conductive layer 61 (the other of the first insulating layer 21 and the second insulating layer 22). Figure 5 In the example of , the thickness of the first insulating layer 21 may be thinner than the thickness of the second insulating layer 22. Thus, for example, depletion of the end of the semiconductor layer 30 on the side opposite to the first conductive layer 61 can be further suppressed. However, in the embodiment, the insulating layer on the first conductive layer 61 side may be thinner than the insulating layer on the side opposite to the first conductive layer 61.

[0092] Figure 6 It is a schematic diagram showing the impurity concentration in the semiconductor device according to the embodiment.

[0093] Figure 6 This is a schematic graph showing an example of the distribution of the concentration of the first conductivity type impurity along the Z direction of the semiconductor layer 30. The vertical axis is the concentration Cn1 of the first conductivity type impurity in the first semiconductor region 31. The horizontal axis is the position pZ in the Z direction.

[0094] The thickness T1 (length along the Z direction) of the first upper end region 31t is, for example, greater than 100nm and less than 1000nm, for example, 500nm. The thickness T2 (length along the Z direction) of the first lower end region 31u is, for example, greater than 100nm and less than 1000nm, for example, 500nm. The thickness T3 of the first intermediate region 31c (that is, the distance along the Z direction between the first upper end region 31t and the first lower end region 31u) is, for example, greater than 3000nm and less than 60000nm. The thickness T1 is thinner than the thickness T3. The thickness T2 is thinner than the thickness T3. Thus, for example, the on-resistance can be reduced without compromising the withstand voltage.

[0095] The first conductivity type impurity concentration of the first upper end region 31t may be different from the first conductivity type impurity concentration of the first lower end region 31u. The concentration distribution of the first conductivity type impurity along the Z direction in the first upper end region 31t has a maximum concentration C31t (e.g., a peak concentration). The concentration distribution of the first conductivity type impurity along the Z direction in the first lower end region 31u has a maximum concentration C31u (e.g., a peak concentration). The maximum concentration C31t may be different from the maximum concentration C31u.

[0096] As described above, in this example, the first conductive layer 61 is disposed below the first lower end region 31u. Then, the first conductive type impurity concentration is higher in the first upper end region 31t than in the first lower end region 31u. For example, in the concentration distribution of the first conductive type impurity along the Z direction, the maximum concentration C31t in the first upper end region 31t is higher than the maximum concentration C31u in the first lower end region 31u.

[0097] Without limitation thereto, the first conductivity type impurity concentration of the first upper region 31t may be equal to or lower than the first conductivity type impurity concentration of the first lower region 31u. For example, the maximum concentration C31t may be lower than the maximum concentration C31u.

[0098] For example, the amount of first conductivity type impurities (total amount of impurities (number of atoms)) contained in the first upper region 31t is greater than the amount of first conductivity type impurities contained in the first intermediate region 31c. 2 ) is greater than the first conductive type impurity amount per unit area of ​​the first intermediate region 31c. In addition, per unit area refers to per unit area on a plane perpendicular to the Z direction. For example, the difference between the first conductive type impurity amount contained in the first upper end region 31t and the first conductive type impurity amount contained in the first intermediate region 31c per unit area on a plane perpendicular to the Z direction is 5×10 10 atoms / cm 2 Above and 1.5×10 11 atoms / cm 2 Since the amount of the first conductivity type impurities in the first upper end region 31 t is large, depletion can be suppressed, and a decrease in the breakdown voltage can be suppressed.

[0099] The same is true for the second semiconductor region 32 and the third semiconductor region 33. That is, for example, the amount of impurities of the first conductivity type contained in the second upper region 32t is greater than the amount of impurities of the first conductivity type contained in the second intermediate region 32c. For example, the amount of impurities of the first conductivity type contained in the third upper region 33t is greater than the amount of impurities of the first conductivity type contained in the third intermediate region 33c.

[0100] In addition, for example, the amount of impurities of the first conductivity type contained in the first lower end region 31u is greater than the amount of impurities of the first conductivity type contained in the first intermediate region 31c. For example, the amount of impurities of the first conductivity type per unit area in the first lower end region 31u (atoms / cm 2 ) is greater than the first conductive type impurity amount per unit area of ​​the first intermediate region 31c. For example, the difference between the first conductive type impurity amount contained in the first lower end region 31u and the first conductive type impurity amount contained in the first intermediate region 31c per unit area on a plane perpendicular to the Z direction is 5×10 10 atoms / cm 2 Above and 1.5×10 11 atoms / cm 2 Since the amount of the first conductivity type impurities in the first lower end region 31 u is large, depletion can be suppressed, and a decrease in the breakdown voltage can be suppressed.

[0101] The same is true for the second semiconductor region 32 and the third semiconductor region 33. That is, for example, the amount of impurities of the first conductivity type contained in the second lower end region 32u is greater than the amount of impurities of the first conductivity type contained in the second intermediate region 32c. For example, the amount of impurities of the first conductivity type contained in the third lower end region 33u is greater than the amount of impurities of the first conductivity type contained in the third intermediate region 33c.

[0102] The concentration of the first conductivity type impurity in the first upper region 31 t is, for example, 1.3×10 16 atoms / cm 3 Above and 6.5×10 16 atoms / cm 3 The concentration of the first conductivity type impurity in the first lower end region 31u is, for example, 1.3×10 16 atoms / cm 3 Above and 6.5×10 16 atoms / cm 3 The concentration of the first conductivity type impurity in the first intermediate region 31 c is, for example, 1×10 16 atoms / cm 3 Above and 5×10 16atoms / cm 3 the following.

[0103] Figure 7 is a schematic perspective view of a semiconductor device according to an exemplary embodiment.

[0104] Figure 8 is a schematic top view of a semiconductor device according to an exemplary embodiment. Figure 8 Indicates observation from above Figure 7 situation.

[0105] Fig. 9 and Fig.10 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0106] Fig. 9 express Figure 8 The cross section at line B1-B2 is shown. Fig.10 express Figure 8 The cross section at line B3-B4 is shown.

[0107] exist Figure 7 to Figure 10 In the semiconductor device 101 shown in FIG. 1 , the opposing region 38 of the semiconductor layer 30 is of the second conductivity type (p-type). Figure 8 As shown, a portion 52 a of the second conductive portion 52 is shaped to protrude from a portion 52 b of the second conductive portion 52 toward the first conductive portion 51 .

[0108] The opposing region 38 includes a first portion 38a and a second portion 38b. The first portion 38a is located between a portion 52a of the second conductive portion 52 and the third conductive portion 53 in the X direction. The second portion 38b is located between the first portion 38a and the first semiconductor region 31 and between a portion 52a of the second conductive portion 52 and the first semiconductor region 31 in the Y direction. The first portion 38a and the second portion 38b are in contact with a portion 52a of the second conductive portion 52. A first insulating region 71 is disposed between the first portion 38a and the third conductive portion 53 and between the second portion 38b and the third conductive portion 53.

[0109] The second portion 38b of the opposing region 38 forms a pn junction with the first semiconductor region 31. The direction from the pn junction to the third conductive portion 53 is along the Y direction. As the second conductivity type impurity, boron can be used, for example.

[0110] Regarding the structure of the semiconductor device 101 other than the above, the same description as that of the structure of the semiconductor device 100 can be applied.

[0111] The semiconductor device 101 is, for example, a pn-type transistor. The height of the potential barrier formed between the opposing region 38 and the first semiconductor region 31 can be controlled by the potential of the third conductive portion 53. By controlling the potential of the third conductive portion 53, an off state in which substantially no current flows between the first conductive portion 51 and the second conductive portion 52 is obtained. By controlling the potential of the third conductive portion 53, an on state in which carriers flow from the second conductive portion 52 to the first conductive portion 51 via the semiconductor layer 30 is obtained. In the case where the opposing region 38 is of the second conductivity type, for example, the influence of the high-concentration impurity layer (the first upper end region 31t, the first lower end region 31u) on the threshold voltage of the transistor can be suppressed.

[0112] In the semiconductor device 101, a decrease in the breakdown voltage can be suppressed as in the semiconductor device 100. For example, the on-resistance can be reduced without impairing the breakdown voltage.

[0113] Fig.11 is a schematic cross-sectional view of a semiconductor device according to an exemplary embodiment.

[0114] Fig.11 The semiconductor device 102 of the embodiment shown in FIG. 1 includes a second conductive layer 62. With regard to the other details, the same description as that of the semiconductor device 100 can be applied to the structure of the semiconductor device 102. Figure 3 Similarly, the cross section of the semiconductor device 100 shown in FIG. Fig.11 A cross section of the semiconductor device 102 is shown.

[0115] The second conductive layer 62 is electrically connected to the second conductive portion 52. For example, when the transistor is in an on state, carriers flow from the second conductive layer 62 to the first conductive layer 61 via the second conductive portion 52, the semiconductor layer 30, and the first conductive portion 51.

[0116] The second conductive layer 62 is arranged on the side of the semiconductor layer 30 opposite to the first conductive layer 61. That is, the semiconductor layer 30 is located between the first conductive layer 61 and the second conductive layer 62. In this example, the second conductive layer 62 is located above the semiconductor layer 30, and the first conductive layer 61 is located below the semiconductor layer 30. That is, the first upper end region 31t is between the second conductive layer 62 and the first lower end region 31u. Similarly, the second upper end region 32t is between the second conductive layer 62 and the second lower end region 32u, and the third upper end region 33t is between the second conductive layer 62 and the third lower end region 33u. The second conductive layer 62 may also be located above the first insulating layer 21 and in contact with the first insulating layer 21.

[0117] In the semiconductor device 102, it is also possible to suppress a decrease in the breakdown voltage, similarly to the semiconductor device 100. For example, the on-resistance can be reduced without impairing the breakdown voltage.

[0118] For example, in the semiconductor device 102, the first conductivity type impurity concentration in the first upper region 31t may be higher than the first conductivity type impurity concentration in the first lower region 31u. For example, in the semiconductor device 102, the first insulating layer 21 may be thinner than the second insulating layer 22. Thus, for example, depletion of the source side (the side opposite to the drain) of the semiconductor layer 30 can be suppressed.

[0119] Fig.12 (a) and Fig.12 (b) is a schematic top view of a semiconductor device according to an exemplary embodiment.

[0120] exist Fig.12 In the semiconductor device 103 of the embodiment shown in (a), the source region 36 and the drain region 37 are provided in the semiconductor layer 30. The part 52a of the second conductive portion 52 is a shape protruding from the part 52b of the second conductive portion 52 toward the first conductive portion 51. Regarding the other contents, the same description as the structure of the semiconductor device 100 can be applied to the structure of the semiconductor device 103. Figure 2 Similarly, the top view of the semiconductor device 100 shown in FIG. Fig.12 (a) is a top view of the semiconductor device 103 .

[0121] In the semiconductor device 103 , the facing region 38 is of the first conductivity type and includes a first portion 38 a and a second portion 38 b . The first portion 38 a and the second portion 38 b make Schottky contact with a portion 52 a of the second conductive portion 52 .

[0122] The source region 36 is located between the second conductive portion 52 (a portion 52b) and the opposing region 38 in the Y direction. The source region 36 is located between the second conductive portion 52 (a portion 52a) and the third conductive portion 53 in the X direction. The source region 36 is of the first conductivity type. In the semiconductor device 103, the impurity concentration of the first conductivity type in the source region 36 is higher than the impurity concentration of the first conductivity type in the opposing region 38. By providing the source region 36, a good electrical connection is obtained between the second conductive portion 52 and the semiconductor layer 30. For example, the on-resistance can be reduced.

[0123] The drain region 37 is provided between the second semiconductor region 32 and the first conductive portion 51 and between the third semiconductor region 33 and the first conductive portion 51. The drain region 37 is of the first conductive type. The impurity concentration of the first conductive type in the drain region 37 is higher than the impurity concentration of the first conductive type in the first semiconductor region 31 (for example, the first intermediate region 31c or the first upper region 31t). By providing the drain region 37, a good electrical connection is obtained between the first conductive portion 51 and the semiconductor layer 30.

[0124] exist Fig.12 In the semiconductor device 104 of the embodiment shown in (b), the source region 36 and the drain region 37 are also provided in the semiconductor layer 30. With regard to the other contents, the same description as that of the semiconductor device 101 can be applied to the structure of the semiconductor device 104. Figure 8 Similarly, the top view of the semiconductor device 101 shown in FIG. Fig.12 (b) is a plan view of the semiconductor device 104. The semiconductor device 104 is, for example, an npn-type transistor.

[0125] As described above, in each semiconductor device according to the embodiment, at least one of the source region 36 and the drain region 37 may be provided as appropriate.

[0126] The implementation may also include the following structures (for example, technical solutions).

[0127] (Structure 1)

[0128] A semiconductor device comprising:

[0129] A support having a first surface;

[0130] a first conductive portion, wherein a direction from the first surface toward the first conductive portion is along a first direction perpendicular to the first surface;

[0131] a second conductive portion, which is spaced apart from the first conductive portion in a second direction along the first surface;

[0132] a semiconductor layer located between the first conductive portion and the second conductive portion, having a first end face and a second end face located between the first end face and the support body, wherein the semiconductor layer comprises an opposing region and a first semiconductor region of a first conductivity type, the opposing region being located between the second conductive portion and the first semiconductor region and opposing a portion of the second conductive portion;

[0133] a third conductive portion that is spaced apart from a portion of the second conductive portion and the opposing region in a third direction that intersects the second direction and is along the first surface; and

[0134] a fourth conductive portion being away from the first semiconductor region in the third direction,

[0135] The first semiconductor region includes a first upper region including a portion of the first end face, a first lower region including a portion of the second end face, and a first intermediate region located between the first upper region and the first lower region.

[0136] The concentration of the first conductivity type impurity in the first upper region is higher than the concentration of the first conductivity type impurity in the first middle region.

[0137] The concentration of the first conductivity type impurity in the first lower end region is higher than the concentration of the first conductivity type impurity in the first intermediate region.

[0138] (Structure 2)

[0139] The semiconductor device according to Structure 1, wherein:

[0140] The facing region is of the first conductivity type and is in Schottky contact with a portion of the second conductive portion.

[0141] (Structure 3)

[0142] The semiconductor device according to Structure 1, wherein:

[0143] The opposing region is of the second conductivity type.

[0144] (Structure 4)

[0145] The semiconductor device according to any one of Structures 1 to 3, further comprising:

[0146] a first insulating layer in contact with the first end surface; and

[0147] The second insulating layer is in contact with the second end surface.

[0148] (Structure 5)

[0149] The semiconductor device according to Structure 4, wherein:

[0150] The first insulating layer is in contact with one end of the fourth conductive portion in the first direction.

[0151] The second insulating layer is in contact with the other end of the fourth conductive portion in the first direction.

[0152] (Structure 6)

[0153] The semiconductor device according to Structure 4 or 5, wherein:

[0154] The thickness of the first insulating layer is greater than or equal to 250 nm and less than or equal to 1250 nm.

[0155] The second insulating layer has a thickness of not less than 250 nm and not more than 1250 nm.

[0156] (Structure 7)

[0157] The semiconductor device according to any one of Structures 1 to 6, wherein:

[0158] further comprising a first conductive layer electrically connected to the first conductive portion,

[0159] One of the first upper end region and the first lower end region is located between the other of the first upper end region and the first lower end region and the first conductive layer,

[0160] The concentration of the first conductivity type impurity in the other of the first upper region and the first lower region is higher than the concentration of the first conductivity type impurity in the one of the first upper region and the first lower region.

[0161] (Structure 8)

[0162] The semiconductor device according to Structure 7, wherein:

[0163] further comprising a first conductive layer electrically connected to the first conductive portion,

[0164] The other of the first upper end region and the first lower end region is located between the one of the first upper end region and the first lower end region and the first conductive layer.

[0165] (Structure 9)

[0166] The semiconductor device according to any one of Structures 4 to 6, wherein:

[0167] further comprising a first conductive layer electrically connected to the first conductive portion,

[0168] The first lower end region is located between the first insulating layer and the second insulating layer,

[0169] The first upper end region is located between the first lower end region and the first insulating layer,

[0170] One of the first insulating layer and the second insulating layer is located between the other of the first insulating layer and the second insulating layer and the first conductive layer,

[0171] The thickness of the other of the first insulating layer and the second insulating layer is thinner than the thickness of the one of the first insulating layer and the second insulating layer.

[0172] (Structure 10)

[0173] The semiconductor device according to Structure 9, wherein:

[0174] further comprising a first conductive layer electrically connected to the first conductive portion,

[0175] The other of the first insulating layer and the second insulating layer is located between the one of the first insulating layer and the second insulating layer and the first conductive layer.

[0176] (Structure 11)

[0177] The semiconductor device according to structure 8 or 10, wherein:

[0178] The second end surface is located between the first end surface and the first conductive layer.

[0179] (Structure 12)

[0180] The semiconductor device according to structure 8, 10 or 11, wherein:

[0181] further comprising a second conductive layer electrically connected to the second conductive portion,

[0182] The semiconductor layer is located between the first conductive layer and the second conductive layer.

[0183] (Structure 13)

[0184] The semiconductor device according to any one of Structures 1 to 12, wherein:

[0185] The semiconductor layer includes a second semiconductor region of the first conductivity type that is away from the fourth conductive portion in the second direction and located between the fourth conductive portion and the first conductive portion.

[0186] The second semiconductor region includes a second upper region including a portion of the first end face, a second lower region including a portion of the second end face, and a second intermediate region located between the second upper region and the second lower region.

[0187] The concentration of the first conductivity type impurity in the second upper region is higher than the concentration of the first conductivity type impurity in the second middle region.

[0188] The concentration of the first conductivity type impurity in the second lower end region is higher than the concentration of the first conductivity type impurity in the second middle region.

[0189] (Structure 14)

[0190] The semiconductor device according to Structure 13, wherein

[0191] The semiconductor layer includes a third semiconductor region of the first conductivity type located between the first semiconductor region and the first conductive portion in the second direction.

[0192] A direction from the second semiconductor region toward the third semiconductor region is along the third direction,

[0193] The third semiconductor region includes a third upper region including a portion of the first end face, a third lower region including a portion of the second end face, and a third intermediate region located between the third upper region and the third lower region.

[0194] The concentration of the first conductivity type impurity in the third upper region is higher than the concentration of the first conductivity type impurity in the third middle region.

[0195] The concentration of the first conductivity type impurity in the third lower end region is higher than the concentration of the first conductivity type impurity in the third middle region.

[0196] (Structure 15)

[0197] The semiconductor device according to any one of Structures 1 to 14, wherein:

[0198] The fourth conductive portion is electrically connected to the second conductive portion.

[0199] (Structure 16)

[0200] The semiconductor device according to any one of Structures 1 to 15, wherein:

[0201] The thickness of the first upper end region is greater than or equal to 100 nm and less than or equal to 1000 nm.

[0202] The thickness of the first lower end region is greater than or equal to 100 nm and less than or equal to 1000 nm.

[0203] The thickness of the first upper end region is thinner than the thickness of the first middle region,

[0204] The thickness of the first lower end region is thinner than the thickness of the first middle region.

[0205] (Structure 17)

[0206] The semiconductor device according to Structure 16, wherein

[0207] An amount of impurities of the first conductivity type contained in the first upper end region is larger than an amount of impurities of the first conductivity type contained in the first intermediate region.

[0208] (Structure 18)

[0209] The semiconductor device according to Structure 17, wherein

[0210] The difference between the amount of impurities of the first conductivity type contained in the first upper end region and the amount of impurities of the first conductivity type contained in the first intermediate region per unit area on a plane perpendicular to the first direction is 5×10 10 atoms / cm 2 Above and 1.5×10 11 atoms / cm 2 the following.

[0211] (Structure 19)

[0212] The semiconductor device according to any one of Structures 1 to 18, wherein:

[0213] The concentration of the first conductivity type impurity in the first intermediate region is 1×10 16 atoms / cm 3 Above and 5×10 16 atoms / cm 3 the following,

[0214] The concentration of the first conductivity type impurity in the first upper region is 1.3×10 16 atoms / cm 3 Above and 6.5×10 16 atoms / cm 3 the following.

[0215] (Structure 20)

[0216] The semiconductor device according to any one of Structures 1 to 19, wherein:

[0217] The semiconductor device further includes an insulating portion including a first insulating region provided between the third conductive portion and the opposing region and a second insulating region provided between the fourth conductive portion and the first semiconductor region.

[0218] In an embodiment, information related to the shape of the semiconductor region is obtained, for example, by electron microscope observation. Information related to the material and the impurity concentration in the semiconductor region is obtained, for example, by EDX (Energy Dispersive X-ray Spectroscopy) or SIMS (Secondary Ion Mass Spectrometry). Information related to the carrier concentration in the semiconductor region is obtained, for example, by SCM (Scanning Capacitance Microscopy).

[0219] According to the embodiment, it is possible to provide a semiconductor device capable of suppressing a decrease in breakdown voltage.

[0220] In addition, in this specification, "nitride semiconductor" is assumed to be included in B x In y Al z Ga 1－x－y－z In a chemical formula such as N (0≤x≤1, 0≤y≤1, 0≤z≤1, x+y+z≤1), semiconductor substances of all compositions obtained by changing the composition ratios x, y and z within their respective ranges. In addition, substances that further include Group V elements other than N (nitrogen) in the above chemical formula, substances that further include various elements added to control various physical properties such as conductivity type, and substances that further include various elements inadvertently included are also defined as substances included in the "nitride semiconductor".

[0221] In the present specification, the term “electrically connected” includes not only a case of direct contact connection but also a case of connection via other conductive members or the like.

[0222] In the present specification, “perpendicular” and “parallel” do not only mean strictly perpendicular and strictly parallel, but also include concepts such as deviations in the manufacturing process, and any combination of substantially perpendicular and substantially parallel will suffice.

[0223] Above, with reference to specific examples, the embodiments of the present invention have been described. However, the present invention is not limited to these specific examples. For example, as long as those skilled in the art can implement the present invention in the same manner by appropriately selecting from the known range and obtain the same effect, the same effect is included in the scope of the present invention.

[0224] A combination of two or more elements in each specific example within a technically possible range is also included in the scope of the present invention as long as it includes the gist of the present invention.

[0225] Furthermore, any semiconductor devices that can be implemented by a person skilled in the art by appropriately changing the design of the semiconductor devices described above as embodiments of the present invention also belong to the scope of the present invention as long as they include the gist of the present invention.

[0226] Furthermore, it should be understood that within the scope of the concept of the present invention, a person skilled in the art can conceive of various changes and modifications, and these changes and modifications also belong to the scope of the present invention.

[0227] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device, characterized in that: have: A support having a first surface; a first conductive portion, wherein a direction from the first surface toward the first conductive portion is along a first direction perpendicular to the first surface; a second conductive portion, which is spaced apart from the first conductive portion in a second direction along the first surface; a semiconductor layer located between the first conductive portion and the second conductive portion, having a first end face and a second end face located between the first end face and the support body, wherein the semiconductor layer comprises an opposing region and a first semiconductor region of a first conductivity type, the opposing region being located between the second conductive portion and the first semiconductor region and opposing a portion of the second conductive portion; a third conductive portion, which is away from a portion of the second conductive portion and the opposing region in a third direction intersecting the second direction and along the first surface; as well as a fourth conductive portion being away from the first semiconductor region in the third direction, The first semiconductor region includes a first upper region including a portion of the first end face, a first lower region including a portion of the second end face, and a first intermediate region located between the first upper region and the first lower region. The concentration of the first conductivity type impurity in the first upper region is higher than the concentration of the first conductivity type impurity in the first middle region. The concentration of the first conductivity type impurity in the first lower end region is higher than the concentration of the first conductivity type impurity in the first intermediate region.

2. The semiconductor device according to claim 1, wherein: The facing region is of the first conductivity type and is in Schottky contact with a portion of the second conductive portion.

3. The semiconductor device according to claim 1, wherein: The opposing region is of the second conductivity type.

4. The semiconductor device according to any one of claims 1 to 3, wherein: Also available: a first insulating layer in contact with the first end surface; and The second insulating layer is in contact with the second end surface.

5. The semiconductor device according to claim 4, wherein: The first insulating layer is in contact with one end of the fourth conductive portion in the first direction. The second insulating layer is in contact with the other end of the fourth conductive portion in the first direction.

6. The semiconductor device according to claim 4, wherein: The thickness of the first insulating layer is greater than or equal to 250 nm and less than or equal to 1250 nm. The second insulating layer has a thickness of not less than 250 nm and not more than 1250 nm.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that A concentration of a first conductivity type impurity in one of the first upper region and the first lower region is higher than a concentration of a first conductivity type impurity in the other of the first upper region and the first lower region.

8. The semiconductor device according to claim 7, wherein: further comprising a first conductive layer electrically connected to the first conductive portion, The other of the first upper end region and the first lower end region is located between the one of the first upper end region and the first lower end region and the first conductive layer.

9. The semiconductor device according to claim 4, wherein: The first lower end region is located between the first insulating layer and the second insulating layer, The first upper end region is located between the first lower end region and the first insulating layer, One of the first insulating layer and the second insulating layer has a thickness thinner than the other of the first insulating layer and the second insulating layer.

10. The semiconductor device according to claim 9, wherein: further comprising a first conductive layer electrically connected to the first conductive portion, The other of the first insulating layer and the second insulating layer is located between the one of the first insulating layer and the second insulating layer and the first conductive layer.

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