Semiconductor device, power module, power conversion circuit, vehicle and manufacturing method of semiconductor device

Abstract

The invention discloses a semiconductor device, a power module, a power conversion circuit, a vehicle and a preparation method of the semiconductor device, and the semiconductor device comprises a semiconductor body which comprises a well region, a first region, a second region and an isolation region, the first region is located on a first surface, and the well region is located on the side, away from the first surface, of the first region; the second region is located on the first surface and extends into the semiconductor body from the first surface; the isolation region is arranged between the second region and the first region; the first surface is provided with a gate trench, and the gate structure is located in the gate trench; the follow current structure is arranged on the side, away from the second area, of the first surface, and the follow current structure is used for providing a follow current channel; the source electrode is located on the first surface and electrically connected with the follow current structure; the drain electrode is located on the second surface. According to the semiconductor device, the follow current channel is added in the device, so that the reverse conduction voltage drop is reduced, and the performance stability and safety of the semiconductor device are improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular, to a semiconductor device, a power module, a power conversion circuit, a vehicle, and a method for manufacturing a semiconductor device. Background Art

[0002] Silicon carbide trench devices have the advantages of high current density and small cell pitch, and are widely used. In existing double trench devices, a freewheeling diode is integrated between the source and the drain, but when a positive voltage is connected to the source, its reverse conduction voltage drop is too large, affecting the stability and reliability of the device. Summary of the invention

[0003] The present invention provides a semiconductor device, a power module, a power conversion circuit, a vehicle and a method for preparing a semiconductor device, which realizes adding a freewheeling channel in the device to reduce the reverse conduction voltage drop and improve the performance stability and safety of the semiconductor device.

[0004] In a first aspect, an embodiment of the present invention provides a semiconductor device, including:

[0005] A semiconductor body, comprising a first surface and a second surface arranged opposite to each other, the semiconductor body comprising a well region, a first region, a second region and an isolation region, the first region being arranged on the first surface and extending from the first surface into the semiconductor body, the well region being located on a side of the first region away from the first surface; the second region being arranged on the first surface and extending from the first surface into the semiconductor body; the isolation region being arranged between the second region and the first region; the first region and the second region being of a first conductivity type, the well region being of a second conductivity type, and the first conductivity type and the second conductivity type being different; a gate trench being arranged on the first surface; and the gate trench extending from the first surface into the semiconductor body;

[0006] A gate structure, located in the gate trench;

[0007] a freewheeling structure, arranged on a side of the first surface away from the second region, wherein the orthographic projection of the freewheeling structure on the first surface at least covers the orthographic projection of the second region on the first surface; the freewheeling structure is used to provide a freewheeling channel;

[0008] A source electrode, located on the first surface and electrically connected to the freewheeling structure;

[0009] The drain is located on the second surface.

[0010] Optionally, the freewheeling structure comprises a stacked first semiconductor conductive layer, a second semiconductor conductive layer and a third semiconductor conductive layer; the first semiconductor conductive layer is located on a side close to the first surface; the first semiconductor conductive layer and the third semiconductor conductive layer are of the first conductivity type, and the second semiconductor conductive layer is of the second conductivity type;

[0011] The freewheeling structure also includes a first insulating layer, which is located on a side of the third semiconductor conductive layer away from the first surface; the first insulating layer covers the third semiconductor conductive layer, and covers the side walls of the first semiconductor conductive layer, the second semiconductor conductive layer and the third semiconductor conductive layer; the first insulating layer is provided with a first opening area, and the first opening area at least exposes a portion of the third semiconductor conductive layer.

[0012] Optionally, the freewheeling structure further includes a metal conductive layer, and the metal conductive layer is located between the first semiconductor conductive layer and the second region.

[0013] Optionally, the semiconductor body further includes:

[0014] A buried layer is located on a side of the gate structure away from the first surface; the buried layer extends along a first direction; the buried layer also includes a second opening area, and the orthographic projection of the second opening area on the first surface at least overlaps with the orthographic projection of the gate structure and the freewheeling structure on the first surface; the first direction is a direction parallel to the first surface.

[0015] In a second aspect, an embodiment of the present invention provides a power module, comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device.

[0016] In a third aspect, an embodiment of the present invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0017] The power conversion circuit includes a circuit board and at least one semiconductor device according to any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0018] In a fourth aspect, an embodiment of the present invention provides a vehicle, comprising a load and a power conversion circuit as described in any embodiment of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0019] In a fifth aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0020] A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the semiconductor body comprising a well region, a first region, a second region and an isolation region, the first region being arranged on the first surface and extending from the first surface into the semiconductor body, the well region being located on a side of the first region away from the first surface; the second region being arranged on the first surface and extending from the first surface into the semiconductor body; the isolation region being arranged between the second region and the first region; the first region and the second region being of a first conductivity type, the well region being of a second conductivity type, and the first conductivity type and the second conductivity type being different; a gate trench being arranged on the first surface; and the gate trench extending from the first surface into the semiconductor body;

[0021] forming a gate structure in the gate trench;

[0022] A freewheeling structure is formed on a side of the first surface away from the second region, wherein the orthographic projection of the freewheeling structure on the first surface at least covers the orthographic projection of the second region on the first surface; the freewheeling structure is used to provide a freewheeling channel;

[0023] forming a source electrode on the first surface, wherein the source electrode is electrically connected to the freewheeling structure;

[0024] A drain electrode is formed on the second surface.

[0025] Optionally, forming a freewheeling structure on a side of the first surface away from the second region includes:

[0026] Forming a first semiconductor conductive layer, a second semiconductor conductive layer and a third semiconductor conductive layer in sequence on the first surface;

[0027] A first insulating layer is formed on a side of the third semiconductor conductive layer away from the first surface, the first insulating layer covers the third semiconductor conductive layer, and covers the side walls of the first semiconductor conductive layer, the second semiconductor conductive layer and the third semiconductor conductive layer; the first insulating layer is provided with a first opening area, and the first opening area at least exposes a portion of the third semiconductor conductive layer.

[0028] Optionally, a semiconductor body is provided, comprising:

[0029] forming an epitaxial layer on one side of the substrate;

[0030] A surface of the epitaxial layer away from the substrate is used as a first surface, a well region is formed on the first surface, and the well region extends from the first surface into the epitaxial layer;

[0031] forming the first region with a gap on the first surface, wherein the first region extends from the first surface into the epitaxial layer;

[0032] The second region is formed on the first surface of the interval region between adjacent first regions, and the second region extends from the first surface into the semiconductor body; parts of the well regions on both sides of the second region serve as the isolation region between the second region and the first region; wherein the first region and the second region are of the first conductivity type, the well region is of the second conductivity type, and the first conductivity type and the second conductivity type are different;

[0033] A gate trench is formed on the first surface; the gate trench extends from the first surface into the epitaxial layer.

[0034] Optionally, before forming the first semiconductor conductive layer, a metal conductive layer is formed on the surface of the second region, and the metal conductive layer is located between the first semiconductor conductive layer and the second region.

[0035] Optionally, forming an epitaxial layer on one side of the substrate includes:

[0036] forming a first epitaxial layer on one side of the substrate;

[0037] A buried layer is formed along a first direction on a surface of the first epitaxial layer away from the substrate, the buried layer extends from the surface of the first epitaxial layer away from the substrate to the first epitaxial layer, the buried layer is provided with a second opening area, and the orthographic projection of the second opening area on the first surface at least overlaps with the orthographic projection of the gate structure and the freewheeling structure on the first surface; the first direction is a direction parallel to the first surface;

[0038] A second epitaxial layer is formed on a surface of the first epitaxial layer away from the substrate, and the first epitaxial layer and the second epitaxial layer constitute the epitaxial layer.

[0039] The semiconductor device provided in the embodiment of the present invention introduces a freewheeling structure, and the freewheeling structure is arranged on the side of the first surface away from the second region, wherein the orthographic projection of the freewheeling structure on the first surface at least covers the orthographic projection of the second region on the first surface, and the source electrode is electrically connected to the freewheeling structure. Therefore, when the source electrode has a voltage, the freewheeling structure is used to provide a freewheeling channel to reduce the conduction voltage, and the current passes through the source electrode, the freewheeling structure, the second region and the epitaxial layer in sequence until it is output by the drain electrode. Thereby, a freewheeling channel is added to the device to reduce the reverse conduction voltage drop, and the performance stability and safety of the semiconductor device are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1A schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention;

[0041] Figure 2 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0042] Figure 3 A flowchart of another method for preparing a semiconductor body device provided by an embodiment of the present invention;

[0043] Figure 4-Figure 8 A schematic diagram of an intermediate structure of a semiconductor body device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] Silicon carbide trench devices have the advantages of high current density and small cell pitch. Silicon carbide trench devices generally need to integrate freewheeling diodes, whose function is to conduct when the source level is given a positive voltage to reduce power loss. Existing freewheeling diodes usually form PN junctions with the epitaxial layer through an ion implantation process. The potential barrier of the PN junction is relatively high, so the conduction voltage drop is relatively large, which increases power loss.

[0046] In view of this, Figure 1 A schematic diagram of a semiconductor device according to an embodiment of the present invention is shown in FIG. Figure 1 ,include:

[0047] A semiconductor body 100 includes a first surface and a second surface that are arranged opposite to each other. The semiconductor body 100 includes a well region 30, a first region 40, a second region 50 and an isolation region 60. The first region 40 is arranged on the first surface and extends from the first surface into the semiconductor body 100. The well region 30 is located on a side of the first region 40 away from the first surface. The second region 50 is arranged on the first surface and extends from the first surface into the semiconductor body 100. The isolation region 60 is arranged between the second region 50 and the first region 40. The first region 40 and the second region 50 are of a first conductivity type, the well region 30 is of a second conductivity type, and the first conductivity type and the second conductivity type are different. A gate trench 121 is arranged on the first surface. The gate trench 121 extends from the first surface into the semiconductor body 100.

[0048] The gate structure 120 is located in the gate trench 121;

[0049] The freewheeling structure 110 is arranged on a side of the first surface away from the second area 50, and the orthographic projection of the freewheeling structure 110 on the first surface at least covers the orthographic projection of the second area 50 on the first surface; the freewheeling structure 110 is used to provide a freewheeling channel;

[0050] The source electrode 130 is located on the first surface and is electrically connected to the freewheeling structure 110;

[0051] The drain 140 is located on the second surface.

[0052] Specifically, the semiconductor device in the embodiment of the present invention may be a silicon carbide trench metal oxide semiconductor field effect transistor (MOSFET), and the semiconductor body 100 includes a substrate 10, an epitaxial layer 20, a well region 30, a first region 40, and a second region 50. The material of the substrate 10 and the epitaxial layer 20 may be silicon carbide, and the epitaxial layer 20 is formed on one side of the substrate 10. Exemplarily, the epitaxial layer 20 may be formed on the surface of the substrate 10 by epitaxial growth. The side surface of the epitaxial layer 20 away from the substrate 10 is used as the first surface, the first region 40 is arranged on the first surface, and extends from the first surface to the epitaxial layer 20, and the well region 30 is located in the epitaxial layer 20 away from the first surface of the first region 40. The well region 30 and the first region 40 may be formed by epitaxial growth, ion implantation, or vapor deposition. Exemplarily, in the embodiment of the present invention, the well region 30 and the first region 40 can be formed by ion implantation. For example, the well region 30 is first formed on the first surface by ion implantation, and the well region 30 extends from the first surface to the epitaxial layer 20. Then, the first region 40 is formed on the first surface by ion implantation, and the first region 40 extends from the first surface to the well region 30. The well region 30 and the first region 40 can be used to form a conductive channel of a semiconductor device, wherein the first region 40 is of the first conductivity type and the well region 30 is of the second conductivity type.

[0053] The first conductivity type in the embodiment of the present invention may be an N-type conductivity type, and the second conductivity type may be a P-type conductivity type, or the first conductivity type may be a P-type conductivity type, and the second conductivity type may be an N-type doping. Among them, the N-type conductivity type can be obtained by doping ions in the semiconductor, such as P (phosphorus) or N (nitrogen) ions, and the P-type conductivity type can be obtained by doping ions Al (aluminum) ions or B (boron) ions in the semiconductor. P+ and N+ shown in the figure indicate that the ion doping concentration in the region is high, and P- and N- indicate that the ion doping concentration in the region is low. Exemplarily, the embodiment of the present invention takes the first conductivity type as N-type conductivity type and the second conductivity type as P-type conductivity type as an example. When the semiconductor device is an N-type device, the substrate 10 is the first conductivity type, for example, it can be an N+ silicon carbide substrate 10; the epitaxial layer 20 is the first conductivity type, for example, it can be an N-silicon carbide epitaxial layer 20; when the semiconductor device is a P-type device, the substrate 10 is the second conductivity type, for example, it can be a P+ silicon carbide substrate 1010; the epitaxial layer 20 is the second conductivity type, for example, it can be a P-silicon carbide epitaxial layer 20.

[0054] The second region 50 can be formed on the first surface by ion implantation and extend into the epitaxial layer 20. The second region 50 can improve the uniformity of the current entering the epitaxial layer 20 and avoid a large local current density. Among them, the region where the second region 50 contacts the first region 40 is provided with an isolation region 60, and the isolation region 60 can avoid the second region 50 from being short-circuited with the first region 40. Part of the well region 30 can be reused as the isolation region 60, that is, the difference between the conductivity type of the well region 30 and the second region 50 and the first region 40 is utilized to isolate the second region 50 and the first region 40. For example, in the preparation process, part of the well region 30 is extended to the first surface along the thickness direction of the device, so that part of the well region 30 has a certain width dimension between the second region 50 and the first region 40, thereby achieving isolation between the second region 50 and the first region 40. In the preparation process, the well region 30 can be first formed on the first surface by ion implantation, the well region 30 extends from the first surface to the inside of the epitaxial layer 20, and then the first region 40 with a pattern is formed on the first surface by ion implantation, the first region 40 extends from the first surface to the inside of the well region 30. In other words, the first regions 40 with intervals are formed on the first surface, and the well regions 30 between adjacent first regions 40 can be reused as isolation regions 60 in subsequent structures.

[0055] The gate trench 121 can be formed on the first surface by an etching process. The gate trench 121 passes through the first region 40 and the well region 30 and extends from the first surface to the epitaxial layer 20. A gate structure 120 is arranged in the gate trench 121, and the well regions 30 on both sides of the gate structure 120 can form a vertical conductive channel. Among them, a second insulating layer 122 is arranged between the gate structure 120 and the gate trench 121. The second insulating layer 122 is arranged on the inner wall and bottom of the gate trench 121. The second insulating layer 122 can be a gate oxide layer, and the gate oxide layer can be a high dielectric constant (K) material. The gate structure 120 can be an N+ polysilicon material. The work function of the N+ polysilicon material is low, and the threshold voltage of the device can be effectively adjusted.

[0056] The freewheeling structure 110 is located at one side of the gate trench 121. In some embodiments, the freewheeling structure 110 can be respectively disposed on both sides of the gate trench 121. Figure 1 As shown, the two freewheeling structures 110 can be arranged symmetrically or asymmetrically. The freewheeling structure 110 is used to provide a freewheeling channel. Figure 1 In the structure shown, a third insulating layer 123 is further included between the source and the gate structure 120. The third insulating layer 123 may be an interlayer dielectric layer (ILD). The third insulating layer 123 covers the surface of the gate structure 120. The third insulating layer 123 isolates the gate structure 120 from the source 130. Exemplarily, the source 130 may be formed by sputtering or the like. The source 130 is a metal conductive layer. The material of the source 130 may be titanium (Ti), nickel (Ni) or silver (Ag).

[0057] The semiconductor device provided in the embodiment of the present invention introduces a freewheeling structure 110, and the freewheeling structure 110 is arranged on the side of the first surface away from the second region 50, wherein the orthographic projection of the freewheeling structure 110 on the first surface at least covers the orthographic projection of the second region 50 on the first surface, and the source 130 is electrically connected to the freewheeling structure 110. Therefore, when the source 130 has a voltage, the freewheeling structure 110 is used to provide a freewheeling channel to reduce the conduction voltage, and the current passes through the source 130, the freewheeling structure 110, the second region 50 and the epitaxial layer 20 in sequence until it is output by the drain. Thereby, a freewheeling channel is added to the device to reduce the reverse conduction voltage drop and improve the performance stability and safety of the semiconductor device.

[0058] Continue to see Figure 1Optionally, the freewheeling structure 110 includes a stacked first semiconductor conductive layer 111, a second semiconductor conductive layer 112, and a third semiconductor conductive layer 113; the first semiconductor conductive layer 111 is located on a side close to the first surface; the first semiconductor conductive layer 111 and the third semiconductor conductive layer 113 are of the first conductivity type, and the second semiconductor conductive layer 112 is of the second conductivity type;

[0059] The freewheeling structure 110 also includes a first insulating layer 114, which is located on the side of the third semiconductor conductive layer 113 away from the first surface; the first insulating layer 114 covers the third semiconductor conductive layer 113, and covers the side walls of the first semiconductor conductive layer 111, the second semiconductor conductive layer 112 and the third semiconductor conductive layer 113; the first insulating layer 114 is provided with a first opening area 115, and the first opening area 115 at least exposes a portion of the third semiconductor conductive layer 113.

[0060] Specifically, the first semiconductor conductive layer 111, the second semiconductor conductive layer 112 and the third semiconductor conductive layer 113 can be made of polycrystalline silicon material, wherein the second semiconductor conductive layer 112 is arranged between the first semiconductor conductive layer 111 and the third semiconductor conductive layer 113. In combination with the above embodiments, the first semiconductor conductive layer 111 and the third semiconductor conductive layer 113 can be of the first conductive type, for example, the first semiconductor conductive layer 111 and the third semiconductor conductive layer 113 are of N-type conductive type, and the second semiconductor conductive layer 112 is of P-type conductive type. Therefore, the first semiconductor conductive layer 111, the second semiconductor conductive layer 112 and the third semiconductor conductive layer 113 constitute a thin film transistor (TFT) structure. The first semiconductor conductive layer 111 is located on the first surface and contacts the second region 50. The first insulating layer 114 is arranged on the side of the third semiconductor conductive layer 113 away from the first surface. The first insulating layer 114 can cover the side walls of each semiconductor conductive layer to prevent the source 130 from contacting the side walls of each semiconductor conductive layer and causing a short circuit. The first insulating layer 114 is also provided with a first opening area 115. The first opening area 115 can expose a portion of the third semiconductor conductive layer 113, so that the third semiconductor conductive layer 113 can be electrically connected to the source 130 through the first opening area 115. In the TFT structure composed of the first semiconductor conductive layer 111, the second semiconductor conductive layer 112 and the third semiconductor conductive layer 113, the third semiconductor conductive layer 113 is the source 130 of the TFT, the second semiconductor conductive layer 112 is the channel of the TFT, the second semiconductor conductive layer 112 is the drain 140 of the TFT, and the source 130 is the gate of the TFT, that is, the source 130 and the gate are short-circuited in the TFT structure. Therefore, when a positive voltage is input to the source 130, the gate of the TFT is also a positive voltage, the channel of the TFT is turned on, and the current direction is the source 130, the third semiconductor conductive layer 113, the second semiconductor conductive layer 112, the first semiconductor conductive layer 111, the second region 50, the epitaxial layer 20 and the drain 140. Compared with the PN junction formed by the ion implantation region and the epitaxial layer 20, the TFT structure composed of the first semiconductor conductive layer 111, the second semiconductor conductive layer 112 and the third semiconductor conductive layer 113 has a small polysilicon energy band width and a low electron potential barrier between the conduction band and the Fermi energy level. When the source 130 is given a high potential, it is more conducive to reverse conduction, thereby reducing the reverse conduction voltage drop.

[0061] Continue to see Figure 1 Optionally, the freewheeling structure 110 further includes a metal conductive layer 115 , and the metal conductive layer 115 is located between the first semiconductor conductive layer 111 and the second region 50 .

[0062] Specifically, a metal conductive layer 115 is disposed on the side of the first semiconductor conductive layer 111 close to the second region 50, and the metal conductive layer 115 is in contact with the second region 50. The metal conductive layer 115 is used to reduce the contact resistance between the first semiconductor conductive layer 111 and the second region 50, thereby reducing the influence of the large difference in work function between the first semiconductor conductive layer 111 and the second region 50, thereby reducing the on-resistance of the semiconductor device and improving the conductive efficiency of the device. According to the conductivity type of the second region 50, the metal material of the metal conductive layer 115 can be selected. For example, the metal material of the metal conductive layer 115 in the embodiment of the present invention can be nickel.

[0063] Optionally, the semiconductor body 100 further includes: a buried layer 70, located between the substrate 10 and the gate structure 120; the buried layer 70 is extended along a first direction; the first direction is a direction parallel to the first surface, the buried layer 70 is extended along the first direction in the epitaxial layer 20 between the gate structure 120 and the substrate 10, and the buried layer 70 is of the second conductivity type, wherein, when the buried layer 70 is used in a terminal, it is necessary to make the buried layer 70 and the source 130 have the same potential, therefore, a depletion region can be formed between the buried layer 70 and the epitaxial layer 20, thereby shielding the electric field of the gate structure 120, improving the problem of gate oxide layer breakdown, and ensuring the reliability of the device operation. Furthermore, a second opening area 71 is also provided on the buried layer 70, and the second opening area 71 is used to adjust the current flow path of the freewheeling diode formed by the freewheeling structure 110, and the current flow path when the semiconductor device is working. Among them, the orthographic projection of the second opening area 71 on the first surface at least overlaps with the orthographic projections of the gate structure 120 and the freewheeling structure 110 on the first surface, that is, the second opening area 71 is at least arranged below the freewheeling structure 110 close to the substrate 10, thereby forming a current channel for the freewheeling diode. The second opening area 71 is at least arranged below the gate structure 120 close to the substrate 10, thereby forming a current channel when the semiconductor device is working. Further, the orthographic projection of the buried layer 70 on the first surface at least overlaps with the orthographic projection of the corner area of ​​the gate groove 121 on the first surface, that is, a buried layer 70 with a certain width dimension along the first direction is arranged below the corner area of ​​the gate groove 121 close to the substrate 10, to ensure that the buried layer 70 can perform electric field shielding protection on the corner area of ​​the gate groove 121, further improving the reliability of the device operation.

[0064] An embodiment of the present invention provides a power module based on the above embodiment, including a substrate and a semiconductor device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device.

[0065] The power module provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device of any embodiment of the present invention.

[0066] An embodiment of the present invention provides a power conversion circuit based on the above embodiments, and the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device as in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0067] The power conversion circuit provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the semiconductor device of any embodiment of the present invention.

[0068] An embodiment of the present invention provides a vehicle based on the above embodiment, including a load and a power conversion circuit as in any embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0069] An embodiment of the present invention provides a method for preparing a semiconductor device based on the above embodiment. Figure 2 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention, combined with Figure 1 ,refer to Figure 2 , the preparation method comprises:

[0070] S110, providing a semiconductor body 100, the semiconductor body 100 includes a first surface and a second surface arranged opposite to each other, the semiconductor body 100 includes a well region 30, a first region 40, a second region 50 and an isolation region 60, the first region 40 is arranged on the first surface, extending from the first surface into the semiconductor body 100, and the well region 30 is located on a side of the first region 40 away from the first surface; the second region 50 is arranged on the first surface, and extends from the first surface into the semiconductor body 100; the isolation region 60 is arranged between the second region 50 and the first region 40; the first region 40 and the second region 50 are of a first conductivity type, the well region 30 is of a second conductivity type, and the first conductivity type and the second conductivity type are different; a gate trench 121 is arranged on the first surface; the gate trench 121 extends from the first surface into the semiconductor body 100;

[0071] Specifically, the semiconductor body 100 includes a substrate 10, an epitaxial layer 20, a well region 30, a first region 40, and a second region 50. The materials of the substrate 10 and the epitaxial layer 20 can be silicon carbide. The epitaxial layer 20 is formed on one side of the substrate 10, and the epitaxial layer 20 can be formed on the surface of the substrate 10 by epitaxial growth. The surface of the epitaxial layer 20 on one side away from the substrate 10 is used as the first surface. The first region 40 is arranged on the first surface and extends from the first surface to the epitaxial layer 20. The well region 30 is located in the epitaxial layer 20 away from the first surface of the first region 40. The well region 30 and the first region 40 can be formed by epitaxial growth, ion implantation, or vapor deposition. In the embodiment of the present invention, the well region 30 and the first region 40 can be formed by ion implantation. The well region 30 is first formed on the first surface by ion implantation, and the well region 30 extends from the first surface to the epitaxial layer 20. Then, the first region 40 is formed on the first surface by ion implantation, and the first region 40 extends from the first surface to the well region 30. The well region 30 and the first region 40 may be used to form a conductive channel of a semiconductor device, wherein the first region 40 is of the first conductive type and the well region 30 is of the second conductive type.

[0072] In the embodiment of the present invention, taking the first conductivity type being N-type and the second conductivity type being P-type as an example, when the semiconductor device is an N-type device, the substrate 10 is of the first conductivity type, for example, it may be an N+ silicon carbide substrate 10; the epitaxial layer 20 is of the first conductivity type, for example, it may be an N-silicon carbide epitaxial layer 20; when the semiconductor device is a P-type device, the substrate 10 is of the second conductivity type, for example, it may be a P+ silicon carbide substrate 10; the epitaxial layer 20 is of the second conductivity type, for example, it may be a P-silicon carbide epitaxial layer 20.

[0073] The second region 50 can be formed on the first surface by ion implantation and extend into the epitaxial layer 20, wherein the region where the second region 50 contacts the first region 40 is provided with an isolation region 60, and the isolation region 60 can prevent the second region 50 from being short-circuited with the first region 40. Part of the well region 30 is reused as the isolation region 60, that is, the difference between the conductivity type of the well region 30 and the second region 50 and the first region 40 is utilized to isolate the second region 50 and the first region 40. In the preparation process, part of the well region 30 is extended to the first surface along the thickness direction of the device, so that part of the well region 30 has a certain width dimension between the second region 50 and the first region 40, thereby achieving isolation between the second region 50 and the first region 40. In the preparation process, the well region 30 can also be formed on the first surface by ion implantation, and the well region 30 extends from the first surface to the epitaxial layer 20, and then the first region 40 with a pattern is formed on the first surface by ion implantation, and the first region 40 extends from the first surface to the well region 30. That is, the first regions 40 with intervals are formed on the first surface, and the well regions 30 between adjacent first regions 40 can be reused as isolation regions 60 in subsequent structures. The gate trench 121 can be formed on the first surface by an etching process, and the gate trench 121 passes through the first region 40 and the well region 30, and extends from the first surface to the epitaxial layer 20.

[0074] S120, forming a gate structure 120 in the gate trench 121;

[0075] Specifically, a gate structure 120 is disposed in the gate trench 121, and the well regions 30 on both sides of the gate structure 120 can form a vertical conductive channel. A second insulating layer 122 is disposed between the gate structure 120 and the gate trench 121, and the second insulating layer 122 is disposed on the inner wall and bottom of the gate trench 121. The second insulating layer 122 can be a gate oxide layer, and the gate oxide layer can be a high dielectric constant (K) material. The gate structure 120 can be an N+ polysilicon material, and the work function of the N+ polysilicon material is low, which can effectively adjust the threshold voltage of the device.

[0076] S130, forming a freewheeling structure 110 on a side of the first surface away from the second region 50, wherein the orthographic projection of the freewheeling structure 110 on the first surface at least covers the orthographic projection of the second region 50 on the first surface; the freewheeling structure 110 is used to provide a freewheeling channel;

[0077] Specifically, the freewheeling structure 110 is located on one side of the gate trench 121. In some embodiments, the freewheeling structure 110 may be disposed on both sides of the gate trench 121, such as Figure 1 As shown, the two freewheeling structures 110 may be arranged symmetrically or asymmetrically.

[0078] S140, forming a source electrode 130 on the first surface, wherein the source electrode 130 is electrically connected to the freewheeling structure 110;

[0079] Combination Figure 1 In the structure shown, a third insulating layer 123 is further included between the source 130 and the gate structure 120. The third insulating layer 123 may be an interlayer dielectric layer (ILD). The third insulating layer 123 covers the surface of the gate structure 120. The third insulating layer 123 isolates the gate structure 120 from the source 130. Exemplarily, the source 130 may be formed by sputtering or the like. The source 130 is a conductive layer. The material of the source 130 may be titanium (Ti), nickel (Ni) or silver (Ag).

[0080] S150 , forming a drain electrode 140 on the second surface.

[0081] Optionally, forming the freewheeling structure 110 on a side of the first surface away from the second region 50 includes:

[0082] A first semiconductor conductive layer 111, a second semiconductor conductive layer 112 and a third semiconductor conductive layer 113 are sequentially stacked on the first surface;

[0083] A first insulating layer 114 is formed on a side of the third semiconductor conductive layer 113 away from the first surface, and the first insulating layer 114 covers the third semiconductor conductive layer 113, and covers the side walls of the first semiconductor conductive layer 111, the second semiconductor conductive layer 112 and the third semiconductor conductive layer 113; the first insulating layer 114 is provided with a first opening area 115, and the first opening area 115 at least exposes a portion of the third semiconductor conductive layer 113.

[0084] Specifically, the first semiconductor conductive layer 111, the second semiconductor conductive layer 112 and the third semiconductor conductive layer 113 may be made of polysilicon material, wherein the second semiconductor conductive layer 112 is disposed between the first semiconductor conductive layer 111 and the third semiconductor conductive layer 113. In combination with the above embodiment, the first semiconductor conductive layer 111 and the third semiconductor conductive layer 113 may be of the first conductivity type, for example, the first semiconductor conductive layer 111 and the third semiconductor conductive layer 113 are of the N-type conductivity type, and the second semiconductor conductive layer 112 is of the P-type conductivity type. Therefore, the first semiconductor conductive layer 111, the second semiconductor conductive layer 112 and the third semiconductor conductive layer 113 form a TFT structure.

[0085] The first semiconductor conductive layer 111 is located on the first surface and contacts the second region 50. The first insulating layer 114 is disposed on the side of the third semiconductor conductive layer 113 away from the first surface. The first insulating layer 114 can cover the sidewalls of each semiconductor conductive layer to prevent the source 130 from contacting the sidewalls of each semiconductor conductive layer and causing a short circuit. The first insulating layer 114 is also provided with a first opening area 115. The first opening area 115 can expose a portion of the third semiconductor conductive layer 113, so that the third semiconductor conductive layer 113 can be electrically connected to the source 130 through the first opening area 115. In the preparation process, the first insulating layer 114 can be deposited simultaneously with the third insulating layer 123 to obtain an insulating layer. According to the design pattern, the insulating layer needs to expose a portion of the first region 40 as an ohmic contact region and a portion of the third semiconductor conductive layer 113, so that the source 130 can be connected to a portion of the first region 40 and a portion of the third semiconductor conductive layer 113.

[0086] In the TFT structure composed of the first semiconductor conductive layer 111, the second semiconductor conductive layer 112 and the third semiconductor conductive layer 113, the third semiconductor conductive layer 113 is the source 130 of the TFT, the second semiconductor conductive layer 112 is the channel of the TFT, the second semiconductor conductive layer 112 is the drain 140 of the TFT, and the source 130 is the gate of the TFT, that is, the source 130 and the gate are short-circuited in the TFT structure. Therefore, when a positive voltage is input to the source 130, the gate of the TFT is also a positive voltage, the channel of the TFT is turned on, and the current direction is the source 130, the third semiconductor conductive layer 113, the second semiconductor conductive layer 112, the first semiconductor conductive layer 111, the second region 50, the epitaxial layer 20 and the drain 140. Compared with the PN junction formed by the ion implantation region and the epitaxial layer 20, the TFT structure composed of the first semiconductor conductive layer 111, the second semiconductor conductive layer 112 and the third semiconductor conductive layer 113 has a small polysilicon energy band width and a low electron potential barrier between the conduction band and the Fermi energy level. When the source 130 is given a high potential, it is more conducive to reverse conduction, thereby reducing the reverse conduction voltage drop.

[0087] As an optional embodiment, Figure 1 Taking the semiconductor device structure as an example, Figure 3 A flowchart of another method for preparing a semiconductor body device provided by an embodiment of the present invention, Figure 4-Figure 8 A schematic diagram of an intermediate structure of a semiconductor body device provided by an embodiment of the present invention, referring to Figure 3-Figure 8 , the preparation method comprises:

[0088] S210, forming a first epitaxial layer 21 on one side of the substrate 10;

[0089] S220, forming a buried layer 70 along a first direction on a surface of the first epitaxial layer 21 away from the substrate 10, wherein the buried layer 70 extends from the surface of the first epitaxial layer 21 away from the substrate 10 to the first epitaxial layer 21, and the buried layer 70 is provided with a second opening area 71, and the orthographic projection of the second opening area 71 on the first surface at least overlaps with the orthographic projections of the gate structure 120 and the freewheeling structure 110 on the first surface; the first direction is a direction parallel to the first surface;

[0090] Specifically, the buried layer 70 is extended along the first direction in the epitaxial layer 20 between the gate structure 120 and the substrate 10, and the buried layer 70 is of the second conductivity type. When the buried layer 70 is used in the terminal, it is necessary to make the buried layer 70 and the source 130 have the same potential. Therefore, a depletion region can be formed between the buried layer 70 and the epitaxial layer 20, so as to play a role in shielding the electric field of the gate structure 120, improve the problem of gate oxide layer breakdown, and ensure the reliability of device operation. Further, an opening area is also provided on the buried layer 70, and the opening area is used to adjust the current flow path of the freewheeling diode formed by the freewheeling structure 110, and the current flow path when the semiconductor device is working. Among them, the orthographic projection of the opening area on the first surface at least overlaps with the orthographic projection of the gate structure 120 and the freewheeling structure 110 on the first surface, that is, the opening area is at least arranged below the freewheeling structure 110 close to the substrate 10, thereby forming a current channel for the freewheeling diode. The opening area is at least arranged below the gate structure 120 close to the substrate 10, thereby forming a current channel when the semiconductor device is working. Furthermore, the orthographic projection of the buried layer 70 on the first surface at least overlaps with the orthographic projection of the corner region of the gate trench 121 on the first surface, that is, a buried layer 70 with a certain width along the first direction is provided below the corner region of the gate trench 121 near the substrate 10, ensuring that the buried layer 70 can perform electric field shielding protection on the corner region of the gate trench 121, further improving the reliability of the device operation. Its structure is as follows Figure 4 shown.

[0091] S230, forming a second epitaxial layer 22 on the surface of the first epitaxial layer 21 away from the substrate 10, the first epitaxial layer 21 and the second epitaxial layer 22 constitute the epitaxial layer 20. Its structure is as follows Figure 5 shown.

[0092] S240, the surface of the epitaxial layer 20 away from the substrate 10 is used as the first surface, and a well region 30 is formed on the first surface, wherein the well region 30 extends from the first surface into the epitaxial layer 20;

[0093] S250, forming a first region 40 with a gap on the first surface, the first region 40 extending from the first surface to the epitaxial layer 20; wherein the implantation position of the first region 40 can be designed according to a preset pattern, and the well region 30 between adjacent first regions 40 can be reused as an isolation region 60 in a subsequent structure. Its structure is as follows Figure 6 shown.

[0094] S260, forming a second region 50 on the first surface of the spacing region between adjacent first regions 40, wherein the second region 50 extends from the first surface into the semiconductor body 100; parts of the well regions 30 on both sides of the second region 50 serve as an isolation region 60 between the second region 50 and the first region 40; wherein the first region 40 and the second region 50 are of the first conductivity type, the well region 30 is of the second conductivity type, and the first conductivity type and the second conductivity type are different;

[0095] Among them, the second region 50 can be formed on the first surface of the epitaxial layer 20 through an ion implantation process and extend from the first surface to the epitaxial layer 20. By utilizing the difference in conductivity type between the well region 30 and the second region 50 and the first region 40, the well region 30 between adjacent first regions 40 is reused as an isolation region 60 to achieve isolation between the second region 50 and the first region 40.

[0096] S270, forming a gate trench 121 on the first surface; the gate trench 121 extends from the first surface into the epitaxial layer 20. Its structure is as follows Figure 7 shown.

[0097] S280 , forming a gate structure 120 in the gate trench 121 .

[0098] S290, forming a first semiconductor conductive layer 111, a second semiconductor conductive layer 112 and a third semiconductor conductive layer 113 in sequence on the first surface;

[0099] Optionally, before forming the first semiconductor conductive layer 111, a metal conductive layer 115 is formed on the surface of the second region 50, and the metal conductive layer 115 is located between the first semiconductor conductive layer 111 and the second region 50. Specifically, the metal conductive layer 115 is arranged on the side of the first semiconductor conductive layer 111 close to the second region 50, and the metal conductive layer 115 is in contact with the second region 50. The metal conductive layer 115 is used to reduce the contact resistance between the first semiconductor conductive layer 111 and the second region 50, thereby reducing the influence caused by the large difference in work function between the first semiconductor conductive layer 111 and the second region 50, thereby reducing the on-resistance of the semiconductor device and improving the conductive efficiency of the device. According to the conductivity type of the second region 50, the metal material of the metal conductive layer 115 can be selected. Exemplarily, the metal material of the metal conductive layer 115 in the embodiment of the present invention can be nickel.

[0100] S300. A first insulating layer 114 is formed on a side of the third semiconductor conductive layer 113 away from the first surface, wherein the first insulating layer 114 covers the third semiconductor conductive layer 113, and covers the side walls of the first semiconductor conductive layer 111, the second semiconductor conductive layer 112 and the third semiconductor conductive layer 113; the first insulating layer 114 is provided with a first opening area 115, and the first opening area 115 at least exposes a portion of the third semiconductor conductive layer 113.

[0101] Specifically, the first insulating layer 114 and the third insulating layer 123 can be deposited simultaneously to obtain an insulating layer. According to the design pattern, the insulating layer needs to expose a portion of the first region 40 as an ohmic contact region and a portion of the third semiconductor conductive layer 113, so that the source 130 can be connected to a portion of the first region 40 and a portion of the third semiconductor conductive layer 113. The structure is as follows Figure 8 shown.

[0102] S310, forming a source 130 and a drain 140 on one side of the substrate 10. The structure is as follows Figure 1 shown.

[0103] It should be noted that, according to the convenience of the preparation process, the corresponding step sequence can be adjusted to a certain extent, and no specific limitation is made here.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other, the semiconductor body comprising a well region, a first region, a second region and an isolation region, the first region being arranged on the first surface and extending from the first surface into the semiconductor body, the well region being located on a side of the first region away from the first surface; the second region being arranged on the first surface and extending from the first surface into the semiconductor body; the isolation region being arranged between the second region and the first region; the first region and the second region being of a first conductivity type, the well region being of a second conductivity type, and the first conductivity type and the second conductivity type being different; a gate trench being arranged on the first surface; and the gate trench extending from the first surface into the semiconductor body; A gate structure, located in the gate trench; a freewheeling structure, arranged on a side of the first surface away from the second region, wherein an orthographic projection of the freewheeling structure on the first surface at least covers an orthographic projection of the second region on the first surface; The freewheeling structure is used to provide a freewheeling channel; A source electrode, located on the first surface and electrically connected to the freewheeling structure; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein: The freewheeling structure comprises a stacked first semiconductor conductive layer, a second semiconductor conductive layer and a third semiconductor conductive layer; the first semiconductor conductive layer is located close to the first surface; the first semiconductor conductive layer and the third semiconductor conductive layer are of the first conductivity type, and the second semiconductor conductive layer is of the second conductivity type; The freewheeling structure also includes a first insulating layer, which is located on a side of the third semiconductor conductive layer away from the first surface; the first insulating layer covers the third semiconductor conductive layer, and covers the side walls of the first semiconductor conductive layer, the second semiconductor conductive layer and the third semiconductor conductive layer; the first insulating layer is provided with a first opening area, and the first opening area at least exposes a portion of the third semiconductor conductive layer.

3. The semiconductor device according to claim 2, characterized in that The freewheeling structure further includes a metal conductive layer, and the metal conductive layer is located between the first semiconductor conductive layer and the second region.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: The semiconductor body further comprises: A buried layer is located on a side of the gate structure away from the first surface; the buried layer extends along a first direction; the buried layer also includes a second opening area, and the orthographic projection of the second opening area on the first surface at least overlaps with the orthographic projection of the gate structure and the freewheeling structure on the first surface; the first direction is a direction parallel to the first surface.

5. A power module, characterized in that: It comprises a substrate and at least one semiconductor device according to any one of claims 1 to 4, wherein the substrate is used to carry the semiconductor device.

6. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is electrically connected to the circuit board.

7. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 6, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

8. A method for preparing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the semiconductor body comprising a well region, a first region, a second region and an isolation region, the first region being arranged on the first surface and extending from the first surface into the semiconductor body, the well region being located on a side of the first region away from the first surface; the second region being arranged on the first surface and extending from the first surface into the semiconductor body; the isolation region being arranged between the second region and the first region; the first region and the second region being of a first conductivity type, the well region being of a second conductivity type, and the first conductivity type and the second conductivity type being different; a gate trench being arranged on the first surface; and the gate trench extending from the first surface into the semiconductor body; forming a gate structure in the gate trench; A freewheeling structure is formed on a side of the first surface away from the second region, wherein an orthographic projection of the freewheeling structure on the first surface at least covers an orthographic projection of the second region on the first surface; The freewheeling structure is used to provide a freewheeling channel; forming a source electrode on the first surface, wherein the source electrode is electrically connected to the freewheeling structure; A drain electrode is formed on the second surface.

9. The method for preparing a semiconductor device according to claim 8, characterized in that: Forming a freewheeling structure on a side of the first surface away from the second region comprises: Forming a first semiconductor conductive layer, a second semiconductor conductive layer and a third semiconductor conductive layer in sequence on the first surface; A first insulating layer is formed on a side of the third semiconductor conductive layer away from the first surface, the first insulating layer covers the third semiconductor conductive layer, and covers the side walls of the first semiconductor conductive layer, the second semiconductor conductive layer and the third semiconductor conductive layer; the first insulating layer is provided with a first opening area, and the first opening area at least exposes a portion of the third semiconductor conductive layer.

10. The method for preparing a semiconductor device according to claim 8, characterized in that: Provide a semiconductor body, including: forming an epitaxial layer on one side of the substrate; A surface of the epitaxial layer away from the substrate is used as a first surface, a well region is formed on the first surface, and the well region extends from the first surface into the epitaxial layer; forming the first region with a gap on the first surface, wherein the first region extends from the first surface into the epitaxial layer; The second region is formed on the first surface of the interval region between adjacent first regions, and the second region extends from the first surface into the semiconductor body; parts of the well regions on both sides of the second region serve as the isolation region between the second region and the first region; wherein the first region and the second region are of the first conductivity type, the well region is of the second conductivity type, and the first conductivity type and the second conductivity type are different; A gate trench is formed on the first surface; the gate trench extends from the first surface into the epitaxial layer.

11. The method for preparing a semiconductor device according to claim 9, characterized in that: Before forming the first semiconductor conductive layer, a metal conductive layer is formed on the surface of the second region, and the metal conductive layer is located between the first semiconductor conductive layer and the second region.

12. The method for preparing a semiconductor device according to claim 10, characterized in that: Forming an epitaxial layer on one side of the substrate includes: forming a first epitaxial layer on one side of the substrate; A buried layer is formed along a first direction on a surface of the first epitaxial layer away from the substrate, the buried layer extends from the surface of the first epitaxial layer away from the substrate to the first epitaxial layer, the buried layer is provided with a second opening area, and the orthographic projection of the second opening area on the first surface at least overlaps with the orthographic projection of the gate structure and the freewheeling structure on the first surface; the first direction is a direction parallel to the first surface; A second epitaxial layer is formed on a surface of the first epitaxial layer away from the substrate, and the first epitaxial layer and the second epitaxial layer constitute the epitaxial layer.

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