Power device and preparation method thereof, semiconductor device, memory and electronic equipment

Abstract

The invention relates to a power device and a preparation method thereof, a semiconductor device, a memory and electronic equipment. The substrate of the first ion type is located on the metal drain electrode; the epitaxial layer of the first ion type is located on the substrate of the first ion type; the source electrodes are located on the two opposite sides of the top of the epitaxial layer of the first ion type, and the source electrodes cover part of the top surface of the epitaxial layer of the first ion type; the grid electrode is located on the portion, not covered by the source electrode, of the epitaxial layer of the first ion type, the grid electrode makes contact with the top of the epitaxial layer of the first ion type, and an air conditioning area is formed at the bottom of the grid electrode. By adding the air conditioning area between the grid electrode and the drain electrode, at least the parasitic capacitance can be reduced, the working frequency of the power device is improved, and the on-resistance of the power device is not affected.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a power device and a preparation method thereof, a semiconductor device, a memory, and an electronic device. Background Art

[0002] Power electronic devices are developing in the direction of high power, high frequency and integration. In the 1980s, the current capacity of thyristors reached 6000A and the blocking voltage was as high as 6500V. However, the operating frequency of such devices is relatively low. Increasing their operating frequency depends on how to speed up the recombination speed of minority carriers in the base region (referred to as minority carriers) during the device shutdown period and extract more carriers through the gate.

[0003] However, although reducing the minority carrier lifetime can effectively shorten the process of turning off the current, it will increase the forward voltage drop of the device during the on-time. Therefore, it is necessary to take into account the requirements of conversion speed and device on-state power loss. Summary of the invention

[0004] Based on this, it is necessary to provide a power device and its preparation method, semiconductor device, memory, and electronic device to address the above technical problems, which can at least reduce parasitic capacitance and increase the operating frequency of the power device.

[0005] In order to achieve the above-mentioned purpose and other purposes, in the first aspect, the present disclosure provides a power device, including: a metal drain; a substrate of a first ion type, located on the metal drain; an epitaxial layer of a first ion type, located on the substrate of the first ion type; a source, located on two opposite sides of the top of the epitaxial layer of the first ion type, the source covering a portion of the top surface of the epitaxial layer of the first ion type; a gate, located on a portion of the epitaxial layer of the first ion type not covered by the source, the gate portion contacts the top of the epitaxial layer of the first ion type, and an air conditioning area is formed at the bottom of the gate.

[0006] In the power device in the above embodiment, by adding an air conditioning area between the gate and the drain, at least the parasitic capacitance can be reduced, and the operating frequency of the power device can be increased without affecting the on-resistance of the power device.

[0007] In one embodiment, the source includes: a well region of the second ion type and a switch ratio adjustment region, wherein the switch ratio adjustment region is located in the well region of the second ion type and covers a portion of the top surface of the epitaxial layer of the first ion type.

[0008] In one embodiment, the gate includes a gate oxide layer and a polysilicon layer, and the polysilicon layer is located on the gate oxide layer.

[0009] In a second aspect, the embodiments of the present disclosure further provide a semiconductor device, including: a power device in any of the above embodiments, which can at least reduce parasitic capacitance, increase the operating frequency of the power device and not affect the on-resistance of the power device.

[0010] In a third aspect, an embodiment of the present disclosure further provides a memory, comprising: a semiconductor device in any of the above embodiments.

[0011] In a fourth aspect, an embodiment of the present disclosure further provides an electronic device, comprising: a semiconductor device in any of the above embodiments, or a memory in any of the above embodiments.

[0012] In the fifth aspect, the embodiments of the present disclosure also provide a method for preparing a power device, comprising: providing a metal drain; forming a substrate of a first ion type on the metal drain; forming an epitaxial layer of a first ion type on the substrate of the first ion type; forming a source on two opposite sides of the top of the epitaxial layer of the first ion type, the source covering a portion of the top surface of the epitaxial layer of the first ion type; forming a gate on a portion of the epitaxial layer of the first ion type not covered by the source, the gate portion being in contact with the top of the epitaxial layer of the first ion type, and an air conditioning area being formed at the bottom of the gate.

[0013] In the alignment pattern preparation method in the above embodiment, by adding an air conditioning area between the gate and the drain, at least the parasitic capacitance can be reduced, and the operating frequency of the power device can be increased without affecting the on-resistance of the power device.

[0014] In one embodiment, a gate is formed on a portion of an epitaxial layer of a first ion type that is not covered by a source, comprising: forming a barrier layer on the epitaxial layer of the first ion type, the barrier layer covering a portion of the epitaxial layer of the first ion type that is not covered by the source; depositing a gate oxide layer and a polysilicon layer on the barrier layer and the epitaxial layer of the first ion type; and removing the barrier layer, the gate oxide layer and the polysilicon layer on the source to form a gate.

[0015] In one embodiment, the step of removing the barrier layer, the gate oxide layer and the polysilicon layer on the source electrode comprises: removing the polysilicon layer on the source electrode; removing the barrier layer; and removing the gate oxide layer on the source electrode.

[0016] In one embodiment, removing the polysilicon layer on the source includes: forming a sacrificial layer covering the polysilicon layer, and a patterned photoresist layer covering the sacrificial layer; using the patterned photoresist layer as a mask to pattern the sacrificial layer; using the patterned sacrificial layer as a mask and the gate oxide layer as an etching end point to etch and remove the polysilicon layer on the source. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A schematic diagram of a process for preparing a power device provided in an embodiment;

[0019] Figure 2 A schematic diagram of a longitudinal cross-section of a structure obtained in step S4000 of a method for preparing an alignment pattern provided in an embodiment;

[0020] Figure 3 Schematic diagram of the structure obtained in step S5000 of the alignment pattern preparation method provided in one embodiment Figure 1 ;

[0021] Figure 4 Schematic diagram of the structure obtained in step S5000 of the alignment pattern preparation method provided in one embodiment Figure 2 ;

[0022] Figure 5 Schematic diagram of the structure obtained in step S5000 of the alignment pattern preparation method provided in one embodiment Figure 3 ;

[0023] Figure 6 Schematic diagram of the structure obtained in step S5000 of the alignment pattern preparation method provided in one embodiment Figure 4 .

[0024] Description of reference numerals:

[0025] 201, metal drain; 202, substrate of the first ion type; 203, epitaxial layer of the first ion type; 204, well region of the second ion type; 205, switch ratio adjustment region; 301, blocking layer; 401, gate oxide layer; 402, polysilicon layer; 501, air adjustment region. DETAILED DESCRIPTION

[0026] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0028] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0029] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0030] When used herein, the singular forms "a", "an" and " / the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of features, integers, steps, operations, elements and / or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0031] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0032] Please refer to Figure 1-Figure 6 The present disclosure provides a method for preparing a power device, comprising the following steps:

[0033] Step S1000: providing a metal drain 201 .

[0034] Step S2000 : forming a first ion type substrate 202 on the metal drain 201 .

[0035] Step S3000 : forming an epitaxial layer 203 of the first ion type on the substrate 202 of the first ion type.

[0036] Step S4000 : forming source electrodes on two opposite sides of the top of the first ion type epitaxial layer 203 .

[0037] The source electrode covers a portion of the top surface of the first ion type epitaxial layer 203 .

[0038] Step S5000 : forming a gate on a portion of the first ion type epitaxial layer 203 that is not covered by the source.

[0039] The gate portion is in contact with the top of the first ion type epitaxial layer 203 , and an air conditioning region 501 is formed at the bottom of the gate.

[0040] As an example, the first ion type may be N-type, and the second ion type may be P-type.

[0041] As an example, please refer to Figure 1-Figure 6 The first ion type substrate 202, the first ion type epitaxial layer 203 and the source electrode can be formed by ion implantation and the like. Specifically, the ion implantation methods include but are not limited to conventional ion implantation (Beamline Ion Implantation), plasma immersion ion implantation (Plasma Immersion Ion Implantation, PIII), molecular ion implantation (Molecular Ion Implantation), and the like.

[0042] In the above embodiment, by adding the air conditioning area 501 between the gate and the drain, at least the parasitic capacitance can be reduced, and the operating frequency of the power device can be increased without affecting the on-resistance of the power device.

[0043] In some embodiments, please refer to Figure 2 The source includes: a well region 204 of the second ion type and a switch ratio adjustment region 205, wherein the switch ratio adjustment region 205 is located in the well region 204 of the second ion type and covers a portion of the top surface of the epitaxial layer 203 of the first ion type.

[0044] In some embodiments, the gate includes a gate oxide layer 401 and a polysilicon layer 402 , and the polysilicon layer 402 is located on the gate oxide layer 401 .

[0045] Please continue to refer to Figure 1-Figure 6 The larger the gate-source capacitance, the stronger the control ability over the P-well and the lower the power consumption; the smaller the gate-drain capacitance, the larger the switching ratio, the faster the response speed and the higher the device frequency.

[0046] Specifically, the gate is the main position for controlling the well region 204 of the second ion type near the source, and the middle position of the gate has almost no effect on the on and off of the well region 204 of the second ion type. However, the area directly facing the entire lower surface of the gate and the epitaxial layer 203 of the first ion type affects the gate-drain capacitance. Therefore, increasing the distance between the middle position of the gate and the epitaxial layer 203 of the first ion type can effectively reduce the gate-drain (Cgd0) capacitance, while having a smaller impact on the gate-source capacitance.

[0047] In step S4000, please refer to Figure 2 , forming Figure 2The steps of the basic structure of the power device shown may include: substrate selection and wafer preparation, epitaxial layer growth, lithography and patterning, doping process, dielectric isolation and passivation, metallization and interconnection, etc., wherein the substrate material can be selected according to the device requirements, for example: traditional materials such as silicon (Si), which are low-cost and suitable for medium and low voltage applications; wide bandgap materials such as silicon carbide (SiC) or gallium nitride (GaN), which are suitable for high-frequency, high-temperature, and high-power scenarios, and may also include cleaning and polishing the wafer to remove surface impurities and defects; it may also include growing a high-quality single crystal layer on the substrate to form a drift region (Drift region) of the device. Region); power devices require thicker drift regions (such as tens of microns) to improve withstand voltage; may also include regulating the resistivity and carrier concentration of the epitaxial layer through gas phase doping (such as phosphorus and boron); may also include using photoresist and mask to define device structures (such as gate, source, body region, etc.); may also include trench structures (Trench) for reducing on-resistance (such as trench MOSFET); may also include alternately doped P / N column structures to optimize the balance between withstand voltage and conduction loss (Super junction) Junction); may also include forming the source region, body region, drain region, etc. of the device by high-energy ion implantation, which may require multiple implantations and annealing to accurately control the doping distribution; high-temperature annealing to activate the doped atoms and repair lattice damage and other processes; may also include LOCOS (local oxidation) for electrical isolation between devices; high-voltage isolation is achieved by etching deep grooves and filling oxides; may also include depositing silicon nitride or polyimide layers to protect the surface of the device to prevent leakage and contamination; may also include forming ohmic contacts by sputtering or evaporating metals such as aluminum and copper, and after thinning the wafer, depositing a thick metal layer (such as Ti / Ni / Ag) on ​​the back to reduce the on-resistance and improve heat dissipation; may also include connecting the various parts of the device using copper or aluminum metal layers and other process steps.

[0048] Due to the above formation Figure 2 The steps of the basic structure of the power device shown can be formed according to the experience of those skilled in the art and will not be described in detail here.

[0049] In some embodiments, a gate is formed on a portion of the first ion type epitaxial layer 203 not covered by the source, including: forming a blocking layer 301 on the first ion type epitaxial layer 203, the blocking layer 301 covering a portion of the first ion type epitaxial layer 203 not covered by the source; depositing a gate oxide layer 401 and a polysilicon layer 402 on the blocking layer 301 and the first ion type epitaxial layer 203; removing the blocking layer 301, the gate oxide layer 401 and the polysilicon layer 402 on the source to form a gate.

[0050] Wherein, the barrier layer 301 may be TiN.

[0051] For details, please refer to Figure 3 , Figure 3 The structure formed after forming the barrier layer 301 on the epitaxial layer 203 of the first ion type, as an example, TiN can be formed by the following methods: physical vapor deposition (PVD) can be used to sputter (such as magnetron sputtering) a titanium target in an inert gas (such as Ar) and a reaction gas (N 2 ) in a mixed atmosphere, the deposition rate is fast, the film is dense, the resistivity is low, the process is mature, and it is suitable for large-area uniform deposition; chemical vapor deposition (CVD) can be used to generate TiN through gas phase chemical reaction. Common precursors are TiCl 4 With NH 3 , TiN is generated by reaction at high temperature; plasma enhanced CVD (PECVD) can be used to activate the reaction by plasma to reduce the temperature (<500°C); organic titanium precursors (such as TDMAT) can be used to reduce the process temperature; atomic layer deposition (ALD) can be used to alternately introduce titanium precursors (such as TDMAT) and nitrogen-containing reactants (such as NH 3 or plasma N 2 / H 2 ), TiN is grown layer by layer; Reactive sputtering can be used to introduce N while sputtering the titanium target. 2 Titanium atoms react with nitrogen on the substrate surface to form TiN; nitridation annealing can be used to anneal the deposited titanium film in a nitrogen-containing atmosphere (such as NH 3 or N 2 ) is annealed at medium and high temperatures to form TiN.

[0052] For details, please refer to Figure 4 , Figure 4 The structure is obtained after a gate oxide layer 401 and a polysilicon layer 402 are deposited on the barrier layer 301 and the first ion type epitaxial layer 203. Specifically, the gate oxide layer 401 is usually silicon dioxide (SiO 2 ) or high dielectric constant (High-κ) materials (such as HfO 2 、Al 2 O 3 ), which serves as an insulating layer between the gate and the channel. The deposition methods of the gate oxide layer 401 mainly include: thermal oxidation, the principle of which is that the silicon substrate is heated to 800°C~1200°C and then reacted with oxygen (O 2 ) or water vapor (H 2 O) to form SiO 2 layer, dry oxygen oxidation (Dry Oxidation), which is O 2atmosphere to generate a dense and high-quality oxide layer (with precise thickness control but slow speed), wet oxidation (Wet Oxidation): H 2 O atmosphere has a fast oxidation rate but slightly more interface defects. As an example, temperature and time determine the thickness, and annealing is required after oxidation to reduce the interface state charge (Q tt ). Atomic layer deposition (ALD, Atomic Layer Deposition) can also be used to deposit atomically uniform high-κ materials (such as HfO 2 ) layer by layer, which is suitable for advanced nodes (such as FinFET, GAA); chemical vapor deposition (CVD) can also be used to deposit SiO 4 through a gas-phase reaction (such as SiH 2 + O 2 → SiO 2 + 2H 2 ). Specifically, the deposition of the polysilicon layer 402 (Poly-Si) requires a controllable doping concentration and low resistivity. The deposition method can be low-pressure chemical vapor deposition (LPCVD) by thermally decomposing silane (SiH 4 ) at a high temperature (600°C - 650°C) to deposit the polysilicon layer 402. During the deposition process, PH 3 (N-type) or B 2 H 6 (P-type) is introduced to directly form doped polysilicon. After depositing undoped polysilicon, doping is performed by ion implantation and activated at a high temperature. Physical vapor deposition (PVD) technology can also be used for special requirements (such as ultra-thin layers), but the step coverage is poor. The interface between the gate oxide layer 401 and the silicon substrate requires a low defect density (optimized by in-situ cleaning and annealing). Precise control of temperature, pressure, and gas flow is required for ALD and LPCVD to ensure that the thickness deviation across the entire wafer is <±2%. During in-situ doping, the concentration gradient of the gas-phase dopant needs to be prevented. To avoid metal contamination (such as Na⁺, Fe⁺), high-purity gases and chamber cleaning processes are required.

[0053] Here, the present application does not limit the deposition methods of the gate oxide layer 401 and the polysilicon layer 402, and those skilled in the art can select the specific processes for depositing the gate oxide layer 401 and the polysilicon layer 402 according to requirements.

[0054] In some embodiments, the steps of removing the barrier layer 301, the gate oxide layer 401, and the polysilicon layer 402 on the source include: removing the polysilicon layer 402 on the source; removing the barrier layer 301; removing the gate oxide layer 401 on the source.

[0055] Here, when removing the gate oxide layer 401 and the polysilicon layer 402, the same photomask can be used, thereby reducing the consumption of photomasks.

[0056] As an example, removing the polysilicon layer 402 on the source includes: forming a sacrificial layer covering the polysilicon layer 402, and a patterned photoresist layer covering the sacrificial layer; using the patterned photoresist layer as a mask to pattern the sacrificial layer; using the patterned sacrificial layer as a mask and the gate oxide layer 401 as an etching end point to etch and remove the polysilicon layer 402 on the source.

[0057] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0058] Based on the same inventive concept, the embodiment of the present disclosure also provides a power device obtained based on the method for preparing the power device in the above embodiment. The implementation scheme for solving the problem provided by the power device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more power device embodiments provided below can refer to the limitations of the alignment pattern preparation method above, and will not be repeated here.

[0059] In some embodiments, please refer to Figure 6 A power device includes: a metal drain 201; a first ion type substrate 202, located on the metal drain 201; a first ion type epitaxial layer 203, located on the first ion type substrate 202; a source, located on two opposite sides of the top of the first ion type epitaxial layer 203, the source covering a portion of the top surface of the first ion type epitaxial layer 203; a gate, located on a portion of the first ion type epitaxial layer 203 not covered by the source, the gate portion contacts the top of the first ion type epitaxial layer 203, and an air conditioning area 501 is formed at the bottom of the gate.

[0060] In the power device in the above embodiment, by adding the air conditioning area 501 between the gate and the drain, at least the parasitic capacitance can be reduced, and the operating frequency of the power device can be increased without affecting the on-resistance of the power device.

[0061] In one embodiment, the source includes: a well region 204 of the second ion type and a switch ratio adjustment region 205, wherein the switch ratio adjustment region 205 is located in the well region 204 of the second ion type and covers a portion of the top surface of the epitaxial layer 203 of the first ion type.

[0062] In one embodiment, the gate includes a gate oxide layer 401 and a polysilicon layer 402 , and the polysilicon layer 402 is located on the gate oxide layer 401 .

[0063] In some embodiments, the embodiments of the present disclosure further provide a semiconductor device, including: the power device in any of the above embodiments, which can at least reduce parasitic capacitance, increase the operating frequency of the power device and not affect the on-resistance of the power device.

[0064] In some embodiments, the present disclosure also provides a memory, including: the semiconductor device in any of the above embodiments.

[0065] In some embodiments, the present disclosure provides an electronic device, including a memory as described in any one of the embodiments of the present disclosure; or a semiconductor device as described in any one of the embodiments of the present disclosure. The electronic device is, for example but not limited to, suitable types of electronic products such as consumer electronic products, home electronic products, vehicle-mounted electronic products, and financial terminal products. Consumer electronic products include mobile phones, tablet computers, laptop computers, desktop monitors, all-in-one computers, etc. Home electronic products include smart door locks, televisions, refrigerators, wearable devices, etc. Vehicle-mounted electronic products include vehicle-mounted navigation systems, vehicle-mounted DVDs, etc. Financial terminal products include ATM machines, self-service terminals, etc.

[0066] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0067] The above embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A power device, characterized in that: include: Metal drain; A substrate of a first ion type, located on the metal drain; An epitaxial layer of a first ion type, located on a substrate of the first ion type; A source electrode, located at two opposite sides of the top of the epitaxial layer of the first ion type, the source electrode covering a portion of the top surface of the epitaxial layer of the first ion type; The gate is located on a portion of the epitaxial layer of the first ion type that is not covered by the source electrode, the gate portion contacts the top of the epitaxial layer of the first ion type, and an air conditioning area is formed at the bottom of the gate.

2. The power device according to claim 1, characterized in that: The source comprises: A well region of the second ion type and a switch ratio adjustment region, wherein the switch ratio adjustment region is located in the well region of the second ion type and covers a portion of the top surface of the epitaxial layer of the first ion type.

3. The power device according to claim 1, characterized in that: The gate includes a gate oxide layer and a polysilicon layer, and the polysilicon layer is located on the gate oxide layer.

4. A semiconductor device, characterized in that: include: A power device as claimed in any one of claims 1 to 3.

5. A memory, characterized in that: include: The semiconductor device according to claim 4.

6. An electronic device, characterized in that: include: The semiconductor device according to claim 4; or The memory as claimed in claim 5.

7. A method for preparing a power device, characterized in that: include: providing a metal drain; forming a substrate of a first ion type on the metal drain; forming an epitaxial layer of the first ion type on the substrate of the first ion type; forming source electrodes on two opposite sides of the top of the epitaxial layer of the first ion type, wherein the source electrodes cover a portion of the top surface of the epitaxial layer of the first ion type; A gate is formed on a portion of the first ion type epitaxial layer not covered by the source electrode, wherein the gate portion contacts the top of the first ion type epitaxial layer, and an air conditioning region is formed at the bottom of the gate.

8. The method according to claim 7, characterized in that Forming a gate on a portion of the epitaxial layer of the first ion type that is not covered by the source electrode, comprising: forming a barrier layer on the epitaxial layer of the first ion type, wherein the barrier layer covers a portion of the epitaxial layer of the first ion type that is not covered by the source electrode; Depositing a gate oxide layer and a polysilicon layer on the barrier layer and the first ion type epitaxial layer; The barrier layer, the gate oxide layer and the polysilicon layer on the source are removed to form a gate.

9. The method according to claim 8, characterized in that The steps of removing the barrier layer, the gate oxide layer and the polysilicon layer on the source electrode include: removing the polysilicon layer on the source electrode; Removing barrier layers; Remove the gate oxide layer on the source.

10. The method according to claim 9, characterized in that Removing the polysilicon layer on the source, including: forming a sacrificial layer covering the polysilicon layer, and a patterned photoresist layer covering the sacrificial layer; Using the patterned photoresist layer as a mask, patterning the sacrificial layer; The patterned sacrificial layer is used as a mask, and the gate oxide layer is used as an etching end point to etch and remove the polysilicon layer on the source electrode.

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