Semiconductor device and manufacturing method thereof

Abstract

A method of fabricating a semiconductor device includes providing a partially fabricated semiconductor device including a dummy gate structure disposed over a semiconductor layer stack. In some embodiments, the method further includes removing the dummy gate structure and at least a portion of each semiconductor layer of the semiconductor layer stack to form a trench. In some examples, the method further includes forming one or more refill layers in a bottom portion of the trench, and forming one or more refill layers in a top portion of the trench above the bottom portion of the trench. In some embodiments, one or more refill layers in the top and bottom portions of the trench define top and bottom portions of the isolation structure, respectively. In some examples, the at least one refill layer of the respective top and bottom portions of the isolation structure has different material compositions. The embodiment of the invention also relates to a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] The electronics industry has experienced an increasing demand for smaller and faster electronic devices that can simultaneously support more and more complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by scaling down semiconductor IC sizes (e.g., minimum component size) and thereby increasing production efficiency and reducing associated costs. However, this scaling has also increased the complexity of semiconductor manufacturing processes. Therefore, achieving continued advancements in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies.

[0003] As an example, in order to continue to provide the desired scaling and increased density for semiconductor devices in advanced technology nodes, it is necessary to continue to reduce the contact polysilicon pitch (CPP) (or "gate pitch"). In at least some prior implementations, the continuous polysilicon on diffusion edge (CPODE) process has been used to scale the CPP. For example, the CPODE process can be used to provide isolation between adjacent active regions (e.g., device regions including source, drain, and gate structures). However, in some prior implementations, the CPODE region can be formed in a manner that causes undesirable leakage currents, thereby undermining the ability of the CPODE region to provide electrical isolation and, more generally, compromising device performance and reliability. Therefore, the prior art has not proven to be completely satisfactory in all respects. Summary of the invention

[0004] An embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising: providing a partially manufactured semiconductor device, the partially manufactured semiconductor device comprising a dummy gate structure disposed above a semiconductor layer stack; removing at least a portion of the dummy gate structure and each semiconductor layer of the semiconductor layer stack to form a trench; forming one or more refill layers in a bottom portion of the trench; and forming one or more refill layers in a top portion of the trench above the bottom portion of the trench, wherein the one or more refill layers in the top portion and the bottom portion of the trench respectively define a top portion and a bottom portion of an isolation structure, and wherein at least one refill layer of the corresponding top portion and bottom portion of the isolation structure has different material compositions.

[0005] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, comprising: forming a trench passing through a dummy device structure in an isolation region of a substrate; forming a first refill layer and a sacrificial layer in a bottom portion of the trench, the sacrificial layer being located above the first refill layer; after removing the sacrificial layer to expose the first refill layer, conformally depositing a second refill layer in the bottom portion of the trench above the exposed first refill layer and in a top portion of the trench; and forming a third refill layer in the top portion and the bottom portion of the trench including above the second refill layer, wherein the first refill layer, the second refill layer, and the third refill layer in the top portion and the bottom portion of the trench provide an isolation structure in the isolation region, and wherein the first refill layer is composed of a material different from at least one of the second refill layer and the third refill layer.

[0006] Another embodiment of the present disclosure provides a semiconductor device, comprising: an active region including a transistor; and an isolation structure, arranged in an isolation region defined at a boundary of the active region; wherein the isolation structure comprises a bottom portion and a top portion, the bottom portion comprising a first refill layer, the top portion being arranged above the bottom portion, the top portion comprising one or more refill layers; wherein the first refill layer is composed of a material different from at least one of the one or more refill layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A simplified top-down layout diagram of a multi-gate device according to one or more aspects of the present disclosure is shown;

[0009] Figure 2A and Figure 3A According to some embodiments, a Figure 1 A cross-sectional view of an exemplary semiconductor device embodiment in which a plane defined by section YY' is substantially parallel to a plane;

[0010] Figure 2B and Figure 3B According to some embodiments, a Figure 1 A cross-sectional view of an embodiment of an exemplary semiconductor device in which a plane defined by a cross section XX' is substantially parallel to a plane;

[0011] Figure 4is a flow chart of a method of manufacturing a multi-gate device according to one or more aspects of the present disclosure;

[0012] Figure 5 , Figure 6 , Figure 7 and Figure 8 Provided based on Figure 4 The various stages of the method are followed by Figure 1 A cross-sectional view of an embodiment of a semiconductor device in which a plane defined by section XX' is substantially parallel to a plane;

[0013] Fig. 9A , Fig. 9B , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 and Fig.15 Provided based on Figure 4 Various embodiments of the method are manufactured along with Figure 1 Cross-sectional views of various alternative embodiments of semiconductor devices wherein the plane defined by the cross section XX' is substantially parallel to the plane;

[0014] Fig.16 is a flow chart of another method of manufacturing a multi-gate device according to one or more aspects of the present disclosure;

[0015] Fig.17 , Fig.18 , Fig.19 , Fig. 20 and Fig.21 Provided based on Fig.16 The various stages of the method are followed by Figure 1 A cross-sectional view of an embodiment of the semiconductor device wherein the plane defined by the section XX' is substantially parallel to the plane; and

[0016] Fig. 22 , Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig. 27 and Fig.28 Provided based on Fig.16 Various embodiments of the method are manufactured along with Figure 1 A cross-sectional view of various alternative embodiments of the semiconductor device wherein the plane defined by the cross section XX' is substantially parallel to the plane. DETAILED DESCRIPTION

[0017] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the embodiments and / or configurations discussed.

[0018] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0019] In addition, when "about", "approximately", etc. are used to describe a numerical value or a range of values, the term is intended to cover values ​​within a reasonable range, taking into account the inherent variations during manufacturing as understood by those of ordinary skill in the art. For example, based on the known manufacturing tolerances for manufacturing components having characteristics associated with the numerical value, the numerical value or range of values ​​covers a reasonable range including the described numerical value, such as within + / -10% of the described numerical value. For example, a material layer with a thickness of "about 5nm" can cover a size range from 4.25nm to 5.75nm, where the manufacturing tolerance associated with the deposited material layer is known to those of ordinary skill in the art to be + / -15%. In addition, the disclosed dimensions of different components can implicitly disclose the size ratios between different components. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the embodiments and / or configurations discussed.

[0020] It should also be noted that the present disclosure presents embodiments in the form of multi-gate transistors. Multi-gate transistors include those transistors whose gate structures are formed on at least two sides of the channel region. These multi-gate devices may include P-type metal oxide semiconductor devices or N-type metal oxide semiconductor multi-gate devices. Due to their fin-like structures, specific examples may be presented herein as and referred to as fin field effect transistors (FinFETs). Embodiments of the type of multi-gate transistors referred to as full-all-around gate (GAA) devices are also presented herein. GAA devices include any device whose gate structure or part thereof is formed on the 4 sides of the channel region (e.g., surrounding the portion of the channel region). The devices presented herein also include embodiments having channel regions arranged in nanosheet channels, nanowire channels, strip channels, and / or other suitable channel configurations. Embodiments of devices that may have one or more channel regions (e.g., nanowires / nanosheets) associated with a single continuous gate structure are presented herein. However, those of ordinary skill in the art will recognize that the teachings may be applied to a single channel (e.g., a single nanowire / nanosheet) or any number of channels. Those of ordinary skill in the art may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure. For example, in some cases, aspects of the present disclosure may be equally applicable to planar transistor devices, cross-plane devices, complementary FET (CFET) devices, and the like.

[0021] Continuing to provide the desired scaling and increased density for semiconductor devices in advanced technology nodes requires scaling the contact polysilicon pitch (CPP) (or "gate pitch"). In at least some existing embodiments, a continuous polysilicon on diffusion edge (CPODE) process has been used to scale the CPP. For purposes of the present disclosure, a "diffusion edge" may be equivalently referred to as an active edge, where, for example, the active edge abuts an adjacent active area. In addition, the active area includes an area where transistor structures (e.g., including a source, a drain, and a gate / channel structure) are formed. In some examples, the active area may be disposed between insulating regions. By performing a dry etching process along the active edge (e.g., at the boundary of adjacent active areas) to form a cut region and filling the cut region with a dielectric such as silicon nitride (SiN), the CPODE process can provide an isolation region (or dielectric plug) between adjacent active regions, and thus provide an isolation region between adjacent transistors.

[0022] For example, and in accordance with at least one embodiment of the CPODE process, a CPODE dry etching process can be performed along an active edge including a dummy device structure (e.g., such as a dummy gate stack and a plurality of channels). In particular, a CPODE dry etching process can be performed to form a cut region along the active edge, the cut region including a groove formed along the active edge. After the grooves are formed in the cut region, a refill process is performed, wherein a refill dielectric (e.g., such as SiN or a SiN-like dielectric) is used to fill the grooves in the cut region. In some cases, the interface between the semiconductor substrate and the refill dielectric can induce a fixed charge, which in turn can cause an undesirable leakage current. In other words, the refill dielectric (e.g., SiN or a SiN-like dielectric) can attract charge, and unwanted leakage current may flow in the semiconductor substrate below. As a result, the device performance and reliability of the transistor formed in the adjacent active region may be reduced. In some examples, a thick no-fixed-charge layer (e.g., such as a SiO layer or a SiO-like layer) may be formed as a liner layer within the trenches of the cut region prior to depositing the SiN refill dielectric in an attempt to mitigate leakage current between the semiconductor substrate and the refill dielectric. However, in various cases, the thick no-fixed-charge layer may be easily consumed by exposure to a post-wet cleaning process (e.g., such as a process that may be performed during removal of a dummy polysilicon gate), resulting in the formation of voids, which may cause yield or reliability issues. Therefore, the prior art has not proven to be completely satisfactory in all respects.

[0023] Embodiments of the present disclosure provide advantages over the prior art, but it should be understood that other embodiments may provide different advantages, not all advantages must be discussed herein, and no particular advantage is required by all embodiments. For example, the embodiments discussed herein include structures and related methods of forming CPODE structures (or dielectric plugs) in which multiple dielectric layers of different material components are stacked at least partially in a vertical direction to provide leakage current reduction (e.g., at the interface between the substrate and the bottom of the CPODE structure). In an example, the CPODE refill material (bottom CPODE refill material) used to refill the bottom portion of the CPODE structure may include a single layer or multiple layers and is selected to include a non-fixed charge material. In some embodiments, the CPODE refill material (top CPODE refill material) and / or the number of layers used to refill the top portion of the CPODE structure may be different from the bottom CPODE refill material and / or the number of layers. It is certain that in some cases, the bottom CPODE refill material and the top CPODE refill material may both include at least one layer formed of the same material. In some embodiments, the bottom CPODE refill material includes a SiO-like material, and the top CPODE refill material includes a SiN-like material. In some embodiments, the bottom CPODE refill material can be buried below a plane defined by the top surface of an adjacent shallow trench isolation (STI) region, and the overall depth of the disclosed CPODE structure can be deeper than the adjacent STI region (or shallower than the adjacent STI region in some cases). In various examples, the bottom CPODE refill material is selected to provide leakage current reduction, and the top CPODE refill material is selected to mitigate losses (e.g., such as losses that may occur in existing embodiments during removal of the pseudo-polysilicon gate). By adopting the disclosed CPODE process and related structures, the device performance and reliability of transistors formed in adjacent active regions will be improved. In addition, the disclosed embodiments are compatible with existing processes and can be implemented with minimal additional cost. After reading this disclosure, other embodiments and advantages will be clear to those skilled in the art.

[0024] As previously mentioned, embodiments of the present disclosure may be applicable to various types of devices, such as planar transistor devices, FinFET devices, GAA devices, fork-plane devices, CFET devices, etc. However, for clarity of discussion, aspects of the disclosed embodiments will be discussed with reference to exemplary multi-gate devices, such as shown and described below. For example, Figure 1A simplified top-down layout diagram of a multi-gate device 100 is provided. For the purposes of this discussion, the multi-gate device 100 may include a FinFET device, a GAA transistor, or other type of multi-gate device. The multi-gate device 100 may include a plurality of fin elements 104 extending from a substrate, gate structures 108, 110 disposed above and around the fin elements 104, and source / drain regions 105 (e.g., formed in, on, and / or around the fins 104). In some cases, the gate structure 110 may include a dummy gate structure formed along an active edge. In an example, the multi-gate device 100 also includes a cut metal gate (CMG) region 112, which provides isolation between metal layers of adjacent structures (e.g., on either side of the CMG region 112). The multi-gate device 100 may also include a CPODE region 114, which includes a CPCODE structure, disposed along an active edge and at least partially overlapping the dummy gate structure (gate structure 110). The CPODE region 114 and the CPODE structure formed therein can provide an isolation region (or dielectric plug) between adjacent active regions (e.g., such as regions located on either side of the CPODE region 114). In at least some cases, the CMG region 112 can overlap the CPODE region 114, as shown. The channel region of the multi-gate device 100 (which can include multiple semiconductor channel layers (e.g., when the multi-gate device 100 includes a GAA transistor)) is disposed within the fin 104, below the gate structure 108, and along the same plane as the active region 114 formed by the CMG region 112. Figure 1 The plane defined by the cross section XX' is substantially parallel to the plane. In some embodiments, sidewall spacers may also be formed on the sidewalls of the gate structures 108, 110. Although some examples of configurations of the CMG region 112 and the CPODE region 114 have been given, it will be understood that other configurations are possible while still within the scope of the present disclosure. Figure 4 and Fig.16 Various other components of the multi-gate device 100 are discussed in greater detail in the method of FIG.

[0025] According to an embodiment of the present disclosure, Figure 4 and Fig.16 The method can be implemented or modified in various ways to manufacture semiconductor devices having CPODE structures with various configurations. Figure 4 and Fig.16 Before we start with the method, and to provide background for the discussion, we first refer to Figure 2A / Figure 2B and Figure 3A / Figure 3B , which respectively provide different configurations including CPODE structures and according to different embodiments of the disclosed method (e.g., such as Figure 4 and Fig.16Exemplary embodiments of semiconductor devices 200 and 300 fabricated by methods of the type described hereinabove) are described in more detail below. Figure 2A and Figure 3A Provided along with Figure 1 The cross-sectional view of the embodiment of the semiconductor device 200 , 300 is a plane defined by the plane YY′ that is substantially parallel to the plane. Figure 2B and Figure 3B Provided along with Figure 1 The cross-sectional view of the embodiment of the semiconductor device 200 , 300 is a plane in which the plane defined by the cross section XX′ is substantially parallel to the plane.

[0026] like Figure 2B and Figure 3B As shown, the semiconductor devices 200 and 300 include a first active region 203, a second active region 205, and an active edge 207, wherein the active edge 207 is defined at a boundary between the first active region 203 and the second active region 205. In some embodiments, the first active region 203 includes a first GAA device 209, the second active region 205 includes a second GAA device (not shown), the active edge 207 of the semiconductor device 200 includes a CPODE structure 213, and the active edge 207 of the semiconductor device 300 includes a CPODE structure 313. Each of the CPODE structures 213 and 313 provides an isolation region between the first active region 203 and the second active region 205 for the first semiconductor device 200 and the second semiconductor device 300, respectively. As described in more detail below, the CPODE structures 213, 313 may be formed by performing a dry etching process along the active edge 207 and through the pseudo GAA structure disposed along the active edge 207 to form a cut region and fill the cut region with a plurality of dielectric layers of different material compositions at least partially stacked in a vertical direction. Additionally, in some embodiments, the CPODE structures 213, 313 (as well as other CPODE structures discussed below) may include a CPODE structure formed in a CPODE region (such as the CPODE region 114 discussed above).

[0027] Each GAA device formed in the first active area 203 and the second active area 205 and the CPODE structure 213, 313 are formed on a substrate 202 having a fin 204. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon substrate. The substrate 202 may include various layers, including a conductive layer or an insulating layer formed on the semiconductor substrate. Depending on the design requirements known in the art, the substrate 202 may include various doping configurations. The substrate 202 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Optionally, the substrate 202 may include a compound semiconductor and / or an alloy semiconductor. In addition, the substrate 202 may optionally include an epitaxial layer, may be strained for performance enhancement, may include a silicon on insulator (SOI) structure, and / or have other suitable enhancement components.

[0028] The fin 204 may include a nanosheet channel layer 206. In some embodiments, the nanosheet channel layer 206 may include silicon (Si). However, in some embodiments, the nanosheet channel layer 206 may include other materials, such as germanium, a compound semiconductor (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), an alloy semiconductor (such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP), or a combination thereof. For example, the nanosheet channel layer 206 may be epitaxially grown by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0029] From an end view of the nanosheet channel layer 206 (eg, Figure 2A and Figure 3A ) Referring to the X dimension and Y dimension of the nanosheet channel layer 206, the X dimension may be equal to about 5-14 nm, and the Y dimension may be equal to about 5-8 nm. In some cases, the X dimension of the nanosheet channel layer 206 is substantially the same as the Y dimension of the nanosheet channel layer 206. For example, when the X dimension is greater than the Y dimension, the nanosheet channel layer 206 may be referred to as a "nanosheet". In some cases, the spacing between adjacent nanosheet channel layers 206 (e.g., along the Y direction) is equal to about 4-8 nm.

[0030] In various embodiments, each fin 204 includes a substrate portion 202A formed from the substrate 202 and a nanosheet channel layer 206. It should be noted that while the fin 204 is shown as including three (3) nanosheet channel layers 206, this is for illustrative purposes only and is not intended to limit the specific references in the claims. It is understood that any number of nanosheet channel layers 206 may be formed, where, for example, the number of nanosheet channel layers 206 depends on the desired number of channel regions of the GAA device (e.g., the device formed in each of the first active region 203 and the second active region 205). In some embodiments, the number of nanosheet channel layers 206 is between 3 and 10.

[0031] Shallow trench isolation (STI) features 217 may also be formed between the fins 204. In some embodiments, the STI features 217 include SiO 2 , silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-K dielectrics, combinations thereof, and / or other suitable materials known in the art. In various examples, the dielectric layer used to form STI features 217 can be deposited by a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, and / or other suitable processes.

[0032] In various examples, the device formed in each of the first active region 203 and the second active region 205 also includes a gate structure, which may include a high-K / metal gate stack. In some embodiments, the gate structure may form a gate associated with a multi-channel provided by a nanosheet channel layer 206 in a channel region of a corresponding GAA device. The gate structure may include a gate dielectric 208, which includes an interface layer (IL) and a high-K gate dielectric layer formed above the interface layer. In some embodiments, the total thickness of the gate dielectric 208 is about 1-5nm. As used and described herein, the high-K gate dielectric includes a dielectric material having a high dielectric constant, for example, a dielectric constant greater than that of thermal silicon oxide (~3.9).

[0033] In some embodiments, the interfacial layer of the gate dielectric 208 may include a silicon oxide (SiO 2 ), HfSiO, or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. In some examples, the interfacial layer includes the chemical oxide layer discussed above. The high-K gate dielectric layer of the gate dielectric 208 may include a high-K dielectric material, such as hafnium oxide (HfO 2 Alternatively, the high-K gate dielectric layer may include other high-K dielectric materials, such as TiO 2、HfZrO、Ta 2 O 3 、HfSiO 4 、ZrO 2 、ZrSiO 2 、LaO、AlO、ZrO、TiO、Ta 2 O 5 , Y 2 O 3 、SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfLiO, (Ba,Sr)TiO 3 (BST), Al 2 O 3 、Si 3 N 4 , oxynitride (SiON), combinations thereof, or other suitable materials. The high-K gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0034] The gate structure may also include a metal gate formed above the gate dielectric 208, the metal gate having a metal layer 212. The metal layer 212 may include a metal, a metal alloy, or a metal silicide. The metal layer 212 may include a single layer or an optional multilayer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy, or various combinations of metal silicides. For example, the metal layer 212 may include Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metal materials, or combinations thereof. In various embodiments, the metal layer 212 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In addition, the metal layer 212 may be formed separately for N-type transistors and P-type transistors, and different metal layers may be used for N-type transistors and P-type transistors. In addition, the metal layer 212 can provide an N-type or P-type work function, can be used as a transistor gate electrode, and in at least some embodiments, the metal layer 212 can include a polysilicon layer. Figure 2B and Figure 3BAs shown, the gate structure includes a portion between each nanosheet channel layer 206 of the fin 204, wherein each of the nanosheet channel layers 206 provides a semiconductor channel layer for a device formed in each of the first active region 203 and the second active region 205. In addition, in some examples, another metal layer (e.g., such as a selectively grown tungsten (W) layer) can be formed over the metal layer 212. In some cases, the selectively grown W layer can include a fluorine-free W (FFW) layer. In various examples, the selectively grown W layer can be used as an etch stop layer and can also provide reduced contact resistance (e.g., to the metal layer 212).

[0035] In some embodiments, the spacer layer 215 can be formed on the sidewalls of the top portion of the gate structure of each device (formed in each of the first active region 203 and the second active region 205), and on the pseudo GAA structure disposed along the active edge 207. The spacer layer 215 can be formed before forming the high-K / metal gate stack of the gate structure and before forming the CPODE structure 213, 313. For example, in some cases, the spacer layer 215 can be formed on the sidewalls of a previously formed dummy (sacrificial) gate stack that is removed and replaced by the above-mentioned high-K / metal gate stack as part of a replacement gate (last gate) process. In some cases, the spacer layer 215 can have a thickness of about 2-10 nm. In various embodiments, the thickness of the spacer layer 215 can be selected to provide a desired sidewall profile after the CPODE dry etching process, as discussed in more detail below. In some examples, the spacer layer 215 can include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, SiOHCN, a low-K material (e.g., having a dielectric constant "K" of <7), and / or combinations thereof. In some embodiments, the spacer layer 215 includes multiple layers, such as a main spacer layer, a liner layer, etc.

[0036] In various examples, each device formed in each of the first active region 203 and the second active region 205 and the pseudo GAA structure disposed along the active edge 207 also includes an internal spacer 219. The internal spacer 219 can be disposed between adjacent channels of the nanosheet channel layer 206, at the lateral ends of the nanosheet channel layer 206, and in contact with a portion of the gate structure between each nanosheet channel layer 206 (or in contact with a portion of the CPODE structure 213, 313 along the active edge 207, as shown). In some embodiments, the internal spacer 219 includes amorphous silicon. In some examples, the internal spacer 219 can include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, low-K materials (e.g., having a dielectric constant "K" of <7) and / or combinations thereof. In various examples, the internal spacer 219 can extend below the spacer layer 215 described above while abutting adjacent source / drain features described below.

[0037] In some embodiments, source / drain features 221 are formed in source / drain regions adjacent to and on either side of the gate structure of each device (formed in each of the first active region 203 and the second active region 205 and located above the substrate portion 202A). As a result, the CPODE structures 213, 313 along the active edge 207 are disposed between the first source / drain feature 221 of the first device in the first active region 203 and the second source / drain feature 221 of the second device in the second active region 205. As shown, the source / drain features 221 of the devices formed in each of the first active region 203 and the second active region 205 are in contact with the internal spacers 219 and the nanosheet channel layer 206 of the corresponding devices formed in the first active region 203 and the second active region 205. In addition, the source / drain features 221 (formed in each of the first active area 203 and the second active area 205) disposed on either side of the active edge 207 are separated from the CPODE structures 213, 313 by the internal spacer 219 of the pseudo GAA structure previously formed along the active edge 207 and the portion of the nanosheet channel layer 206.

[0038] In various examples, the source / drain component 221 includes a semiconductor epitaxial layer, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP or other suitable materials, which can be formed by one or more epitaxial processes. In some embodiments, the source / drain component 221 can be in-situ doped during the epitaxial process. For example, in some embodiments, the epitaxially grown SiGe source / drain component can be doped with boron. In some cases, the epitaxially grown Si source / drain component can be doped with carbon to form a Si:C source / drain component, doped with phosphorus to form a Si:P source / drain component, or doped with carbon and phosphorus to form a SiCP source / drain component. In some embodiments, the source / drain component 221 is not doped in-situ, but an implantation process is performed to dope the source / drain component 221. In some embodiments, the formation of the source / drain component 221 can be performed in a separate processing sequence for each of the N-type and P-type source / drain components. Additionally, in some examples, an isolation layer 245 (e.g., such as a flexible bottom isolation layer) may be optionally formed below the source / drain features 221 and above the undoped layer 247. In an embodiment, the isolation layer 245 may be used to reduce leakage current and may include a dielectric layer such as SiN, SiON, SiOCN, SiOC, SiCN, SiO 2 、AlO x , HfO x Etc. In some examples, the undoped layer 247 may include an undoped Si layer or an undoped SiGe layer.

[0039] An interlayer dielectric (ILD) layer 223 may also be formed over the devices 200, 300. In some embodiments, a contact etch stop layer (CESL) 227 is formed over the devices 200, 300 before the ILD layer 223 is formed. In some examples, the CESL 227 includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other materials known in the art. The CESL 227 may be formed by a plasma enhanced chemical vapor deposition (PECVD) process and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 223 includes materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (such as borophosphosilicate glass (BPSG), FSG, phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials). The ILD layer 223 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, a hard mask layer (e.g., such as SiN) may be formed over the ILD layer 223.

[0040] In some embodiments, a CMG process may be performed to isolate the metal layer 212 of adjacent structures. As part of the CMG process, a photolithography and etching process may be performed to etch at least a portion of the metal layer 212, the dielectric layer 208, and the underlying STI features 217 in the CMG region 230 to form a trench that exposes the underlying STI features 217. A refill process is performed to form a dielectric layer 232 in the trench formed in the CMG region 230. Thus, the dielectric layer 232 electrically isolates the metal layer 212 of the adjacent structures. In some embodiments, the dielectric layer 232 includes a nitride layer, such as SiN. Alternatively, in some cases, the dielectric layer 232 may include SiO 2 , silicon oxynitride, FSG, low-k dielectrics, combinations thereof, and / or other suitable materials known in the art. In various examples, dielectric layer 232 can be deposited by a CVD process, a SACVD process, a flowable CVD process, an ALD process, a PVD process, and / or other suitable processes. Furthermore, in some embodiments, CMG region 230 can include CMG region 112 discussed above.

[0041] As shown, the CPODE structure 213 of the semiconductor device 200 includes a bottom portion 213B and a top portion 213T located above the bottom portion 213B. In various embodiments, each of the bottom portion 213B and the top portion 213T may include one or more refill material layers. In the illustrated example of the semiconductor device 200, the bottom portion 213B includes a single refill material layer 213B-1, and the top portion 213T includes a plurality of refill material layers 213T-1 and 213T-2. In various embodiments, the refill material layer 213B-1 may include SiO 2 , SiN, SiCN, SiCON, SiCO, SiON, AlO, HfO, another HK material (e.g., having a dielectric constant K of >=7), or a multilayer composite refill material consisting of a combination thereof. In some embodiments, the refill material layer 213B-1 can be described as including a SiO-like material. More generally, the refill material layer 213B-1 can include a non-fixed charge material for reducing leakage current. In some examples, the refill material layers 213T-1 and 213T-2 can also include SiO 2, SiN, SiCN, SiCON, SiCO, SiON, AlO, HfO, another HK material (e.g., having a dielectric constant K of >= 7), or a multilayer composite refill material consisting of a combination thereof. In some embodiments, the refill material layers 213T-1 and 213T-2 may be described as including SiN-like materials. In various examples, the refill material layer 213B-1 may be different from the refill material layers 213T-1 and 213T-2. As part of the CPODE process, in some embodiments, the formation of the CPODE structure 213 may generally include a dry etching process along the active edge 207, and through a pseudo GAA structure disposed along the active edge 207 to form a cutting area (e.g., including a trench); filling the cutting area (e.g., including filling the trench) with the refill material layer 213B-1 and performing an etch back process; and sequentially depositing the refill material layers 213T-1 and 213T-2. Refer to the following. Figure 4 Additional CPODE process details for forming the CPODE structure 213 are discussed in detail in the method of FIG.

[0042] The CPODE structure 313 of the semiconductor device 300 similarly includes a bottom portion 313B and a top portion 313T located above the bottom portion 313B. In various embodiments, each of the bottom portion 313B and the top portion 313T may include one or more refill material layers. In the illustrated example of the semiconductor device 300, the bottom portion 313B includes a plurality of refill material layers 313B-1, 313T-1, and 313T-2, and the top portion 313T includes a plurality of refill material layers 313T-1 and 313T-2. In various embodiments, each of the refill material layers 313B-1, 313T-1, and 313T-2 may include SiO 2, SiN, SiCN, SiCON, SiCO, SiON, AlO, HfO, another HK material (e.g., having a dielectric constant K of >=7), or a multilayer composite refill material consisting of a combination thereof. In some embodiments, the refill material layer 313B-1 can be described as including a SiO-like material. More generally, the refill material layer 313B-1 can include a material without a fixed charge. In some cases, the refill material layers 313T-1 and 313T-2 can be described as including a SiN-like material. In various examples, the refill material layer 313B-1 can be different from the refill material layers 313T-1 and 313T-2. As part of the CPODE process, in some embodiments, the formation of the CPODE structure 313 may generally include a dry etching process along the active edge 207 and through the pseudo GAA structure set along the active edge 207 to form a cutting area (e.g., including a groove); filling the cutting area (e.g., including filling the groove) with a refill material layer 313B-1 and a sacrificial layer; performing a back etching process; removing the sacrificial layer, and sequentially depositing refill material layers 313T-1 and 313T-2. In particular, in this example, due to the use of a sacrificial layer, the refill material layers 313T-1 and 313T-2 are at least partially deposited within the bottom portion 313B. Refer to the following Fig.16 Additional CPODE process details for forming CPODE structure 313 are discussed in detail in the method of FIG.

[0043] In some embodiments, the CPODE structures 213, 313 have a total depth 'D1' measured from a plane flush with the top surface of the substrate table (e.g., the top surface of the substrate portion 202A) to a plane flush with the bottom of the CPODE structures 213, 313. In some examples, the depth 'D1' can be in the range of about 80-250nm. As shown, the total depth 'D1' can be composed of a depth 'D2' and a depth 'D3'. The depth 'D2' is measured from a plane flush with the top surface of the substrate table to a plane flush with the bottom of the top portion 213T, 313T of the corresponding CPODE structure 213, 313. Note that the plane flush with the bottom of the top portion 213T, 313T and the plane flush with the top of the bottom portion 213B, 313B of the corresponding CPODE structure 213, 313 are coplanar. Depth 'D3' is measured from the top of bottom portion 213B, 313B (or equivalently from the bottom of top portion 213T, 313T) to a plane flush with the bottom of CPODE structure 213, 313 (or equivalently a plane flush with the bottom of bottom portions 213B and 313B).

[0044] As also shown, the STI feature 217 has a depth 'D5' measured from a plane flush with the top surface of the substrate mesa to a plane flush with the bottom of the STI feature 217. In some examples, the depth 'D5' can be in a range between about 50-150nm. In addition, the depth 'D4' can be defined as the distance from the plane flush with the top surface of the substrate mesa to the plane flush with the top of the STI feature 217. In some embodiments, the depth 'D4' can be in a range between about 3-30nm. In various examples, the depth 'D2' can be greater than the depth 'D4' and less than the depth 'D5'. As a result, bottom portions 213B, 313B of CPODE structures 213, 313 are buried within substrate 202 below a plane flush with the tops of STI features 217 (e.g., to prevent exposure to post-processing), and tops of bottom portions 213B, 313B of CPODE structures 213, 313 are higher (closer to the top of substrate 202) than the bottoms of STI features 217. Although the total depth 'D1' of CPODE structures 213, 313 is shown as being greater than the depth 'D5' of STI features 217, in at least some embodiments, the total depth 'D1' may be less than the depth 'D5'.

[0045] The exemplary embodiments of semiconductor devices 200, 300 discussed above and including the corresponding CPODE structures 213, 313 may be fabricated according to various embodiments of the disclosed methods discussed below (eg, such as Figure 4 and Fig.16 ). In addition, variations of the disclosed method may be provided to fabricate semiconductor devices having CPODE structures of various other configurations, as discussed below. It should also be noted that the aspects of the semiconductor devices 200, 300 discussed above are equally applicable to the various embodiments of the disclosed methods, devices, and CPODE structures discussed below. Therefore, reference numbers, terms, or other descriptors used in the discussion of the semiconductor devices 200, 300 may also be used in the discussion below to indicate the same components or aspects of the various embodiments. In addition, although the examples disclosed herein are discussed with reference to a CPODE structure having two portions (e.g., a top portion and a bottom portion), other embodiments are possible. For example, in some cases, the CPODE structure may have three or more portions, each of which includes one or more refill layers composed of a SiO-like material, a SiN-like material, another material described herein, or a combination thereof.

[0046] Reference now Figure 4, wherein a method 400 for fabricating a semiconductor device 500 including a CPODE structure according to various embodiments is shown. The method 400 is discussed below with reference to a semiconductor device including a GAA device having a channel region, which may be referred to as a nanosheet and may include various geometries (e.g., cylindrical, bar-shaped) and sizes. However, it will be understood that aspects of the method 400 (including the disclosed CPODE structure) may be equally applied to other types of devices as discussed above without departing from the scope of the present disclosure. In some embodiments, the method 400 may be used to fabricate a multi-gate device 100 (described above with reference to Figure 1 ) or semiconductor device 200 (referenced above Figure 2A / Figure 2B As described above, one or more aspects discussed above with reference to the multi-gate device 100 and / or the semiconductor device 200 may also be applied to the method 400. It should be understood that the method 400 includes steps that are characteristic of a complementary metal oxide semiconductor (CMOS) technology process flow, and therefore is only briefly described herein. In addition, additional steps may be performed before, after, and / or during the method 400.

[0047] Reference below Figures 5 to 8 Describing method 400, Figures 5 to 8 A semiconductor device 500 is shown at various stages of fabrication according to the method 400 . Figures 5 to 8 Provides a Figure 1 The cross-sectional view of the semiconductor device 500 of the embodiment is substantially parallel to the plane defined by the cross section XX'. The method 400 begins at block 402, where a partially fabricated multi-gate device is provided. Figure 5 and Figure 2BIn an embodiment of block 402, an initially provided, partially fabricated semiconductor device 500 may include the semiconductor device 200 at an early stage of processing (e.g., before performing a replacement gate process and before performing a CMG process). As discussed above, the semiconductor device 500 thus includes a first active region 203, a second active region 205, and an active edge 207. The first active region 203 includes a first GAA device 209, the second active region 205 includes a second GAA device (not shown), and the active edge 207 initially includes a pseudo GAA structure, wherein a CPODE structure will be subsequently formed. As described above, the semiconductor device 500 also includes a nanosheet channel layer 206, an inner spacer 219, a spacer layer 215, a source / drain feature 221, an ILD layer 223, a CESL 227, an isolation layer 245, and an undoped layer 247. The semiconductor device 500 provided before the replacement gate process includes a dummy gate structure and a sacrificial layer 507 (e.g., such as a sacrificial SiGe layer), which is interposed between adjacent nanosheet channel layers 206 to provide a semiconductor layer stack. In some embodiments, the dummy gate structure includes a dummy gate dielectric 508 and a dummy gate electrode 512. The dummy gate dielectric 508 includes a dielectric material such as silicon oxide, a high-K dielectric material, other suitable dielectric materials, or a combination thereof. The dummy gate electrode 512 includes a suitable dummy gate material such as polysilicon.

[0048] Method 400 proceeds to block 404 where a CPODE etching process is performed. Figure 5In an embodiment of block 404, a CPODE etching process is performed to form a trench 515 in a CPODE region 506 of the semiconductor device 500. The CPODE region 506 may include an active edge 207 and a pseudo GAA structure initially formed along the active edge 207. In some cases, the CPODE etching process includes a dry etching process. In some embodiments, the CPODE etching process removes the pseudo gate structure (including the pseudo gate electrode 512 and the pseudo gate dielectric 508), and portions of the nanosheet channel layer 206 that are not protected by the spacer layer 215 (directly disposed under the spacer layer 215), the sacrificial layer 507, and portions of the internal spacer 219 from the CPODE region 506. As a result, the trench 515 may include at least some portions of the nanosheet channel layer 206 and the internal spacer 219 along the sidewalls (in the sidewall region) of the trench 515 and disposed between the trench 515 and the adjacent source / drain features 221. It should be noted that the CPODE etching process may also remove at least some substrate portions 202A (e.g., within the CPODE region 506) of the pseudo GAA structure initially formed along the active edge 207. In various embodiments, the thickness of the spacer layer 215 may be selected to provide a desired sidewall profile after the CPODE etching process, for example, depending on various device and / or process parameters and specifications.

[0049] The method 400 proceeds to block 406 where a first refill process is performed. Figure 5 and Figure 6 In an embodiment of block 406, a first refill process is used to form a first refill layer 602 over the device 500 and within the trench 515 formed by the CPODE etching process. In some embodiments, the first refill layer 602 may include SiO 2 , SiN, SiCN, SiCON, SiCO, SiON, AlO, HfO, another HK material (e.g., having a dielectric constant K of >=7), or a multilayer composite refill material consisting of a combination thereof. In some embodiments, the first refill layer 602 can be described as including a SiO-like material. More generally, the first refill layer 602 can include a fixed charge-free material that effectively reduces leakage current between the substrate 202 and the first refill layer 602. In various examples, the first refill layer 602 can be deposited by a CVD process, a SACVD process, a flowable CVD process, an ALD process, a PVD process, and / or other suitable processes. In some cases, after forming the first refill layer 602, a CMP process can be performed to remove excess material and planarize the top surface of the device 500.

[0050] The method 400 proceeds to block 408 where an etch back process is performed. Figure 6 and Figure 7, after performing the CMP process, in an embodiment of box 408, an etch-back process is performed to etch back the first refill layer 602, thereby forming a back-etched first refill layer 602B-1 and a trench 715 in the CPODE region 506 of the semiconductor device 500. In some embodiments, the etch-back process includes a wet etching process, a dry etching process, or a combination thereof. Like the trench 515, the trench 715 may include at least some portions of the nanosheet channel layer 206 and the internal spacer 219 along the sidewalls (in the sidewall region) of the trench 715 and disposed between the trench 715 and the adjacent source / drain features 221. In particular, the etch-back process of box 408 is used to define a bottom portion 713B of the CPODE structure including the back-etched first refill layer 602B-1 (similar to the bottom portion 213B including the refill material layer 213B-1 discussed above). Additionally, the etch-back process of block 408 is used to define a depth ' D3 ' measured from the top of the bottom portion 713B to a plane flush with the bottom of the bottom portion 713B.

[0051] The method 400 proceeds to block 410 where a second refill process is performed. Figure 7 and Figure 8 In the embodiment of block 410, the second refill process is used to form a second refill layer 802T-1 over the device 500 and along the sidewalls and bottom surface of the trench 715 formed by the etch-back process of block 408. Therefore, in some cases, the second refill layer 802T-1 can be described as being conformally deposited within the trench 715. In some embodiments, the second refill layer 802T-1 may include SiO 2 , SiN, SiCN, SiCON, SiCO, SiON, AlO, HfO, another HK material (e.g., having a dielectric constant K of >=7), or a multilayer composite refill material consisting of a combination thereof. In some embodiments, the second refill layer 802T-1 can be described as including a SiN-like material. In various examples, the second refill layer 802T-1 can be different from the first refill layer 602B-1. In various examples, the second refill layer 802T-1 can be deposited by a CVD process, a SACVD process, a flowable CVD process, an ALD process, a PVD process, and / or other suitable processes.

[0052] Method 400 proceeds to block 412 where a third refill process is performed. Figure 7 and Figure 8 In an embodiment of block 412, a third refill process is used to form a third refill layer 802T-2 over the device 500, within the trench 715, and over the second refill layer 802T-1 previously deposited at block 410. In some embodiments, the third refill layer 802T-2 may include SiO2 , SiN, SiCN, SiCON, SiCO, SiON, AlO, HfO, another HK material (e.g., having a dielectric constant K of >=7), or a multilayer composite refill material consisting of a combination thereof. In some embodiments, the third refill layer 802T-2 may also be described as including a SiN-like material. In various examples, the third refill layer 802T-2 may be different from the second refill layer 802T-1 and the first refill layer 602B-1. In various examples, the third refill layer 802T-2 may be deposited by a CVD process, a SACVD process, a flowable CVD process, an ALD process, a PVD process, and / or other suitable processes. After forming the third refill layer 802T-2, a CMP process may be performed to remove excess material and planarize the top surface of the device 500. In addition, after forming the third refill layer 802T-2, a top portion 713T of the CPODE structure is defined, which includes the second refill layer 802T-1 and the third refill layer 802T-2 (similar to the top portion 213T discussed above including the refill material layers 213T-1 and 213T-2). More specifically, after forming the third refill layer 802T-2, a CPODE structure 713 (including a bottom portion 713B and a top portion 713T) is defined, wherein the CPODE structure 713 is substantially the same as the CPODE structure 213 discussed above. It should also be noted that the etch-back process of box 408 is also used to define a depth 'D2' measured from a plane flush with the top surface of the substrate table to a plane flush with the bottom of the top portion 713T. Therefore, the total depth 'D1' of the CPODE structure 713 is the sum of the depth 'D2' and the depth 'D3'.

[0053] The method 400 proceeds to block 414, where subsequent processing is performed. For example, in some embodiments, after forming the CPODE structure 713, a channel release process and a replacement gate process may be performed to remove the dummy gate structure (including the dummy gate dielectric 508 and the dummy gate electrode 512) and the sacrificial layer 507, and replace them with a high-K / metal gate stack, such as described with reference to the semiconductor device 200. In some cases, after the channel release process and the replacement gate process, a CMG process may be performed to form a dielectric layer in the CMG region of the metal layer that isolates adjacent structures, also as described above with reference to the semiconductor device 200. Therefore, in some embodiments, after block 414, the semiconductor device 500 may be substantially the same as the semiconductor device 200 discussed above.

[0054] Although method 400 is described as first forming the CPODE structure 713, then performing a channel release process and a replacement gate process, and then performing a CMG process, other embodiments are possible and within the scope of the present disclosure. For example, in some cases, method 400 may first perform a channel release process and a replacement gate process, followed by a CMG process, and then the CPODE structure 713 may be formed. In other examples, method 400 may first perform a channel release process and a replacement gate process, then form the CPODE structure 713, and then the CMG process may be performed. In yet other embodiments, method 400 may first perform a CMG process, then form the CPODE structure 713, and then the channel release process and the replacement gate process may be performed. In some cases, method 400 may first perform a CMG process, then perform a channel release process and a replacement gate process, and then the CPODE structure 713 may be formed.

[0055] Typically, the semiconductor device 500 may be further processed to form various components and regions known in the art. For example, subsequent processing may form contact openings, contact metals, and various contacts / vias / lines and multilayer interconnect components (e.g., metal layers and interlayer dielectrics) on the substrate 202, which are configured to connect various components to form functional circuits, which may include one or more multi-gate devices. In a further example, the multilayer interconnects may include vertical interconnects (such as vias or contacts) and horizontal interconnects (such as metal lines). Various interconnect components may be made of various conductive materials, including copper, tungsten and / or silicide. In one example, inlay and / or dual inlay processes are used to form copper-related multilayer interconnect structures. In addition, additional process steps may be implemented before, during, and after the method 400, and some of the above process steps may be replaced or eliminated according to various embodiments of the method 400. In addition, although the method 400 is shown and described as including a device 500 having a GAA device, it will be understood that other device configurations are possible. In some embodiments, the method 400 may be used to fabricate various types of devices, such as planar transistor devices, FinFET devices, cross-plane devices, CFET devices, and the like.

[0056] As previously mentioned, variations of the disclosed method can be provided to fabricate semiconductor devices having CPODE structures with various other configurations. With respect to method 400, the process steps of the method can be modified to fabricate devices having a variety of different CPODE structure configurations. For example, referring to Fig. 9A , Fig. 9B and Figures 10 to 15 , which illustrate embodiments of semiconductor devices having CPODE structures manufactured according to method 400 and having different configurations. As shown in the figure, Fig. 9A , Fig. 9B and Figures 10 to 15Examples include the device after subsequent processing of block 414 (eg, after a channel release process and a replacement gate process, and including a high-K / metal gate stack).

[0057] refer to Fig. 9A , there is shown a semiconductor device 900, which is similar to the semiconductor devices 200, 500 manufactured using the method 400. However, the semiconductor device 900 includes a different CPODE structure 913. In particular, in the CPODE structure 913, the second refill layer 802T-1 is the same as the first refill layer 602B-1. In contrast, in the CPODE structure 713 of the semiconductor device 500, the second refill layer 802T-1 is different from the first refill layer 602B-1.

[0058] refer to Fig. 9B , there is shown a semiconductor device 950 that is similar to the semiconductor devices 200 , 500 manufactured using method 400 . However, the semiconductor device 950 includes a different CPODE structure 963 . In particular, in the CPODE structure 963 , the second refill layer 802T-1 and the third refill layer 802T-2 can be the same (e.g., composed of the same material). As a result, the bottom portion 713B of the CPODE structure 963 includes one dielectric layer (the first refill layer 602B-1), and the top portion 713T of the CPODE structure 963 effectively includes one dielectric layer (the second refill layer 802T-1 and the third refill layer 802T-2 composed of the same material). In addition, in at least some cases, frames 410 and 412 can be combined into a single deposition of refill material for forming the top portion 713T of the CPODE structure 963, rather than separately depositing the second refill layer 802T-1 and the third refill layer 802T-2.

[0059] refer to Fig.10, there is shown a semiconductor device 1000, which is similar to the semiconductor devices 200, 500 manufactured using the method 400. However, the semiconductor device 1000 includes a different CPODE structure 1013. In particular, in the CPODE structure 1013, the bottom portion 713B includes multiple refill layers. As shown, the bottom portion 713B may include a first refill layer 602B-1 and another refill layer 602B-2. In some embodiments, the first refill layer 602B-1 may be conformally deposited within the trench 515 (e.g., along the sidewalls and bottom surface of the trench 515), rather than completely filling the trench 515 with the first refill layer at box 406 of the method 400. Thereafter, an additional bottom refill layer 602B-2 may be deposited within the trench 515 and over the first refill layer 602B-1, thereby filling the trench 515. In some embodiments, the additional bottom refill layer 602B-2 may include SiO 2 , SiN, SiCN, SiCON, SiCO, SiON, AlO, HfO, another HK material (e.g., having a dielectric constant K of >=7), or a multilayer composite refill material consisting of a combination thereof. In some embodiments, the additional bottom refill layer 602B-2 can be described as including a SiO-like material. In various examples, the additional bottom refill layer 602B-2 can be different from the first refill layer 602B-1. In some embodiments, the additional bottom refill layer 602B-2 can also be different from the third refill layer 802T-2 and the second refill layer 802T-1 of the top portion 713T. In various examples, the additional bottom refill layer 602B-2 can be deposited by a CVD process, a SACVD process, a flowable CVD process, an ALD process, a PVD process, and / or other suitable processes. After forming the additional bottom refill layer 602B-2, the method 400 continues to box 408, where, as described above, an etch back process is performed.

[0060] refer to Fig.11 , there is shown a semiconductor device 1100, which is similar to the semiconductor devices 200, 500 manufactured using the method 400. However, the semiconductor device 1100 includes a different CPODE structure 1113. In particular, in the CPODE structure 1113, the bottom portion 713B includes a refill layer and an air gap. As shown, the bottom portion 713B can include a first refill layer 602B-1 and an air gap 602B-3. Fig.10 As with the embodiment of the present invention, the first refill layer 602B-1 may be conformally deposited within the trench 515 (eg, along the sidewalls and bottom surface of the trench 515), rather than completely filling the trench 515 with the first refill layer at block 406 of the method 400. Thereafter, Fig.10In contrast to the embodiment of the present invention, the method 400 continues to block 408, where, as described above, an etch back process is performed instead of depositing another bottom refill layer to completely fill the trench 515. In various embodiments, including the air gap 602B-3 reduces parasitic capacitance and can enhance the performance of the device 1100. It should also be noted that the subsequent deposition of the second refill layer 802T-1 and the third refill layer 802T-2 can be adjusted (e.g., by appropriately selecting the materials and / or deposition processes for the second refill layer 802T-1 and the third refill layer 802T-2) so that the second refill layer 802T-1 and the third refill layer 802T-2 are not deposited within the air gap 602B-3. In other words, the air gap 602B-3 can be substantially free of the second refill layer 802T-1 and the third refill layer 802T-2.

[0061] refer to Fig.12 , there is shown a semiconductor device 1200, which is similar to the semiconductor devices 200, 500 manufactured using the method 400. However, the semiconductor device 1200 includes a different CPODE structure 1213. In particular, in the CPODE structure 1213, the materials selected for the first refill layer 602B-1 and the third refill layer 802T-2 include a poor gap filling material. The poor gap filling material can be intentionally selected so that a gap S1 is formed in the bottom portion 713B and a gap S2 is formed in the top portion 713T. In some examples, the poor gap filling material can be selected for only one of the first refill layer 602B-1 and the third refill layer 802T-2, so that only one of the gaps S1 or S2 can be formed. As an illustration, the poor gap fill material for the first refill layer 602B-1 may be deposited as part of a first layer refill process at block 406 of method 400, and the poor gap fill material for the third refill layer 802T-2 may be deposited as part of a third layer refill process at block 412 of the method 400. In some embodiments, including the gaps S1, S2 may reduce parasitic capacitance and enhance performance of the device 1200.

[0062] refer to Fig.13 , there is shown a semiconductor device 1300, which is similar to the semiconductor devices 200, 500 manufactured using the method 400. However, the semiconductor device 1300 includes a different CPODE structure 1313. In an example, the CPODE structure 1313 can be Fig. 9A and Fig.12 For example, in CPODE structure 1313, second refill layer 802T-1 is identical to first refill layer 602B-1 (e.g., Fig. 9AIn addition, the materials selected for the first refill layer 602B-1 and the third refill layer 802T-2 include poor gap filling materials, resulting in gaps S1 in the bottom portion 713B and gaps S2 in the top portion 713T (e.g., similar to Fig.12 As described above, in some examples, a poor gap filling material may be selected for only one of the first refill layer 602B-1 and the third refill layer 802T-2, so that only one of the gaps S1 or S2 may be formed.

[0063] refer to Fig.14 , there is shown a semiconductor device 1400, which is similar to the semiconductor devices 200, 500 manufactured using the method 400. However, the semiconductor device 1400 includes a different CPODE structure 1413. In an example, the CPODE structure 1413 can be Fig.10 and Fig.12 For example, in CPODE structure 1413, bottom portion 713B may include a first refill layer 602B-1 and another refill layer 602B-2 (eg, with Fig.10 In addition, the material selected for the third refill layer 802T-2 includes a poor gap-filling material, resulting in gaps S2 within the top portion 713T (eg, Fig.12 Implementation example).

[0064] refer to Fig.15 , there is shown a semiconductor device 1500, which is similar to the semiconductor devices 200, 500 manufactured using the method 400. However, the semiconductor device 1500 includes a different CPODE structure 1513. In an example, the CPODE structure 1513 can be Fig.11 and Fig.12 For example, in CPODE structure 1513, bottom portion 713B may include first refill layer 602B-1 and air gap 602B-3 (eg, with Fig.11 In addition, the material selected for the third refill layer 802T-2 includes a poor gap-filling material, resulting in gaps S2 within the top portion 713T (eg, Fig.12 Implementation example).

[0065] Reference now Fig.16, wherein a method 1600 for fabricating a semiconductor device 1700 including a CPODE structure according to various embodiments is shown. The method 1600 is discussed below with reference to a semiconductor device including a GAA device having a channel region, which may be referred to as a nanosheet and may include various geometries (e.g., cylindrical, bar-shaped) and sizes. However, it will be understood that aspects of the method 1600 (including the disclosed CPODE structure) may be equally applied to other types of devices as discussed above without departing from the scope of the present disclosure. In some embodiments, the method 1600 may be used to fabricate a multi-gate device 100 (described above with reference to FIG. 1 ). Figure 1 ) or semiconductor device 300 (referenced above Figure 3A / Figure 3B Thus, one or more aspects discussed above with reference to the multi-gate device 100 and / or the semiconductor device 300 may also be applied to the method 1600. In addition, the method 1600 is similar in some aspects to Figure 4 Therefore, one or more aspects discussed above with reference to method 400 may also be applied to method 1600. It should be understood that method 1600 includes steps that are characteristic of a CMOS technology process flow and is therefore only briefly described herein. In addition, additional steps may be performed before, after, and / or during method 1600.

[0066] Reference below Figures 17 to 21 Describing method 1600, Figures 17 to 21 A semiconductor device 1700 is shown at various stages of fabrication according to method 1600 . Figures 17 to 21 Provides a Figure 1 The method 1600 begins at block 1602, where a partially fabricated multi-gate device is provided. In some embodiments, the partially fabricated multi-gate device provided at block 1602 may be similar to that in Figure 4 The device provided at block 402 of FIG. Fig.17 and Figure 3BIn the embodiment of block 1602, the initially provided, partially manufactured semiconductor device 1700 may include the semiconductor device 300 at an early stage of processing (e.g., before performing a replacement gate process and before a CMG process). As discussed above, the semiconductor device 1700 thus includes a first active region 203, a second active region 205, and an active edge 207. The first active region 203 includes a first GAA device 209, the second active region 205 includes a second GAA device (not shown), and the active edge 207 initially includes a pseudo GAA structure in which a CPODE structure will be subsequently formed. As described above, the semiconductor device 1700 also includes a nanosheet channel layer 206, an inner spacer 219, a spacer layer 215, a source / drain feature 221, an ILD layer 223, a CESL 227, an isolation layer 245, and an undoped layer 247. The semiconductor device 1700 provided before the replacement gate process includes a dummy gate structure and a sacrificial layer 507 (e.g., a sacrificial SiGe layer) between adjacent nanosheet channel layers 206. In some embodiments, the dummy gate structure includes a dummy gate dielectric 508 and a dummy gate electrode 512. The dummy gate dielectric 508 includes a dielectric material such as silicon oxide, a high-K dielectric material, other suitable dielectric materials, or a combination thereof. The dummy gate electrode 512 includes a suitable dummy gate material such as polysilicon.

[0067] Method 1600 proceeds to block 1604 where a CPODE etching process is performed. Fig.17In an embodiment of block 1604, a CPODE etching process is performed to form a trench 1715 in a CPODE region 1706 of the semiconductor device 1700. The CPODE region 1706 may include an active edge 207 and a pseudo GAA structure initially formed along the active edge 207. In some cases, the CPODE etching process includes a dry etching process. In some embodiments, the CPODE etching process removes the pseudo gate structure (including the pseudo gate electrode 512 and the pseudo gate dielectric 508) and portions of the nanosheet channel layer 206 that are not protected by the spacer layer 215 (directly disposed under the spacer layer 215), the sacrificial layer 507, and portions of the internal spacer 219 from the CPODE region 1706. As a result, the trench 1715 may include at least some portions of the nanosheet channel layer 206 and the internal spacer 219 along the sidewalls (in the sidewall region) of the trench 1715 and disposed between the trench 1715 and the adjacent source / drain features 221. It should be noted that the CPODE etching process may also remove at least some of the substrate portion 202A of the pseudo GAA structure that was initially formed along the active edge 207 (e.g., within the CPODE region 1706). In various embodiments, the thickness of the spacer layer 215 may be selected to provide a desired sidewall profile after the CPODE etching process, for example, depending on various device and / or process parameters and specifications.

[0068] The method 1600 proceeds to block 1606 where a first refill process is performed. Fig.17 and Fig.18 In an embodiment of block 1606, a first refill process is used to form a first refill layer 1802 over the device 1700, and the first refill layer 1802 is conformally located within the trench 1715 formed by the CPODE etching process (e.g., along the sidewalls and bottom surface of the trench 1715). In some embodiments, the first refill layer 1802 may include SiO 2 , SiN, SiCN, SiCON, SiCO, SiON, AlO, HfO, another HK material (e.g., having a dielectric constant K of >=7), or a multilayer composite refill material consisting of a combination thereof. In some embodiments, the first refill layer 1802 can be described as including a SiO-like material. More generally, the first refill layer 1802 can include a non-fixed charge material that effectively reduces leakage current between the substrate 202 and the first refill layer 1802. In various examples, the first refill layer 1802 can be deposited by a CVD process, a SACVD process, a flowable CVD process, an ALD process, a PVD process, and / or other suitable processes.

[0069] Method 1600 proceeds to block 1607 where a sacrificial layer is formed. Still referring to Fig.17 and Fig.18 In an embodiment of block 1607, a sacrificial layer 1804 may be deposited within the trench 1715 and over the first refill layer 1802, thereby filling the trench 1715. In some embodiments, the sacrificial layer 1804 comprises a bottom anti-reflective coating (BARC) layer. In some cases, the sacrificial layer 1804 may optionally include other materials, such as resins, other polymers, or photoresists. In various examples, the sacrificial layer 1804 may be deposited by a CVD process, a SACVD process, a flowable CVD process, an ALD process, and / or other suitable processes. In some cases, after forming the first refill layer 1802 and the sacrificial layer 1804, a CMP process may be performed to remove excess material and planarize the top surface of the device 1700.

[0070] The method 1600 proceeds to block 1608 where an etch back process is performed. Fig.18 and Fig.19 After performing the CMP process, in an embodiment of block 1608, an etch-back process is performed to etch back the first refill layer 1802 and the sacrificial layer 1804, thereby forming the etched-back first refill layer 1802B-1, the etched-back sacrificial layer 1804B-1, and the trench 1915 in the CPODE region 1706 of the semiconductor device 1700. In some embodiments, the etch-back process includes a wet etching process, a dry etching process, or a combination thereof. Like the trench 1715, the trench 1915 may include at least some portions of the nanosheet channel layer 206 and the internal spacer 219 along the sidewalls (in the sidewall region) of the trench 1915 and disposed between the trench 1915 and the adjacent source / drain features 221. In particular, the etch-back process of block 1608 is used to at least partially define a bottom portion 1913B of the CPODE structure including the etched-back first refill layer 1802B-1 and the etched-back sacrificial layer 1804B-1. Additionally, the etch-back process of block 1608 is used to define a depth 'D3' measured from the top of the bottom portion 1913B to a plane flush with the bottom of the bottom portion 1913B.

[0071] Method 1600 continues at block 1609 where the sacrificial layer is removed. Fig.19 and Fig. 20 In an embodiment of block 1609, the etched-back sacrificial layer 1804B-1 may be removed to form a trench 2015 below the trench 1915, the trenches 1915, 2015 forming a continuous trench. As shown, the trench 2015 may include the etched-back first refill layer 1802B-1 along the sidewalls (in the sidewall region) of the trench 2015. In various embodiments, the etched-back sacrificial layer 1804B-1 may be removed using wet etching, dry etching, or a combination thereof.

[0072] The method 1600 proceeds to block 1610 where a second refill process is performed. Fig. 20 and Fig.21 In the embodiment of block 1610, the second refill process is used to form a second refill layer 2102T-1 over device 1700, along the sidewalls of trench 1915, and along the sidewalls and bottom surface of trench 2015 (formed at block 1609 by removing the etched-back sacrificial layer 1804B-1), including over the etched-back first refill layer 1802B-1 disposed along the sidewalls of trench 2015. Thus, in some cases, second refill layer 2102T-1 can be described as being conformally deposited within trenches 1915 and 2015. Although the width of trench 2015 is narrower than the width of trench 1915, due to the presence of the etched-back first refill layer 1802B-1 disposed along the sidewalls of trench 2015, in some examples, the conformally deposited second refill layer 2102T-1 may not completely fill trench 2015. In some embodiments, second refill layer 2102T-1 may include SiO 2 , SiN, SiCN, SiCON, SiCO, SiON, AlO, HfO, another HK material (e.g., having a dielectric constant K of >=7), or a multilayer composite refill material consisting of a combination thereof. In some embodiments, the second refill layer 2102T-1 can be described as including a SiN-like material. In various examples, the second refill layer 2102T-1 can be different from the first refill layer 1802B-1. In various examples, the second refill layer 2102T-1 can be deposited by a CVD process, a SACVD process, a flowable CVD process, an ALD process, a PVD process, and / or other suitable processes.

[0073] Method 1600 proceeds to block 1612 where a third refill process is performed. Fig. 20 and Fig.21 In an embodiment of block 1612, a third refill process is used to form a third refill layer 2102T-2 over the device 1700, within the trenches 1915, 2015, and over the second refill layer 2102T-1 previously deposited at block 1610, thereby filling the trenches 1915, 2015. In some embodiments, the third refill layer 2102T-2 may include SiO 2, SiN, SiCN, SiCON, SiCO, SiON, AlO, HfO, another HK material (e.g., having a dielectric constant K of >= 7), or a multilayer composite refill material consisting of a combination thereof. In some embodiments, the third refill layer 2102T-2 may also be described as including a SiN-like material. In various examples, the third refill layer 2102T-2 may be different from the second refill layer 2102T-1 and the first refill layer 1802B-1. In various examples, the third refill layer 2102T-2 may be deposited by a CVD process, a SACVD process, a flowable CVD process, an ALD process, a PVD process, and / or other suitable processes. After forming the third refill layer 2102T-2, a CMP process may be performed to remove excess material and planarize the top surface of the device 1700. In addition, after forming the third refill layer 2102T-2, a bottom portion 1913B is further defined, the bottom portion 1913B including the first refill layer 1802B-1, the second refill layer 2102T-1 located above the first refill layer 1802B-1, and the third refill layer 2102T-2 located above the second refill layer 2102T-1. In addition, after forming the third refill layer 2102T-2, a top portion 1913T of the CPODE structure is defined, the top portion 1913T including the second refill layer 2102T-1 and the third refill layer 2102T-2. More specifically, after forming the third refill layer 2102T-2, a CPODE structure 1913 (including the bottom portion 1913B and the top portion 1913T) is defined, wherein the CPCODE structure 1913 is substantially the same as the CPODE structure 313 discussed above. It should also be noted that the etch back process of block 1608 is also used to define a depth 'D2' measured from a plane flush with the top surface of the substrate mesa to a plane flush with the bottom of the top portion 1913T. Therefore, the total depth 'D1' of the CPODE structure 1913 is the sum of the depth 'D2' and the depth 'D3'.

[0074] The method 1600 proceeds to block 1614, where subsequent processing is performed. For example, in some embodiments, after forming the CPODE structure 1913, a channel release process and a replacement gate process may be performed to remove the dummy gate structure (including the dummy gate dielectric 508 and the dummy gate electrode 512) and the sacrificial layer 507, and replace them with a high-K / metal gate stack, such as described with reference to the semiconductor device 300. In some cases, after the channel release process and the replacement gate process, a CMG process may be performed to form a dielectric layer in the CMG region of the metal layer that isolates adjacent structures, also as described above with reference to the semiconductor device 300. Therefore, in some embodiments, after block 1614, the semiconductor device 1700 may be substantially the same as the semiconductor device 300 discussed above.

[0075] Although method 1600 is described as first forming the CPODE structure 1913, then performing a channel release process and a replacement gate process, and then performing a CMG process, other embodiments are possible and within the scope of the present disclosure. For example, in some cases, method 1600 may first perform a channel release process and a replacement gate process, followed by a CMG process, and then the CPODE structure 1913 may be formed. In other examples, method 1600 may first perform a channel release process and a replacement gate process, then form the CPODE structure 1913, and then the CMG process may be performed. In yet other embodiments, method 1600 may first perform a CMG process, then form the CPODE structure 1913, and then the channel release process and the replacement gate process may be performed. In some cases, method 1600 may first perform a CMG process, then perform a channel release process and a replacement gate process, and then the CPODE structure 1913 may be formed.

[0076] Typically, the semiconductor device 1700 may be further processed to form various components and regions known in the art. For example, subsequent processing may form contact openings, contact metals, and various contacts / vias / lines and multilayer interconnect components (e.g., metal layers and interlayer dielectrics) on the substrate 202, which are configured to connect various components to form functional circuits, which may include one or more multi-gate devices. In a further example, the multilayer interconnects may include vertical interconnects (such as vias or contacts) and horizontal interconnects (such as metal lines). Various interconnect components may be made of various conductive materials, including copper, tungsten and / or silicide. In one example, inlay and / or dual inlay processes are used to form copper-related multilayer interconnect structures. In addition, additional process steps may be implemented before, during, and after the method 1600, and some of the above process steps may be replaced or eliminated according to various embodiments of the method 1600. In addition, although the method 1600 is shown and described as including a device 1700 having a GAA device, it will be understood that other device configurations are possible. In some embodiments, method 1600 may be used to fabricate various types of devices, such as planar transistor devices, FinFET devices, fork-plane devices, CFET devices, and the like.

[0077] Again, as previously described, variations of the disclosed method may be provided to fabricate semiconductor devices having CPODE structures having various other configurations. With respect to method 1600, the process steps of the method may be modified to fabricate devices having a variety of different CPODE structure configurations. For example, referring to Figure 22 to Figure 28 , Figure 22 to Figure 28 An embodiment of a semiconductor device having a CPODE structure manufactured according to method 1600 and having different configurations is shown. As shown in the figure, Figure 22 to Figure 28Examples include the device after subsequent processing of block 1614 (eg, after a channel release process and a replacement gate process, and including a high-K / metal gate stack).

[0078] refer to Fig. 22 , there is shown a semiconductor device 2200, which is similar to the semiconductor devices 300, 1700 manufactured using the method 1600. However, the semiconductor device 2200 includes a different CPODE structure 2213. In particular, in the CPODE structure 2213, the second refill layer 2102T-1 is the same as the first refill layer 1802B-1. In contrast, in the CPODE structure 1913 of the semiconductor device 1700, the second refill layer 2102T-1 is different from the first refill layer 1802B-1.

[0079] refer to Fig.23 , there is shown a semiconductor device 2300, which is similar to the semiconductor devices 300, 1700 manufactured using the method 1600. However, the semiconductor device 2300 includes a different CPODE structure 2313. In particular, in the CPODE structure 2313, the second refill layer 2102T-1 is the same as the third refill layer 2102T-2. In contrast, in the CPODE structure 1913 of the semiconductor device 1700, the second refill layer 2102T-1 is different from the third refill layer 2102T-2.

[0080] refer to Fig.24 , wherein a semiconductor device 2400 is shown, which is similar to the semiconductor devices 300, 1700 manufactured using the method 1600. However, the semiconductor device 2400 includes a different CPODE structure 2413. In particular, in the CPODE structure 2413, the bottom portion 1913B includes one or more refill layers and an air gap. In the example shown, the bottom portion 1913B can include a first refill layer 1802B-1, a second refill layer 2102T-1, and an air gap 1802B-2. As shown in reference Fig.21As described, the second refill layer 2102T-1 can be conformally deposited over the first refill layer 1802B-1 in the bottom portion 1913B. As described above, in some examples, the conformal deposition of the second refill layer 2102T-1 may not completely fill the trench 2015. Thereafter, a third refill process is used to form a third refill layer 2102T-2. In particular, it should be noted that the deposition of the third refill layer 2102T-2 can be adjusted (e.g., by appropriately selecting a material and / or deposition process for the third refill layer 2102T-2) so that the third refill layer 2102T-2 is not deposited within the air gap 1802B-2. In other words, the air gap 1802B-2 can be substantially free of the third refill layer 2102T-2. It should also be noted that in the CPODE structure 2413, the second refill layer 2102T-1 and the third refill layer 2102T-2 can be composed of the same material or different materials. In various embodiments, including the air gap 1802B-2 reduces parasitic capacitance and can enhance the performance of the device 2400. In some optional embodiments, the bottom portion 1913B can include only the first refill layer 1802B-1 and the air gap 1802B-2. For example, in some cases, the deposition of the second refill layer 2102T-1 and the third refill layer 2102T-2 can be adjusted (e.g., by appropriately selecting the materials and / or deposition processes for the second refill layer 2102T-1 and the third refill layer 2102T-2) so that the second refill layer 2102T-1 and the third refill layer 2102T-2 are not deposited within the air gap 1802B-2. In other words, in such an example, the air gap 1802B-2 can be substantially free of the second refill layer 2102T-1 and the third refill layer 2102T-2.

[0081] refer to Fig.25 , there is shown a semiconductor device 2500, which is similar to the semiconductor devices 300, 1700 manufactured using method 1600. However, the semiconductor device 2500 includes a different CPODE structure 2513. In particular, in the CPODE structure 2513, the material selected for the third refill layer 2102T-2 includes a poor gap filling material. The poor gap filling material can be intentionally selected so as to form a gap S3 within the top portion 1913T. As an illustration, the poor gap filling material for the third refill layer 2102T-2 can be deposited as part of the third layer refill process of box 1612 of method 1600. In some embodiments, including the gap S3 can reduce parasitic capacitance and enhance the performance of the device 2500.

[0082] refer to Fig.26, which shows a semiconductor device 2600. The semiconductor device 2600 is similar to the semiconductor devices 300, 1700 manufactured using the method 1600. However, the semiconductor device 2600 includes a different CPODE structure 2613. In an example, the CPODE structure 2613 can be Fig. 22 and Fig.25 a combination of aspects of the embodiments shown therein. For example, in the CPODE structure 2613, the second refill layer 2102T-1 is the same as the first refill layer 1802B-1 (e.g., the same as in the embodiment of Fig. 22 ). In addition, the material selected for the third refill layer 2102T-2 includes a poor gap-fill material, creating a gap S3 within the top portion 1913T (e.g., the same as in the embodiment of Fig.25 ).

[0083] Refer to Fig. 27 , which shows a semiconductor device 2700. The semiconductor device 2700 is similar to the semiconductor devices 300, 1700 manufactured using the method 1600. However, the semiconductor device 2700 includes a different CPODE structure 2713. In an example, in the CPODE structure 2713, the materials selected for the second refill layer 2102T-1 and the third refill layer 2102T-2 include poor gap-fill materials. The poor gap-fill materials can be intentionally selected to form a gap S3 within the top portion 1913T and a gap S4 within the bottom portion 1913B. As an illustration, the poor gap-fill material for the second refill layer 2102T-1 can be deposited as part of the second refill process of block 1610 of the method 1600, and the third refill layer 2102T-2 can be deposited as part of the third layer refill process of block 1612 of the method 1600. In some embodiments, including the gaps S3, S4 can reduce parasitic capacitance and enhance the performance of the device 2700. It should be noted that in the CPODE structure 2713, the second refill layer 2102T-1 and the third refill layer 2102T-2 can be composed of the same material or different materials. In addition, in at least some cases, blocks 1610 and 1612 can be combined into a single deposition of a poor gap-fill refill material instead of separately depositing the second refill layer 2102T-1 and the third refill layer 2102T-2, and this single deposition effectively forms the gaps S3, S4.

[0084] Refer to Fig.28 , which shows a semiconductor device 2800. The semiconductor device 2800 is similar to the semiconductor devices 300, 1700 manufactured using the method 1600. However, the semiconductor device 2800 includes a different CPODE structure 2813. In an example, the CPODE structure 2813 can be Fig.24 and Fig. 27 For example, in CPODE structure 2813, bottom portion 1913B may include first refill layer 1802B-1, second refill layer 2102T-1, and air gap 1802B-2 (eg, Fig.24 In some optional embodiments, such as reference Fig.24 As described in the embodiment of the present invention, the bottom portion 1913B may include only the first refill layer 1802B-1 and the air gap 1802B-2. In addition, in the CPODE structure 2813, the material selected for the third refill layer 2102T-2 includes a poor gap filling material, resulting in a gap S3 in the top portion 1913T (e.g., Fig. 27 2014). In some cases, the material selected for the second refill layer 2102T-1 and the third refill layer 2102T-2 includes a poor gap filling material. It should also be noted that in the CPODE structure 2813, the second refill layer 2102T-1 and the third refill layer 2102T-2 can be composed of the same material or different materials. In addition, in at least some cases, blocks 1610 and 1612 can be combined into a single deposition of a poor gap filling refill material, rather than separately depositing the second refill layer 2102T-1 and the third refill layer 2102T-2, such as when the bottom portion 1913B includes only the first refill layer 1802B-1 and the air gap 1802B-2, the single deposition effectively forms the gap S3 while retaining the air gap 1802B-2.

[0085] With respect to the description provided herein, a structure and related methods for forming a CPODE structure (or dielectric plug) having multiple dielectric layers of different material components stacked at least partially in a vertical direction to provide leakage current reduction are disclosed. In an example, the CPODE refill material (bottom CPODE refill material) used to refill the bottom portion of the CPODE structure may include a single layer or multiple layers and is selected to include a non-fixed charge material. In some embodiments, the CPODE refill material (top CPODE refill material) and / or the number of layers used to refill the top portion of the CPODE structure may be different from the bottom CPODE refill material and / or the number of layers. It is certain that in some cases, both the bottom CPODE refill material and the top CPODE refill material may include at least one layer formed of the same material. In some embodiments, the bottom CPODE refill material includes a SiO-like material, and the top CPODE refill material includes a SiN-like material. In some embodiments, the bottom CPODE refill material can be buried below a plane defined by the top surface of an adjacent STI region, and the overall depth of the disclosed CPODE structure can be deeper than (or shallower than, in some cases, than) an adjacent STI region. In various examples, the bottom CPODE refill material is selected to provide leakage current reduction, and the top CPODE refill material is selected to mitigate losses (e.g., such as losses that may occur in prior embodiments during removal of a pseudo-polysilicon gate). By employing the disclosed CPODE process and associated structures, device performance and reliability of transistors formed in adjacent active regions will be enhanced. Those skilled in the art will readily appreciate that the methods and structures described herein can be applied to various other semiconductor devices to advantageously obtain similar benefits from these other devices without departing from the scope of the present disclosure.

[0086] Thus, one embodiment of the present disclosure describes a method comprising: providing a partially manufactured semiconductor device comprising a dummy gate structure disposed above a semiconductor layer stack. In some embodiments, the method further comprises removing the dummy gate structure and at least a portion of each semiconductor layer of the semiconductor layer stack to form a trench. In some examples, the method further comprises forming one or more refill layers in a bottom portion of the trench, and forming one or more refill layers in a top portion of the trench above the bottom portion of the trench. In some embodiments, the one or more refill layers in the top and bottom portions of the trench define a top portion and a bottom portion of an isolation structure, respectively. In some examples, at least one refill layer of the corresponding top and bottom portions of the isolation structure has a different material composition.

[0087] In some embodiments, the bottom portion of the isolation structure includes a first refill layer, and wherein the top portion of the isolation structure includes a second refill layer and a third refill layer located above the second refill layer.

[0088] In some embodiments, the bottom portion of the isolation structure includes a first refill layer, and wherein the top portion of the isolation structure includes a second refill layer and a third refill layer located above the second refill layer, wherein the first refill layer, the second refill layer, and the third refill layer are different from each other.

[0089] In some embodiments, the bottom portion of the isolation structure includes a first refill layer, and wherein the top portion of the isolation structure includes a second refill layer and a third refill layer located above the second refill layer, wherein the first refill layer is the same as the second refill layer.

[0090] In some embodiments, the bottom portion of the isolation structure includes a SiO-like material, and wherein the top portion of the isolation structure includes a SiN-like material.

[0091] In some embodiments, the bottom portion of the isolation structure includes a fixed charge free material.

[0092] In some embodiments, the isolation structure includes an air gap, a gap, or a combination thereof.

[0093] In some embodiments, the top portion of the isolation structure extends to a first depth in an underlying substrate, wherein a top surface of an adjacent shallow trench isolation (STI) feature extends to a second depth in the underlying substrate, and wherein a bottom surface of the adjacent shallow trench isolation feature extends to a third depth in the underlying substrate.

[0094] In some embodiments, the top portion of the isolation structure extends to a first depth in an underlying substrate, wherein a top surface of an adjacent shallow trench isolation (STI) feature extends to a second depth in the underlying substrate, and wherein a bottom surface of the adjacent shallow trench isolation feature extends to a third depth in the underlying substrate, wherein the first depth is greater than the second depth, and wherein the first depth is less than the third depth.

[0095] In some embodiments, the top portion of the isolation structure extends to a first depth in an underlying substrate, wherein a top surface of an adjacent shallow trench isolation (STI) feature extends to a second depth in the underlying substrate, and wherein a bottom surface of the adjacent shallow trench isolation feature extends to a third depth in the underlying substrate, wherein a total depth of the isolation structure is greater than the third depth.

[0096] In another embodiment, a method is discussed, comprising: forming a trench through a dummy device structure in an isolation region of a substrate. In some embodiments, the method further comprises forming a first refill layer in a bottom portion of the trench and a sacrificial layer located above the first refill layer. In some examples, after removing the sacrificial layer to expose the first refill layer, the method further comprises conformally depositing a second refill layer in a bottom portion of the trench above the exposed first refill layer and in a top portion of the trench. In some embodiments, the method further comprises forming a third refill layer in a top portion and a bottom portion of the trench (including above the second refill layer). In some examples, the first refill layer, the second refill layer, and the third refill layer in the top portion and the bottom portion of the trench provide an isolation structure in the isolation region. In some embodiments, the first refill layer is composed of a material different from at least one of the second refill layer and the third refill layer.

[0097] In some embodiments, the first refill layer is the same as the second refill layer.

[0098] In some embodiments, the second refill layer is the same as the third refill layer.

[0099] In some embodiments, the first refill layer includes a non-fixed charge material.

[0100] In some embodiments, the isolation structure includes an air gap, a gap, or a combination thereof.

[0101] In some embodiments, a top surface of the first refill layer is buried in the substrate below a plane defined by top surfaces of adjacent shallow trench isolation (STI) features, and wherein a bottom surface of the first refill layer extends deeper into the substrate than a bottom surface of the adjacent shallow trench isolation features.

[0102] In some embodiments, the total depth of the isolation structure is greater than a depth of an adjacent shallow trench isolation (STI) feature.

[0103] In yet another embodiment, a semiconductor device is discussed, comprising: an active region and an isolation structure disposed in an isolation region defined at a boundary of the active region. In some embodiments, the isolation structure comprises a bottom portion and a top portion disposed above the bottom portion. In some examples, the bottom portion comprises a first refill layer, and the top portion comprises a second refill layer and a third refill layer. In some embodiments, the first refill layer is composed of a material different from at least one of the second refill layer and the third refill layer. An embodiment of the present invention also provides a semiconductor device, comprising: an active region including a transistor; and an isolation structure disposed in an isolation region defined at a boundary of the active region; wherein the isolation structure comprises a bottom portion and a top portion, the bottom portion comprising a first refill layer, the top portion disposed above the bottom portion, the top portion comprising one or more refill layers; wherein the first refill layer is composed of a material different from at least one of the one or more refill layers.

[0104] In some embodiments, the isolation structure includes an air gap, a gap, or a combination thereof.

[0105] In some embodiments, the semiconductor device also includes a shallow trench isolation (STI) feature adjacent to the active area, wherein the top portion of the isolation structure extends to a first depth in the underlying substrate, wherein a top surface of the shallow trench isolation feature extends to a second depth in the underlying substrate, wherein a bottom surface of the shallow trench isolation feature extends to a third depth in the underlying substrate, and wherein the first depth is greater than the second depth and less than the third depth.

[0106] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing a partially fabricated semiconductor device comprising a dummy gate structure disposed above a semiconductor layer stack; removing at least a portion of the dummy gate structure and each semiconductor layer of the semiconductor layer stack to form a trench; forming one or more refill layers in a bottom portion of the trench; as well as One or more refill layers are formed in a top portion of the trench above the bottom portion of the trench, wherein the one or more refill layers in the top portion and the bottom portion of the trench define a top portion and a bottom portion of an isolation structure, respectively, and wherein at least one refill layer of the corresponding top portion and bottom portion of the isolation structure has different material compositions.

2. The method according to claim 1, wherein: The bottom portion of the isolation structure includes a first refill layer, and wherein the top portion of the isolation structure includes a second refill layer and a third refill layer located above the second refill layer.

3. The method according to claim 2, wherein: The first refill layer, the second refill layer, and the third refill layer are different from each other.

4. The method according to claim 2, wherein: The first refill layer is identical to the second refill layer.

5. The method according to claim 1, wherein: The bottom portion of the isolation structure includes a SiO-like material, and wherein the top portion of the isolation structure includes a SiN-like material.

6. The method according to claim 1, wherein: The bottom portion of the isolation structure includes a fixed charge free material.

7. The method according to claim 1, wherein: The isolation structure includes an air gap, a gap or a combination thereof.

8. The method according to claim 1, wherein: The top portion of the isolation structure extends to a first depth in an underlying substrate, wherein a top surface of an adjacent shallow trench isolation feature extends to a second depth in the underlying substrate, and wherein a bottom surface of the adjacent shallow trench isolation feature extends to a third depth in the underlying substrate.

9. A method for manufacturing a semiconductor device, comprising: forming a trench through the dummy device structure in an isolation region of the substrate; forming a first refill layer and a sacrificial layer in a bottom portion of the trench, the sacrificial layer being located over the first refill layer; after removing the sacrificial layer to expose the first refill layer, conformally depositing a second refill layer within the bottom portion of the trench over the exposed first refill layer and within a top portion of the trench; as well as A third refill layer is formed within the top portion and the bottom portion of the groove including above the second refill layer, wherein the first refill layer, the second refill layer and the third refill layer in the top portion and the bottom portion of the groove provide an isolation structure in the isolation region, and wherein the first refill layer is composed of a material different from at least one of the second refill layer and the third refill layer.

10. A semiconductor device comprising: an active region, the active region comprising a transistor; as well as an isolation structure disposed in an isolation region defined at a boundary of the active region; Wherein, the isolation structure comprises: a bottom portion comprising a first refill layer; and a top portion disposed over the bottom portion, the top portion comprising one or more refill layers; Wherein the first refill layer is composed of a different material than at least one of the one or more refill layers.

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