Formation method of semiconductor device
By defining and forming PMOS, NMOS and dummy gate regions on the material layer of the semiconductor device, the metal residue problem caused by over-grinding and dishing during the manufacturing process is solved, the efficiency and reliability of the device are improved, and the response speed of the circuit is improved.
Patent Information
- Application Number
- CN202311526342.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-14
- Publication Date
- 2025-05-23
AI Technical Summary
During the manufacturing process of metal oxide semiconductor (MOS) transistors, problems of over-grinding and/or dishing may occur in certain areas of the material layer, resulting in the retention of metal residues and affecting the effectiveness and reliability of subsequent manufacturing processes.
By defining the first PMOS region, the first NMOS region and the first dummy gate region on the material layer and forming corresponding PMOS, NMOS and dummy gates in these regions, ensuring that the height of the dummy gate is smaller than that of PMOS and NMOS, thereby avoiding the problem of dishing or over-grinding.
Effectively prevent metal residues from remaining in the Periphery area or Dummy Seal Ring area, ensure the normal progress of subsequent manufacturing processes, improve the efficiency and reliability of the device, and improve the response speed of the circuit by reasonably setting the heights of PMOS, NMOS and dummy gates.
Smart Images
Figure CN120035222A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method for forming a semiconductor device. Background Art
[0002] Metal-oxide semiconductor (MOS) transistors are generally formed using polysilicon gate electrodes. When making MOS integrated circuits, N-channel MOSFETs (NMOS) need to be made on a P substrate; P-channel MOSFETs (Positive Metal-Oxide-Semiconductors, PMOS) need to be made on an N substrate. Figure 1 As shown, in the process of metal aluminum chemical mechanical polishing, over-polishing and / or dishing may occur in the A region of the material layer, resulting in some metal residues remaining in the region. The presence of the metal residues may cause disadvantages to the subsequent manufacturing process and reduce the performance and reliability of the device. Summary of the invention
[0003] An object of the present disclosure is to provide a method for forming a semiconductor device, which method can at least partially solve the technical problems existing in the related art.
[0004] In order to achieve the above object, the present disclosure provides a method for forming a semiconductor device, the method comprising:
[0005] Step S10: providing a substrate and a material layer having multiple thin films stacked on the substrate, for forming a gate structure;
[0006] Step S21: defining a first dummy gate region while defining a first PMOS region and a first NMOS region on the material layer; and
[0007] Step S30: forming a PMOS in the first PMOS region, forming an NMOS in the first NMOS region, and forming a dummy gate in the first dummy gate region;
[0008] The height of the PMOS is equal to the height of the NMOS, and the dummy gate is lower than the heights of the PMOS and the NMOS.
[0009] Optionally, the material layer includes a first PR layer disposed at the topmost layer, and the method further includes: in the step S21, removing material of the first PR layer except the first PMOS region, the first NMOS region and the first dummy gate region.
[0010] Optionally, before the step S21, the step S10 includes the step S11: providing the first PR layer, the Barc layer, the Nfdarc layer, the Apf layer, the Oxide layer and the A-Si layer stacked in sequence from top to bottom.
[0011] Optionally, the method further includes: in the step S21, adding a Sin layer between the Oxide layer and the A-Si layer.
[0012] Optionally, the method comprises:
[0013] Step S22 after step S21: etching the first PMOS region, the first NMOS region and the first dummy gate region, and terminating at the oxide layer to form a second PMOS region in the first PMOS region, a second NMOS region in the first NMOS region, a second dummy gate region in the first dummy gate region, and etching the portion of the material layer except the first PMOS region, the first NMOS region and the first dummy gate region to the substrate.
[0014] Optionally, the forming method further includes a step S23 after the step S22:
[0015] The second dummy gate region is exposed, and the second PR layer is simultaneously covered at the second PMOS region and the second NMOS region.
[0016] Optionally, the forming method further includes a step S24 after the step S23:
[0017] removing the Sin layer at the second dummy gate region and reducing the thickness of the A-Si layer at the second dummy gate region to form a third dummy gate region; and
[0018] The second PR layer of the second PMOS region and the second NMOS region is removed.
[0019] Optionally, the forming method further includes a step S25 after the step S24: removing the oxide layer and the Sin layer in the second PMOS region and the second NMOS region respectively to form a third PMOS region and a third NMOS region respectively.
[0020] Optionally, step S30 includes step S31 after step S25: using a thin film material deposition process to respectively set a contact etch stop layer in the third PMOS region, the third NMOS region and the third dummy gate region.
[0021] Optionally, the forming method includes step S32 after step S31:
[0022] A chemical mechanical polishing manufacturing process is used to polish the contact etch stop layer of the fourth PMOS region and the fourth NMOS region to expose the A-Si layer of the fourth PMOS region and the fourth NMOS region, and a metal gate is used to replace the A-Si layer in the fourth PMOS region and the fourth NMOS region.
[0023] Through the above technical solution, by simultaneously defining the first dummy gate region in the first PMOS region and the first NMOS region of the material layer, in the Periphery region or the Dummy Seal Ring region, and forming a dummy gate with a height smaller than that of PMOS and NMOS, the problem of discing or over-grinding, that is, the problem of the dielectric layer being concave at the dummy gate, can be avoided, thereby effectively preventing metal residues from being left in the Periphery region or the Dummy Seal Ring region, thereby effectively ensuring that the subsequent manufacturing process is not adversely affected and the performance and reliability of the device are reduced. In addition, by setting the heights of PMOS, NMOS and the dummy gate more reasonably, when the voltage between the dummy gate and the PMOS or NMOS changes, the response time is faster, thereby improving the operating speed of the circuit.
[0024] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:
[0026] Figure 1 It is a partial structural cross-sectional view of a semiconductor device provided in the related art;
[0027] Figure 2-Figure 8 is a cross-sectional view of a local structure of a semiconductor device provided by an exemplary embodiment of the present disclosure;
[0028] Fig. 9 It is a schematic flow chart of a method for forming a semiconductor device provided in an exemplary embodiment of the present disclosure.
[0029] Description of Reference Numerals
[0030] 10-PMOS; 11-first PMOS region; 12-second PMOS region; 13-third PMOS region; 20-NMOS; 21-first NMOS region; 22-second NMOS region; 23-third NMOS region; 30-dummy gate; 31-first dummy gate region; 32-second dummy gate region; 33-third dummy gate region; 34-fourth dummy gate region; 41a-first PR layer; 41b-second PR layer; 50-contact etch stop layer; 60-metal gate; 70-substrate. DETAILED DESCRIPTION
[0031] The specific implementation of the present disclosure is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the present disclosure, and is not used to limit the present disclosure.
[0032] In the present disclosure, unless otherwise stated, the directional words used, such as "top" and "bottom", are defined according to the usage habits of the semiconductor device provided by the present disclosure. Figure 8 The terms used in this disclosure, such as "first", "second", etc., are intended to distinguish one element from another and do not have order or importance. In addition, when the following description refers to the drawings, the same reference numerals in different drawings represent the same or similar elements.
[0033] Reference Figure 2-Figure 9 The present disclosure provides a method for forming a semiconductor device. The method may include step S10. In step S10, a substrate 70 and a material layer having multiple thin films stacked on the substrate 70 are provided. The multiple thin films may be photoresist layers of different materials, respectively, for forming a gate structure. The method may also include step S21. In step S21, a first PMOS region 11 and a first NMOS region 21 may be defined on the material layer, and correspondingly in the periphery region (peripheral region, i.e., the peripheral region of PMOS and NMOS) or the dummy seal ring region (virtual seal ring region, i.e., corresponding to Figure 3 The method may further include step S30, in which a PMOS 10 may be formed in the first PMOS region 11, an NMOS 20 may be formed in the first NMOS region 21, and a dummy gate 30 may be formed in the first dummy gate region 31, wherein the height of the PMOS 10 is equal to the height of the NMOS 20, and the dummy gate 30 is lower than the heights of the PMOS 10 and the NMOS 20.
[0034] Through the above technical solution, by defining the first dummy gate region 31 in the periphery region or the dummy seal ring region while defining the first PMOS region 11 and the first NMOS region 21 of the material layer, and forming a dummy gate 30 with a height less than that of PMOS 10 and NMOS 20, the problem of discing or over-grinding, that is, the problem of the dielectric layer being concave at the dummy gate, can be avoided, thereby effectively preventing metal residues from being left in the periphery region or the dummy seal ring region, thereby effectively ensuring that the subsequent manufacturing process is not disadvantageous and reduces the performance and reliability of the device. In addition, by setting the heights of PMOS 10 and NMOS 20 and the dummy gate 30 more reasonably, when the voltage between the dummy gate 30 and PMOS 10 or NMOS 20 changes, the response time is faster, and the operating speed of the circuit can be improved.
[0035] Reference Figure 2 and Fig. 9 The material layer may include a first PR layer 41a disposed on the topmost layer, and the method further includes removing the material of the first PR layer 41a except the first PMOS region 11, the first NMOS region 21 and the first dummy gate region 31 in step S21, thereby retaining a portion required for forming a semiconductor.
[0036] Reference Figure 2 and Figure 3 Before step S21, step S10 includes step S11, in which a first PR layer 41a (Bottom Anti-Reflective Coating, photoresist layer), a Barc layer (Bottom Anti-Reflective Coating, bottom anti-reflective coating), a Nfdarc layer (Nitrogen-free dielectric anti-reflective coating, nitrogen-free dielectric anti-reflective coating), an Apf layer (Anti-Reflective Coating, anti-reflective coating), an Oxide layer (oxide layer) and an A-Si layer (Amorphous Silicon, amorphous silicon layer) stacked in sequence from top to bottom can be provided, so that the material layer can undergo chemical reaction and cross-linking reaction at the same time after light exposure to form soluble and insoluble regions to meet the formation needs of semiconductor devices.
[0037] Reference Figure 3 and Fig. 9The method provided in this embodiment also includes, in step S21, adding a SiN layer (silicon nitride layer) between the oxide layer and the A-Si layer of the material layer, that is, forming a SiN layer on the surface of the A-Si layer, and etching the SiN layer to pattern it, so as to obtain a SiN hard mask layer. According to the embodiment provided by the present disclosure, the SiN layer can be patterned by dry etching, which has the advantage of good directionality and can obtain a better SiN hard mask layer morphology.
[0038] Reference Figure 4 and Fig. 9 , the method provided in this embodiment also includes a step S22 after step S21. In step S22, the first PMOS region 11, the first NMOS region 21 and the first dummy gate region 31 are etched and terminated at the oxide layer to form a second PMOS region 12 in the first PMOS region 11, a second NMOS region 22 in the first NMOS region 21, and a second dummy gate region 32 in the first dummy gate region 31, and the portion of the material layer other than the first PMOS region 11, the first NMOS region 21 and the first dummy gate region 31 is etched to the substrate. In the present disclosure, by terminating the photolithography at the oxide layer (i.e., the oxide layer), it is possible to effectively provide protection for the underlying material (such as silicon and other materials), effectively prevent chemical and physical damage, and provide surface flatness so as to perform precise pattern definition in subsequent process steps.
[0039] Reference Figure 5 and Fig. 9 The formation method provided by the present disclosure further includes a step S23 after step S22, in which the second dummy gate region 32 is exposed, and the second PR layer 41b is simultaneously covered at the second PMOS region 12 and the second NMOS region 22, so that the second PMOS region 12, the second NMOS region and the second dummy gate region 32 can be effectively isolated to prevent mutual interference in subsequent steps. At the same time, in the manufacturing process, using photoresist to cover multiple areas at one time can simplify the process steps. Compared with processing the second PMOS region 12 and the second NMOS region 22 separately, covering the second PR layer at the same time can improve production efficiency and reduce manufacturing costs.
[0040] Reference Figure 6 and Fig. 9, the formation method provided by the present disclosure also includes a step S24 after step S23. In step S24, the Sin layer at the second dummy gate region 32 is removed, and the Sin layer can be removed from the second dummy gate region 32 by dry chemical etching or physical etching. At the same time, the thickness of the A-Si layer at the second dummy gate region 32 is reduced to reach the required thickness, thereby forming a third dummy gate region 33, thereby meeting the process requirements. In addition, in step S24, the second PR layer 41b of the second PMOS region 13 and the second NMOS region 23 is also removed, specifically, by wet or dry chemical etching or physical etching.
[0041] Reference Fig. 9 The formation method provided by the present disclosure further includes a step S25 after step S24, in which the oxide layer and the Sin layer in the second PMOS region 12 and the second NMOS region 22 are removed respectively to form the third PMOS region 13 and the third NMOS region 23 respectively. By removing the oxide (i.e., the oxide layer) and the silicon nitride layer (i.e., the Sin layer), a purer and more uniform surface can be obtained to avoid contamination or impurities, which is helpful for subsequent manufacturing steps and device performance. By removing the oxide (i.e., the oxide layer) and the silicon nitride layer (i.e., the Sin layer), the height difference between the gates can be eliminated to obtain a more uniform surface, which is helpful for subsequent manufacturing steps and device performance.
[0042] Further, refer to Figure 7 and Fig. 9 Step S300 in the method for forming a semiconductor device provided by the present disclosure also includes step S31 after step S25: using a thin film material deposition process, for example, an ILD0 Dep (Zero layer Inter-Layer-Dielectric Deposition) process can be used, and dielectric materials are deposited on the surfaces of the third PMOS region 13, the third NMOS region 23 and the third dummy gate region 33 to respectively set a contact etch stop layer 50, namely CESL SiN (Contact Etch Stop Layer SiN), on the third PMOS region 13, the third NMOS region 23 and the third dummy gate region 33. The contact etch stop layer can be made of silicon nitride (SiN) to prevent the etching process from over-etching the underlying material. In the embodiment provided in the present disclosure, step S25 may also include a PREB process (photoresist back etching) to remove the hard mask layer (i.e., the above-mentioned SiN layer) on the top of the third PMOS region 13, the third NMOS region 23 and the third dummy gate region 33 to ensure the quality and adhesion of the contact etch stop layer 50.
[0043] Reference Figure 8 and Fig. 9 The formation method provided by the present disclosure further includes a step S32 after the step S31, in which a chemical mechanical polishing manufacturing process is adopted to grind the contact etch stop layer 50 on the top of the third PMOS region 13 and the third NMOS region 23 to expose the A-Si layer of the third PMOS region 13 and the third NMOS region 23, so as to facilitate the subsequent process steps, and a metal gate 60 is adopted to replace the A-Si layer in the third PMOS region 13 and the third NMOS region 23, thereby forming PMOS10 and NMOS20 respectively. On the one hand, the resistance of the third PMOS region 13 and the third NMOS region 23 can be reduced, and the efficiency of current transmission can be improved, thereby improving the conductivity of PMOS10 and NMOS20. On the other hand, the metal gate has higher stability and durability than the A-Si layer, thereby improving the reliability and long-term stability of PMOS10 and NMOS20.
[0044] The preferred embodiments of the present disclosure are described in detail above in conjunction with the accompanying drawings. However, the present disclosure is not limited to the specific details in the above embodiments. Within the technical concept of the present disclosure, the technical solution of the present disclosure can be subjected to a variety of simple modifications, and these simple modifications all belong to the protection scope of the present disclosure. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present disclosure will not further describe various possible combinations.
[0045] In addition, various embodiments of the present disclosure may be arbitrarily combined, and as long as they do not violate the concept of the present disclosure, they should also be regarded as the contents disclosed by the present disclosure.
Claims
1. A method for forming a semiconductor device, It is characterized in that The forming method comprises: Step S10: providing a substrate and a material layer having multiple thin films stacked on the substrate, for forming a gate structure; Step S21: defining a first dummy gate region while defining a first PMOS region and a first NMOS region on the material layer; and Step S30: forming a PMOS in the first PMOS region, forming an NMOS in the first NMOS region, and forming a dummy gate in the first dummy gate region; The height of the PMOS is equal to the height of the NMOS, and the dummy gate is lower than the heights of the PMOS and the NMOS.
2. The method for forming a semiconductor device according to claim 1, It is characterized in that The material layer includes a first PR layer disposed on the topmost layer. The method further includes: in the step S21 , removing material of the first PR layer except the first PMOS region, the first NMOS region, and the first dummy gate region.
3. The method for forming a semiconductor device according to claim 2, It is characterized in that Before the step S21, the step S10 includes the step S11: providing the first PR layer, the Barc layer, the Nfdarc layer, the Apf layer, the Oxide layer and the A-Si layer stacked in sequence from top to bottom.
4. The method for forming a semiconductor device according to claim 3, It is characterized in that The method further includes: in the step S21, adding a Sin layer between the Oxide layer and the A-Si layer.
5. The method for forming a semiconductor device according to claim 4, It is characterized in that The method comprises: Step S22 after step S21: etching the first PMOS region, the first NMOS region and the first dummy gate region, and terminating at the oxide layer to form a second PMOS region in the first PMOS region, a second NMOS region in the first NMOS region, a second dummy gate region in the first dummy gate region, and etching the portion of the material layer except the first PMOS region, the first NMOS region and the first dummy gate region to the substrate.
6. The method for forming a semiconductor device according to claim 5, It is characterized in that The forming method further comprises a step S23 after the step S22: The second dummy gate region is exposed, and the second PR layer is simultaneously covered at the second PMOS region and the second NMOS region.
7. The method for forming a semiconductor device according to claim 6, It is characterized in that The forming method further comprises a step S24 after the step S23: removing the Sin layer at the second dummy gate region, and reducing the thickness of the A-Si layer at the second dummy gate region to form a third dummy gate region; and The second PR layer of the second PMOS region and the second NMOS region is removed.
8. The method for forming a semiconductor device according to claim 7, It is characterized in that The forming method further includes a step S25 after the step S24: removing the oxide layer and the Sin layer in the second PMOS region and the second NMOS region respectively to form a third PMOS region and a third NMOS region respectively.
9. The method for forming a semiconductor device according to claim 8, It is characterized in that Step S30 includes step S31 after step S25: using a thin film material deposition process to respectively set a contact etch stop layer in the third PMOS region, the third NMOS region and the third dummy gate region.
10. The method for forming a semiconductor device according to claim 9, It is characterized in that The forming method comprises step S32 after step S31: A chemical mechanical polishing manufacturing process is used to polish the contact etch stop layer of the third PMOS region and the third NMOS region to expose the A-Si layer of the third PMOS region and the third NMOS region, and a metal gate is used to replace the A-Si layer in the third PMOS region and the third NMOS region.