Semiconductor device design method and system
By designing raised patterns of different width values in semiconductor devices and testing multiple semiconductor devices, the target saturation current that meets preset performance conditions is selected, and the problem that gate connection area design is difficult to take into account both electrical signal transmission reliability and electrical performance, achieving accurate determination of raised size and performance.
Patent Information
- Application Number
- CN202510104033.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-22
- Publication Date
- 2025-05-23
AI Technical Summary
In semiconductor devices, the convex design of the gate connection region along the gate width direction is difficult to take into account both the electrical signal transmission reliability and electrical performance.
By designing raised patterns with different width values, multiple semiconductor devices are tested, the target saturation current that meets the preset performance conditions are selected, and their corresponding width value is determined as the target width value.
The convex dimensions of the gate connection region in the semiconductor device along the gate width direction are accurately determined, taking into account the reliability and electrical performance of electrical signals.
Smart Images
Figure CN120035223A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device design method and system thereof. Background Art
[0002] As the size of process nodes decreases, the area of semiconductor devices decreases. In one application scenario, the semiconductor device includes MOS transistors, which are connected to each other to form some functional electrical devices or connected to external logic circuits.
[0003] The gate of the MOS transistor is connected to the corresponding control line through a conductive plug. However, the cross-sectional size of the conductive plug is generally larger than the gate width. Therefore, when designing, the connection area on the gate needs to be designed to be a protrusion along the gate width to prevent the conductive plug from falling outside the connection area, thereby improving the reliability of electrical signal transmission.
[0004] However, the protrusion of the gate connection region along the gate width direction may affect the electrical performance of the MOS transistor and the semiconductor device including the MOS transistor.
[0005] Therefore, how to balance the electrical signal transmission reliability and electrical performance of semiconductor devices is a topic that the industry needs to consider.
[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0007] In view of the problems in the prior art, the purpose of the present invention is to provide a semiconductor device design method and system thereof, which overcomes the difficulties of the prior art and can accurately determine the protrusion size of the gate connection area along the gate width direction in the semiconductor device.
[0008] A first aspect of the present disclosure provides a semiconductor device design method, wherein the semiconductor device includes a MOS transistor, and a gate of the MOS transistor has a connection area for connecting a conductive plug; the semiconductor device design method includes:
[0009] For the pattern of the semiconductor device, the connection region in the MOS transistor pattern is provided with convex patterns with different widths along the gate width direction, so as to obtain a plurality of patterns of the semiconductor device;
[0010] Using the patterns of the plurality of semiconductor devices, respectively manufacturing the plurality of semiconductor devices;
[0011] A plurality of groups of saturation currents are tested corresponding to the plurality of semiconductor devices, and a target saturation current that meets a first preset performance condition is screened out from the plurality of groups of saturation currents, and a width value corresponding to the target saturation current is used as a target width value.
[0012] In some embodiments, the first preset performance condition includes that the target saturation current is not lower than a preset value.
[0013] In some implementations, the semiconductor device design method further includes:
[0014] The threshold voltage and the breakdown voltage of the plurality of semiconductor devices are tested respectively, so that the threshold voltage and the breakdown voltage corresponding to the target saturation current both reach their respective second preset performance conditions.
[0015] In some implementations, the semiconductor device design method further includes:
[0016] Before testing a plurality of groups of saturation currents corresponding to the plurality of semiconductor devices, conductive plugs are respectively made above the connection regions of the plurality of semiconductor devices;
[0017] respectively collecting positional relationship images between a plurality of conductive plugs on the semiconductor device and the connection region, and judging whether the conductive plug falls within the range of the connection region according to the positional relationship images;
[0018] The conductive plug corresponding to the target saturation current falls within the connection area.
[0019] In some embodiments, the step of providing the connection region in the MOS transistor pattern with convex patterns having different widths along the gate width direction comprises:
[0020] Obtaining a gate width value in each of the MOS transistor patterns;
[0021] For the connection region of the gate in each MOS transistor pattern, sub-protrusion patterns are respectively arranged on both sides along the gate width direction, and the width value of the protrusion pattern includes sub-width values of the sub-protrusion patterns on both sides along the gate width direction.
[0022] In some implementations, the sub-widths of the sub-protrusion patterns on both sides of the connection region in each of the MOS transistor patterns are equal.
[0023] In some embodiments, the semiconductor device is a static random access memory, a non-volatile memory, a programmable logic device, or a power device.
[0024] In some embodiments, the semiconductor device is the static random access memory, and each of the static random access memory cells includes a pull-up MOS transistor and a pull-down MOS transistor with a common gate, wherein the connection region is located at the common gate of the pull-up MOS transistor and the pull-down MOS transistor.
[0025] A second aspect of the present disclosure provides a semiconductor device design system, wherein the semiconductor device includes a MOS transistor, and a gate of the MOS transistor has a connection area for connecting a conductive plug; the semiconductor device design system includes:
[0026] A setting module, for the pattern of the semiconductor device, sets a convex pattern with different width values along the gate width direction in the connection area of the MOS transistor pattern therein, so as to obtain a plurality of patterns of the semiconductor device;
[0027] A manufacturing module, using patterns of a plurality of the semiconductor devices to manufacture a plurality of the semiconductor devices respectively;
[0028] The testing module tests a plurality of groups of saturation currents corresponding to the plurality of semiconductor devices, selects a target saturation current that meets a first preset performance condition from the plurality of groups of saturation currents, and uses a width value corresponding to the target saturation current as a target width value.
[0029] In some embodiments, the first preset performance condition includes that the target saturation current is not lower than a preset value.
[0030] Using the semiconductor device design method of this embodiment, in the pattern design stage, protrusions with different width values are designed for the gate connection area used to connect the conductive plug, and corresponding patterns of multiple semiconductor devices are obtained, and the width values of the gate connection areas in any two semiconductor device patterns are different. Further, the multiple semiconductor device patterns are used to make a finished structure of a semiconductor device for testing. Thereafter, the saturation current of the finished structure of the semiconductor device is tested, and multiple groups of saturation currents can be obtained corresponding to multiple semiconductor devices. Finally, a target saturation current that meets the first preset performance condition is screened out from the multiple groups of saturation currents. The target saturation current is considered to have good electrical performance while being able to meet the electrical connection requirements of the conductive plug.
[0031] By using the semiconductor device design method of this embodiment, the protrusion size of the gate connection region in the semiconductor device along the gate width direction can be accurately determined, taking into account both the electrical signal transmission reliability and the electrical performance of the semiconductor device.
[0032] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Other features, objectives and advantages of the present invention will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following accompanying drawings.
[0034] Figure 1 and Figure 2 It is a pattern schematic diagram of a semiconductor device in a semiconductor device design method provided in an embodiment of the present disclosure.
[0035] Figure 3 It is a flow chart of a semiconductor device design method provided by an embodiment of the present disclosure.
[0036] Figure 4 exhibit Figure 3 A schematic diagram of a pattern of a semiconductor device in a semiconductor device design method is shown.
[0037] Figure 5 A module structure diagram of a semiconductor device design system provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION
[0038] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0039] In addition, the accompanying drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the figures represent the same or similar parts, and their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.
[0040] In addition, the concepts such as "first" and "second" mentioned in the present disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.
[0041] The present disclosure provides a semiconductor device design method, such as Figure 1 As shown, the semiconductor device includes a MOS transistor, the gate of which has a connection region s for connecting a conductive plug. In order to adapt to the size of the conductive plug above, the connection region s has a protrusion along the gate width direction KK (refer to arrow J).
[0042] Recombination Figure 2 As shown, the protrusion J will extend to the overlapping area s1 of the gate G and the channel, which will increase the channel length and affect the electrical performance of the MOS transistor. Therefore, the semiconductor device design method proposed in the embodiment of the present disclosure is used to design the width value of the protrusion along the gate width direction KK (corresponding to the channel length direction).
[0043] like Figure 3 As shown, the semiconductor device design method includes but is not limited to the following steps:
[0044] Step 310: for the pattern of the semiconductor device, arranging convex patterns with different widths along the gate width direction in the connection region of the MOS transistor pattern, and correspondingly obtaining a plurality of patterns of the semiconductor device;
[0045] Step 320: using the patterns of the plurality of semiconductor devices to respectively manufacture the plurality of semiconductor devices;
[0046] Step 330: testing a plurality of groups of saturation currents corresponding to the plurality of semiconductor devices, and screening out a target saturation current that meets a first preset performance condition from the plurality of groups of saturation currents, and using a width value corresponding to the target saturation current as a target width value.
[0047] In one embodiment, a protrusion is formed in the connection region along the gate width direction, so that the overall width of the connection region is greater than the width of other regions of the gate.
[0048] Using the semiconductor device design method of this embodiment, in the pattern design stage, a raised pattern with different width values is designed for the gate connection area used to connect the conductive plug, and a plurality of semiconductor device patterns are obtained correspondingly, and the width values of the raised patterns in the gate connection area in any two semiconductor device patterns are different. Further, the plurality of semiconductor device patterns are used to manufacture a finished structure of a semiconductor device for testing. Thereafter, the saturation current is tested for the finished structure of the semiconductor device, and a plurality of groups of saturation currents can be obtained corresponding to the plurality of semiconductor devices. Finally, a target saturation current that meets the first preset performance condition is screened out from the plurality of groups of saturation currents. The target saturation current is considered to have good electrical performance while being able to meet the electrical connection requirements of the conductive plug.
[0049] By using the semiconductor device design method of this embodiment, the protrusion size of the gate connection region in the semiconductor device along the gate width direction can be accurately determined, taking into account both the electrical signal transmission reliability and the electrical performance of the semiconductor device.
[0050] In the embodiment of the present disclosure, before manufacturing the same MOS transistor or the device unit composed of MOS transistor and other structures in the semiconductor device, the above step 110 is performed, specifically using one or more electronic design automation (EDA) tools for testing semiconductor device design. In some embodiments, the EDA tool is a set of one or more sets of executable instructions executed by a processor or controller or a programmed computer to perform a specified function.
[0051] In performing step 110, a pattern design of a semiconductor device is generated or provided by a circuit engineer. In some embodiments, the design is generated or provided in the form of a schematic netlist such as a Simulation Program for Integrated Circuits (SPICE) netlist.
[0052] In some implementations, when executing step 110, a protrusion pattern with different width values is set in the gate connection region of at least one MOS transistor along the gate width direction, and then a plurality of design patterns of the semiconductor device can be obtained accordingly.
[0053] Among them, different width values of the raised pattern can be automatically generated according to a certain algorithm. For example, based on a certain empirical value, the width is automatically reduced according to a certain step length, so as to obtain multiple gradually increasing width values. The implementation method itself does not limit the specific value of the step length.
[0054] In the embodiments of the present disclosure, Figure 4 As shown, in the pattern of the MOS transistor, the convex pattern J2 of the gate connection region s includes sub-convex patterns J21 and J22 located on both sides along the gate width direction KK, and the width value of the convex pattern J2 includes two sub-width values x1 and x2 of the sub-convex patterns J21 and J12.
[0055] It should be noted that due to the existence of registration accuracy, the use of Figure 4 When the pattern shown is used to make a specific device, the raised pattern J2 may extend to the overlapping position with the AA area. Figure 2 The protrusion J1 is shown.
[0056] In this embodiment, step 110 is performed to set convex patterns with different width values in the connection area of the MOS transistor pattern along the gate width direction, specifically including:
[0057] Obtaining a gate width value in each of the MOS transistor patterns;
[0058] For the connection area of the gate in each MOS transistor pattern, sub-protrusion patterns are respectively set on both sides along the gate width direction, and the width value of the protrusion pattern includes the sub-width values of the sub-protrusion patterns on both sides along the gate width direction (exemplarily, such as x1 and x2 above).
[0059] In this embodiment, by bulging out toward both sides in the gate connection region, it is possible to avoid warping of one end of the gate, thereby forming a good device morphology and making the manufacturing process more controllable.
[0060] Using this embodiment, the width values of different protrusion patterns are shown in the following table:
[0061] 90％*x2 95％*x2 x2 105％*x2 90％*x1 95％*x1 x1 105％*x1
[0062] As mentioned above, x1 and x2 are reference values. On this basis, 90%*x1, 95%*x1 and 105%*x1 are set. For x2, refer to the above table and will not be repeated here.
[0063] According to the above table, rows and columns are combined to obtain multiple groups of width values, corresponding to which patterns of multiple semiconductor devices are obtained.
[0064] In one embodiment, the sub-width values of the sub-protrusion patterns on both sides of the connection region in each MOS transistor pattern are equal, which can ensure that the protrusions on both sides of the gate connection region are symmetrical with respect to the gate connection region, thereby obtaining a semiconductor device with good morphology.
[0065] In the embodiments of the present disclosure, the semiconductor device may be a static random-access memory (SRAM), a non-volatile memory (NVM), a programmable logic device (PLD), or a power device.
[0066] Taking SRAM as an example, it includes a plurality of SRAM cells, each RAM cell includes a pull-up MOS transistor and a pull-down MOS transistor with a common gate, wherein the connection region is located at the common gate of the pull-up MOS transistor and the pull-down MOS transistor.
[0067] In the embodiment of the present disclosure, when multiple patterns of semiconductor devices are obtained by executing step 110, step 120 is executed to respectively manufacture multiple semiconductor devices using these patterns.
[0068] Specifically, the semiconductor device includes a semiconductor substrate and a plurality of MOS transistors formed in and / or on the semiconductor substrate. The semiconductor substrate includes but is not limited to bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon-germanium substrate. In some embodiments, other semiconductor materials including group III, group IV, and group V elements are used. These MOS transistors can constitute a plurality of functional devices with a periodic structure.
[0069] Examples of MOS transistors include, but are not limited to, metal oxide field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field effect transistors (PEFT / NEFT), etc., fin field effect transistors (FinFETs) with raised source / drains, and planar MOS transistors. Examples of passive components include, but are not limited to, capacitors, inductors, fuses, resistors, and interconnects. Examples of interconnects include, but are not limited to, vias, conductive pads, wires, and conductive redistribution layers.
[0070] In an embodiment of the present disclosure, when multiple semiconductor devices are fabricated, step 130 is performed to test multiple sets of saturation currents corresponding to the multiple semiconductor devices.
[0071] Among them, the saturation current (Idsat) refers to the maximum current flowing between the source / drain when the gate voltage (Vg) is constant. The saturation current is inversely correlated with the channel length direction. When the channel length increases, the saturation current decreases, and conversely, when the channel length decreases, the saturation current increases.
[0072] In a semiconductor device, different protrusions have different width values, such that the overlapping regions with the AA region also have different width values, and the AA region below the overlapping region corresponds to the extended region of the channel.
[0073] If the channel length is too long, then the control ability of the gate over the channel becomes poor, the threshold voltage increases, resulting in too small a saturation current and deteriorating chip performance. Therefore, in this embodiment, by testing the saturation current and screening out the target saturation current that meets the first preset performance condition, that is, the width value corresponding to the target saturation current is appropriate and can be used as the final target width value.
[0074] In one embodiment, the first preset performance condition includes that the target saturation current is not lower than a preset value. The preset value is set according to the actual MOS transistor product and is not limited herein.
[0075] In an embodiment of the present disclosure, the semiconductor device design method may further include:
[0076] Testing the threshold voltage and breakdown voltage of the multiple semiconductor devices respectively, such that the threshold voltage and breakdown voltage corresponding to the target saturation current both meet their respective second preset performance conditions.
[0077] The threshold voltage (Vt) is the minimum voltage required to generate strong inversion. When the gate voltage Vg < Vt, the MOS transistor is in the off state, and when Vg ≥ Vt, a conductive channel is generated between the source / drain, and the MOS transistor is in the on state.
[0078] The breakdown voltage is the maximum voltage that the drain-source voltage Vd can withstand when Vg = Vs = 0. When Vd is greater than this voltage, a conductive channel is formed between the source and the drain and is not affected by the gate voltage. In the case where the device is made smaller and smaller, this situation will become more and more serious.
[0079] In the process of semiconductor device design, in addition to testing the saturation current, the threshold voltage and the breakdown voltage are also tested, so that the target saturation current corresponding to the final target width value satisfies the first preset performance condition, and at the same time, the corresponding threshold voltage and breakdown voltage also satisfy their respective second preset performance conditions.
[0080] In the embodiment of the present disclosure, the semiconductor device design method further includes:
[0081] Before testing multiple groups of saturation currents corresponding to multiple semiconductor devices, conductive plugs are respectively fabricated above the connection regions of the multiple semiconductor devices;
[0082] Respectively collect the position relationship images between the conductive plugs on the multiple semiconductor devices and the connection regions, and judge whether the conductive plugs fall within the range of the connection regions according to the position relationship images;
[0083] Among them, the conductive plug corresponding to the target saturation current falls within the connection region.
[0084] In this embodiment, by further forming a conductive plug and photographing the morphology of the semiconductor device, for example, using a transmission electron microscope (English: Transmission electron microscope, abbreviation: TEM, CTEM) to photograph the position relationship image between the conductive plug and the gate connection region to judge whether the conductive plug falls outside or inside the connection region. If it falls outside the gate connection region, it means that the convex width value of the gate connection region cannot adapt to the size of the conductive plug at this time. If it falls within the gate connection region, it means that the convex width value can adapt to the size of the conductive plug at this time, and the convex width value at this time can be used as the target width value.
[0085] This embodiment further improves the accuracy of the final target width value and ensures the good electrical performance and transmission performance of the semiconductor device.
[0086] The present disclosure also provides a semiconductor device design system, wherein the semiconductor device includes a MOS transistor, the gate of the MOS transistor has a connection area for connecting a conductive plug, such as Figure 5 As shown, the semiconductor device design system specifically includes:
[0087] A setting module 510, a setting module, for the pattern of the semiconductor device, sets a convex pattern with different width values along the gate width direction in the connection area of the MOS transistor pattern therein, and correspondingly obtains a plurality of patterns of the semiconductor device;
[0088] A manufacturing module 520, using the patterns of the plurality of semiconductor devices to manufacture the plurality of semiconductor devices respectively;
[0089] The testing module 530 tests a plurality of groups of saturation currents corresponding to the plurality of semiconductor devices, selects a target saturation current that meets a first preset performance condition from the plurality of groups of saturation currents, and uses a width value corresponding to the target saturation current as a target width value.
[0090] By using the semiconductor device design system and the semiconductor device design method of the present embodiment, the protrusion size of the gate connection area along the gate width direction in the semiconductor device can be accurately determined, taking into account the electrical signal transmission reliability and electrical performance of the semiconductor device.
[0091] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.
Claims
1. A semiconductor device design method, characterized in that: The semiconductor device comprises a MOS transistor, the gate of the MOS transistor having a connection region for connecting a conductive plug; The semiconductor device design method comprises: For the pattern of the semiconductor device, the connection region in the MOS transistor pattern is provided with convex patterns with different widths along the gate width direction, so as to obtain a plurality of patterns of the semiconductor device; Using the patterns of the plurality of semiconductor devices, respectively manufacturing the plurality of semiconductor devices; A plurality of groups of saturation currents are tested corresponding to the plurality of semiconductor devices, and a target saturation current that meets a first preset performance condition is screened out from the plurality of groups of saturation currents, and a width value corresponding to the target saturation current is used as a target width value.
2. The semiconductor device design method according to claim 1, characterized in that: The first preset performance condition includes that the target saturation current is not lower than a preset value.
3. The semiconductor device design method according to claim 1, characterized in that: The semiconductor device design method further includes: The threshold voltage and the breakdown voltage of the plurality of semiconductor devices are tested respectively, so that the threshold voltage and the breakdown voltage corresponding to the target saturation current both reach their respective second preset performance conditions.
4. The semiconductor device design method according to claim 1, characterized in that: The semiconductor device design method further includes: Before testing a plurality of groups of saturation currents corresponding to the plurality of semiconductor devices, conductive plugs are respectively formed above the connection regions of the plurality of semiconductor devices; respectively collecting positional relationship images between a plurality of conductive plugs on the semiconductor device and the connection region, and judging whether the conductive plug falls within the range of the connection region according to the positional relationship images; The conductive plug corresponding to the target saturation current falls within the connection area.
5. The semiconductor device design method according to claim 1, characterized in that: The step of providing the connection region in the MOS transistor pattern with convex patterns of different widths along the gate width direction comprises: Obtaining a gate width value in each of the MOS transistor patterns; For the connection region of the gate in each MOS transistor pattern, sub-protrusion patterns are respectively arranged on both sides along the gate width direction, and the width value of the protrusion pattern includes sub-width values of the sub-protrusion patterns on both sides along the gate width direction.
6. The semiconductor device design method according to claim 5, characterized in that: The sub-width values of the sub-protrusion patterns on both sides of the connection region in each of the MOS transistor patterns are equal.
7. The semiconductor device design method according to claim 1, characterized in that: The semiconductor device is a static random access memory, a non-volatile memory, a programmable logic device or a power device.
8. The semiconductor device design method according to claim 7, characterized in that: The semiconductor device is the static random access memory, each of the static random access memory cells comprises a pull-up MOS transistor and a pull-down MOS transistor with a common gate, wherein the connection region is located at the common gate of the pull-up MOS transistor and the pull-down MOS transistor.
9. A semiconductor device design system, characterized in that: The semiconductor device comprises a MOS transistor, the gate of the MOS transistor having a connection region for connecting a conductive plug; The semiconductor device design system comprises: A setting module, for the pattern of the semiconductor device, sets a convex pattern with different width values along the gate width direction in the connection area of the MOS transistor pattern therein, so as to obtain a plurality of patterns of the semiconductor device; A manufacturing module, using patterns of a plurality of the semiconductor devices to manufacture a plurality of the semiconductor devices respectively; The testing module tests a plurality of groups of saturation currents corresponding to the plurality of semiconductor devices, selects a target saturation current that meets a first preset performance condition from the plurality of groups of saturation currents, and uses a width value corresponding to the target saturation current as a target width value.
10. The semiconductor device design system according to claim 9, characterized in that: The first preset performance condition includes that the target saturation current is not lower than a preset value.