Multi-stage conditioning and amplifying device, equipment and system for electroencephalogram signals

Abstract

This application relates to the fields of EEG signal processing and brain-computer interfaces, and provides a multi-stage conditioning and amplification device, equipment, and system for EEG signals. The device includes a reference signal buffer distribution module, a first-stage filtering module, eight first-stage differential amplification modules, a second-stage filtering module, eight second-stage differential amplification modules, a bias drive signal generation module, and a differential ADC module. It can perform two-stage filtering and two-stage amplification processing on EEG signals and combine them with a reference signal for joint conditioning, thereby improving the signal-to-noise ratio of the conditioned EEG signals.

Description

Technical Field

[0001] This application relates to the fields of EEG signal processing and brain-computer interface technology, specifically to a multi-level conditioning and amplification device, equipment and system for EEG signals. Background Technology

[0002] Obtaining stable and reliable EEG signals is a prerequisite for scalp-brain-computer interface technology. Electroencephalogram (EEG) signals are spontaneous bioelectrical activities at the scale of brain cell groups. EEG signals are typically very weak, with amplitudes generally between 1 and 100 μV, and are easily affected by various physiological and environmental noises, leading to a reduced signal-to-noise ratio. Electromagnetic interference is the most critical type of noise, including 1 / f noise from components themselves, thermal noise generated by circuits, 50Hz mains frequency noise, differential-mode noise caused by circuit asymmetry, and DC bias errors. To reduce the impact of these noises and improve the signal-to-noise ratio, continuous improvement of the EEG signal conditioning and acquisition system is necessary, which is crucial for enhancing the accuracy and reliability of EEG signal research.

[0003] In existing EEG signal conditioning circuits, the acquired EEG signals are usually directly converted to analog signals after passing through a simple filtering circuit. This results in low utilization of the dynamic range of the analog signal converter, significant impact from quantization noise, low common-mode rejection ratio, and high common-mode noise, leading to a low signal-to-noise ratio and unsatisfactory EEG signal acquisition. Summary of the Invention

[0004] This application provides a multi-stage conditioning and amplification device, equipment, and system for EEG signals, which can perform two-stage filtering and two-stage amplification on EEG signals and combine them with a reference signal for joint conditioning, thereby improving the signal-to-noise ratio of the conditioned EEG signals.

[0005] A first aspect of this application provides a multi-level conditioning and amplification device for electroencephalogram (EEG) signals. The device includes a reference signal buffer distribution module, a first-stage filtering module, eight first-stage differential amplification modules, a second-stage filtering module, eight second-stage differential amplification modules, a bias drive signal generation module, and a differential ADC module.

[0006] The signal output port of the reference signal buffer distribution module is connected to the first type of input port of the first filtering module, and the second type of input port of the first filtering module is the signal receiving port of 8-channel EEG signals.

[0007] The eight Type I signal output ports of the first-stage filtering module are respectively connected to the first input ports of the eight first-stage differential amplifier modules, and the eight Type II signal output ports of the first-stage filtering module are respectively connected to the second input ports of the eight first-stage differential amplifier modules.

[0008] The output ports of the 8-channel first-stage differential amplifier module are connected to the corresponding 8-channel input ports of the second-stage filter module. The 8 output ports of the second-stage filter module are respectively connected to the corresponding input ports of the 8-channel second-stage differential amplifier module. The first type of output ports of the 8-channel second-stage differential amplifier module are connected to the corresponding signal input ports in the differential ADC module. The second type of output ports of the 8-channel second-stage differential amplifier module are connected to the input ports of the bias drive signal generation module. The corresponding signal output ports in the differential ADC module are connected to the microprocessor. The output port of the bias drive signal generation module is connected to the bias drive electrode.

[0009] The reference signal buffer allocation module is used to receive the reference signal of the acquired EEG signal, and to generate 8 identical and independent reference signals based on the reference signal.

[0010] The gain of the first-stage differential amplifier module is less than the gain of the second-stage differential amplifier module.

[0011] In this example, the EEG signal is filtered by the first-stage filtering module to retain the effective frequency band. Simultaneously, the reference signal is buffered and distributed to generate eight identical and independent reference signals, which serve as the differential reference input signals for the eight EEG signals. These signals are then filtered and conditioned to match the electrical parameters of the EEG signals. The processed EEG signal and corresponding reference signal for each channel are then input as a differential pair to the first-stage differential amplifier circuit of the corresponding channel for amplification, improving the signal-to-noise ratio. The output differential signal then passes through a second-stage low-pass filter circuit to further attenuate high-frequency noise before entering the second-stage differential amplifier circuit. The signal is further amplified by a secondary amplifier circuit, and finally, an 8-channel parallel differential ADC circuit performs analog-to-digital conversion on the 8 channels of EEG signals. The MCU controller then performs the acquisition, transmission, and processing of the EEG signals. Simultaneously, a bias drive signal generation and output are implemented. That is, the DC bias of the signal output from the second-stage differential amplifier circuit generates a common-mode voltage signal with opposite polarity through the bias drive signal generation module. This signal is connected to the human body through the bias drive electrode to provide a common-mode reference voltage for the human body and limit the common-mode interference noise to a very narrow range, reducing the common-mode interference of the EEG signals and further improving the signal-to-noise ratio of the EEG signals.

[0012] In one specific implementation, the reference signal buffer allocation module includes a first unity-gain buffer, a second unity-gain buffer, a sixtieth capacitor, a sixty-first capacitor, a sixty-second capacitor, and a sixty-third capacitor, wherein,

[0013] The first, fifth, sixth, and tenth ports of the first unity-gain buffer are used to receive reference signals of EEG signals. The third port of the first unity-gain buffer is connected to the positive power supply port and the first terminal of the sixtieth capacitor, and the second terminal of the sixtieth capacitor is grounded. The eighth port of the first unity-gain buffer is connected to the negative power supply port and the first terminal of the sixty-first capacitor, and the second terminal of the sixty-first capacitor is grounded. The second, fourth, seventh, and ninth ports of the first unity-gain buffer are respectively connected to the corresponding first type of input ports in the first filtering module.

[0014] The first, fifth, sixth, and tenth ports of the second unity-gain buffer are used to receive reference signals of EEG signals. The third port of the second unity-gain buffer is connected to the positive power supply port and the first terminal of the sixty-second capacitor, and the second terminal of the sixty-second capacitor is grounded. The eighth port of the second unity-gain buffer is connected to the negative power supply port and the first terminal of the sixty-third capacitor, and the second terminal of the sixty-third capacitor is grounded. The second, fourth, seventh, and ninth ports of the second unity-gain buffer are respectively connected to the corresponding first type of input ports in the first filtering module.

[0015] In one specific implementation, the first-stage differential amplifier module includes a first amplifier chip, a 168th capacitor, a 112th resistor, a 169th capacitor, a 170th capacitor, a 171st capacitor, a 172nd capacitor, a 173rd capacitor, and a 113th resistor, wherein...

[0016] The first signal input port and the second signal input port of the first-stage differential amplifier module are connected in parallel with the 168th capacitor, and then connected to the first port and the fourth port of the first amplifier chip respectively. The second port and the third port of the first amplifier chip are connected in series with the 112th resistor.

[0017] The fifth port of the first amplifier chip is connected to the first terminal of the first 169 capacitor and the positive power supply port, and the second terminal of the first 169 capacitor is grounded.

[0018] The sixth port of the first amplifier chip is connected to the fourteenth port, and the fourteenth port of the first amplifier chip is the second output port of the first stage differential amplifier module.

[0019] The seventh port of the first amplifier chip is grounded, the eighth port of the first amplifier chip is connected to the negative power supply port, the zero port, and the first end of the 170th capacitor, the second end of the 170th capacitor is grounded, and the ninth port of the first amplifier chip is grounded.

[0020] The twelfth port of the first amplifier chip is connected to the first terminal of the first 173 capacitor and the first terminal of the first 113 resistor. The second terminal of the first 173 capacitor is grounded. The second terminal of the first 113 resistor is connected to the fifteenth port of the first amplifier chip. The fifteenth port of the first amplifier chip is the second output port of the first stage differential amplifier module.

[0021] The thirteenth port of the first amplifier chip is connected to the first terminal and the negative power supply port of the first 172 capacitors, and the second terminal of the first 172 capacitors is grounded. The sixteenth port of the first amplifier chip is connected to the first terminal and the positive power supply port of the first 171 capacitors, and the second terminal of the first 171 capacitors is grounded.

[0022] In one specific implementation, the second-stage filtering module includes eight second-sub-filter modules with identical electrical parameters. The input ports of the eight second-sub-filter modules are connected to the output ports of the corresponding first-stage differential amplifier modules, and the output ports of the eight second-sub-filter modules are connected to the input ports of the corresponding second-stage differential amplifier modules.

[0023] The second sub-filter module includes a 114th resistor, a 115th resistor, a 174th capacitor, and a 175th capacitor. The first output port of the first stage differential amplifier module is connected in series with the first terminal of the 174th capacitor. The first terminal of the 174th capacitor is connected to the first output port of the second sub-filter module, and the second terminal of the 174th capacitor is grounded.

[0024] The first 115 resistor is connected in series between the second output port of the first stage differential amplifier module and the first terminal of the first 175 capacitor. The first terminal of the first 175 capacitor and the first 115 resistor are connected to the second output port of the second sub-filter module. The second terminal of the first 175 capacitor is grounded.

[0025] In one specific implementation, the bias drive signal generation module includes a bias drive amplifier, a drive signal source network, an external resistor, a compensation capacitor, a first resistor, and a second resistor, wherein...

[0026] The drive signal source network is connected to the second type of output port of the 8-channel second-stage differential amplifier module. The output port of the drive signal source network is connected to the first end of the external resistor, the first end of the compensation capacitor, and the inverting input terminal of the bias drive amplifier. The second end of the external resistor and the second end of the compensation capacitor are connected to the output terminal of the bias drive amplifier. The non-inverting input terminal of the bias drive amplifier is connected to the first end of the first resistor and the first end of the second resistor. The second end of the first resistor is connected to the positive power supply port, and the second end of the second resistor is connected to the negative power supply port.

[0027] In one specific implementation, the capacitance value of the compensation capacitor ranges from 1.5nF to 500pF.

[0028] In one specific implementation, the first-stage filtering module includes a low-pass filter circuit and a high-pass filter circuit. The cutoff frequency of the low-pass filter circuit is between 1.5 kHz and 40 kHz, and the cutoff frequency of the high-pass filter circuit is less than 0.5 Hz.

[0029] In one specific implementation, the amplification gain value of the first-stage differential amplifier module is between 2 and 10.

[0030] A second aspect of this application provides a multi-level conditioning and amplification device for electroencephalogram (EEG) signals, including a housing and a multi-level conditioning and amplification device for EEG signals as described in any one of the first aspects, wherein the multi-level conditioning and amplification device for EEG signals is disposed inside the housing.

[0031] A third aspect of this application provides a high signal-to-noise ratio dry electrode EEG signal acquisition system. The high signal-to-noise ratio dry electrode EEG signal acquisition system includes a rigid-flexible active electrode device and an EEG signal multi-stage conditioning and amplification device as described in any one aspect of the first application. The rigid-flexible active electrode device is connected to the EEG signal multi-stage conditioning and amplification device. The rigid-flexible active electrode device is used to transmit the acquired EEG signal, reference signal, and common-mode bias voltage signal to the EEG signal multi-stage conditioning and amplification device. The EEG signal multi-stage conditioning and amplification device is used to amplify and condition the received EEG signal. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1This application provides a schematic diagram of the structure of a high signal-to-noise ratio dry electrode EEG signal acquisition system.

[0034] Figure 2 This application provides a schematic diagram of the structure of a multi-level conditioning and amplification device for electroencephalogram (EEG) signals.

[0035] Figure 3 This application provides a schematic diagram of the structure of a reference signal buffer allocation module.

[0036] Figure 4 This application provides a schematic diagram of the structure of a first-stage differential amplifier module.

[0037] Figure 5 This application provides a schematic diagram of the circuit structure of a second-stage differential amplifier module and a differential ADC module.

[0038] Figure 6 A circuit structure diagram of a bias drive signal generation module is provided for an embodiment of this application;

[0039] Figure 7 This application provides a PCB stack-up architecture diagram of a circuit board for a multi-level conditioning and amplification device for electroencephalogram (EEG) signals. Detailed Implementation

[0040] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0041] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0042] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.

[0043] To better understand the multi-level conditioning and amplification device for EEG signals provided in this application embodiment, the following is a brief introduction to the existing EEG signal acquisition scheme.

[0044] While wet electrode-based EEG acquisition and amplification circuits are relatively mature, their long preparation time and inconvenient wearing characteristics severely limit the practical application of brain-computer interfaces. Dry electrode-based EEG signal acquisition suffers from higher contact impedance between the electrodes and skin, leading to increased noise interference and a lower signal-to-noise ratio, thus affecting signal clarity and accuracy. Furthermore, the contact state between the electrodes and skin can be affected by various factors such as sweating, sebum secretion, and hair interference, resulting in significant signal fluctuations. This places higher demands on the filtering, amplification, and acquisition of EEG signals.

[0045] Currently, various control algorithms have emerged in software design, which have improved the signal-to-noise ratio (SNR) of EEG signals to some extent, but have also prolonged data processing time and reduced system real-time performance. In hardware design, EEG acquisition devices employing an active electrode + conditioning acquisition circuit structure have appeared. Although this structure is relatively complex, it can enhance the anti-interference capability at the source of the EEG signal, helping to improve its SNR, and is a promising technical approach. However, the circuit principle and structure, PCB layout and routing, and stack-up structure of active electrodes, especially in dry electrode applications, directly affect the integrity and anti-interference capability of the EEG signal. Similarly, the front-end analog conditioning circuits of the EEG acquisition device, such as low-pass filtering, high-pass filtering, multi-stage amplification, and AD conversion circuits, also affect the transmission integrity and noise suppression capability of the EEG signal due to their circuit principles, interconnections, and electrical parameter matching. Therefore, comprehensive system design is required to ensure signal quality. Thus, research on high SNR EEG acquisition devices still faces various technical challenges.

[0046] In existing EEG signal conditioning circuits, the acquired EEG signals are usually directly converted to analog signals after passing through a simple filtering circuit. This results in low utilization of the dynamic range of the analog signal converter, significant impact from quantization noise, low common-mode rejection ratio, and high common-mode noise, leading to a low signal-to-noise ratio and unsatisfactory EEG signal acquisition.

[0047] In order to solve the above-mentioned technical problems, this application provides a multi-stage conditioning and amplification device for EEG signals, which can perform two-stage filtering and two-stage amplification on EEG signals, and combine them with a reference signal for joint conditioning, thereby improving the signal-to-noise ratio of the conditioned EEG signals.

[0048] Please see Figure 1 , Figure 1 This application provides a schematic diagram of a high signal-to-noise ratio dry electrode EEG signal acquisition system as an embodiment. For example... Figure 1 As shown, the high signal-to-noise ratio dry electrode EEG signal acquisition system 100 includes an EEG signal multi-stage conditioning and amplification device 200 and a rigid-flexible active electrode device 300. The rigid-flexible active electrode device is connected to the EEG signal multi-stage conditioning and amplification device. The rigid-flexible active electrode device is used to send the acquired EEG signal and reference signal to the EEG signal multi-stage conditioning and amplification device. The EEG signal multi-stage conditioning and amplification device is used to amplify and condition the received EEG signal and generate a common-mode bias voltage signal to be sent to the EEG signal multi-stage conditioning and amplification device.

[0049] The multi-stage conditioning and amplification device 200 for EEG signals performs filtering and differential amplification processing after receiving the EEG signal and the reference signal to obtain the final usable EEG signal, which greatly improves the signal quality and signal-to-noise ratio of the acquired EEG signal.

[0050] Specifically, the EEG signal multi-level conditioning and amplification device 200 and the rigid-flex active electrode device 300 are interconnected by high-density ultra-low-height board connectors AXT616124 and AXT516124. The connector terminals are made of copper alloy and have undergone bottom layer electroplating Ni and surface layer electroplating Au treatment, which improves the stability and durability of the contact.

[0051] Please see Figure 2 , Figure 2 This application provides a schematic diagram of a multi-level conditioning and amplification device for electroencephalogram (EEG) signals. Figure 2 As shown, this method is applied to a high signal-to-noise ratio dry electrode EEG signal acquisition system. The device includes a reference signal buffer distribution module 1, a first-stage filtering module 2, an 8-channel first-stage differential amplification module 3, a second-stage filtering module 4, an 8-channel second-stage differential amplification module 5, a bias drive signal generation module 6, and a differential ADC module 7.

[0052] The signal output port of the reference signal buffer distribution module 1 is connected to the first type of input port of the first filtering module, and the second type of input port of the first filtering module is the signal receiving port of 8-channel EEG signals.

[0053] The eight Type I signal output ports of the first-stage filtering module are respectively connected to the first input ports of the eight first-stage differential amplifier modules, and the eight Type II signal output ports of the first-stage filtering module 2 are respectively connected to the second input ports of the eight first-stage differential amplifier modules 3.

[0054] The output ports of the 8-channel first-stage differential amplifier module 3 are connected to the corresponding 8 input ports of the second-stage filter module. The 8 output ports of the second-stage filter module 4 are respectively connected to the corresponding input ports of the 8-channel second-stage differential amplifier module 5. The first type of output ports of the 8-channel second-stage differential amplifier module 5 are connected to the corresponding signal input ports in the differential ADC module 7. The second type of output ports of the 8-channel second-stage differential amplifier module 5 are connected to the input ports of the bias drive signal generation module. The corresponding signal output ports in the differential ADC module 7 are connected to the microprocessor. The output port of the bias drive signal generation module 6 is connected to the bias drive electrode.

[0055] The reference signal buffer allocation module 1 is used to receive the reference signal of the acquired EEG signal, and to generate 8 identical and independent reference signals based on the reference signal.

[0056] The gain of the first-stage differential amplifier module 3 is less than the gain of the second-stage differential amplifier module 5.

[0057] The first-stage filtering module 2 includes 16 first-stage sub-filter modules, each comprising a first-stage low-pass filter circuit and a first-stage high-pass filter circuit. Eight of the 16 first-stage sub-filter modules are type I input ports, and the remaining eight are type II input ports. The eight first-stage sub-filter modules at the type II input ports receive corresponding EEG signals (e.g., eight EEG signals in total), and the eight first-stage sub-filter modules at the type I input ports receive reference signals for their respective EEG signals. All 16 first-stage sub-filter modules have identical electrical parameters. The first-stage low-pass filter circuit is a passive RC low-pass filter circuit with a resistor value of 4.02 kΩ and a capacitor value of 10 nF. The first-stage high-pass filter circuit is a passive RC high-pass filter circuit with a resistor value of 220 kΩ and a capacitor value of 4.7 uF. The output of the first-stage low-pass filter circuit is connected to the input of the first-stage high-pass filter circuit.

[0058] The EEG signals are first passed through a low-pass filter circuit to attenuate high-frequency interference, and then through a high-pass filter circuit to remove DC bias components, thus retaining the effective frequency band of the EEG signals. Simultaneously, a buffer distribution circuit generates eight identical and independent reference signals, which serve as differential reference input signals for the eight EEG signals. These signals are then conditioned by low-pass and high-pass filter circuits with electrical parameters identical to the EEG signals. Next, the processed EEG signal and corresponding reference signal of each channel are used as a differential pair and input to the first-stage differential amplifier module 3 of the corresponding channel for amplification, improving the signal-to-noise ratio. The output differential signal then passes through a second-stage filter module 4 to further attenuate high-frequency noise, and then enters the second-stage differential amplifier module 5 for further amplification. Finally, an eight-channel parallel differential ADC circuit performs analog-to-digital conversion on the eight EEG signals, and the MCU controller ultimately performs the acquisition, transmission, and processing of the EEG signals.

[0059] The device also generates a bias drive signal output. Specifically, the DC bias of the signal output from the second-stage differential amplifier module 5 is used by the bias drive circuit to generate a common-mode voltage signal of opposite polarity. This signal is connected to the human body through the bias drive electrodes, providing a common-mode reference voltage and limiting common-mode interference noise to a very narrow range. This helps reduce common-mode interference of EEG signals on the active and reference electrodes. The signal is extremely weak and will not cause any adverse effects on the human body.

[0060] In this example, the EEG signal is filtered by the first-stage filtering module 2 to retain the effective frequency band of the EEG signal. Simultaneously, the reference signal is buffered and distributed by a circuit to generate eight identical and independent reference signals, which serve as the differential reference input signals for the eight EEG signals. These signals are then filtered and conditioned to match the electrical parameters of the EEG signals. The processed EEG signal and corresponding reference signal for each channel are then used as a differential pair and input to the first-stage differential amplifier circuit of the corresponding channel for amplification, improving the signal-to-noise ratio. The output differential signal then passes through a second-stage low-pass filter circuit to further attenuate high-frequency noise before entering the second-stage differential amplifier circuit. The signal is further amplified by a secondary amplifier circuit, and finally, an 8-channel parallel differential ADC circuit performs analog-to-digital conversion on the 8 channels of EEG signals. The MCU controller then performs the acquisition, transmission, and processing of the EEG signals. Simultaneously, a bias drive signal generation and output are implemented. That is, the DC bias of the output signal from the second-stage differential amplifier circuit is used to generate a common-mode voltage signal with opposite polarity through the bias drive signal generation module 6. This signal is connected to the human body through the bias drive electrode to provide a common-mode reference voltage for the human body and limit the common-mode interference noise to a very narrow range, thereby reducing the common-mode interference of the EEG signals and further improving the signal-to-noise ratio of the EEG signals.

[0061] In a specific implementation, such as Figure 3As shown, the reference signal buffer allocation module 1 includes a first unity-gain buffer 11, a second unity-gain buffer 12, a sixtieth capacitor C60, a sixty-first capacitor C61, a sixty-second capacitor C62, and a sixty-third capacitor C63, wherein...

[0062] The first, fifth, sixth, and tenth ports of the first unity-gain buffer 11 are used to receive reference signals of EEG signals. The third port of the first unity-gain buffer 11 is connected to the positive power supply port and the first end of the sixtieth capacitor C60, and the second end of the sixtieth capacitor C60 is grounded. The eighth port of the first unity-gain buffer 11 is connected to the negative power supply port and the first end of the sixty-first capacitor C61, and the second end of the sixty-first capacitor C61 is grounded. The second, fourth, seventh, and ninth ports of the first unity-gain buffer 11 are respectively connected to the corresponding first type of input ports in the first filtering module.

[0063] The first, fifth, sixth, and tenth ports of the second unity-gain buffer are used to receive reference signals for EEG signals. The third port of the second unity-gain buffer 12 is connected to the positive power supply port and the first terminal of the sixty-second capacitor. The second terminal of the sixty-second capacitor C62 is grounded. The eighth port of the second unity-gain buffer 12 is connected to the negative power supply port and the first terminal of the sixty-third capacitor C63. The second terminal of the sixty-third capacitor C63 is grounded. The second, fourth, seventh, and ninth ports of the second unity-gain buffer 12 are respectively connected to the corresponding first-type input ports in the first filtering module.

[0064] The reference signal buffer distribution module 1 receives a reference signal from the electroencephalogram (EEG) signal. Upon receiving this reference signal, it generates eight identical and independent reference signals through a first unity-gain buffer 11, a second unity-gain buffer 12, and their peripheral circuitry. These eight identical and independent reference signals are then input to the corresponding eight first-stage differential amplifier modules 3. The first unity-gain buffer 11 and the second unity-gain buffer 12 are identical unity-gain buffers, specifically AD8244 unity-gain buffers. The ability to generate eight identical and independent reference signals enhances the reference signal driving capability and reduces inter-channel coupling interference.

[0065] In a specific implementation, such as Figure 4As shown, the first-stage differential amplifier module 3 includes a first amplifier chip 31, a capacitor C168 (168th), a resistor R112 (112th), a capacitor C169 (169th), a capacitor C170 (170th), a capacitor C171 (171st), a capacitor C172 (172nd), a capacitor C173 (173rd), and a resistor R113 (113th).

[0066] The first signal input port and the second signal input port of the first-stage differential amplifier module 3 are connected in parallel with the 168th capacitor C168, and then connected to the first port and the fourth port of the first amplifier chip 31 respectively. The second port and the third port of the first amplifier chip 31 are connected in series with the 112th resistor R112.

[0067] The fifth port of the first amplifier chip 31 is connected to the first terminal of the first 169 capacitor C169 and the positive power supply port, and the second terminal of the first 169 capacitor C169 is grounded.

[0068] The sixth port of the first amplifier chip 31 is connected to the fourteenth port, and the fourteenth port of the first amplifier chip 31 is the second output port of the first stage differential amplifier module 3.

[0069] The seventh port of the first amplifier chip 31 is grounded, the eighth port of the first amplifier chip 31 is connected to the negative power supply port, the zero port, and the first end of the 170th capacitor C170, the second end of the 170th capacitor C170 is grounded, and the ninth port of the first amplifier chip 31 is grounded.

[0070] The twelfth port of the first amplifier chip 31 is connected to the first terminal of the first 173 capacitor C173 and the first terminal of the first 113 resistor R113. The second terminal of the first 173 capacitor C173 is grounded. The second terminal of the first 113 resistor R113 is connected to the fifteenth port of the first amplifier chip 31. The fifteenth port of the first amplifier chip 31 is the second output port of the first stage differential amplifier module 3.

[0071] The thirteenth port of the first amplifier chip 31 is connected to the first end and the negative power supply port of the first 172 capacitor C172, and the second end of the first 172 capacitor C172 is grounded. The sixteenth port of the first amplifier chip 31 is connected to the first end and the positive power supply port of the first 171 capacitor C171, and the second end of the first 171 capacitor C171 is grounded.

[0072] The first amplification chip 31 can be a dual-channel precision instrumentation amplifier. The electrical parameters of the eight first-stage differential amplification modules 3 are identical. In the single-channel fully differential amplification circuit, an RC low-pass filter circuit composed of R113 and C173 is designed to ensure the stability of the negative feedback loop.

[0073] In a specific implementation, such as Figure 2 As shown, the second-stage filtering module 4 includes eight second sub-filter modules 41 with identical electrical parameters. The input ports of the eight second sub-filter modules 41 are connected to the output ports of the corresponding first-stage differential amplifier modules 3, and the output ports of the eight second sub-filter modules 41 are connected to the input ports of the corresponding second-stage differential amplifier modules 5.

[0074] like Figure 4 As shown, the second sub-filter module 41 includes a 114th resistor R114, a 115th resistor R115, a 174th capacitor C174, and a 175th capacitor C175. The first output port of the first stage differential amplifier module 3 is connected in series with the first terminal of the first 174th capacitor C174. The first terminal of the first 174th capacitor C174 is connected to the first output port of the second sub-filter module (represented by AIN7P). The second terminal of the first 174th capacitor C174 is grounded.

[0075] The first 175-cell capacitor C175 is connected in series with the first 175-cell capacitor C175 via the first 115-cell resistor R115. The first 175-cell capacitor C175 is connected to the first 115-cell resistor R115 via the second output port of the second sub-filter module (represented by AIN7N). The second 175-cell capacitor C175 is grounded.

[0076] The differential output signal then passes through a second-stage passive RC low-pass filter circuit (green box), which can further attenuate high-frequency noise in the differential signal.

[0077] In a specific implementation, such as Figure 5 As shown, Figure 5 The circuit structure diagram of the second-stage differential amplifier module 5 and the differential ADC module 7 is shown. The differential ADC module 7 includes 8 differential ADC circuits, each corresponding to one of the 8 channels of the second-stage differential amplifier module 5, as shown below. Figure 5 The diagram shows a schematic of the second-stage differential amplifier module 5 and the differential ADC circuit. The second-stage differential amplifier module 5 and the differential ADC circuit are implemented using the analog front-end integrated circuit ADS1299, and its circuit diagram is shown below. Figure 5As shown, the ADS1299 is a high-performance physiological signal acquisition integrated chip. It contains eight low-noise programmable gain amplifiers (PGAs) and eight synchronous sampling analog-to-digital converters (ADCs). The inputs can be configured as differential inputs, with a common-mode rejection ratio (CMRR) up to 110dB and a DC input impedance up to 1GΩ. The PGA amplification gain can be selected arbitrarily from 1, 2, 4, 6, 8, 12, and 24, the ADC conversion accuracy is up to 24 bits, and the sampling rate is selectable from 250SPS to 16kSPS, making it ideal for acquiring weak EEG signals.

[0078] In a specific implementation, such as Figure 6 As shown, the bias drive signal generation module 6 includes a bias drive amplifier 61, a drive signal source network 62, and an external resistor R. f Compensation capacitor C f The first resistor R1 and the second resistor R2, wherein,

[0079] The drive signal source network 62 is connected to the second type of output port of the 8-channel second-stage differential amplifier module 5, and the output port of the drive signal source network 62 is connected to the external resistor R. f The first terminal, the compensation capacitor C f The first terminal is connected to the inverting input terminal of the bias drive amplifier 61, and the external resistor R is connected to the inverting input terminal of the bias drive amplifier 61. f The second terminal, compensation capacitor C f The second end is connected to the output end of the bias drive amplifier 61. The non-inverting input end of the bias drive amplifier 61 is connected to the first end of the first resistor R1 and the first end of the second resistor R2. The second end of the first resistor R1 is connected to the positive power supply port, and the second end of the second resistor R2 is connected to the negative power supply port.

[0080] The drive signal source network 62 includes 8 pairs of R p 1. R n 1. Connect to the corresponding EEG signal differential pairs respectively. The EEG signal differential pairs are represented as EEG signal differential pair 1 to EEG signal differential pair 8.

[0081] The bias drive amplifier 61 (BIAS amp) is a built-in bias drive amplifier of the ADS1299. The drive signal source of the drive signal source network 62 comes from the differential signals of the eight channels of the second-stage differential amplifier circuit. That is, the DC bias of the EEG signals of the eight channels is superimposed and a common-mode voltage BIAS_OUT with opposite polarity is generated by the inverting proportional amplifier circuit. Then, it is connected to the human skin surface through the bias drive electrode to provide the human body with a common-mode reference voltage with opposite polarity. In this way, most of the common-mode interference signals can be canceled, thereby suppressing common-mode noise on the EEG signal at the input end and greatly improving the signal-to-noise ratio of the entire circuit.

[0082] C in the circuit f To compensate for the capacitor, phase compensation is performed on the amplifier circuit to prevent self-oscillation. The positive input terminal of the operational amplifier is half the sum of the positive power supply AVDD and the negative power supply AVSS, thus forming a closed loop.

[0083] In one specific implementation, the capacitance value of the compensation capacitor ranges from 1.5nF to 500pF.

[0084] In one specific implementation, the first-stage filtering module 2 includes a low-pass filter circuit and a high-pass filter circuit. The cutoff frequency of the low-pass filter circuit is between 1.5 kHz and 40 kHz, and the cutoff frequency of the high-pass filter circuit is less than 0.5 Hz.

[0085] In one specific implementation, the amplification gain value of the first-stage differential amplifier module 3 is an amplification gain value between 2 and 10.

[0086] In one specific implementation, this application embodiment also provides circuit parameter design schemes for the first-stage filtering module 2, the first-stage differential amplifier module 3, the second-stage filtering module 4, the second-stage differential amplifier module 5, the bias drive signal generation module 6, and the differential ADC module 7, as detailed below:

[0087] 1) Electrical parameter design of the first-stage filter module 2:

[0088] The first-stage filtering module 2 includes a low-pass filter circuit and a high-pass filter circuit. Based on practical engineering application experience, this design sets the passband of the band-pass filter circuit composed of low-pass and high-pass filter circuits to be larger, so as to ensure that the EEG signal with a wider frequency band enters the subsequent amplifier circuit for processing with little or no attenuation.

[0089] Depend on Figure 7 It can be seen that in the pre-amplifier RC low-pass filter circuit, the resistor R is chosen to be 4.02kΩ and the capacitor C is chosen to be 10nF. This is determined by the cutoff frequency calculation formula. The cutoff frequency of the low-pass filter circuit is approximately 3.9 kHz. Based on engineering experience, signals within 0.1 times the cutoff frequency can be considered to pass without attenuation; therefore, the frequency of the low-pass filter circuit with no attenuation is set to 390 Hz, covering the effective frequency range of EEG signals. Experiments verify that the acquisition quality of EEG signals can be guaranteed within the range of 1.5 kHz to 40 kHz for the low-pass cutoff frequency fc.

[0090] In the pre-amplifier RC high-pass filter circuit, the resistor R is chosen to be 220kΩ, and the capacitor C is chosen to be 4.7uF. The cutoff frequency is calculated using the formula... The cutoff frequency of the high-pass filter circuit is approximately 0.15Hz. Based on engineering experience, signals above 10 times the cutoff frequency can be considered to pass through without attenuation. Therefore, the frequency of the high-pass filter circuit with no attenuated signals is set to 1.5Hz, covering the effective frequency range of EEG signals. Experiments verify that the acquisition quality of EEG signals can be guaranteed within a high-pass cutoff frequency range (fc) less than 0.5Hz.

[0091] Through experimental comparison, the no-attenuation frequency range of the bandpass filter circuit composed of low-pass and high-pass filter circuits was finally set to 1.5Hz to 390Hz.

[0092] 2) Electrical parameter design of the first-stage differential amplifier module 3

[0093] This design employs a two-stage amplifier circuit. To avoid reducing the signal-to-noise ratio due to excessive amplification noise, the gain of the first-stage amplifier circuit is set relatively low. The amplification gain of the first-stage differential amplifier circuit is uniquely determined by the 112th resistor R112, which is set to 12.4kΩ. According to the gain formula: The calculated amplification gain is approximately 5. Experiments verify that the signal-to-noise ratio remains high when the gain of the first-stage amplifier circuit is between 2 and 10.

[0094] 3) Electrical parameter design of the second-stage filter module 4

[0095] To further filter high-frequency interference in the effective signal, the 114th resistor R114 and the 115th resistor R115 in the second sub-filter module of the second-stage filter module 4 are set to 8.2kΩ, and the 174th capacitor C174 and the 175th capacitor C175 are set to 10nF. This is based on the cutoff frequency calculation formula. The cutoff frequency of the second sub-filter module is approximately 1.9 kHz. Based on engineering experience, signals within 0.1 times the cutoff frequency can be considered to pass without attenuation; therefore, the frequency of the attenuated signal in the second sub-filter module is set to 190 Hz, which meets the requirements for EEG signal acquisition in the effective frequency band. Experiments verify that the acquisition quality of EEG signals is guaranteed within the low-pass cutoff frequency fc range of 1.5 kHz to 10 kHz. The second sub-filter module is a low-pass filter circuit.

[0096] 4) Electrical parameter design of the second-stage differential amplifier module 5

[0097] The second-stage differential amplifier module 5 is a programmable gain amplifier circuit. Setting a higher gain for this stage increases the dynamic range of the subsequent AD conversion circuit, improving signal acquisition accuracy. Simultaneously, the differential amplifier circuit further enhances the signal-to-noise ratio. According to the ADS1299 datasheet, setting the gain to 24 results in the lowest -3dB bandwidth for the ADC circuit, approximately 27kHz, which can suppress high-frequency noise interference to some extent. Thus, the total amplification gain of the two stages is 5 × 24 = 120. Experiments verify that when the gain of the second-stage differential amplifier module 5 is selected from four specifications (6, 8, 12, and 24), combined with the gain of the first-stage differential amplifier module 3 set between 2 and 10, ensuring a total amplification gain of greater than 40 for the two stages effectively guarantees signal acquisition quality.

[0098] 5) Electrical parameter design of differential ADC module 7

[0099] This design considers that the effective signal in EEG is in a low frequency range, and the throughput of the eight parallel 24-bit AD acquisition channels is relatively large. Setting the AD sampling rate too high would put significant communication pressure on the Bluetooth transmission channel, easily causing channel congestion, data loss, and instability in the entire system. Therefore, the AD sampling rate was ultimately set to 500 SPS, which ensures that the overall system parameters are matched, guaranteeing high-precision and high-reliability data acquisition and transmission. Experiments verify that setting the AD sampling rate between 200 SPS and 1000 SPS effectively ensures the integrity of data acquisition and the reliability of data transmission.

[0100] 6) Electrical parameter design of bias drive signal generation module 6

[0101] To fully consider and utilize the DC bias of the eight EEG signals, the drive signal source of the bias drive circuit is configured to be differential signals from the eight channels of the second-stage differential amplifier module 5. This superimposes the DC bias from the eight EEG channels, which is then used by the inverting proportional amplifier circuit to generate a common-mode voltage of opposite polarity. For an AC signal with frequency f, the gain formula for the proportional amplifier circuit is: Z F for: In order to cancel out most of the common-mode interference, the amplification gain of the bias drive circuit is required to be 1, that is, A = -1.

[0102] According to the ADS1299 manual, R in For 220kΩ, R is selected. F Given a capacitance of 1MΩ and a cutoff frequency of 1.9kHz for the second-stage low-pass filter circuit, the compensation capacitor C can be calculated. F The capacitance is 750pF. This parameter setting provides a common-mode reference voltage with opposite polarity to the human body, effectively suppressing most common-mode interference signals and improving the signal-to-noise ratio of the entire circuit. Experiments verify that the compensation capacitor C... F The circuit can operate normally within the range of 1.5nF to 500pF.

[0103] In a specific implementation, such as Figure 7 The diagram shows the PCB stack-up architecture of a multi-level conditioning and amplification device for electroencephalogram (EEG) signals. Figure 7 As shown, it includes a top layer, a first GND layer, an intermediate signal layer, a power layer, a second GND layer, and a bottom layer, wherein,

[0104] The first GND layer, the intermediate signal layer, the power layer, and the second GND layer are sequentially stacked between the top layer and the bottom layer, with the first GND layer adjacent to the top layer and the second GND layer adjacent to the bottom layer. The top layer, intermediate signal layer, and bottom layer are all used for signal transmission.

[0105] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0106] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0107] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0108] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0109] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A multi-stage conditioning amplifier for electroencephalographic signals, characterized by The device comprises a reference signal buffer distribution module, a first-stage filter module, an 8-way first-stage differential amplifier module, a second-stage filter module, an 8-way second-stage differential amplifier module, a bias driving signal generation module and a differential ADC module, wherein, The signal output port of the reference signal buffer distribution module is connected with the first-type input port of the first filter module, and the second-type input port of the first-stage filter module is an 8-way EEG signal signal receiving port; The 8-way first-type signal output ports of the first-stage filter module are respectively connected with the first input ports of the 8-way first-stage differential amplifier module in correspondence, and the 8-way second-type signal output ports of the first-stage filter module are respectively connected with the second input ports of the 8-way first-stage differential amplifier module in correspondence, The output ports of the 8-way first-stage differential amplifier module are connected with the corresponding 8-way input ports of the second-stage filter module, the 8-way output ports of the second-stage filter module are respectively connected with the input ports of the 8-way second-stage differential amplifier module in correspondence, the first-type output ports of the 8-way second-stage differential amplifier module are connected with the corresponding signal input ports in the differential ADC module, the second-type output ports of the 8-way second-stage differential amplifier module are connected with the input ports of the bias driving signal generation module, and the corresponding signal output ports in the differential ADC module are connected with the microprocessor; the output port of the bias driving signal generation module is connected with the bias driving electrode; The reference signal buffer distribution module is used for receiving a reference signal of the collected EEG signal, and generating 8-way same and independent reference signals according to the reference signal; The gain of the first-stage differential amplifier module is less than the gain of the second-stage differential amplifier module; The bias driving signal generation module comprises a bias driving amplifier, a driving signal source network, an external resistor, a compensation capacitor, a first resistor and a second resistor, wherein, The driving signal source network is connected with the second-type output ports of the 8-way second-stage differential amplifier module, the output port of the driving signal source network is connected with the first end of the external resistor, the first end of the compensation capacitor and the inverting input end of the bias driving amplifier, the second end of the external resistor and the second end of the compensation capacitor are connected with the output end of the bias driving amplifier, the non-inverting input end of the bias driving amplifier is connected with the first end of the first resistor and the first end of the second resistor, the second end of the first resistor is connected with the positive power supply port, and the second end of the second resistor is connected with the negative power supply port; The first-stage filter module comprises 16-way first-stage sub-filter modules, each of which comprises a first-stage low-pass filter circuit and a first-stage high-pass filter circuit; among the 16-way first-stage sub-filter modules, 8-way signal input ports are first-type input ports, and the other 8-way signal input ports are second-type input ports; the 8-way first-stage sub-filter modules with the second-type input ports respectively receive corresponding EEG signals, and the EEG signals have 8-way signals in total, and the 8-way first-stage sub-filter modules with the first-type input ports respectively receive reference signals of corresponding EEG signals.

2. The multi-stage conditioning amplifier for electroencephalogram signals according to claim 1, wherein, The reference signal buffer allocation module comprises a first unit gain buffer, a second unit gain buffer, a sixtieth capacitor, a sixty-first capacitor, a sixty-second capacitor and a sixty-third capacitor, wherein, The first port, the fifth port, the sixth port and the tenth port of the first unit gain buffer are used for receiving the reference signal of the electroencephalogram signal, the third port of the first unit gain buffer is connected with a positive power supply port and a first end of the sixtieth capacitor, a second end of the sixtieth capacitor is grounded, the eighth port of the first unit gain buffer is connected with a negative power supply port and a first end of the sixty-first capacitor, a second end of the sixty-first capacitor is grounded, and the second port, the fourth port, the seventh port and the ninth port of the first unit gain buffer are respectively connected with corresponding first-type input ports in the first filter module; The first port, the fifth port, the sixth port and the tenth port of the second unit gain buffer are used for receiving the reference signal of the electroencephalogram signal, the third port of the second unit gain buffer is connected with a positive power supply port and a first end of the sixty-second capacitor, a second end of the sixty-second capacitor is grounded, the eighth port of the second unit gain buffer is connected with a negative power supply port and a first end of the sixty-third capacitor, a second end of the sixty-third capacitor is grounded, and the second port, the fourth port, the seventh port and the ninth port of the second unit gain buffer are respectively connected with corresponding first-type input ports in the first filter module.

3. The multi-stage conditioning amplifier for electroencephalogram signals according to claim 2, wherein, The first differential amplification module comprises a first amplification chip, a first 168 capacitor, a first 112 resistor, a first 169 capacitor, a first 170 capacitor, a first 171 capacitor, a first 172 capacitor, a first 173 capacitor and a first 113 resistor, wherein, The first 168 capacitor is connected in parallel between the first signal input port and the second signal input port of the first differential amplification module, and then the first port of the first amplification chip and the fourth port of the first amplification chip are connected respectively; The fifth port of the first amplification chip is connected with the first end of the first 169 capacitor and a positive power supply port, and the second end of the first 169 capacitor is grounded; The sixth port of the first amplification chip is connected with the fourteenth port of the first amplification chip, and the fourteenth port of the first amplification chip is a second output port of the first differential amplification module; The seventh port of the first amplification chip is grounded, the eighth port of the first amplification chip is connected with a negative power supply port, a zero port and a first end of the first 170 capacitor, the second end of the first 170 capacitor is grounded, and the ninth port of the first amplification chip is grounded; The twelfth port of the first amplification chip is connected with the first end of the first 173 capacitor and the first end of the first 113 resistor, the second end of the first 173 capacitor is grounded, the second end of the first 113 resistor is connected with the fifteenth port of the first amplification chip, and the fifteenth port of the first amplification chip is the second output port of the first differential amplification module; The thirteenth port of the first amplification chip is connected with the first end of the first 172 capacitor and the negative power supply port, the second end of the first 172 capacitor is grounded, the sixteenth port of the first amplification chip is connected with the first end of the first 171 capacitor and the positive power supply port, and the second end of the first 171 capacitor is grounded.

4. The multi-stage conditioning amplifier for electroencephalogram signals according to claim 3, wherein, The second level filter module includes eight second sub-filter modules, the electrical parameters of the eight second sub-filter modules are the same, the input ports of the eight second sub-filter modules are respectively connected with the output ports of the corresponding first differential amplification modules, and the output ports of the eight second sub-filter modules are respectively connected with the input ports of the corresponding second differential amplification modules. The second sub-filter module includes a first 114 resistor, a first 115 resistor, a first 174 capacitor and a first 175 capacitor, the first output port of the first differential amplification module is connected with the first end of the first 174 capacitor in series with the first 114 resistor, the first end of the first 174 capacitor is connected with the first 114 resistor, and the first output port of the second sub-filter module is connected between the first end of the first 174 capacitor and the first 114 resistor; and the second end of the first 174 capacitor is grounded. The second output port of the first differential amplification module is connected with the first end of the first 175 capacitor in series with the first 115 resistor, the first end of the first 175 capacitor is connected with the first 115 resistor, and the second output port of the second sub-filter module is connected between the first end of the first 175 capacitor and the first 115 resistor; and the second end of the first 175 capacitor is grounded.

5. The multi-stage conditioning amplifier for electroencephalogram signals as claimed in claim 1, wherein, The capacitance value of the compensation capacitor ranges from 1.5nF to 500pF.

6. The multi-stage conditioning amplifier for electroencephalogram signals as claimed in claim 1 wherein, The first level filter module includes a low-pass filter circuit and a high-pass filter circuit, the cut-off frequency of the low-pass filter circuit is a frequency value between 1.5KHz and 40kHz, and the cut-off frequency of the high-pass filter circuit is less than 0.5Hz.

7. The multi-stage conditioning amplifier for electroencephalogram signals as claimed in claim 5 wherein, The amplification gain value of the first differential amplification module is an amplification gain value between 2 and 10.

8. A multi-stage conditioning amplifier for electroencephalographic signals, characterized by The brain electrical signal multi-stage conditioning amplification device is arranged in the shell.

9. A high signal-to-noise ratio dry electrode electroencephalogram signal acquisition system, characterized in that, The high signal-to-noise ratio dry electrode brain electrical signal acquisition system includes a rigid-flexible combined active electrode device and the brain electrical signal multi-stage conditioning amplification device, the rigid-flexible combined active electrode device is connected with the brain electrical signal multi-stage conditioning amplification device, the rigid-flexible combined active electrode device is used for sending the acquired brain electrical signal, the reference signal and the common-mode bias voltage signal to the brain electrical signal multi-stage conditioning amplification device, and the brain electrical signal multi-stage conditioning amplification device is used for amplifying and conditioning the received brain electrical signal.

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