Chip random test method and device, equipment and storage medium

Abstract

The invention discloses a chip random test method and device, equipment and a storage medium, and the method comprises the steps: obtaining an architecture description document corresponding to a to-be-tested chip, and analyzing the characteristic information of each sub-module in the to-be-tested chip and the interaction relation between the sub-modules; determining constraint conditions corresponding to the sub-modules, and determining a plurality of test scenes corresponding to the sub-modules according to the constraint conditions; integrating the constraint conditions corresponding to each sub-module in the top verification environment, and determining a target test scene corresponding to each sub-module in a plurality of test scenes according to an integration result; and determining a plurality of random test scenes corresponding to the to-be-tested chip according to the architecture description document, and generating a plurality of random test cases corresponding to the to-be-tested chip according to the target test scene and the random test scenes. According to the technical scheme, the random testing efficiency of the chip and the accuracy of the testing result can be remarkably improved, the requirement for simulation resources is reduced, and the integrity and reliability of the chip testing process are improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and in particular, to a method, apparatus, device, and storage medium for random testing of chips. Background Art

[0002] With the rapid development of artificial intelligence technologies, the scale of system-on-chip (SoC) continues to expand, and the design of internal intellectual property (IP) cores becomes increasingly complex, making the importance and integrity of chip verification particularly crucial. Currently, three methods are generally adopted for chip testing: basic testing (or "smoke testing"), directed testing, and random testing. Among them, basic testing is responsible for verifying whether the basic data path is correct; directed testing is used to test some predictable specific scenarios; while random testing is a method that achieves broader test coverage by constructing random scenarios. Random testing plays an important role in chip debugging because it often can discover problems that designers did not anticipate.

[0003] Although existing random testing methods can achieve randomness to a certain extent, they usually only simply constrain randomness or directly reuse the constraints generated by directed testing, resulting in the difficulty for random testing to break through the specific scenarios preconceived by designers and unable to truly achieve its original intention, that is, to cover those boundary conditions beyond expectations, simulate the real usage environment, and discover hidden special problems.

[0004] Since existing random testing methods are difficult to accurately implement test scenarios, their accuracy rate is low and the efficiency is low, consuming a large amount of simulation resources and time. Secondly, existing random testing methods cannot effectively verify the interaction relationships between sub-modules in the top layer. Especially in some strongly dependent sub-modules, such as the deadlock problem in the instant communication of network-on-chip (NoC). Such problems usually originate from special situations when multiple sub-modules work together, and single verification of sub-modules cannot fully discover these problems. Summary of the Invention

[0005] The present invention provides a method, apparatus, device, and storage medium for random testing of chips, which can significantly improve the random testing efficiency of chips and the accuracy of test results, reduce the demand for simulation resources, and enhance the integrity and reliability of the chip testing process.

[0006] According to one aspect of the present invention, there is provided a method for random testing of chips, the method comprising:

[0007] Obtain the architecture description document corresponding to the chip to be tested. According to the architecture description document, analyze the characteristic information of each sub-module in the chip to be tested and the interaction relationship between each sub-module;

[0008] According to the characteristic information of each sub-module and the interaction relationship between each sub-module, determine the constraint conditions corresponding to each sub-module, and determine multiple test scenarios corresponding to each sub-module according to the constraint conditions;

[0009] In the top-level verification environment, integrate the constraint conditions corresponding to each sub-module, and determine the target test scenario corresponding to each sub-module from the multiple test scenarios according to the integration result;

[0010] According to the architecture description document, determine multiple random test scenarios corresponding to the chip to be tested, and generate multiple random test cases corresponding to the chip to be tested according to the target test scenario and the random test scenario.

[0011] Optionally, according to the architecture description document, analyzing the characteristic information of each sub-module in the chip to be tested and the interaction relationship between each sub-module includes:

[0012] According to the architecture description document, analyze the register transfer level (RTL) circuit structure information corresponding to the chip to be tested;

[0013] According to the RTL circuit structure information, analyze the overall architecture information of the chip to be tested;

[0014] According to the overall architecture information of the chip to be tested, analyze the characteristic information of each sub-module in the chip to be tested and the interaction relationship between each sub-module.

[0015] Optionally, after determining the target test scenario corresponding to each sub-module, it further includes:

[0016] Judge whether each of the target test scenarios is illegal;

[0017] If not, then according to the architecture description document, judge whether the target test scenario meets the expectation;

[0018] If so, perform an ignore operation on the target test scenario.

[0019] Optionally, after generating multiple random test cases corresponding to the chip to be tested, it further includes:

[0020] According to the RTL circuit structure information, judge whether each of the random test cases meets the expectation;

[0021] If not, return to perform the operation of determining the constraint conditions corresponding to each sub-module according to the characteristic information of each sub-module and the interaction relationship between each sub-module until each of the random test cases meets the expectation.

[0022] Optionally, after determining that each of the random test cases meets the expectation, it further includes:

[0023] Reuse the constraint conditions corresponding to each sub-module to analyze the function coverage corresponding to each random test case;

[0024] Detect whether each random test case is valid according to the function coverage.

[0025] Optionally, after detecting whether each random test case is valid according to the function coverage, it further includes:

[0026] If it is determined that the random test case is invalid according to the function coverage, return to perform the operation of generating multiple random test cases corresponding to the chip under test according to the target test scenario and the random test scenario until the random test case is valid.

[0027] Optionally, determining the target test scenario corresponding to each sub-module in the multiple test scenarios according to the integration result includes:

[0028] Perform hierarchical solution on the constraint conditions corresponding to each sub-module in the chip under test according to the integration result;

[0029] Determine the target test scenario corresponding to each sub-module in the multiple test scenarios according to the solution result.

[0030] According to another aspect of the present invention, there is provided a chip random test device, and the device includes:

[0031] A characteristic analysis module, configured to obtain an architecture description document corresponding to the chip under test, and analyze the characteristic information of each sub-module in the chip under test and the interaction relationship between each sub-module according to the architecture description document;

[0032] A constraint determination module, configured to determine the constraint conditions corresponding to each sub-module according to the characteristic information of each sub-module and the interaction relationship between each sub-module, and determine multiple test scenarios corresponding to each sub-module according to the constraint conditions;

[0033] A scenario construction module, configured to integrate the constraint conditions corresponding to each sub-module in the top-level verification environment, and determine the target test scenario corresponding to each sub-module in the multiple test scenarios according to the integration result;

[0034] A use case generation module, configured to determine multiple random test scenarios corresponding to the chip under test according to the architecture description document, and generate multiple random test cases corresponding to the chip under test according to the target test scenario and the random test scenarios.

[0035] According to another aspect of the present invention, there is provided an electronic device, which includes:

[0036] At least one processor; and

[0037] A memory communicatively connected to the at least one processor; wherein,

[0038] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the chip random test method according to any embodiment of the present invention.

[0039] According to another aspect of the present invention, there is provided a computer-readable storage medium storing computer instructions for causing a processor to implement the chip random test method according to any embodiment of the present invention when executed.

[0040] The technical solution provided by the embodiments of the present invention, by obtaining the architecture description document corresponding to the chip under test, analyzing the characteristic information of each sub-module in the chip under test, and the interaction relationship between each sub-module, determining the constraint conditions corresponding to each sub-module, and determining multiple test scenarios corresponding to each sub-module according to the constraint conditions, integrating the constraint conditions corresponding to each sub-module in the top-level verification environment, determining the target test scenario corresponding to each sub-module among multiple test scenarios, determining multiple random test scenarios corresponding to the chip under test according to the architecture description document, and generating multiple random test cases corresponding to the chip under test according to the target test scenario and the random test scenarios, can significantly improve the random test efficiency of the chip and the accuracy of the test results, reduce the demand for simulation resources, and enhance the integrity and reliability of the chip test process.

[0041] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0043] Figure 1a is a flowchart of a chip random testing method provided according to an embodiment of the present invention;

[0044] Figure 1b is a schematic diagram of a scenario applicable to a chip random testing method provided according to an embodiment of the present invention;

[0045] Figure 2 is a flowchart of another chip random testing method provided according to an embodiment of the present invention;

[0046] Figure 3 is a schematic structural diagram of a chip random testing device provided according to an embodiment of the present invention;

[0047] Figure 4 is a schematic structural diagram of an electronic device for implementing the chip random testing method of the embodiment of the present invention. Detailed implementation manners

[0048] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0049] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily need to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0050] Figure 1a is a flowchart of a chip random testing method provided according to an embodiment of the present invention. This embodiment is applicable to the situation of randomly testing chips. This method can be executed by a chip random testing device, which can be implemented in the form of hardware and / or software, and the chip random testing device can be configured in an electronic device. As Figure 1a shown, the method includes:

[0051] Step 110: Obtain the architecture description document corresponding to the chip under test. According to the architecture description document, analyze the characteristic information of each sub-module in the chip under test, as well as the interaction relationships between the sub-modules.

[0052] In this embodiment, the architecture description document may be the core technical document for the design, development, and application of the chip under test, and usually contains key information such as hardware design specifications, instruction set definitions, and functional module descriptions. Specifically, the architecture description document may include the macro-architecture description information and micro-architecture description information of the chip under test.

[0053] After obtaining the architecture description document corresponding to the chip under test, the characteristic information of each sub-module in the chip under test can be analyzed according to the architecture description document, such as the outstanding characteristic, constraint reusability, etc., as well as the interaction relationships between the sub-modules, such as the dependency relationships between the sub-modules and the strength of the dependencies. Thus, the sub-modules in the chip under test can be partitioned.

[0054] Step 120: Determine the constraint conditions corresponding to each sub-module according to the characteristic information of each sub-module and the interaction relationships between the sub-modules, and determine multiple test scenarios corresponding to each sub-module according to the constraint conditions.

[0055] In this step, the constraint conditions (constraints) for each sub-module in the chip under test can be solved separately according to the characteristic information of each sub-module and the interaction relationships between the sub-modules, and multiple test scenarios related to the test requirements can be generated according to the constraint conditions.

[0056] Step 130: Integrate the constraint conditions corresponding to each sub-module in the top-level verification environment, and determine the target test scenarios corresponding to each sub-module from the multiple test scenarios according to the integration result.

[0057] In this embodiment, in order to improve the accuracy of the test results, after determining multiple test scenarios corresponding to each sub-module respectively, the constraint conditions corresponding to each sub-module can be integrated in the top-level verification environment of the chip under test to obtain target test scenarios that are more in line with the working environment of the chip under test.

[0058] Specifically, Figure 1b It can be a schematic diagram of the scenario applicable to a chip random test method in this embodiment, as Figure 1bAs shown, it is assumed that through step 110, sub-module 0 (Sub_block0), sub-module 1 (Sub_block1), and sub-module 2 (Sub_block2) can be divided in the chip under test. Through step 120, test scenarios 0, 1, and 2 corresponding to sub-module 0, test scenarios 3 and 4 corresponding to sub-module 1, and test scenarios 5, 6, and 7 corresponding to sub-module 2 are determined. In the top-level verification environment of the chip under test, after integrating the constraint conditions corresponding to each sub-module, it can be determined that test scenario 0 is the target test scenario corresponding to sub-module 0, test scenario 3 is the target test scenario corresponding to sub-module 1, and test scenario 6 is the target test scenario corresponding to sub-module 2, thereby obtaining the most accurate test scenario corresponding to the chip under test.

[0059] Step 140: According to the architecture description document, determine multiple random test scenarios corresponding to the chip under test, and generate multiple random test cases corresponding to the chip under test based on the target test scenarios and random test scenarios.

[0060] In this embodiment, after obtaining the characteristic information of the sub-modules and the interaction relationships between the sub-modules through step 110, the variables in the constraint conditions corresponding to the sub-modules can be unrestricted, and the variables in the constraint conditions corresponding to the sub-modules are commanded to randomly take values within the legal range, thereby obtaining random test scenarios that are more extensive than the target test scenarios.

[0061] The advantage of this setting is that by covering the random test cases from the most accurate target test scenarios to the most extensive completely random test scenarios and adopting a "extensive but purposeful" random strategy, the test efficiency can be significantly improved, the effectiveness and coverage ability of the test cases can be ensured, the gradual transition of the test cases from precision to extensiveness can be realized, and the balance between precision and efficiency can be achieved.

[0062] Secondly, in this embodiment, by analyzing the characteristic information of each sub-module in the chip under test and the interaction relationships between the sub-modules, it is possible to verify the cross-scenarios between the sub-modules, cover the problems that cannot be discovered by the traditional separate verification of sub-modules, and solve the special problems (such as deadlock problems) between strongly dependent sub-modules.

[0063] Finally, through the chip random test method provided in this embodiment, only one top-level verification environment needs to be maintained to achieve complete scenario modeling, avoiding the maintenance requirements for a large number of sub-module verification environments in the traditional method, thereby greatly saving simulation and human resources. Moreover, the constraint conditions corresponding to the sub-modules determined through this embodiment can be reused during the sub-module verification process, thereby improving the verification efficiency.

[0064] The technical solution provided by the embodiments of the present invention can significantly improve the random test efficiency of the chip and the accuracy of the test results, reduce the demand for simulation resources, and enhance the integrity and reliability of the chip test process by obtaining the architecture description document corresponding to the chip to be tested, analyzing the characteristic information of each sub-module in the chip to be tested and the interaction relationship between each sub-module, determining the constraint conditions corresponding to each sub-module, determining multiple test scenarios corresponding to each sub-module according to the constraint conditions, integrating the constraint conditions corresponding to each sub-module in the top-level verification environment, determining the target test scenario corresponding to each sub-module in the multiple test scenarios, determining multiple random test scenarios corresponding to the chip to be tested according to the architecture description document, and generating multiple random test cases corresponding to the chip to be tested based on the target test scenario and the random test scenario.

[0065] Figure 2 FIG. is a flowchart of another chip random test method provided by the embodiments of the present invention. As Figure 2 shown, the method includes:

[0066] Step 210: Obtain the architecture description document corresponding to the chip to be tested, and analyze the characteristic information of each sub-module in the chip to be tested and the interaction relationship between each sub-module according to the architecture description document.

[0067] In an implementation manner of this embodiment, analyzing the characteristic information of each sub-module in the chip to be tested and the interaction relationship between each sub-module according to the architecture description document includes: analyzing the RTL circuit structure information corresponding to the chip to be tested according to the architecture description document; analyzing the overall architecture information of the chip to be tested according to the RTL circuit structure information; and analyzing the characteristic information of each sub-module in the chip to be tested and the interaction relationship between each sub-module according to the overall architecture information of the chip to be tested.

[0068] Among them, the RTL circuit structure information is used to describe the hardware logic function in the chip to be tested. The advantage of this setting is that it can accurately divide the sub-modules in the chip to be tested to improve the effectiveness of subsequent random test cases.

[0069] Step 220: Determine the constraint conditions corresponding to each sub-module according to the characteristic information of each sub-module and the interaction relationship between each sub-module, and determine multiple test scenarios corresponding to each sub-module according to the constraint conditions.

[0070] Step 230: Integrate the constraint conditions corresponding to each sub-module in the top-level verification environment, and determine the target test scenario corresponding to each sub-module in the multiple test scenarios according to the integration result.

[0071] In a specific embodiment, determining the target test scenarios corresponding to each sub-module in the multiple test scenarios according to the integration result includes: hierarchically solving the constraint conditions corresponding to each sub-module in the chip under test according to the integration result; and determining the target test scenarios corresponding to each sub-module in the multiple test scenarios according to the solution result.

[0072] The advantage of such a setting is that by hierarchically solving the constraint conditions corresponding to each sub-module, more efficient complex scenario testing can be performed on the chip under test, thereby improving the random test efficiency of the chip and the accuracy of the test results.

[0073] In an implementation manner of this embodiment, after determining the target test scenarios corresponding to each sub-module, it further includes: determining whether each of the target test scenarios is illegal; if not, determining whether the target test scenario meets the expectation according to the architecture description document; if so, performing an ignore operation on the target test scenario.

[0074] Specifically, if a certain target test scenario is illegal, the target test scenario can be eliminated; conversely, if the target test scenario is legal, it can be determined whether the target test scenario meets the expectation, and if it meets the expectation, an ignore operation is performed.

[0075] Step 240: Determine multiple random test scenarios corresponding to the chip under test according to the architecture description document, and generate multiple random test cases corresponding to the chip under test according to the target test scenarios and the random test scenarios.

[0076] Step 250: Determine whether each of the random test cases meets the expectation according to the RTL circuit structure information. If so, execute Step 260; if not, return to execute the operation of determining the constraint conditions corresponding to each sub-module in Step 220 according to the characteristic information of each sub-module and the interaction relationship between each sub-module until each of the random test cases meets the expectation.

[0077] The advantage of such a setting is that by repeatedly iterating and optimizing the constraint conditions corresponding to each sub-module, the effectiveness and coverage ability of the test cases can be ensured.

[0078] Step 260: Reuse the constraint conditions corresponding to each sub-module to analyze the function coverage of each of the random test cases.

[0079] In this embodiment, the function coverage is used to measure the call coverage of all functions in the code of the chip under test by the random test cases to confirm the effectiveness of each random test case.

[0080] Specifically, the constraint conditions corresponding to each sub-module can be reused as coverage bins (abbreviated as bins) to Figure 1b take Figure 1b as an example. Suppose the target test scenarios are Scenario 0, Scenario 3, and Scenario 6. Then, the bins of Scenario 0, Scenario 3, and Scenario 6 can be combined. If the bins of Scenario 0, Scenario 3, and Scenario 6 in the random test case are hit, it can be proved that the random test case implements Scenario 0, Scenario 3, and Scenario 6.

[0081] Among them, coverage bins is an important concept in the functional coverage model, which is used to define the jump order of specific values in the coverpoint. In SystemVerilog, coverage bins are used to specify which values or ranges of values the coverpoint should collect to ensure that all critical paths and states in the design can be covered during the verification process.

[0082] Step 270: According to the function coverage, detect whether each of the random test cases is valid. If so, execute Step 280. If not, return to execute the operation of generating multiple random test cases corresponding to the chip under test according to the target test scenario and the random test scenario in Step 240 until the random test case is valid.

[0083] In this embodiment, if it is determined that the random test case is invalid according to the function coverage, return to execute the operation of generating multiple random test cases corresponding to the chip under test according to the target test scenario and the random test scenario until the random test case is valid.

[0084] Step 280: Use each of the random test cases to test the chip under test.

[0085] The technical solution provided by the embodiment of the present invention can significantly improve the random test efficiency of the chip and the accuracy of the test results, reduce the demand for simulation resources, and enhance the integrity and reliability of the chip test process by obtaining the architecture description document corresponding to the chip to be tested, analyzing the characteristic information of each sub-module in the chip to be tested and the interaction relationship between each sub-module, determining the constraint conditions corresponding to each sub-module, determining multiple test scenarios corresponding to each sub-module, integrating the constraint conditions corresponding to each sub-module in the top-level verification environment, determining the target test scenario corresponding to each sub-module in multiple test scenarios, determining multiple random test scenarios corresponding to the chip to be tested according to the architecture description document, generating multiple random test cases corresponding to the chip to be tested according to the target test scenario and the random test scenario, judging whether each random test case meets the expectation according to the RTL circuit structure information, if so, reusing the constraint conditions corresponding to each sub-module to analyze the function coverage corresponding to each random test case, and detecting whether each random test case is effective according to the function coverage, and if so, using each random test case to test the chip to be tested.

[0086] Figure 3 FIG. 4 is a schematic structural diagram of a chip random test device provided by an embodiment of the present invention. The device is applied to an electronic device, such as Figure 3 shown. The device includes: a characteristic analysis module 310, a constraint determination module 320, a scenario construction module 330, and a test case generation module 340.

[0087] The characteristic analysis module 310 is configured to obtain the architecture description document corresponding to the chip to be tested, and analyze the characteristic information of each sub-module in the chip to be tested and the interaction relationship between each sub-module according to the architecture description document;

[0088] The constraint determination module 320 is configured to determine the constraint conditions corresponding to each sub-module according to the characteristic information of each sub-module and the interaction relationship between each sub-module, and determine multiple test scenarios corresponding to each sub-module according to the constraint conditions;

[0089] The scenario construction module 330 is configured to integrate the constraint conditions corresponding to each sub-module in the top-level verification environment, and determine the target test scenario corresponding to each sub-module in the multiple test scenarios according to the integration result;

[0090] The test case generation module 340 is configured to determine multiple random test scenarios corresponding to the chip to be tested according to the architecture description document, and generate multiple random test cases corresponding to the chip to be tested according to the target test scenario and the random test scenario.

[0091] The technical solution provided by the embodiment of the present invention can significantly improve the random test efficiency of the chip and the accuracy of the test results, reduce the demand for simulation resources, and enhance the integrity and reliability of the chip test process by obtaining the architecture description document corresponding to the chip to be tested, analyzing the characteristic information of each sub-module in the chip to be tested and the interaction relationship between each sub-module, determining the constraint conditions corresponding to each sub-module, and determining multiple test scenarios corresponding to each sub-module according to the constraint conditions, integrating the constraint conditions corresponding to each sub-module in the top-level verification environment, determining the target test scenario corresponding to each sub-module in multiple test scenarios, determining multiple random test scenarios corresponding to the chip to be tested according to the architecture description document, and generating multiple random test cases corresponding to the chip to be tested according to the target test scenario and the random test scenario.

[0092] Based on the above embodiment, the characteristic analysis module 310 includes:

[0093] The RTL analysis unit is used to analyze the RTL circuit structure information corresponding to the chip to be tested according to the architecture description document;

[0094] The architecture analysis unit is used to analyze the overall architecture information of the chip to be tested according to the RTL circuit structure information;

[0095] The sub-module analysis unit is used to analyze the characteristic information of each sub-module in the chip to be tested and the interaction relationship between each sub-module according to the overall architecture information of the chip to be tested.

[0096] The scenario construction module 330 includes:

[0097] The scenario judgment unit is used to judge whether each of the target test scenarios is illegal; if not, it is used to judge whether the target test scenario meets the expectation according to the architecture description document; if so, an ignore operation is performed on the target test scenario;

[0098] The hierarchical solution unit is used to hierarchically solve the constraint conditions corresponding to each sub-module in the chip to be tested according to the integration result; and determine the target test scenario corresponding to each sub-module in the multiple test scenarios according to the solution result.

[0099] The test case generation module 340 includes:

[0100] The test case judgment unit is used to judge whether each of the random test cases meets the expectation according to the RTL circuit structure information; if not, it returns to execute the operation of determining the constraint conditions corresponding to each sub-module according to the characteristic information of each sub-module and the interaction relationship between each sub-module until each of the random test cases meets the expectation;

[0101] A function coverage analysis unit is configured to reuse the constraint conditions corresponding to each of the sub-modules to analyze the function coverage corresponding to each of the random test cases;

[0102] A test case detection unit is configured to detect whether each of the random test cases is valid according to the function coverage; if it is determined that the random test case is invalid according to the function coverage, the operation of generating a plurality of random test cases corresponding to the chip under test according to the target test scenario and the random test scenario is returned until the random test case is valid.

[0103] The above device can execute the methods provided in all the foregoing embodiments of the present invention, and has corresponding functional modules and beneficial effects for executing the above methods. For technical details not described in detail in the embodiments of the present invention, reference may be made to the methods provided in all the foregoing embodiments of the present invention.

[0104] Figure 4 FIG. shows a schematic structural diagram of an electronic device 10 that can be used to implement an embodiment of the present invention. The electronic device is intended to represent various forms of digital computers, such as, for example, a laptop computer, a desktop computer, a workbench, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, for example, a personal digital processor, a cellular phone, a smart phone, a wearable device (such as a helmet, glasses, a watch, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0105] As Figure 4 shown, the electronic device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc. The memory stores a computer program executable by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. The input / output (I / O) interface 15 is also connected to the bus 14.

[0106] Multiple components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disc, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0107] The processor 11 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the chip random test method.

[0108] In some embodiments, the chip random test method can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the chip random test method described above can be executed. Alternatively, in other embodiments, the processor 11 can be configured to execute the chip random test method by any other suitable means (e.g., by means of firmware).

[0109] The various embodiments of the systems and technologies described above in this article can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs, which can be executed and / or interpreted on a programmable system including at least one programmable processor, the programmable processor can be a dedicated or general-purpose programmable processor, can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0110] A computer program for implementing the method of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, a special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions / operations specified in the flowchart and / or block diagram to be implemented. The computer program may be executed entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine, or entirely on the remote machine or server.

[0111] In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, the computer-readable storage medium may be a machine-readable signal medium. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0112] In order to provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0113] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected with each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), blockchain network, and the Internet.

[0114] A computing system can include a client and a server. The client and the server are generally far from each other and typically interact through a communication network. The client-server relationship is created by computer programs running on respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system, solving the defects of difficult management and weak business scalability existing in traditional physical hosts and VPS services.

[0115] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is imposed herein.

[0116] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A random chip testing method, characterized in that: The method comprises: Obtaining an architecture description document corresponding to the chip to be tested, and analyzing characteristic information of each submodule in the chip to be tested and the interaction relationship between the submodules according to the architecture description document; Determine the constraint conditions corresponding to each submodule according to the characteristic information of each submodule and the interaction relationship between each submodule, and determine multiple test scenarios corresponding to each submodule according to the constraint conditions; In the top-level verification environment, the constraint conditions corresponding to each submodule are integrated, and the target test scenario corresponding to each submodule is determined from the multiple test scenarios according to the integration result; According to the architecture description document, multiple random test scenarios corresponding to the chip to be tested are determined, and according to the target test scenarios and the random test scenarios, multiple random test cases corresponding to the chip to be tested are generated.

2. The method according to claim 1, characterized in that According to the architecture description document, analyze the characteristic information of each submodule in the chip to be tested and the interaction relationship between each submodule, including: According to the architecture description document, analyzing the register transfer level RTL circuit structure information corresponding to the chip to be tested; Analyze the overall architecture information of the chip to be tested according to the RTL circuit structure information; According to the overall architecture information of the chip to be tested, characteristic information of each submodule in the chip to be tested and the interaction relationship between each submodule are analyzed.

3. The method according to claim 1, characterized in that After determining the target test scenarios corresponding to each submodule, it also includes: Determining whether each of the target test scenarios is illegal; If not, judging whether the target test scenario meets expectations according to the architecture description document; If so, an ignore operation is performed on the target test scenario.

4. The method according to claim 2, characterized in that: After generating multiple random test cases corresponding to the chip to be tested, it also includes: According to the RTL circuit structure information, determine whether each of the random test cases meets expectations; If not, the process returns to executing the operation of determining the constraint conditions corresponding to each submodule according to the characteristic information of each submodule and the interaction relationship between the submodules, until each of the random test cases meets expectations.

5. The method according to claim 4, characterized in that After determining that each of the random test cases meets expectations, the following steps are also included: Reusing the constraint conditions corresponding to each of the submodules to analyze the function coverage corresponding to each of the random test cases; According to the function coverage, detect whether each of the random test cases is valid.

6. The method according to claim 5, characterized in that After detecting whether each of the random test cases is valid according to the function coverage, the method further includes: If it is determined that the random test case is invalid based on the function coverage, the operation of generating multiple random test cases corresponding to the chip to be tested based on the target test scenario and the random test scenario is returned until the random test case is valid.

7. The method according to claim 1, characterized in that Determining a target test scenario corresponding to each submodule in the multiple test scenarios according to the integration result includes: According to the integration results, the constraints corresponding to each submodule in the chip under test are solved hierarchically; According to the solution result, a target test scenario corresponding to each submodule is determined in the multiple test scenarios.

8. A random chip test device, characterized in that: The device comprises: The characteristic analysis module is used to obtain the architecture description document corresponding to the chip under test, and analyze the characteristic information of each submodule in the chip under test and the interaction relationship between the submodules according to the architecture description document; A constraint determination module, used to determine the constraint conditions corresponding to each submodule according to the characteristic information of each submodule and the interaction relationship between the submodules, and determine multiple test scenarios corresponding to each submodule according to the constraint conditions; A scenario construction module, used to integrate the constraint conditions corresponding to each submodule in the top-level verification environment, and determine the target test scenario corresponding to each submodule in the multiple test scenarios according to the integration result; The use case generation module is used to determine multiple random test scenarios corresponding to the chip to be tested according to the architecture description document, and generate multiple random test cases corresponding to the chip to be tested according to the target test scenario and the random test scenario.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the chip random test method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the chip random testing method according to any one of claims 1 to 7 when executed.

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