Array substrate, display panel and display device

Abstract

The present disclosure provides an array substrate, a display panel and a display device. The array substrate comprises a substrate, a plurality of gate lines, a plurality of data lines, a plurality of sub-pixel electrodes, at least one of the plurality of sub-pixel electrodes comprises a first sub-pixel electrode group and a second sub-pixel electrode group, the first sub-pixel electrode group and the second sub-pixel electrode group each comprises two sub-pixel electrode parts arranged along a third direction and electrically connected, in the same sub-pixel electrode, the brightness of the first sub-pixel electrode group is greater than the brightness of the second sub-pixel electrode group, and the two sub-pixel electrode parts of the first sub-pixel electrode group are located on the same side of the two second sub-pixel electrode parts of the second sub-pixel electrode group, the third direction intersects the first direction and the second direction.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0002] The name UV2A comes from the multiplication of ultraviolet (UV) light with the VA method of the LCD panel. This technology can precisely control the alignment of liquid crystal molecules through ultraviolet light, greatly improving the light transmittance.

[0003] The key to UV2A lies in utilizing a special polymer material as an alignment film to precisely control the tilt of liquid crystal molecules along the ultraviolet light direction. Its precision is measured in picometers (one trillionth of a meter). The advantage of UV2A is that the liquid crystal panel has a simple structure without protrusions or slits. This "dream of liquid crystal engineers" was explored as early as 30 years ago. Today, with the availability of new materials, production equipment, and a perfected processing procedure, this dream has been realized. The simple structure of the liquid crystal panel not only improves production efficiency but also offers many advantages in image quality. Summary of the Invention

[0004] This disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0005] Substrate;

[0006] Multiple gate lines are located on one side of the substrate, and the multiple gate lines extend along a first direction;

[0007] Multiple data lines are located on the same side of the substrate as the multiple gate lines, and the multiple data lines extend along a second direction;

[0008] A plurality of sub-pixel electrodes, at least one of the plurality of sub-pixel electrodes comprising: a first sub-pixel electrode group and a second sub-pixel electrode group; both the first sub-pixel electrode group and the second sub-pixel electrode group comprise: two sub-pixel electrode portions arranged and electrically connected along the third direction; in the same sub-pixel electrode, the brightness of the first sub-pixel electrode group is greater than the brightness of the second sub-pixel electrode group, and the two sub-pixel electrode portions of the first sub-pixel electrode group are located on the same side of the two second sub-pixel electrode portions of the second sub-pixel electrode group, the third direction intersecting the first direction and the second direction.

[0009] In one possible implementation, the two sub-pixel electrode portions of the first sub-pixel electrode group are respectively: a first sub-pixel electrode portion and a second sub-pixel electrode portion; the two sub-pixel electrode portions of the second sub-pixel electrode group are respectively: a third sub-pixel electrode portion and a fourth sub-pixel electrode portion.

[0010] The second sub-pixel electrode portion is adjacent to the third sub-pixel electrode portion and is arranged along the first direction.

[0011] In one possible implementation, the first sub-pixel electrode portion is adjacent to the third sub-pixel electrode portion and is arranged along the second direction.

[0012] In one possible implementation, the fourth sub-pixel electrode portion is adjacent to the second sub-pixel electrode portion and is arranged along the second direction.

[0013] In one possible implementation, in the sub-pixel electrodes, the first sub-pixel electrode portion, the second sub-pixel electrode portion, and the third sub-pixel electrode portion are located on one side of the gate line electrically connected to the sub-pixel electrodes, and the fourth sub-pixel electrode portion is located on the other side of the gate line electrically connected to the sub-pixel electrodes.

[0014] In one possible implementation, the array substrate further includes: a first pixel connection portion and a second pixel connection portion;

[0015] In the same sub-pixel electrode, the first sub-pixel electrode portion and the second sub-pixel electrode portion are electrically connected through the first pixel connection portion, and the third sub-pixel electrode portion and the fourth sub-pixel electrode portion are electrically connected through the second pixel connection portion.

[0016] In one possible implementation, the first pixel connection portion extends along the third direction and electrically connects two opposite corners of the first sub-pixel electrode portion and the second sub-pixel electrode portion.

[0017] In one possible implementation, the second pixel connection portion includes: a first sub-connection portion extending along the second direction, a second sub-connection portion, and a third sub-connection portion extending along the third direction and connecting the first sub-connection portion and the second sub-connection portion; wherein, the extension line of the second sub-connection portion is located on the side of the extension line of the first sub-connection portion closer to the second sub-pixel electrode portion.

[0018] In one possible implementation, the array substrate further includes: a pixel driving circuit electrically connected to each of the sub-pixel electrodes in a one-to-one correspondence, and a first trace extending along the second direction; the pixel driving circuit includes: a first transistor, a second transistor, and a third transistor.

[0019] The gate of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the second sub-pixel electrode.

[0020] The gate of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is multiplexed from the first electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the fourth sub-pixel electrode.

[0021] The gate of the third transistor is electrically connected to the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is multiplexed with a portion of the first trace.

[0022] In one possible implementation, the array substrate further includes: a first pixel overlap portion electrically connected to the second sub-pixel electrode portion, and a second pixel overlap portion electrically connected to the fourth sub-pixel electrode portion;

[0023] The first pixel overlap portion has an overlapping area with the second electrode of the first transistor in the substrate. The second sub-pixel electrode portion is electrically connected to the second electrode of the first transistor through the first pixel overlap portion.

[0024] The second pixel overlap portion has an overlapping area with the second electrode of the second transistor in the substrate. The fourth sub-pixel electrode portion is electrically connected to the second electrode of the second transistor through the second pixel overlap portion.

[0025] In one possible implementation, the second pixel overlap portion includes: a first sub-overlap portion, and a second sub-overlap portion connecting the first sub-overlap portion and the fourth sub-pixel electrode;

[0026] There is a gap between the first sub-overlapping portion and the fourth sub-pixel electrode.

[0027] In one possible implementation, the first pixel overlap portion has two first sides extending along the second direction; the second pixel overlap portion has two second sides extending along the second direction;

[0028] The orthographic projection of one of the first edges on the substrate overlaps with the orthographic projection of the second pixel overlapping portion on the substrate; and the orthographic projection of one of the second edges on the substrate overlaps with the orthographic projection of the first pixel overlapping portion on the substrate.

[0029] In one possible implementation, the second electrode of the first transistor includes: a first main portion extending along the first direction, and a first branch extending from one end of the first main portion along the second direction; the orthographic projection of the first main portion on the substrate has an overlapping area with the orthographic projection of the first pixel overlap portion on the substrate; the orthographic projection of the first branch on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate.

[0030] The second electrode of the second transistor includes: a second main portion extending along the first direction, and a second branch extending from one end of the first main portion along the first direction; the orthographic projection of the second main portion on the substrate has an overlapping area with the orthographic projection of the second pixel overlap portion on the substrate; the orthographic projection of the second branch on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate.

[0031] In one possible implementation, the first trace includes: multiple segments of first trace main portions extending along the second direction, and a first trace bend portion connecting two adjacent segments of the first trace main portions;

[0032] The first trace main portion has an overlapping area with the gap between the second sub-pixel electrode portion and the third sub-pixel electrode portion in the orthogonal projection of the substrate; the first trace bend portion has an overlapping area with the gate line in the orthogonal projection of the substrate, and bends toward the side of the third transistor.

[0033] In one possible implementation, the array substrate further includes: a plurality of first common trace groups extending along the second direction; the common trace group includes: a first sub-common trace located on one side of the gate line, and a second sub-common trace located on the other side of the gate line;

[0034] The first sub-common trace includes: a first sub-common trace main portion, and a first sub-common trace protrusion extending from the first sub-common trace main portion toward the gate line; the second sub-common trace includes: a second sub-common trace main portion, and a second sub-common trace protrusion extending from the second sub-common trace main portion toward the gate line.

[0035] The orthographic projection of the first sub-common trace protrusion on the substrate overlaps with the orthographic projection of the first pixel overlap portion on the substrate; the orthographic projection of the second sub-common trace protrusion on the substrate overlaps with the orthographic projection of the second pixel overlap portion on the substrate.

[0036] This disclosure also provides a display panel, which includes the array substrate as provided in this disclosure, and a counter substrate disposed opposite to the array substrate, wherein the counter substrate has a common electrode layer disposed on the side facing the array substrate.

[0037] This disclosure also provides a display device, which includes the display panel as described in this disclosure. Attached Figure Description

[0038] Figure 1This is a schematic diagram of the sub-pixel distribution in 1P4D.

[0039] Figure 2 A schematic diagram illustrating the principle behind the dark lines appearing in the pixel design of a conventional SUV A;

[0040] Figure 3A A top view schematic diagram of an array substrate provided in an embodiment of this disclosure;

[0041] Figure 3B for Figure 3A Schematic diagram of a single film layer of the middle gate line layer;

[0042] Figure 3C for Figure 3A A schematic diagram of a single film layer in the middle data line layer;

[0043] Figure 3D for Figure 3A A schematic diagram of a single-film layer with an active layer;

[0044] Figure 3E for Figure 3A A schematic diagram of the single-film layer of the first insulating layer in the middle;

[0045] Figure 3F for Figure 3A A schematic diagram of a single film layer of the first electrode layer in the middle;

[0046] Figure 3G for Figure 3A A schematic diagram of a single-film layer of the second insulating layer;

[0047] Figure 3H for Figure 3A A schematic diagram of a single film layer of the middle pixel electrode layer;

[0048] Figure 3I for Figure 3A Enlarged view of point S within the dashed box;

[0049] Figure 4 This is a schematic diagram of the connection of a sub-pixel electrode provided in an embodiment of the present disclosure;

[0050] Figure 5 This is an equivalent schematic diagram of a sub-pixel electrode circuit provided in an embodiment of the present disclosure. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0052] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0053] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.

[0054] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0055] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0056] Compared to the UV2A pixel design, Ultra-Small Optical Alignment (SUVA) is an upgraded version of UV2A, combining... Figure 1 and Figure 2 As shown, where, Figure 1The SUVA pixel design, which uses 1P4D (one subpixel contains four domains), effectively reduces pixel dark lines compared to the UV2A pixel design. However, as... Figure 2 As shown, dark lines still exist in the area between liquid crystal region 1 and liquid crystal region 2, which continues to affect the color shift characteristics of the panel. Therefore, a multi-domain approach is needed to further improve the color shift.

[0057] In view of this, see Figure 3A-3I and Figure 4 As shown, where, Figure 3A This is a top view schematic diagram of an array substrate provided in an embodiment of the present disclosure. Figure 3B for Figure 3A Schematic diagram of a single film layer of the middle gate line layer. Figure 3C for Figure 3A A schematic diagram of a single film layer in the middle data line layer. Figure 3D for Figure 3A A schematic diagram of a single-film layer with an active layer. Figure 3E for Figure 3A A schematic diagram of the single-film layer of the first insulating layer. Figure 3F for Figure 3A A schematic diagram of the single-film layer of the first electrode layer. Figure 3G for Figure 3A A schematic diagram of the single-film layer of the second insulating layer. Figure 3H for Figure 3A A schematic diagram of a single film layer of the middle pixel electrode layer. Figure 3I for Figure 3A Enlarged view of point S within the dashed box. Figure 4 This is a schematic diagram of the connection of a sub-pixel electrode provided in an embodiment of the present disclosure. The embodiment of the present invention provides an array substrate, which includes:

[0058] Substrate 1;

[0059] Multiple gate lines 2 are located on one side of the substrate 1 and extend along the first direction X;

[0060] Multiple data lines 3 are located on the same side of the substrate 1 as multiple gate lines 2, and the multiple data lines 3 extend in a second direction Y;

[0061] A plurality of sub-pixel electrodes 4, at least one of the plurality of sub-pixel electrodes 4 including: a first sub-pixel electrode group PA and a second sub-pixel electrode group PB; both the first sub-pixel electrode group PA and the second sub-pixel electrode group PB include: two sub-pixel electrode portions P0 arranged along a third direction Z and electrically connected; in the same sub-pixel electrode 4, the brightness of the first sub-pixel electrode group PA is greater than the brightness of the second sub-pixel electrode group PB, and the two sub-pixel electrode portions P0 of the first sub-pixel electrode group PA are located on the same side of the two second sub-pixel electrode portions P0 of the second sub-pixel electrode group PB extending in the third direction Z, the third direction Z intersecting the first direction X and the second direction Y. Figure 3A In the diagram, H represents the brighter sub-pixel electrode portion P0 in a sub-pixel electrode 4, and L represents the darker sub-pixel electrode portion P0. It should be noted that "brighter" here means that more backlight is transmitted, and "darker" means that less backlight is transmitted. That is, when different voltages are applied to different sub-pixel electrode portions P0, the voltage difference formed with the common electrode of the opposing substrate is different. The greater the voltage difference, the stronger the ability to drive the liquid crystal to rotate, the more backlight is transmitted, and the brighter the sub-pixel electrode portion P0. Conversely, the smaller the voltage difference, the weaker the ability to drive the liquid crystal to rotate, the less backlight is transmitted, and the darker the sub-pixel electrode portion P0.

[0062] In this embodiment, the sub-pixel electrode 4 includes a first sub-pixel electrode group PA and a second sub-pixel electrode group PB. The brightness of the first sub-pixel electrode group PA is greater than the brightness of the second sub-pixel electrode group PB. The two sub-pixel electrode portions P0 of the first sub-pixel electrode group PA are located on the same side of the two second sub-pixel electrode portions P0 of the second sub-pixel electrode group PB extending in the third direction Z. When a sub-pixel electrode 4 includes two brighter sub-pixel electrode portions P0 and two darker sub-pixel electrode portions P0, the wiring can be simplified, the wiring complexity of the array substrate can be reduced, and the defect rate of the array substrate can be reduced. It is also beneficial to realize multiple domains and improve color shift. Moreover, the centers of the two brighter sub-pixel electrode portions P0 and the two darker sub-pixel electrode portions P0 form a rhombus shape, so that the array substrate has a bright and dark cross distribution in the first direction X and the second direction Y, which can also improve the problem of horizontal and vertical dark lines.

[0063] In one possible implementation, the angle formed by the third direction Z and the first direction X can be 30° to 60°, specifically, for example, 45°.

[0064] Specifically, the array substrate may also include a pixel driving circuit corresponding to each sub-pixel electrode 4. The brightness of the first sub-pixel electrode group PA is greater than the brightness of the second sub-pixel electrode group PB. This can be understood as the brightness of the first sub-pixel electrode group PA being greater than the brightness of the second sub-pixel electrode group PB under the drive of the pixel driving circuit.

[0065] In one possible implementation, the array substrate may include a plurality of sub-pixel electrode rows extending along a first direction X and arranged along a second direction Y. Two sub-pixel electrode rows may be distributed between two adjacent gate lines 2, wherein the four sub-pixel electrode portions P0 of a sub-pixel electrode 4 may be distributed in three sub-pixel electrode rows.

[0066] In one possible implementation, combined with Figure 3A As shown, the sub-pixel electrode portion P0 may be provided with a slit F. Each sub-pixel electrode portion P0 may also include a first sub-portion P01 and a second sub-portion P02 arranged along the second direction Y. The extension directions of the slit F of the first sub-portion P01 and the second sub-portion P02 in the same sub-pixel electrode portion P0 are different.

[0067] In one possible implementation, combined with Figure 3A As shown, in the same sub-pixel electrode row, the extension directions of the slits F of the two adjacent first sub-parts P01 in the first direction X are the same, and the extension directions of the slits F of the two adjacent second sub-parts P02 in the first direction X are the same; in two sub-pixel electrode rows between two adjacent gate lines 2, the extension direction of the slits F of the first sub-parts P01 in one sub-pixel electrode row is the same as the extension direction of the slits F of the second sub-parts P02 in the other sub-pixel electrode row; and the extension direction of the slits F of the second sub-parts P02 in one sub-pixel electrode row is the same as the extension direction of the slits F of the first sub-parts P01 in the other sub-pixel electrode row.

[0068] In one possible implementation, combined with Figure 3A As shown, in one of the sub-pixel electrode rows, the angle formed by the extension direction of the slit F in the first sub-part P01 and the first direction X can be between 130° and 160°, specifically, for example, 145°; the angle formed by the extension direction of the slit F in the second sub-part P02 and the first direction X can be between 30° and 60°, specifically, for example, 45°; in the other sub-pixel electrode row, the angle formed by the extension direction of the slit F in the first sub-part P01 and the first direction X can be between 30° and 60°, specifically, for example, 45°; the angle formed by the extension direction of the slit F in the second sub-part P02 and the first direction X can be between 130° and 160°, specifically, for example, 145°.

[0069] In one possible implementation, combined with Figure 3A and Figure 3HAs shown, the two sub-pixel electrode portions P0 of the first sub-pixel electrode group PA are: first sub-pixel electrode portion P1 and second sub-pixel electrode portion P2; the two sub-pixel electrode portions P0 of the second sub-pixel electrode group PB are: third sub-pixel electrode portion P3 and fourth sub-pixel electrode portion P4; the second sub-pixel electrode portion P2 and the third sub-pixel electrode portion P3 are adjacent to each other and arranged along the first direction X.

[0070] In one possible implementation, combined with Figure 3A and Figure 3H As shown, the first sub-pixel electrode portion P1 and the third sub-pixel electrode portion P3 are adjacent to each other and are arranged along the second direction Y.

[0071] In one possible implementation, combined with Figure 3A and Figure 3H As shown, the fourth sub-pixel electrode portion P4 is adjacent to the second sub-pixel electrode portion P2 and is arranged along the second direction Y.

[0072] In one possible implementation, combined with Figure 3A and Figure 3H As shown, in the sub-pixel electrode 4, the first sub-pixel electrode part P1, the second sub-pixel electrode part P2, and the third sub-pixel electrode part P3 are located on one side of the gate line 2 electrically connected to the sub-pixel electrode 4, and the fourth sub-pixel electrode part P4 is located on the other side of the gate line 2 electrically connected to the sub-pixel electrode 4.

[0073] It is understandable that the sub-pixel electrode 4 is electrically connected to the source or drain of the transistor, and the gate of the transistor is electrically connected to the gate line 2.

[0074] In one possible implementation, combined with Figure 3H As shown, the array substrate further includes: a first pixel connection portion 41 and a second pixel connection portion 42; in the same sub-pixel electrode 4, the first sub-pixel electrode portion P1 and the second sub-pixel electrode portion P2 are electrically connected through the first pixel connection portion 41, and the third sub-pixel electrode portion P3 and the fourth sub-pixel electrode portion P4 are electrically connected through the second pixel connection portion 42.

[0075] In this embodiment, the first sub-pixel electrode portion P1 and the second sub-pixel electrode portion P2 are electrically connected through the first pixel connection portion 41, and the third sub-pixel electrode portion P3 and the fourth sub-pixel electrode portion P4 are electrically connected through the second pixel connection portion 42. This allows the first sub-pixel electrode portion P1 and the second sub-pixel electrode portion P2 to be connected close to each other, and the third sub-pixel electrode portion P3 and the fourth sub-pixel electrode portion P4 to be connected close to each other, simplifying the wiring of the array substrate.

[0076] In one possible implementation, combined with Figure 3HAs shown, the first pixel connection portion 41 extends along the third direction Z and electrically connects the two opposite corners of the first sub-pixel electrode portion P1 and the second sub-pixel electrode portion P2. In this way, the first sub-pixel electrode portion P1 and the second sub-pixel electrode portion P2 can be connected in close proximity, simplifying the wiring of the array substrate.

[0077] In one possible implementation, combined with Figure 3H As shown, the second pixel connection portion 42 includes: a first sub-connection portion 421 extending along the second direction Y, a second sub-connection portion 422, and a third sub-connection portion 423 extending along the third direction Z and connecting the first sub-connection portion 421 and the second sub-connection portion 422; wherein, the extension line of the second sub-connection portion 422 is located on the side of the extension line of the first sub-connection portion 421 closer to the second sub-pixel electrode portion P2. In this way, the third sub-pixel electrode portion P3 and the fourth sub-pixel electrode portion P4 can be connected in close proximity, simplifying the wiring of the array substrate.

[0078] In one possible implementation, combined with Figures 3A-3I and Figure 5 As shown, where Figure 5 The equivalent circuit diagram for a sub-pixel is provided. The array substrate further includes: a pixel driving circuit that is electrically connected to the sub-pixel electrode in a one-to-one correspondence, and a first trace 5 extending along the second direction Y; the pixel driving circuit includes: a first transistor T1, a second transistor T2, and a third transistor T3; specifically, the pixel driving circuit may also include a first capacitor C1 and a second capacitor C2.

[0079] The gate of the first transistor T1 is electrically connected to the gate line 2, the first electrode TA of the first transistor T1 is electrically connected to the data line 3, and the second electrode TB of the first transistor T1 is electrically connected to the second sub-pixel electrode P2. Specifically, the second electrode TB of the first transistor T1 can be electrically connected to the second sub-pixel electrode P2 through the first via K1 and the third via K3.

[0080] The gate of the second transistor T2 is electrically connected to the gate line 2. The first electrode TA of the second transistor T2 is multiplexed with the first electrode TA of the first transistor T1. The second electrode TB of the second transistor T2 is electrically connected to the fourth sub-pixel electrode P4. Specifically, the second electrode TB of the second transistor T2 can be electrically connected to the fourth sub-pixel electrode P4 through the second via K2 and the fourth via K4.

[0081] The gate of the third transistor T3 is electrically connected to the gate line 2. The first terminal TA of the third transistor T3 is multiplexed with the second terminal TB of the second transistor T2. The second terminal TB of the third transistor T3 is multiplexed with part of the first trace 5.

[0082] Specifically, the array substrate also includes a first liquid crystal capacitor Cpx1 and a second liquid crystal capacitor Cpx2. The first liquid crystal capacitor Cpx1 can be formed by the first sub-pixel electrode group PA and the common electrode layer of the opposing substrate. The second liquid crystal capacitor Cpx2 can be formed by the second sub-pixel electrode group PB and the common electrode layer of the opposing substrate. The first capacitor C1 can be formed by the first sub-pixel electrode group PA and the first sub-common trace 61. The second capacitor C2 can be formed by the second sub-pixel electrode group PB and the second sub-common trace 62.

[0083] In this embodiment of the invention, the first sub-pixel electrode group PA can be electrically connected to the gate line 1 and the data line 3 through the first transistor T1, and the second sub-pixel electrode group PB can be electrically connected to the gate line 2 and the data line 3 through the second transistor T2. The second terminal of the third transistor T3 is electrically connected to the first trace 5, which can release the storage capacitor in the second capacitor C2 corresponding to the second sub-pixel electrode group PB to the first trace 5 through the third transistor T3. This allows the brightness of the first sub-pixel electrode group PA to be greater than the brightness of the second sub-pixel electrode group PB, thereby enabling pixels with different brightness levels within the same sub-pixel electrode 4 and achieving an 8-domain display effect.

[0084] In one possible implementation, combined with Figure 3H As shown, the array substrate further includes: a first pixel overlap portion 43 electrically connected to the second sub-pixel electrode portion P2, and a second pixel overlap portion 44 electrically connected to the fourth sub-pixel electrode portion P4.

[0085] The first pixel overlap portion 43 has an overlapping area with the second electrode TB of the first transistor T1 in the same area as the first pixel overlap portion 43. The second sub-pixel electrode portion P2 is electrically connected to the second electrode TB of the first transistor T1 through the first pixel overlap portion 43.

[0086] The second pixel overlap portion 44 has an overlapping area with the second electrode TB of the second transistor T2 on the substrate 1. The fourth sub-pixel electrode portion T4 is electrically connected to the second electrode TB of the second transistor T2 through the second pixel overlap portion 44.

[0087] In one possible implementation, combined with Figure 3H As shown, the second pixel overlap portion 44 includes: a first sub-overlap portion 441, and a second sub-overlap portion 442 connecting the first sub-overlap portion 441 and the fourth sub-pixel electrode P4; wherein, there is a gap between the first sub-overlap portion 441 and the fourth sub-pixel electrode P4.

[0088] In one possible implementation, combined with Figure 3HAs shown, the first pixel overlap portion 43 has two first sides w1 extending along the second direction Y; the second pixel overlap portion 44 has two second sides w2 extending along the second direction Y; wherein the orthographic projection of one of the first sides w1 onto the substrate 1 overlaps with the orthographic projection of the second pixel overlap portion 44 onto the substrate 1; wherein the orthographic projection of one of the second sides w2 onto the substrate 1 overlaps with the orthographic projection of the first pixel overlap portion 43 onto the substrate 1.

[0089] In one possible implementation, the orthographic projections of the two first edges w1 onto the substrate 1 can correspond to and coincide with the orthographic projections of the two second edges w2 onto the substrate 1. That is, the first pixel overlap portion 43 and the fourth sub-pixel electrode portion P4 are aligned in the second direction Y.

[0090] In one possible implementation, combined with Figure 3C As shown, the second electrode TB of the first transistor T1 includes: a first main portion TB11 extending along the first direction X, and a first branch portion TB12 extending from one end of the first main portion TB11 along the second direction Y; the orthographic projection of the first main portion TB11 on the substrate 1 overlaps with the orthographic projection of the first pixel overlap portion 43 on the substrate 1; the orthographic projection of the first branch portion TB12 on the substrate 1 overlaps with the orthographic projection of the gate line 2 on the substrate 1.

[0091] The second electrode TB of the second transistor T2 includes: a second main portion TB21 extending along the first direction X, and a second branch TB22 extending from one end of the second main portion TB21 along the first direction X; the orthographic projection of the second main portion TB22 on the substrate 1 overlaps with the orthographic projection of the second pixel overlap portion 44 on the substrate 1; the orthographic projection of the second branch TB22 on the substrate 1 overlaps with the orthographic projection of the gate line 2 on the substrate 1.

[0092] In one possible implementation, combined with Figure 3A , Figure 3H and Figure 3I As shown, the first trace 5 includes: multiple segments of first trace main body 51 extending along the second direction Y, and first trace bend portion 52 connecting two adjacent segments of first trace main body 51.

[0093] The orthographic projection of the first trace main portion 51 onto the substrate 1 overlaps with the gap between the second sub-pixel electrode portion P2 and the third sub-pixel electrode portion P3 on the substrate 1. The orthographic projection of the first trace bend portion 52 onto the substrate 1 overlaps with the orthographic projection of the gate line 2 onto the substrate, and bends towards the side of the third transistor T3. In this embodiment, the first trace 5 further includes the first trace bend portion 52, which faces the side of the third transistor T3, so as to be reused as the second electrode TB of the third transistor T3, in order to avoid the first electrode TA and the second electrode TB of the third transistor T3 having a large distance on the first X, which would affect the performance of the third transistor T3.

[0094] In one possible implementation, combined with Figure 3B As shown, the array substrate also includes: a plurality of first common trace groups 6 extending along the second direction Y; the common trace group 6 includes: a first sub-common trace 61 located on one side of the gate line 2, and a second sub-common trace 62 located on the other side of the gate line 6.

[0095] The first sub-common route 61 includes: a first sub-common route main portion 611, and a first sub-common route protrusion 612 extending from the first sub-common route main portion 611 toward the gate line 2; the second sub-common route 62 includes: a second sub-common route main portion 621, and a second sub-common route protrusion 622 extending from the second sub-common route main portion 621 toward the gate line 2.

[0096] The orthographic projection of the first sub-common trace protrusion 612 onto the substrate 1 overlaps with the orthographic projection of the first pixel overlap portion 43 onto the substrate 1, thus forming a first capacitor C1; the orthographic projection of the second sub-common trace protrusion 622 onto the substrate 1 overlaps with the orthographic projection of the second pixel overlap portion 44 onto the substrate 1, thus forming a second capacitor C2.

[0097] In one possible implementation, combined with Figures 3A-3H As shown, the array substrate can be sequentially disposed on one side of the substrate 1 with the following... Figure 3B The gate layer shown, such as Figure 3C The data line layer shown, such as Figure 3D The active layer shown, such as Figure 3E The first insulating layer 91 shown is as follows: Figure 3F The first electrode layer shown, as Figure 3G The second insulating layer 92 shown is as follows: Figure 3H The pixel electrode layer shown;

[0098] The active layer may include an active pattern 7 corresponding to a transistor;

[0099] The first insulating layer 91 may have a first via K1 and a second via K2; the first insulating layer 91 may be a first passivation layer or an organic ORG layer.

[0100] The first electrode layer may include a first cutout L1, a second cutout L2, a third cutout L3, and a fourth cutout L4. The first cutout L1 may correspond to two identical sub-pixel electrode portions P0 in the first direction X. The orthographic projection of the second cutout L2 onto the substrate 1 and the orthographic projection of the first via K1 onto the substrate 1 allow the second sub-pixel electrode portion P2 to conduct through the second cutout L2 and the second electrode TB of the first transistor T1. The orthographic projection of the third cutout L3 onto the substrate 1 and the orthographic projection of the second via K2 onto the substrate 1 allow the fourth sub-pixel electrode portion P4 to conduct through the third cutout L3 and the second electrode TB of the second transistor T2. The orthographic projection of the fourth cutout L4 onto the substrate 1 may overlap with the orthographic projection of the gate line 2 onto the substrate 1 to reduce the overlap capacitance with the gate line 2. Specifically, the first electrode layer may be a transparent electrode layer, and the material of the first electrode layer may be the same as the material of the pixel electrode layer.

[0101] The second insulating layer 92 may have a third via K3 and a fourth via K4; the second insulating layer 92 may be a second passivation layer.

[0102] In this embodiment of the present disclosure, the array substrate is further provided with a first electrode layer having a first cutout L1. The orthographic projection of the first electrode layer onto the substrate 1 can cover at least a portion of the orthographic projection of the data line 3 onto the substrate 1, and can cover at least a portion of the orthographic projection of the gate line 2 onto the substrate 1, thereby shielding the coupling capacitance between the sub-pixel electrode 4 and the data line 3, and the coupling capacitance between the sub-pixel electrode 4 and the gate line 2, thereby improving the transmittance of the display panel.

[0103] Based on the same inventive concept, the array substrate provided in the embodiments of this disclosure further includes a counter substrate disposed opposite to the array substrate, wherein a common electrode layer is disposed on the side of the counter substrate facing the array substrate.

[0104] Based on the same inventive concept, this disclosure provides a display device, which includes a display panel as provided in the embodiments of this disclosure. Implementation of this display device can refer to the embodiments of the display panel described above, and repeated details will not be repeated.

[0105] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0106] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0107] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, include: Substrate; Multiple gate lines are located on one side of the substrate, and the multiple gate lines extend along a first direction; Multiple data lines are located on the same side of the substrate as the multiple gate lines, and the multiple data lines extend along a second direction; A plurality of sub-pixel electrodes, at least one of the plurality of sub-pixel electrodes comprising: a first sub-pixel electrode group and a second sub-pixel electrode group; both the first sub-pixel electrode group and the second sub-pixel electrode group comprise: two sub-pixel electrode portions arranged and electrically connected along a third direction; in the same sub-pixel electrode, the brightness of the first sub-pixel electrode group is greater than the brightness of the second sub-pixel electrode group, and the two sub-pixel electrode portions of the first sub-pixel electrode group are located on the same side of the two sub-pixel electrode portions of the second sub-pixel electrode group, the third direction intersecting the first direction and the second direction.

2. The array substrate as claimed in claim 1, wherein, The two sub-pixel electrode portions of the first sub-pixel electrode group are respectively: a first sub-pixel electrode portion and a second sub-pixel electrode portion; the two sub-pixel electrode portions of the second sub-pixel electrode group are respectively: a third sub-pixel electrode portion and a fourth sub-pixel electrode portion. The second sub-pixel electrode portion is adjacent to the third sub-pixel electrode portion and is arranged along the first direction.

3. The array substrate as described in claim 2, wherein, The first sub-pixel electrode portion is adjacent to the third sub-pixel electrode portion and is arranged along the second direction.

4. The array substrate as claimed in claim 3, wherein, The fourth sub-pixel electrode portion is adjacent to the second sub-pixel electrode portion and is arranged along the second direction.

5. The array substrate as claimed in claim 4, wherein, In the sub-pixel electrode, the first sub-pixel electrode portion, the second sub-pixel electrode portion, and the third sub-pixel electrode portion are located on one side of the gate line electrically connected to the sub-pixel electrode, and the fourth sub-pixel electrode portion is located on the other side of the gate line electrically connected to the sub-pixel electrode.

6. The array substrate as claimed in claim 4 or 5, wherein, The array substrate further includes: a first pixel connection portion and a second pixel connection portion; In the same sub-pixel electrode, the first sub-pixel electrode portion and the second sub-pixel electrode portion are electrically connected through the first pixel connection portion, and the third sub-pixel electrode portion and the fourth sub-pixel electrode portion are electrically connected through the second pixel connection portion.

7. The array substrate as claimed in claim 6, wherein, The first pixel connection portion extends along the third direction and electrically connects the two opposite corners of the first sub-pixel electrode portion and the second sub-pixel electrode portion.

8. The array substrate as claimed in claim 6, wherein, The second pixel connection portion includes: a first sub-connection portion extending along the second direction, a second sub-connection portion, and a third sub-connection portion extending along the third direction and connecting the first sub-connection portion and the second sub-connection portion; wherein, the extension line of the second sub-connection portion is located on the side of the extension line of the first sub-connection portion closer to the second sub-pixel electrode portion.

9. The array substrate as claimed in claim 5, wherein, The array substrate further includes: a pixel driving circuit electrically connected to each of the sub-pixel electrodes, and a first trace extending along the second direction; the pixel driving circuit includes: a first transistor, a second transistor, and a third transistor; The gate of the first transistor is electrically connected to the gate line, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the second sub-pixel electrode. The gate of the second transistor is electrically connected to the gate line, the first electrode of the second transistor is multiplexed from the first electrode of the first transistor, and the second electrode of the second transistor is electrically connected to the fourth sub-pixel electrode. The gate of the third transistor is electrically connected to the gate line, the first electrode of the third transistor is multiplexed with the second electrode of the second transistor, and the second electrode of the third transistor is multiplexed with a portion of the first trace.

10. The array substrate as claimed in claim 9, wherein, The array substrate further includes: a first pixel overlap portion electrically connected to the second sub-pixel electrode portion, and a second pixel overlap portion electrically connected to the fourth sub-pixel electrode portion; The first pixel overlap portion has an overlapping area with the second electrode of the first transistor in the substrate. The second sub-pixel electrode portion is electrically connected to the second electrode of the first transistor through the first pixel overlap portion. The second pixel overlap portion has an overlapping area with the second electrode of the second transistor in the substrate. The fourth sub-pixel electrode portion is electrically connected to the second electrode of the second transistor through the second pixel overlap portion.

11. The array substrate as claimed in claim 10, wherein, The second pixel overlap portion includes: a first sub-overlap portion, and a second sub-overlap portion connecting the first sub-overlap portion and the fourth sub-pixel electrode; There is a gap between the first sub-overlapping portion and the fourth sub-pixel electrode.

12. The array substrate as claimed in claim 10 or 11, wherein, The first pixel overlap portion has two first sides extending along the second direction; the second pixel overlap portion has two second sides extending along the second direction; The orthographic projection of one of the first edges on the substrate overlaps with the orthographic projection of the second pixel overlapping portion on the substrate; and the orthographic projection of one of the second edges on the substrate overlaps with the orthographic projection of the first pixel overlapping portion on the substrate.

13. The array substrate as claimed in claim 10, wherein, The second electrode of the first transistor includes: a first main portion extending along the first direction, and a first branch extending from one end of the first main portion along the second direction; the orthographic projection of the first main portion on the substrate has an overlapping area with the orthographic projection of the first pixel overlap portion on the substrate; the orthographic projection of the first branch on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate. The second electrode of the second transistor includes: a second main portion extending along the first direction, and a second branch extending from one end of the first main portion along the first direction; the orthographic projection of the second main portion on the substrate has an overlapping area with the orthographic projection of the second pixel overlap portion on the substrate; the orthographic projection of the second branch on the substrate has an overlapping area with the orthographic projection of the gate line on the substrate.

14. The array substrate as claimed in claim 9, wherein, The first trace includes: multiple segments of first trace main body extending along the second direction, and a first trace bend connecting two adjacent segments of the first trace main body; The first trace main portion has an overlapping area with the gap between the second sub-pixel electrode portion and the third sub-pixel electrode portion in the orthogonal projection of the substrate; the first trace bend portion has an overlapping area with the gate line in the orthogonal projection of the substrate, and bends toward the side of the third transistor.

15. The array substrate as claimed in claim 10, wherein, The array substrate further includes: a plurality of first common trace groups extending along the second direction; the first common trace group includes: a first sub-common trace located on one side of the gate line, and a second sub-common trace located on the other side of the gate line; The first sub-common trace includes: a first sub-common trace main portion, and a first sub-common trace protrusion extending from the first sub-common trace main portion toward the gate line; the second sub-common trace includes: a second sub-common trace main portion, and a second sub-common trace protrusion extending from the second sub-common trace main portion toward the gate line. The orthographic projection of the first sub-common trace protrusion on the substrate overlaps with the orthographic projection of the first pixel overlap portion on the substrate; the orthographic projection of the second sub-common trace protrusion on the substrate overlaps with the orthographic projection of the second pixel overlap portion on the substrate.

16. A display panel, wherein, The array substrate includes the array substrate as described in any one of claims 1-15, and further includes a counter substrate disposed opposite to the array substrate, wherein the counter substrate has a common electrode layer disposed on the side facing the array substrate.

17. A display device, wherein, Includes the display panel as described in claim 16.

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