Low-power-consumption wide-input-range voltage pre-stabilizing circuit and control method thereof

Abstract

The invention discloses a low-power-consumption wide-input-range pre-voltage-stabilizing circuit and a control method thereof.The low-power-consumption wide-input-range pre-voltage-stabilizing circuit comprises a voltage-stabilizing negative feedback circuit, a self-biasing high-voltage current source and an MOS tube series connection circuit, the self-biasing high-voltage current source provides bias voltage and bias current for the voltage-stabilizing negative feedback circuit, the MOS tube series connection circuit converts output voltage fluctuation into current variation, and the current variation is controlled by the MOS tube series connection circuit. The voltage stabilization negative feedback circuit and the MOS tube series connection circuit form a negative feedback loop to stabilize the output voltage. The problem that the power consumption of a traditional pre-voltage-stabilizing circuit is increased along with the increase of the external power supply voltage is solved, the low-power-consumption performance is achieved, meanwhile, the input power supply range of the pre-voltage-stabilizing circuit is widened, the fluctuation of the output voltage in the wide input power supply range is reduced, the linear adjustment rate is increased, and the design difficulty of a post-stage circuit is reduced.

Description

Technical Field

[0001] The present invention relates to a pre-voltage stabilization circuit and a control method thereof, in particular to a pre-voltage stabilization circuit with low power consumption and wide input range and a control method thereof, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] Pre-regulator circuits are widely used in the field of semiconductor integrated circuit technology. The pre-regulator circuit is located between the power supply and the internal sub-power supply of the circuit, and pre-reduces the high-voltage power supply input to the integrated circuit to a lower power supply to facilitate subsequent signal processing. The pre-regulator circuit is limited by factors such as power consumption, performance, and circuit implementation difficulty. Most circuits cannot be implemented using circuits such as bandgap references and operational amplifiers. The pre-regulator circuit has the problem that the output voltage is greatly affected by the high-voltage power supply and output load, and the transient response capability is limited, resulting in a long voltage undershoot or overcharge time and a large amplitude, which increases the design difficulty of the subsequent circuit.

[0003] Traditional pre-regulator circuits are generally implemented using the reverse conduction characteristics of Zener diodes, such as Figure 2 As shown. The voltage regulator diode D0 provides a bias voltage for the NMOS tube M0, and the source of M0 is the output of the pre-regulator circuit. This structure can provide a stable output voltage under a high-voltage power supply, but it is difficult to ensure that the NMOS is saturated and turned on under low voltage, resulting in a decrease in the output voltage and load capacity. In the traditional integrated circuit manufacturing process, the electrical characteristics of the Zener tube vary in a large range, the voltage variation range of the negative terminal of the Zener tube is large under high voltage, and the static current is unstable. This structure is greatly affected by the manufacturing process. In short, the traditional pre-regulator circuit has the problem of being greatly affected by the manufacturing process, input voltage range and temperature. These problems are more prominent in integrated circuits with high input voltage range and low power consumption, especially in industrial or automotive-grade circuits with high performance and reliability requirements. Therefore, improving the performance and stability of the pre-regulator circuit is of great significance to improving the performance and reliability of the entire integrated circuit. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a low-power and wide-input range pre-stabilization circuit and a control method thereof, which improves the problem that the power consumption of the traditional pre-stabilization circuit increases with the increase of the external power supply voltage.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: A low-power, wide-input-range pre-voltage regulator circuit comprises a voltage regulator negative feedback circuit, a self-biased high-voltage current source and a MOS tube series circuit. The self-biased high-voltage current source provides a bias voltage and a bias current for the voltage regulator negative feedback circuit. The MOS tube series circuit converts output voltage fluctuations into current variations. The voltage regulator negative feedback circuit and the MOS tube series circuit form a negative feedback loop to stabilize the output voltage.

[0006] Furthermore, the MOS tube series circuit includes a high-voltage PMOS tube HVMP4, a low-voltage PMOS tube LVMP0, a low-voltage PMOS tube LVMP1, a resistor R2 and a low-voltage NMOS tube LVMN2, the source of the high-voltage PMOS tube HVMP4 is connected to the power supply VIN, the drain of the high-voltage PMOS tube HVMP4 is connected to the source of the low-voltage PMOS tube LVMP0 and generates an output voltage VOUT, the gate of the low-voltage PMOS tube LVMP0 is connected to the drain of the low-voltage PMOS tube LVMP0 and the source of the low-voltage PMOS tube LVMP1, the gate of the low-voltage PMOS tube LVMP1 is connected to the drain of the low-voltage PMOS tube LVMP1 and one end of the resistor R2, the other end of the resistor R2 is connected to the drain of the low-voltage NMOS tube LVMN2 and the gate of the low-voltage NMOS tube LVMN2, and the source of the low-voltage NMOS tube LVMN2 is grounded.

[0007] Furthermore, the voltage stabilization negative feedback circuit comprises a high-voltage PMOS tube HVMP2, a high-voltage PMOS tube HVMP3, a high-voltage NMOS tube HVMN1, a high-voltage NMOS tube HVMN2, a low-voltage NMOS tube LVMN1 and a resistor R1, a source of the high-voltage PMOS tube HVMP2 and a source of the high-voltage PMOS tube HVMP3 are connected to a power supply VIN, a gate of the high-voltage PMOS tube HVMP2 and a gate of the high-voltage PMOS tube HVMP3, a drain of the high-voltage PMOS tube HVMP2 and a high-voltage NMOS tube H The drain of the high-voltage PMOS tube HVMP3 is connected to the gate of the high-voltage PMOS tube HVMP4 and the drain of the high-voltage NMOS tube HVMN2, the source of the high-voltage NMOS tube HVMN1 is connected to the drain of the low-voltage NMOS tube LVMN1, the gate of the low-voltage NMOS tube LVMN1 is connected to the gate of the low-voltage NMOS tube LVMN2, the source of the high-voltage NMOS tube HVMN2 is connected to one end of the resistor R1, and the source of the low-voltage NMOS tube LVMN1 and the other end of the resistor R1 are grounded.

[0008] Further, the self-biased high-voltage current source includes a high-voltage PMOS tube HVMP0, a high-voltage PMOS tube HVMP1, a high-voltage NMOS tube HVMN0, a low-voltage NMOS tube LVMN0 and a resistor R0, a source of the high-voltage PMOS tube HVMP0 and a source of the high-voltage PMOS tube HVMP1 are connected to a power supply VIN, a gate of the high-voltage PMOS tube HVMP0 is connected to a gate of the high-voltage PMOS tube HVMP1, a drain of the high-voltage PMOS tube HVMP1 and a drain of the high-voltage NMOS tube HVMN0, a drain of the high-voltage PMOS tube HVMP0 is connected to a gate of the high-voltage NMOS tube HVMN0, a gate of the high-voltage NMOS tube HVMN1, a gate of the high-voltage NMOS tube HVMN2 and a drain of the low-voltage NMOS tube LVMN0, a source of the high-voltage NMOS tube HVMN0 is connected to a gate of the low-voltage NMOS tube LVMN0 and one end of the resistor R0, and a source of the low-voltage NMOS tube LVMN0 and the other end of the resistor R0 are grounded.

[0009] Furthermore, the high-voltage PMOS transistor HVMP2 and the high-voltage PMOS transistor HVMP3 form a first current mirror, and the mirror ratio of the first current mirror is 1:1.

[0010] Furthermore, the low voltage NMOS transistor LVMN2 and the low voltage NMOS transistor LVMN1 form a second current mirror, and the mirror ratio of the second current mirror is 1:1.

[0011] A control method for a low-power, wide-input-range pre-regulator circuit comprises the following steps: The self-biased high-voltage current source provides a bias voltage for the high-voltage NMOS tube HVMN1 and a bias current for the high-voltage NMOS tube HVMN2. The self-biased high-voltage current source does not need a startup circuit to start, and uses a negative feedback structure to generate a stable current output. The current I0 flowing through the high-voltage NMOS tube HVMN0 generated by the negative feedback structure meets the formula: ; Among them, V0 is the node voltage where the resistor R0 is connected to the gate of the low-voltage NMOS tube LVMN0, is the average mobility of electrons in the channel, is the gate oxide capacitance of the gear area, is the width-to-length ratio of the transistor channel, is the gate-source threshold voltage, is the gate-source voltage of the high-voltage NMOS tube HVMN0; The voltage stabilizing negative feedback circuit and the MOS tube series circuit form a negative feedback loop; Assuming the resistor ratio ; The current passing through the high-voltage NMOS transistor HVMN0 is I0, and the current passing through the high-voltage NMOS transistor HVMN2 is I3. According to ; obtain ; The current I3 is determined by the replication of the self-biased current source; Assume that the current passing through the high-voltage PMOS transistor HVMP2 is I1, and the current passing through the low-voltage NMOS transistor LVMN2 is I4. The high-voltage PMOS transistor HVMP2 and the high-voltage PMOS transistor HVMP3 form a first current mirror, and the mirror ratio of the first current mirror is 1:1. The low-voltage NMOS transistor LVMN2 and the low-voltage NMOS transistor LVMN1 form a second current mirror, and the mirror ratio of the second current mirror is 1:1. Thus, obtain ; During normal operation ; The expression of the output voltage VOUT is: ; When the output voltage VOUT fluctuates downward, the current I4 passing through the resistor R2 decreases, and the current I2 after mirror current replication decreases. At this time, I2 < I3, and the gate voltage of the high-voltage PMOS transistor HVMP4 is pulled down, and the output voltage VOUT is adjusted to be higher through the negative feedback loop; when the output voltage VOUT fluctuates upward, the current I4 passing through the resistor R2 increases, and the current I2 after mirror current replication increases. At this time, I2 > I3, and the gate voltage of the high-voltage PMOS transistor HVMP4 is pulled up, and the output voltage VOUT is adjusted to be lower through the negative feedback loop; When the input power supply VIN fluctuates downward, the current I0 generated by the self-biased current source and the current I3 are not affected, but the output voltage VOUT fluctuates downward through the parasitic capacitance coupling of the high-voltage PMOS transistor HVPM4. The gate-source voltage of the high-voltage PMOS transistor HVPM3 decreases, resulting in a decrease in the current I2. At this time, I2 < I3, and the gate voltage of the high-voltage PMOS transistor HVMP4 is pulled down, and the output voltage VOUT becomes higher; when the input power supply VIN fluctuates upward, the output voltage VOUT fluctuates upward through the parasitic capacitance coupling of the high-voltage PMOS transistor HVPM4. The gate-source voltage of the high-voltage PMOS transistor HVPM3 increases, resulting in an increase in the current I2. At this time, I2 > I3, and the gate voltage of the high-voltage PMOS transistor HVMP4 is pulled up, and the output voltage VOUT becomes lower; As long as it is ensured that both I2 and I3 are saturation region currents, that is ; ; The pre-regulated output VOUT does not change with load.

[0012] Compared with the prior art, the present invention has the following advantages and effects: the present invention discloses a low-power consumption and wide-input range pre-stabilization circuit and a control method thereof, which improves the problem that the power consumption of the traditional pre-stabilization circuit increases with the increase of the external power supply voltage, has the performance of low power consumption, and at the same time improves the input power supply range of the pre-stabilization circuit, reduces the fluctuation of the output voltage under the wide input power supply range, improves the linear regulation rate, and reduces the design difficulty of the subsequent circuit; the MOS tube series circuit converts the output voltage fluctuation into the current change, and uses the current negative feedback loop to stabilize the pre-stabilization output, thereby improving the load regulation rate and enhancing the transient recovery ability of the pre-stabilization circuit. At the same time, the output voltage can be flexibly adjusted, thereby enhancing the applicability of the present technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of a low-power consumption and wide-input range pre-stabilizing circuit of the present invention.

[0014] Figure 2 It is a schematic diagram of a pre-stabilization circuit in the prior art. DETAILED DESCRIPTION

[0015] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0016] like Figure 1 As shown, a low-power, wide-input-range pre-voltage-stabilizing circuit of the present invention comprises a voltage-stabilizing negative feedback circuit, a self-biased high-voltage current source and a MOS tube series circuit. The self-biased high-voltage current source provides a bias voltage and a bias current for the voltage-stabilizing negative feedback circuit. The MOS tube series circuit converts the output voltage fluctuation into a current variation. The voltage-stabilizing negative feedback circuit and the MOS tube series circuit form a negative feedback loop to stabilize the output voltage.

[0017] The MOS tube series circuit includes a high-voltage PMOS tube HVMP4, a low-voltage PMOS tube LVMP0, a low-voltage PMOS tube LVMP1, a resistor R2 and a low-voltage NMOS tube LVMN2. The source of the high-voltage PMOS tube HVMP4 is connected to a power source VIN, the drain of the high-voltage PMOS tube HVMP4 is connected to the source of the low-voltage PMOS tube LVMP0 and generates an output voltage VOUT, the gate of the low-voltage PMOS tube LVMP0 is connected to the drain of the low-voltage PMOS tube LVMP0 and the source of the low-voltage PMOS tube LVMP1, the gate of the low-voltage PMOS tube LVMP1 is connected to the drain of the low-voltage PMOS tube LVMP1 and one end of the resistor R2, the other end of the resistor R2 is connected to the drain of the low-voltage NMOS tube LVMN2 and the gate of the low-voltage NMOS tube LVMN2, and the source of the low-voltage NMOS tube LVMN2 is grounded.

[0018] The voltage stabilizing negative feedback circuit includes a high-voltage PMOS tube HVMP2, a high-voltage PMOS tube HVMP3, a high-voltage NMOS tube HVMN1, a high-voltage NMOS tube HVMN2, a low-voltage NMOS tube LVMN1 and a resistor R1. The source of the high-voltage PMOS tube HVMP2 and the source of the high-voltage PMOS tube HVMP3 are connected to the power supply VIN, and the gate of the high-voltage PMOS tube HVMP2 is connected to the gate of the high-voltage PMOS tube HVMP3, the drain of the high-voltage PMOS tube HVMP2 and the high-voltage NMOS tube HVMN1. 1, the drain of the high-voltage PMOS tube HVMP3 is connected to the gate of the high-voltage PMOS tube HVMP4 and the drain of the high-voltage NMOS tube HVMN2, the source of the high-voltage NMOS tube HVMN1 is connected to the drain of the low-voltage NMOS tube LVMN1, the gate of the low-voltage NMOS tube LVMN1 is connected to the gate of the low-voltage NMOS tube LVMN2, the source of the high-voltage NMOS tube HVMN2 is connected to one end of the resistor R1, and the source of the low-voltage NMOS tube LVMN1 and the other end of the resistor R1 are grounded.

[0019] The self-biased high-voltage current source includes a high-voltage PMOS tube HVMP0, a high-voltage PMOS tube HVMP1, a high-voltage NMOS tube HVMN0, a low-voltage NMOS tube LVMN0 and a resistor R0. The source of the high-voltage PMOS tube HVMP0 and the source of the high-voltage PMOS tube HVMP1 are connected to the power supply VIN, the gate of the high-voltage PMOS tube HVMP0 is connected to the gate of the high-voltage PMOS tube HVMP1, the drain of the high-voltage PMOS tube HVMP1 and the drain of the high-voltage NMOS tube HVMN0, the drain of the high-voltage PMOS tube HVMP0 is connected to the gate of the high-voltage NMOS tube HVMN0, the gate of the high-voltage NMOS tube HVMN1, the gate of the high-voltage NMOS tube HVMN2 and the drain of the low-voltage NMOS tube LVMN0, the source of the high-voltage NMOS tube HVMN0 is connected to the gate of the low-voltage NMOS tube LVMN0 and one end of the resistor R0, and the source of the low-voltage NMOS tube LVMN0 and the other end of the resistor R0 are grounded.

[0020] The high-voltage PMOS tube HVMP2 and the high-voltage PMOS tube HVMP3 form a first current mirror, and the mirror ratio of the first current mirror is 1:1.

[0021] The low voltage NMOS transistor LVMN2 and the low voltage NMOS transistor LVMN1 form a second current mirror, and the mirror ratio of the second current mirror is 1:1.

[0022] A control method for a low-power, wide-input-range pre-regulator circuit comprises the following steps: The self-biased high-voltage current source provides a bias voltage for the high-voltage NMOS tube HVMN1 and a bias current for the high-voltage NMOS tube HVMN2. The self-biased high-voltage current source does not need a startup circuit to start, and uses a negative feedback structure to generate a stable current output. The current I0 flowing through the high-voltage NMOS tube HVMN0 generated by the negative feedback structure meets the formula: ; Among them, V0 is the node voltage where the resistor R0 is connected to the gate of the low-voltage NMOS tube LVMN0, is the average mobility of electrons in the channel, is the gate oxide capacitance of the gear area, is the width-to-length ratio of the transistor channel, is the gate-source threshold voltage, is the gate-source voltage of the high-voltage NMOS tube HVMN0. From the formula, it can be seen that the generated current and power consumption of the self-biased high-voltage current source have nothing to do with the power supply voltage.

[0023] The voltage stabilization negative feedback circuit and the MOS tube series circuit form a negative feedback loop, which is used to reduce the fluctuation of the pre-voltage stabilization circuit caused by external factors.

[0024] Assuming the resistor ratio ; The current passing through the high-voltage NMOS transistor HVMN0 is I0, and the current passing through the high-voltage NMOS transistor HVMN2 is I3. According to ; obtain ; The current I3 is determined by copying the self-biased current source.

[0025] Assume that the current passing through the high-voltage PMOS transistor HVMP2 is I1, and the current passing through the low-voltage NMOS transistor LVMN2 is I4. The high-voltage PMOS transistor HVMP2 and the high-voltage PMOS transistor HVMP3 form a first current mirror, and the mirror ratio of the first current mirror is 1:1. The low-voltage NMOS transistor LVMN2 and the low-voltage NMOS transistor LVMN1 form a second current mirror, and the mirror ratio of the second current mirror is 1:1. Thus, obtain .

[0026] During normal operation ; The expression of the output voltage VOUT is: .

[0027] The structure of the series-connected MOS transistors can be flexibly adjusted to meet the requirements of different output voltages.

[0028] When the output voltage VOUT fluctuates downward, the current I4 passing through the resistor R2 decreases, and the current I2 after mirror current replication decreases. At this time, I2 < I3, and the gate voltage of the high-voltage PMOS transistor HVMP4 is pulled down, and the output voltage VOUT is adjusted to be higher through the negative feedback loop; when the output voltage VOUT fluctuates upward, the current I4 passing through the resistor R2 increases, and the current I2 after mirror current replication increases. At this time, I2 > I3, and the gate voltage of the high-voltage PMOS transistor HVMP4 is pulled up, and the pre-output voltage VOUT is adjusted to be lower through the negative feedback loop.

[0029] When the input power supply VIN fluctuates downward, the current I0 and the current I3 generated by the self - bias current source are not affected, but the output voltage VOUT fluctuates downward through the parasitic capacitance coupling of the high - voltage PMOS transistor HVPM4. The gate - source voltage of the high - voltage PMOS transistor HVPM3 decreases, resulting in a decrease in the current I2. At this time, I2 < I3, the gate voltage of the high - voltage PMOS transistor HVMP4 is pulled down, and the output voltage VOUT becomes higher; when the input power supply VIN fluctuates upward, the output voltage VOUT fluctuates upward through the parasitic capacitance coupling of the high - voltage PMOS transistor HVPM4. The gate - source voltage of the high - voltage PMOS transistor HVPM3 increases, resulting in an increase in the current I2. At this time, I2 > I3, the gate voltage of the high - voltage PMOS transistor HVMP4 is pulled up, and the output voltage VOUT becomes lower, having good linear regulation rate and transient enhancement performance.

[0030] As long as it is ensured that both I2 and I3 are saturation - region currents, that is ; ; The pre - regulated output VOUT does not change with the load, having good load regulation performance.

[0031] In the present invention, the mirror ratio of the current mirror can be adjusted according to the circuit transient characteristics and stability requirements.

[0032] The present invention discloses a pre - regulated circuit with low power consumption and wide input range and its control method, which improves the problem that the power consumption of the traditional pre - regulated circuit increases with the increase of the external power supply voltage, has the performance of low power consumption, at the same time increases the input power supply range of the pre - regulated circuit, reduces the fluctuation of the output voltage in the wide input power supply range, improves the linear regulation rate, reduces the design difficulty of the subsequent circuit; the MOS transistor series - connection circuit converts the output voltage fluctuation into a current change amount, uses the current negative - feedback loop to stabilize the pre - regulated output, improves the load regulation rate, enhances the transient recovery ability of the pre - regulated circuit, and at the same time the output voltage can be flexibly adjusted, enhancing the applicability of the present technology.

[0033] The above - mentioned are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art, without departing from the scope of the technical solution of the present invention, may make some changes or modifications to the above - disclosed technical content to form equivalent embodiments of equivalent changes. However, as long as it does not depart from the content of the technical solution of the present invention, according to the technical essence of the present invention, any simple modification, equivalent replacement, and improvement made to the above - mentioned embodiments within the spirit and principle of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A low power consumption and wide input range pre-regulator circuit, characterized in that: It includes a voltage-stabilizing negative feedback circuit, a self-biased high-voltage current source and a MOS tube series circuit. The self-biased high-voltage current source provides a bias voltage and a bias current for the voltage-stabilizing negative feedback circuit. The MOS tube series circuit converts the output voltage fluctuation into a current variation. The voltage-stabilizing negative feedback circuit and the MOS tube series circuit form a negative feedback loop to stabilize the output voltage.

2. The low power consumption and wide input range pre-stabilization circuit according to claim 1, characterized in that: The MOS tube series circuit includes a high-voltage PMOS tube HVMP4, a low-voltage PMOS tube LVMP0, a low-voltage PMOS tube LVMP1, a resistor R2 and a low-voltage NMOS tube LVMN2, the source of the high-voltage PMOS tube HVMP4 is connected to the power supply VIN, the drain of the high-voltage PMOS tube HVMP4 is connected to the source of the low-voltage PMOS tube LVMP0 and generates an output voltage VOUT, the gate of the low-voltage PMOS tube LVMP0 is connected to the drain of the low-voltage PMOS tube LVMP0 and the source of the low-voltage PMOS tube LVMP1, the gate of the low-voltage PMOS tube LVMP1 is connected to the drain of the low-voltage PMOS tube LVMP1 and one end of the resistor R2, the other end of the resistor R2 is connected to the drain of the low-voltage NMOS tube LVMN2 and the gate of the low-voltage NMOS tube LVMN2, and the source of the low-voltage NMOS tube LVMN2 is grounded.

3. The low power consumption and wide input range pre-stabilization circuit according to claim 2, characterized in that: The voltage stabilization negative feedback circuit comprises a high-voltage PMOS tube HVMP2, a high-voltage PMOS tube HVMP3, a high-voltage NMOS tube HVMN1, a high-voltage NMOS tube HVMN2, a low-voltage NMOS tube LVMN1 and a resistor R1, a source of the high-voltage PMOS tube HVMP2 and a source of the high-voltage PMOS tube HVMP3 are connected to a power source VIN, a gate of the high-voltage PMOS tube HVMP2 and a gate of the high-voltage PMOS tube HVMP3, a drain of the high-voltage PMOS tube HVMP2 and a high-voltage NMOS tube HVMN2 are connected to each other, and a voltage stabilization negative feedback circuit comprises a high-voltage PMOS tube HVMP2, a high-voltage PMOS tube HVMP3 and a drain of the high-voltage PMOS tube HVMP2 and a high-voltage NMOS tube HVMN1. The drain of the high-voltage PMOS tube HVMP3 is connected to the gate of the high-voltage PMOS tube HVMP4 and the drain of the high-voltage NMOS tube HVMN2, the source of the high-voltage NMOS tube HVMN1 is connected to the drain of the low-voltage NMOS tube LVMN1, the gate of the low-voltage NMOS tube LVMN1 is connected to the gate of the low-voltage NMOS tube LVMN2, the source of the high-voltage NMOS tube HVMN2 is connected to one end of the resistor R1, and the source of the low-voltage NMOS tube LVMN1 and the other end of the resistor R1 are grounded.

4. The low power consumption and wide input range pre-stabilization circuit according to claim 3, characterized in that: The self - biased high - voltage current source includes a high - voltage PMOS transistor HVMP0, a high - voltage PMOS transistor HVMP1, a high - voltage NMOS transistor HVMN0, a low - voltage NMOS transistor LVMN0, and a resistor R0. The source electrodes of the high - voltage PMOS transistor HVMP0 and the high - voltage PMOS transistor HVMP1 are connected to the power supply VIN. The gate electrode of the high - voltage PMOS transistor HVMP0 is connected to the gate electrode of the high - voltage PMOS transistor HVMP1, the drain electrode of the high - voltage PMOS transistor HVMP1, and the drain electrode of the high - voltage NMOS transistor HVMN0. The drain electrode of the high - voltage PMOS transistor HVMP0 is connected to the gate electrode of the high - voltage NMOS transistor HVMN0, the gate electrodes of the high - voltage NMOS transistors HVMN1 and HVMN2, and the drain electrode of the low - voltage NMOS transistor LVMN0. The source electrode of the high - voltage NMOS transistor HVMN0 is connected to the gate electrode of the low - voltage NMOS transistor LVMN0 and one end of the resistor R0. The source electrode of the low - voltage NMOS transistor LVMN0 and the other end of the resistor R0 are grounded.

5. The low power consumption and wide input range pre-stabilization circuit according to claim 4, characterized in that: The high - voltage PMOS transistor HVMP2 and the high - voltage PMOS transistor HVMP3 form a first current mirror, and the mirror ratio of the first current mirror is 1:

1.

6. The low power consumption and wide input range pre-stabilization circuit according to claim 4, characterized in that: The low - voltage NMOS transistor LVMN2 and the low - voltage NMOS transistor LVMN1 form a second current mirror, and the mirror ratio of the second current mirror is 1:

1.

7. A control method for a low power consumption and wide input range pre-regulator circuit according to any one of claims 1 to 6, characterized in that It includes the following steps: The self - biased high - voltage current source provides a bias voltage for the high - voltage NMOS transistor HVMN1 and a bias current for the high - voltage NMOS transistor HVMN2. The self - biased high - voltage current source does not require a startup circuit to start. It uses a negative - feedback structure to generate a stable current output. The current I0 flowing through the high - voltage NMOS transistor HVMN0 generated by the negative - feedback structure conforms to the formula: ； Among them, V0 is the node voltage where the resistor R0 is connected to the gate of the low-voltage NMOS tube LVMN0, is the average mobility of electrons in the channel, is the gate oxide capacitance of the gear area, is the width-to-length ratio of the transistor channel, is the gate-source threshold voltage, is the gate-source voltage of the high-voltage NMOS tube HVMN0; The voltage - stabilizing negative - feedback circuit and the MOS transistor series - connection circuit form a negative - feedback loop. Assume the resistance ratio ； The current passing through the high - voltage NMOS transistor HVMN0 is I0, and the current passing through the high - voltage NMOS transistor HVMN2 is I3. According to ； Get ； The current I3 is determined by the replication of the self - bias current source. Assume the current passing through the high - voltage PMOS transistor HVMP2 is I1, and the current passing through the low - voltage NMOS transistor LVMN2 is I4. The high - voltage PMOS transistor HVMP2 and the high - voltage PMOS transistor HVMP3 form a first current mirror, and the mirror ratio of the first current mirror is 1:

1. The low - voltage NMOS transistor LVMN2 and the low - voltage NMOS transistor LVMN1 form a second current mirror, and the mirror ratio of the second current mirror is 1:

1. Thus, we get ； When working normally ； The expression of the output voltage VOUT is: ； When the output voltage VOUT fluctuates downward, the current I4 passing through the resistor R2 decreases, and the current I2 after mirror - image current replication decreases. At this time, I2 < I3, and the gate voltage of the high - voltage PMOS transistor HVMP4 is pulled down, and the output voltage VOUT is adjusted to be higher through the negative - feedback loop. When the output voltage VOUT fluctuates upward, the current I4 passing through the resistor R2 increases, and the current I2 after mirror - image current replication increases. At this time, I2 > I3, and the gate voltage of the high - voltage PMOS transistor HVMP4 is pulled up, and the pre - output voltage VOUT is adjusted to be lower through the negative - feedback loop. When the input power supply VIN fluctuates downward, the current I0 and the current I3 generated by the self-biased current source are not affected, but the output voltage VOUT fluctuates downward through the parasitic capacitance coupling of the high-voltage PMOS transistor HVPM4. The gate-source voltage of the high-voltage PMOS transistor HVPM3 decreases, resulting in a decrease in the current I2. At this time, I2 < I3, and the gate voltage of the high-voltage PMOS transistor HVMP4 is pulled down, and the output voltage VOUT becomes higher; when the input power supply VIN fluctuates upward, the output voltage VOUT fluctuates upward through the parasitic capacitance coupling of the high-voltage PMOS transistor HVPM4. The gate-source voltage of the high-voltage PMOS transistor HVPM3 increases, resulting in an increase in the current I2. At this time, I2 > I3, and the gate voltage of the high-voltage PMOS transistor HVMP4 is pulled up, and the output voltage VOUT becomes lower; As long as it is ensured that both I2 and I3 are saturation region currents, that is ； ； the pre-regulated output VOUT does not change with the load.

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