Multi-port synchronous FIFO (First In First Out) data reading method, device, system, equipment and medium

Abstract

The invention provides a multi-port synchronous FIFO (First In First Out) data reading method, device, system and equipment and a medium, and the method comprises the following steps: when a plurality of reading ports trigger corresponding data reading requests in parallel, obtaining a reading enable signal corresponding to each reading port and the current state information of FIFO; the read enable signal is used for indicating whether the read port performs read operation or not; for each read port, determining a target address according to the read enable signal and the current state information of the FIFO; the target address is used for representing an identifier of the data reading address; selecting target data from the register file or the write port data through a multiplexer according to the target address; the write port data refers to data currently written into the FIFO; and inputting the target data into the register through the input port to execute a beating operation, and executing a reading operation through the data reading interface corresponding to the FIFO. According to the scheme, the problem of large MUX delay caused by the increase of the FIFO depth in the traditional design is avoided, and the overall operation speed and performance of the system are improved.

Description

Technical Field

[0001] The present application relates to the field of processor technology, and in particular to a multi-port synchronous FIFO data reading method, device, system, equipment and medium. Background Art

[0002] In modern digital system design, multi-port synchronous First-In First-Out (FIFO) memory is a first-in first-out queue storage structure with multiple read and write ports, and all read and write operations are synchronized based on the same global clock signal. It has been widely used in various data processing and transmission scenarios, such as high-speed data acquisition systems, network communication equipment, and multimedia signal processing platforms. In these application scenarios, multi-port synchronous FIFO can achieve data buffering and coordination between different clock domains, ensuring efficient and stable data flow between multiple modules.

[0003] At present, the related technology adopts the classic multi-port synchronous FIFO circuit structure. In the design structure of the classic multi-port synchronous FIFO, each output port needs to select data from the register stack through a large multiplexer MUX bound to the FIFO depth during the read operation. As the demand for FIFO depth increases, the number of MUX input ports increases, the internal combinational logic becomes more complex, and a large delay (Delay1) is generated, which leads to a decrease in the operating speed and performance of the entire system. Summary of the invention

[0004] The embodiments of the present application provide a multi-port synchronous FIFO data reading method, apparatus, system, device and medium.

[0005] A first aspect of an embodiment of the present application provides a multi-port synchronous FIFO data reading method, the method comprising: When multiple read ports trigger corresponding data read requests in parallel, obtain a read enable signal corresponding to each of the read ports and current status information of the FIFO; the read enable signal is used to indicate whether the read port performs a read operation; For each of the read ports, a target address is determined according to the read enable signal and the current state information of the FIFO; the target address is used to represent an identifier of a data read address; According to the target address, target data is selected from the register file or the write port data through a multiplexer; the write port data refers to the data currently being written into the FIFO; The target data is input into the register through the input port to perform a beat operation and a read operation is performed through the data read interface corresponding to the FIFO.

[0006] A second aspect of an embodiment of the present application provides a multi-port synchronous FIFO data reading device, comprising: An acquisition module, used for acquiring a read enable signal corresponding to each read port and current status information of the FIFO when multiple read ports trigger corresponding data read requests in parallel; the read enable signal is used to indicate whether the read port performs a read operation; A determination module, used for determining a target address for each of the read ports according to the read enable signal and the current state information of the FIFO; the target address is used to represent an identifier of a data read address; A selection module, used for selecting target data from a register file or write port data through a multiplexer according to the target address; the write port data refers to data currently being written into the FIFO; The reading module is used to perform a beat operation on the target data through a register and to perform a read operation through the multi-port synchronous FIFO data reading interface.

[0007] According to a third aspect of the embodiments of the present application, a multi-port synchronous FIFO data reading system is provided, comprising: a register stack, a plurality of multiplexers, a plurality of registers, a plurality of read pointers, a plurality of read ports and a data reading interface, wherein each of the multiplexers establishes a communication connection with the corresponding register, and the data reading interface establishes a communication connection with each of the registers and each of the read pointers respectively; Each of the read pointers is used to: when multiple read ports trigger corresponding data read requests in parallel, obtain the read enable signal corresponding to the read port and the current state information of the FIFO and send them to the corresponding multiplexer; the read enable signal is used to indicate whether the read port performs a read operation; Each of the multiplexers is used to: for each of the read ports, determine a target address according to the read enable signal and the current state information of the FIFO; select target data from a register stack or write port data according to the target address; the target address is used to represent the identifier of the data read address; the write port data refers to the data currently being written into the FIFO; Each of the registers is used to: perform a beat operation on the target data and transmit the target data to the data reading interface; The data reading interface is used to perform a reading operation on the target data.

[0008] According to a fourth aspect of an embodiment of the present application, a computer device is provided, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above methods when executing the computer program.

[0009] According to a fifth aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above methods are implemented.

[0010] In the embodiment of the present application, a multi-port synchronous FIFO data reading method, device, system, equipment and medium are provided, the method comprising: when multiple read ports trigger corresponding data read requests in parallel, obtaining the read enable signal corresponding to each read port and the current status information of the FIFO, and for each read port, determining the target address according to the read enable signal and the current status information of the FIFO, and selecting the target from the register stack or the write port data through a multiplexer according to the target address, inputting the target data into the register through the input port to perform a beat operation, and performing a read operation through the data read interface corresponding to the FIFO. The technical solution in the present application can determine the target address in advance according to the obtained read enable signal and the current status information of the FIFO when multiple read ports trigger data read requests in parallel, so that the corresponding target data can be directly selected from the register stack or the write port data, avoiding the large MUX delay problem caused by the increase in FIFO depth in the traditional design, and performing a beat operation according to the target data through the register to read through the data read interface, alleviating the timing bottleneck of the downstream long combinational logic, and further improving the overall operation speed and performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 A schematic diagram of an existing FIFO structure provided for one embodiment of the present application; Figure 2 A schematic diagram of a structure for generating a delay by reading data through different reading ports provided in one embodiment of the present application; Figure 3 A schematic diagram of the structure of a computer device provided in one embodiment of the present application; Figure 4 A flowchart of a multi-port synchronous FIFO data reading method provided by an embodiment of the present application; Figure 5 A flowchart of a method for generating a corresponding target address according to a read enable signal provided in another embodiment of the present application; Figure 6 A schematic diagram of the structure of a multi-port synchronous FIFO data reading device provided by an embodiment of the present application; Figure 7 A schematic diagram of the structure of a multi-port synchronous FIFO data reading system provided in one embodiment of the present application. DETAILED DESCRIPTION

[0012] In the process of implementing the present application, the inventors discovered that the traditional multi-port synchronous FIFO circuit structure has the problem of output data timing delay, which leads to a decrease in the operating speed and performance of the entire system.

[0013] In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0014] As mentioned in the background technology, the above-mentioned multi-port synchronous FIFO structure has the characteristics of synchronous reading and writing, multiple read and write ports, read and write control logic, full and empty state detection, address mapping, data consistency, etc. Among them, synchronous reading and writing means that all read and write operations are performed in the same clock domain, which means that the read and write clock frequencies are the same, thereby avoiding synchronization problems that may occur in cross-clock domain designs. Multiple read and write ports refer to the design containing multiple independent read and write interfaces, allowing multiple data sources to write data to the FIFO at the same time, or read data from the FIFO, thereby improving data throughput and the parallel processing capability of the system. The read and write control logic includes the management and update logic of the read and write pointers, as well as the generation of read and write enable signals. Since it is a synchronous FIFO, the generation of these control signals must consider the clock domain synchronization problem to ensure that the read and write operations within a given clock cycle are mutually exclusive to prevent data competition. Full and empty state detection refers to judging the state of the FIFO by comparing the read pointer and the write pointer, including full, empty, and half-full states. These state signals are the result of the combinational logic and are fed back to the read and write controller in time to prevent overflow or underflow. Address mapping refers to the situation of multiple read / write ports. There may be a complex address mapping algorithm to ensure that each read / write port can correctly access the corresponding storage location of the FIFO. Data consistency means that in a multi-port synchronous FIFO, it must be ensured that no matter which port the data is written or read from, the first-in-first-out order is always maintained. In practical applications, multi-port synchronous FIFO is often used in high-performance data exchange, multi-processor communication, pipeline design, and high-speed data acquisition. It can efficiently realize data distribution, collection, and temporary storage, and effectively solve the data synchronization and cache requirements in the parallel processing process.

[0015] See also Figure 1 As shown, Figure 1The schematic diagram of the existing classic multi-port synchronous FIFO structure includes multiple key components and interface signals. The key components include: register file, multiplexer (MUX), write pointer, read pointer, flag logic, data write interface and data read interface. The register file is used to store data and is the storage body of FIFO. The flag is used to generate the status flag signal of FIFO, including full and empty signals, which are fed back to the write interface and read interface to control the read and write operations. There are multiplexers on both the write path and the read path. The multiplexer on the write path is used to select the corresponding write port data (wport1_data, wport2_data, etc.) to write to the register file according to the write enable signal; the multiplexer on the read path selects the data output (rport1_data, rport2_data ..., rportN_data, etc.) from the register file according to the read enable (read enable 1, read enable 2, ..., read enable N) signal. The write pointer (write pointer 1Write Pointer1, write pointer 2Write Pointer2 ..., write pointer NWrite PointerN) is used to track the location of data writing, and the read pointer module (Read Pointer1, Read Pointer2 ..., ReadPointerN, etc.) is used to track the location of data reading. The write enable signal (write enable 1, write enable 2, ..., write enable N) controls the write pointer update, and the read enable signal (RE1, RE2, etc.) controls the read pointer update.

[0016] The write interface has multiple write ports (wport1, wport2, etc., collectively referred to as wport), and the read interface has multiple read ports (rport1, rport2, etc., collectively referred to as rport).

[0017] The above interface signals include write interface signals and read interface signals. The write interface signals include: i_valid, i_ready and full, and the read interface signals include: o_valid, o_ready and empty. Among them, i_valid indicates whether the input data is valid, i_ready indicates whether the FIFO is ready to receive new data, and full feedbacks the full state of the FIFO to prevent new data from being written. o_valid indicates whether the output data is valid, o_ready indicates whether the receiving end is ready to receive data, and empty is used to feedback the empty state of the FIFO to prevent data from being read. The above circuit realizes the orderly writing and reading of data through the coordinated work of these components and signals, ensuring the correct operation of the FIFO in different states.

[0018] In the read operation of the classic multi-port synchronous FIFO design, each read port (rport) has a corresponding read address pointer (Read Pointer1 - N). When a read operation occurs, these read address pointers indicate the location where data is read from the register file (RegisterFile). Since there are multiple read ports, each read port must select the corresponding data from the numerous storage units in the register file, so each read port needs to pass through a multiplexer (MUX). The role of the MUX is to select the correct read data (rport(1-N)_data) required by the read port from different storage locations in the register file based on the signal of the read address pointer.

[0019] As the demand for FIFO depth (DP) increases, the number of storage units in the register stack will increase. Because the MUX needs to select data from these storage units, the number of MUX input ports will also increase accordingly. The MUX uses combinational logic to implement the data selection function. The more input ports there are, the more complex its internal logic structure is, and the longer the signal propagation path is. In this way, the time it takes for the signal to propagate from the input of the MUX to the output will become longer. This time is the combinational logic delay (Delay1). When the FIFO is connected to a very long combinational logic downstream, the delay on the entire signal path is the sum of the delays of each part. Since the delay (Delay1) generated by the MUX at the read port is large as the FIFO depth increases, it accounts for a high proportion of the delay of the entire signal path. If this delay is too large, the data cannot be stably transmitted to the downstream logic within the specified clock cycle, thereby affecting the operating speed of the entire system, making the read port output a timing bottleneck for the entire system.

[0020] See also Figure 2As shown, the existing classic multi-port synchronous FIFO design will have the problem of output data timing delay when each read data request occurs. For example, multiple read requests include: read port (rport1) request, read port (rport2) request, ..., read port (rportN) request, and each read port (rport) has a corresponding read address pointer (Read Pointer1 -N). When a read operation occurs, these read address pointers will indicate the location where data is read from the register file. Therefore, each read port needs to pass through a multiplexer (MUX). The role of the MUX is to select the correct read data (rport (1 - N)_data) required by the read port from different storage locations in the register file according to the signal of the read address pointer, that is, the rport1 request corresponds to the output rport1 read data, the rport2 request corresponds to the output rport2 read data, and the rportN request corresponds to the output rportN read data. Since each read port will pass through a large MUX selector, a combinational logic delay (Delay1) is generated, which in turn affects the operating speed and performance of the entire system.

[0021] Based on the above-mentioned defects, the present application provides a multi-port synchronous FIFO timing optimization method. Compared with the related art, the technical solution in the present application can determine the target address in advance based on the read enable signal and the current status information of the FIFO when multiple read ports trigger data read requests in parallel, so that the corresponding target data can be directly selected from the register stack or write port data, avoiding the large MUX delay problem caused by the increase in FIFO depth in traditional designs, and performing a beat operation according to the target data through the register to read through the data read interface, alleviating the timing bottleneck in the downstream long combinational logic, and further improving the overall operation speed and performance of the system.

[0022] See also Figure 3 , a schematic diagram of the structure of a computer device provided in an embodiment of the present application. Figure 3As shown, the computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium can be, for example, a disk. The non-volatile storage medium stores files (which can be files to be processed or processed files), an operating system and a computer program, etc. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a multi-port synchronous FIFO data reading method is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0023] See also Figure 4 The following embodiments take the above-mentioned computer device as the execution subject, and apply the multi-port synchronous FIFO data reading method provided in the embodiment of the present application to the above-mentioned computer device to perform data reading as an example for specific description. The multi-port synchronous FIFO data reading provided in the embodiment of the present application includes the following steps 201-204: Step 201: When multiple read ports trigger corresponding data read requests in parallel, obtain a read enable signal corresponding to each read port and current status information of the FIFO; the read enable signal is used to indicate whether the read port performs a read operation.

[0024] It should be noted that each of the above read ports (rport1-N) corresponds to a read enable signal (RE1 - REN). When the read enable signal of a read port is valid, it indicates that the read port needs to read data. The current status information of the FIFO can include empty state, full state, nearly empty state, and nearly full state.

[0025] In the process of obtaining the above-mentioned read enable signal, combinational logic can be used to combine the empty state of the FIFO and the external read request signal. When the FIFO is not empty and there is a data read request, the read enable signal is valid. For example, a logic AND gate is used, with the non-empty signal and the external data read request as input, and the output is the read enable signal.

[0026] The above FIFO structure may include a write pointer and a read pointer. The write pointer is used to track the location where data is written, and the read pointer is used to track the location where data is read. The working principle of FIFO is that data is written from one end and read from the other end. The write pointer points to the location where the next data is to be written, and the read pointer points to the location where the next data is to be read.

[0027] When the write operation is faster than the read operation, the write pointer will gradually move forward and approach the read pointer. When the write pointer catches up with the read pointer, that is, the two point to the same position, it means that all the storage units in the FIFO have been written with data, and there is no free space to store new data, so the FIFO is full at this time.

[0028] Under normal circumstances, the read pointer moves forward as data is read, and the write pointer moves forward as data is written. When the read operation is faster than the write operation, the read pointer will gradually distance itself from the write pointer. When the read pointer and the write pointer are equal again, there are two possible situations. One is that the FIFO has never been written to, and the FIFO is naturally empty at this time; the other is that the FIFO once had data, but after a series of read and write operations, all the data has been read out. At this time, although the FIFO is not empty (because there was data before), there is actually no data to read, so it also means that the FIFO is empty.

[0029] Step 202: For each read port, determine the target address according to the read enable signal and the current status information of the FIFO; the target address is used to identify the data read address.

[0030] The target address is the address where data needs to be read, and its function is to determine the address of the next read operation in advance so as to read data more efficiently. Different current status information in the FIFO corresponds to different selected target addresses.

[0031] It is understandable that in the process of determining the target address, in addition to the read enable signal, the current status information of the FIFO needs to be considered. The current status information may also include the current write pointer position, the depth of the FIFO, etc. This information can help determine whether the read port should read data from the register stack or from the write port data.

[0032] Step 203: According to the target address, target data is selected from the register file or the write port data through a multiplexer; the write port data refers to the data currently being written into the FIFO.

[0033] It should be noted that the target data refers to the data to be read. The target data may be represented in different data forms, for example, in the form of a table, a picture, a text, an audio or video or other forms. The target data may be one, two or more. For each write port, there is a corresponding multiplexer. When the multi-port parallel FIFO includes N read ports (rport1-N) and N write ports, it also includes N multiplexers, each of which is used to perform a selection operation.

[0034] Specifically, after obtaining the target address, for each read port, the target data can be obtained from the register stack or selected from the write port data through a multiplexer according to the target address. The multiplexer has a selection function and can select the target data from one of the two situations. The target data is the data corresponding to the target address.

[0035] Step 204: input the target data into the register through the input port to perform a beat operation and perform a read operation through the data read interface corresponding to the FIFO.

[0036] It is understandable that the register may be a D-type flip-flop (DFF). There are multiple registers in the multi-port parallel FIFO, each multiplexer corresponds to a register, and corresponds to multiple input ports, each input port corresponds to a read port and a write port. The multi-port parallel FIFO may also include a data read interface, through which the read target data may be output.

[0037] Specifically, after the target data is selected by the multiplexer, the target data is transmitted to the register (DFF, D-type flip-flop) for a beat operation. The main purpose of the beat operation is to synchronize the data. In digital circuits, since the signal transmission delay on different paths may be different, the arrival time of the data may be inconsistent, which may cause unstable or erroneous data. By temporarily storing the data for one beat (i.e. one clock cycle), the data is stabilized in the register to ensure that the data can be correctly processed and transmitted in the next clock cycle.

[0038] In an embodiment of the present application, a multi-port synchronous FIFO data reading method is provided, the method comprising: when multiple read ports trigger corresponding data read requests in parallel, obtaining the read enable signal corresponding to each read port and the current status information of the FIFO, and for each read port, determining the target address according to the read enable signal and the current status information of the FIFO, and selecting the target from the register stack or the write port data through a multiplexer according to the target address, inputting the target data into the register through the input port to perform a beat operation, and performing a read operation through the data read interface corresponding to the FIFO. The technical solution in the present application can determine the target address in advance according to the obtained read enable signal and the current status information of the FIFO when multiple read ports trigger data read requests in parallel, so that the corresponding target data can be directly selected from the register stack or the write port data, avoiding the large MUX delay problem caused by the increase in FIFO depth in the traditional design, and performing a beat operation according to the target data through the register to read through the data read interface, alleviating the timing bottleneck of the downstream long combinational logic, and further improving the overall operation speed and performance of the system.

[0039] In an optional embodiment of the present application, the embodiment of the present application provides a specific implementation method for determining the target address according to the read enable signal and the current state information of the FIFO, and the method includes: When the current status information of the FIFO is full, the corresponding current read address is generated according to the read enable signal, and the current read address is used as the target address; when the current status information of the FIFO is empty and the data write request corresponding to the write port is detected to be triggered, the write port address is determined according to the read enable signal and used as the target address.

[0040] It should be noted that when a multi-port synchronous FIFO has a multi-read port request, according to the existing classic FIFO design, the corresponding read address (Read Pointer1~N) is calculated through the read enable signal (RE1-N) of each read port, and then the corresponding read address (Read Pointer1~N) is used to select the data in the register file. In the embodiment of the present application, the current read address (Read Pointer Next1 - N) corresponding to each read port is calculated through the read enable signal (RE1-N) of each read port (rport1-N), and the current read address is used as the target address. The current read address can directly select the current read register file data (rport (1-N) _data_reg) of each read port from the register file, and the data is obtained in advance in this way.

[0041] After obtaining the read enable signal and FIFO status information, the current read address (Read Pointer Next1 - N) is generated through specific address calculation logic based on the read enable signal and FIFO status information. This calculation logic may be a complex combinational circuit, which will perform corresponding operations based on different input signals to determine the correct read address of each read port.

[0042] For example, one possible calculation method is to add an offset to the current write pointer position when the read enable signal is valid. This offset may be related to factors such as the number of the read port and the depth of the FIFO, thereby obtaining the current read address. In this way, the current read register file data (rport (1 - N) _data_reg) of each read port can be directly selected from the register file through this current read address.

[0043] When the current status information of the FIFO is empty and the data write request corresponding to the write port is detected, the current read address of each read port is determined according to the read enable signal, and a comparison logic judgment is performed based on the current read address of each read port and the write data address (Write Pointer (1-N), so as to determine the write port address according to the comparison result and use it as the target address.

[0044] In the embodiment of the present application, the read enable signal determines whether the read operation is allowed according to the read enable signal and the current state information of the FIFO, and the current state information of the FIFO reflects the storage status of the data in the FIFO. By combining these two factors to determine the target address, data underflow caused by performing a read operation when the FIFO is empty, and stopping the read operation due to mistakenly believing that the FIFO is full when it is not full can be avoided, thereby ensuring that the data read each time is valid and improving the accuracy of data processing.

[0045] In an optional embodiment of the present application, see Figure 5 As shown, when the current status information of the FIFO is in an empty state and a data write request corresponding to the write port is detected to be triggered, a corresponding target address is generated according to a read enable signal, including: Step 301: when the current status information of the FIFO is empty, a data read request corresponding to a read port and a data write request corresponding to a write port occur simultaneously and the number of read ports and write ports is the same, determine the current read address of each read port according to a read enable signal.

[0046] Step 302: Obtain the current write data address of the FIFO.

[0047] Step 303: Perform a comparative logic judgment based on the current read address and write data address of each read port, and select a target address from the data of all write ports; the write data address is used to represent the current data address of the FIFO.

[0048] It should be noted that when the FIFO is empty, read requests and write requests occur at the same time and the number of reads and writes is the same, some problems will occur. Among them, the number of read and write ports is consistent to indicate that the number of write ports and read ports is the same. For example, the FIFO has 1 write port data and 1 read port requesting to read data at the same time, or 2 write port data and 2 read ports requesting to read data at the same time...until there are N write port data and N read ports requesting to read data at the same time. In these cases, since the data has not been written into the register stack in time, the data cannot be read directly from the register stack, otherwise wrong data will be read or no data will be readable.

[0049] In order to solve the above problem, it is necessary to obtain the write data address and compare the current read address of each read port with the existing write data address (Write Pointer (1 -N)) in the current FIFO. Through this judgment, N groups of selection signals are obtained, which are used to control an N-to-1 multiplexer (MUX) to select the corresponding data from the write port data (wport (1-N)_data) and directly send it to the input port (port (1 - N)_data_nxt) of the DFF (trigger). Then, through a 2-to-1 MUX, the current read FIFO data (rport (1 - N)_data_nxt) is finally obtained, thereby ensuring that the correct read data can be obtained even in special circumstances.

[0050] Among them, in the multi-port synchronous FOFO, the write pointer can be used to obtain the current write data address of the FIFO. The write pointer is used in the FIFO to indicate the location of the next data to be written. In the normal write operation process, the write pointer will point to each address of the FIFO storage unit in turn. After each write operation is completed, the write pointer will be updated to the address of the next storage unit. Therefore, by recording the value of the write pointer, the current write data address can be obtained.

[0051] For example, in hardware design, the write pointer is usually implemented by a counter. When the write enable signal is valid, the counter performs a counting operation driven by the clock signal, and the count value represents the address of the write pointer.

[0052] In this embodiment, when the current status information of the FIFO is an empty state, the data read request corresponding to the read port and the data write request corresponding to the write port occur simultaneously and the number of read ports and write ports is the same, the current read address and write data address of each read port can be comprehensively considered, thereby ensuring that the read data can be correctly obtained when the data is not completely written to the register stack, overcoming the large MUX delay problem caused by the increase in FIFO depth in traditional designs, and speeding up the read data output speed.

[0053] In an optional embodiment of the present application, the above-mentioned comparison logic judgment based on the current read address and write data address of each read port, and selecting the target address from the data of all write ports includes the following method steps: The current read address of each read port is compared bit by bit with the write data address to obtain a comparison result; the comparison result is used to indicate whether the current read address is consistent with the write data address; if the current read address is consistent with the write data address, the write data address is used as the target address.

[0054] Specifically, for each read port, the current read address (Read Pointer Next1-N) is compared with the existing write data address (Write Pointer (1-N) in the FIFO one by one to obtain the comparison result. This comparison method is usually performed bit by bit, starting from the highest bit, until a different bit is found or all bits are compared.

[0055] For example, if the current read address of read port 1 is 0101, and the write data address corresponding to write port 1 in FIFO is 0110, then starting from the highest bit, the first bit is 0 and the second bit is 1, then the first and second bits are equal, and the third bit is different. The current read address corresponding to the read port is 0, and the write data address corresponding to the write port is 1. At this time, it can be determined that the address of read port 1 is different from the address of write port 1. Then generate a selection signal based on the result of the address comparison.

[0056] If the current read address of the read port is equal to a write data address, the corresponding selection signal is set to valid (usually high level 1), indicating that the data of the write port needs to be selected, and the write data address corresponding to the write port is used as the target address; if they are not equal, the selection signal is set to invalid (usually low level 0).

[0057] For example, after comparison, it is found that the current read address of read port 2 is equal to the write data address of write port 3, then the signal corresponding to write port 3 in the selection signal group is set to 1, and the selection signals corresponding to other write ports are 0. In this way, N groups of selection signals are obtained, each group of signals corresponds to a write port. These N groups of selection signals are used as the control signals of the N-to-1 multiplexer MUX, and the input of MUX is the data of each write port (wport (1-N)_data).

[0058] In this embodiment, by comparing the current read address of each read port with the write data address bit by bit, it is possible to determine whether the current read address of each read port matches the write data address. When the two addresses are completely consistent, the target address is determined, so that the valid data corresponding to the read port requirements can be accurately screened out from multiple write data. For multi-port FIFOs, multiple read ports may initiate read requests at the same time. By bitwise comparison, the address comparison operation of each read port can be processed in parallel, so that each read port can independently and quickly find the corresponding write data, thereby supporting concurrent read and write operations of multiple ports and improving the data processing efficiency of FIFO.

[0059] In an optional embodiment of the present application, the above method of selecting target data from a register file or write port data through a multiplexer according to the target address includes the following method steps: When the target address is the current read address, the current read register file data corresponding to each read port is selected from the register file as the target data; When the target address is a write data address, data corresponding to the write data address is selected from the write port data as the target data.

[0060] As an implementable manner, if the target address is a current read address, corresponding current read register file data is directly selected from the register file according to the current read address as the target data.

[0061] As another possible implementation method, when the target address is a write port address, a selection signal can be generated based on the current read address and the write data address. According to the selection signal, the corresponding write port data can be selected as the target data through the multiplexer MUX and sent to the input port (port (1-N)_data_nxt) of the DFF register.

[0062] Exemplarily, when the selection signal indicates that the write port data of write port 3 is selected, the N-to-1 MUX will output the data wport3_data of write port 3 to the corresponding position in the input port port (1-N)_data_nxt of the register, and the data of other write ports will be ignored.

[0063] Furthermore, after obtaining the data from the DFF input port, it is necessary to finally determine the current read FIFO data (rport (1-N)_data_nxt) through a 2-to-1 multiplexer MUX. The 2-to-1 here is usually a selection between the data directly read from the register stack (rport (1-N)_data_reg) and the write port data obtained from the write port after the N-to-1 MUX selection (port (1-N)_data_nxt). The selection may be based on other conditions such as the FIFO status. For example, if the FIFO is not empty and there is no read-write conflict (that is, the data has been written into the register stack), the 2-to-1 MUX will select the data read from the register stack as the current read FIFO data; if there is a read-write conflict, that is, the data has not been written into the register stack, then the data obtained from the write port after the N-to-1 MUX processing is selected as the current read FIFO data, and the current read FIFO data is the target data.

[0064] In this embodiment, according to the target address, it is possible to accurately select whether to select the corresponding data from the register stack or the write port data, thereby improving the flexibility of data acquisition, ensuring that the correct data is selected at the right time, avoiding errors caused by data conflicts, and avoiding unnecessary data transmission and processing processes, thereby reducing data delays.

[0065] In an optional embodiment of the present application, the above method further includes: When the FIFO is in an empty state and there is a valid write enable signal, the data of each write port is assigned to each input port of the register as the target data.

[0066] When there is a stored data in the FIFO and the read enable signal is valid, the data of each write port is assigned to each input port of the register as the target data.

[0067] When there are two stored data in the FIFO and the read enable signal is valid, the data read from the FIFO is assigned to the first input port in the register as the target data, and the data of the other write ports are assigned to the remaining input ports of the register in sequence as the target data; the other write ports refer to all the write ports except the first write port.

[0068] When there are n stored data in FIFO and the read enable signal is valid, the data read from FIFO is assigned as the target data to the first n-1 input ports in the register in sequence, and the data from the write port is assigned as the target data to the last input port of the register, n≥1.

[0069] Specifically, in a multi-port synchronous FIFO, the rule for updating the data of the register (DFF) input port can be selected according to the different states of the FIFO, the existing storage items (empty, with different numbers of storage items) and the read and write operations. The rule includes the following specific contents.

[0070] As an optional implementation, when the FIFO is empty and there is a write operation to update the data of the DFF input port, it can be represented by the following text structure: condi = empty&wen rdata_nxt_p1 = wdata_p1; rdata_nxt_p2 = wdata_p2; ... rdata_nxt_pn = wdata_pn; It should be noted that the above text structure indicates that the data of the DFF input port is updated only when the FIFO is empty (empty signal is valid) and write is enabled (wen signal is valid), which means that when there is no data in the FIFO and there is new data to be written, the subsequent DFF data update operation will be triggered. In the process of data update, the data of each write port (wdata_p1-wdata_pn) is assigned to the corresponding DFF input port (rdata_nxt_p1-rdata_nxt_pn), that is, the data wdata_p1 of write port 1 is assigned to the data rdata_nxt_p1 of the first input port 1 in DFF, the data wdata_p2 of write port 2 is assigned to the data rdata_nxt_p2 of the second input port 2 in DFF, ..., the data wdata_pn of write port n is assigned to the data rdata_nxt_pn of the last input port n in DFF. The purpose of doing this is that when the FIFO is empty, if there is a write operation, the newly written data is directly prepared as the data that can be read at the next moment, and the data is transferred and prepared in advance.

[0071] As another optional implementation, when there is one storage item in the FIFO and a read operation updates the data at the DFF input port, it can be represented by the following text structure: condi = 1entry&ren rdata_nxt_p1 = wdata_p1; rdata_nxt_p2 = wdata_p2; ... rdata_nxt_pn = wdata_pn; It should be noted that the above text structure indicates that it is established when there is only one storage item in the FIFO (1entry signal is valid) and there is a read enable signal (ren signal is valid). That is, when there is only one data in the FIFO and there is a read request, the DFF data needs to be updated. In the process of data update, the data of each write port is also assigned to the corresponding input port of the DFF, that is, the data wdata_p1 of write port 1 is assigned to the data rdata_nxt_p1 of the first input port 1 in the DFF, the data wdata_p2 of write port 2 is assigned to the data rdata_nxt_p1 of the second input port 2 in the DFF, ..., and the data wdata_pn of write port n is assigned to the data rdata_nxt_pn of the last input port n in the DFF. This is because when there is only one data in the FIFO and a read operation is to be performed, the newly written data may need to be prepared in advance to meet the needs of continuous reading and writing and avoid data transmission delays.

[0072] As another optional implementation, when the FIFO has two storage items and the data of the DFF input port is updated during a read operation, it can be represented by the following text structure: condi = 2entry&ren rdata_nxt_p1 = fifo_r; rdata_nxt_p2 = wdata_p1; ... rdata_nxt_pn = wdata_pn; It should be noted that the above text structure indicates that the data of the DFF input port is updated only when there are 2 storage items in the FIFO (2entry signal is valid) and read enable (ren signal is valid). During the data update process, the data rdata_nxt_p0 of the first input port 1 is assigned to fifo_r, and fifo_r represents the data read from the FIFO. The other ports (rdata_nxt_p1-rdata_nxt_pn) are still assigned to the data of the write port (wdata_p1-wdata_pn), that is, the data fifo_r read from the FIFO is assigned to the data rdata_nxt_p1 of the first input port 1 in the DFF, and the data wdata_p1 of the write port 1 is assigned to the data rdata_nxt_p2 of the second input port 2 in the DFF, ..., and the data wdata_pn of the write port n is assigned to the data rdata_nxt_pn of the last input port n in the DFF. This may be because when there are two data in the FIFO, the first reading port can read the data directly from the FIFO, while other ports may need to wait for the newly written data or process the data in a specific order.

[0073] As another optional implementation, when the FIFO has N storage items and the data of the DFF input port is updated during a read operation, it can be represented by the following text structure: condi = Nentry&ren rdata_nxt_p1 = fifo_r; rdata_nxt_p2 = fifo_r; ... rdata_nxt_pn = wdata_pn; It should be noted that the above text structure indicates that the data of the DFF input port is updated only when there are N storage items in the FIFO (Nentry signal is valid) and read enable (ren signal is valid). During the data update process, the data of the first n-1 DFF input ports (rdata_nxt_p1-rdata_nxt_p(n - 1)) are assigned to fifo_r, that is, the data read from the FIFO. The last input port n (rdata_nxt_pn) is assigned to the data of the write port (wdata_pn), that is, the data fifo_r read from the FIFO is assigned to the data rdata_nxt_p1 of the first input port 1 in the DFF, and the data fifo_r read from the FIFO is assigned to the data rdata_nxt_p2 of the second input port 2 in the DFF, ..., and the data wdata_pn of the write port n is assigned to the data rdata_nxt_pn of the last input port n in the DFF. This is based on the storage situation and read-write rules of the FIFO. The first n-1 input ports can directly read the existing data from the FIFO, while the last input port needs to prepare the newly written data to ensure the continuity and correctness of the data.

[0074] In this embodiment, according to different states and read and write operation conditions of the FIFO, the data of the DFF input port can be reasonably selected and updated, ensuring that the read and write operations of the data in the FIFO can be performed efficiently and accurately, eliminating the combinational logic delay of the output data.

[0075] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0076] On the other hand, the present application also provides a multi-port synchronous FIFO data reading device, see Figure 6 As shown, the device comprises: The acquisition module 810 is used to acquire the read enable signal corresponding to each read port and the current status information of the FIFO when multiple read ports trigger corresponding data read requests in parallel; the read enable signal is used to indicate whether the read port performs a read operation; The determination module 820 is used to determine the target address for each read port according to the read enable signal and the current state information of the FIFO; the target address is used to represent the identifier of the data read address; The selection module 830 is used to select target data from the register file or the write port data through the multiplexer according to the target address; the write port data refers to the data currently being written into the FIFO; The reading module 840 is used to perform a beat operation on the target data through a register and perform a read operation through a multi-port synchronous FIFO data reading interface.

[0077] Each module in the above-mentioned multi-port synchronous FIFO data reading device can be implemented in whole or in part by software, hardware and a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules.

[0078] The multi-port synchronous FIFO data reading device provided in the embodiment of the present application can determine the target address in advance according to the read enable signal and the current status information of the FIFO when multiple read ports trigger data read requests in parallel, so that the corresponding target data can be directly selected from the register stack or the write port data, avoiding the large MUX delay problem caused by the increase in FIFO depth in traditional designs, and performing a beat operation according to the target data through the register to read through the data read interface, alleviating the timing bottleneck of the downstream long combinational logic, and further improving the overall operation speed and performance of the system.

[0079] On the other hand, this application also provides a multi-port synchronous FIFO data reading system, see Figure 7 As shown, the system includes: a register stack, multiple multiplexers, multiple registers, multiple read pointers, and multiple read ports. Each multiplexer establishes a communication connection with the corresponding register, and the data reading interface establishes a communication connection with each register and each read pointer respectively.

[0080] Each read pointer is used for: when multiple read ports trigger corresponding data read requests in parallel, obtaining the read enable signal corresponding to the read port and the current status information of the FIFO and sending them to the corresponding multiplexer; the read enable signal is used to indicate whether the read port performs a read operation; each multiplexer is used for: for each read port, determining the target address according to the read enable signal and the current status information of the FIFO; according to the target address, selecting the target data from the register stack or the write port data; the target address is used to represent the identifier of the data read address; the write port data refers to the data currently being written to the FIFO; each register is used for: performing a beat operation on the target data and transmitting the target data to the data read interface; the data read interface is used for: performing a read operation on the target data.

[0081] Specifically, the register file is used to store data and is the core part of storing data in the multi-port synchronous FIFO. It has multiple ports, including multiple write ports (wport) and multiple read ports (rport), and can realize parallel read and write operations.

[0082] The above system may further include a plurality of comparison logic modules (Compare Logic), taking N comparison logic modules as an example, for example, they are: Compare Logic 1, Compare Logic 2, ..., Compare Logic N, which are used to compare related signals such as a write pointer and a read pointer to determine the state of a FIFO (first-in-first-out queue), such as full or empty.

[0083] The above system may also include multiple read pointers, taking N read pointers (read pointer 1, read pointer 2, ..., read pointer N) as an example, which are updated by N read enable signals (RE), such as read enable signal 1 (RE1), read enable signal 2 (RE2), ..., read enable signal N (REN), and each read pointer is used to indicate the location of reading data from the register stack. The system also includes multiple write pointers, taking N write pointers (write pointer 1, write pointer 2, ..., write pointer N) as an example, which are updated by N write enable signals (WE), and the corresponding write enable signals are respectively: write enable signal 1 (WE1), write enable signal 2 (WE2), ..., write enable signal N (WEN), and each write pointer is used to indicate the location of writing data to the register stack.

[0084] The multiplexers MUX are used to determine the target address according to the read enable signal and the current status information of the FIFO, and select the target data from the register stack or the write port data according to the target address.

[0085] The above-mentioned multiple registers are, for example, N DFFs, such as register 1 (DFF1), register 2 (DFF2), etc., register N (DFFN). Each register performs a beat operation on the target data and sends it to the data read interface, so that a read operation is performed through the data read interface.

[0086] During the write operation, the write port (wport) receives the write enable signal (WEN), write pointer (write pointer) and write data (wport_data), and the data is written to the register file after processing. When the write enable signal is valid, the data is stored in the corresponding address under the action of the clock. During the read operation, the read port (rport) has its own read pointer (read pointer). After being processed by the comparison logic, the multiplexer selects the data (rport_data) to be read from the register file for output. Each read port can perform read operations independently.

[0087] Optionally, the above system also has a state detection. When the write operation is frequent and the write pointer catches up to the read pointer to a certain extent, the comparison logic outputs a full signal after judgment, indicating that there is no free space in the register stack, which is characterized as a full state. If the read operation is faster than the write operation, the read pointer and the write pointer are equal and meet specific conditions, the comparison logic outputs an empty signal, indicating that there is no valid data to read, that is, the table is in an empty state. Among them, valid is used to indicate the validity of the data, and ready is used to indicate the readiness status of these signals and ports to help coordinate read and write operations.

[0088] The data reading system of the multi-port synchronous FIFO provided in the embodiment of the present application can determine the target address in advance according to the read enable signal and the current status information of the FIFO when multiple read ports trigger data read requests in parallel, so that the corresponding target data can be directly selected from the register stack or the write port data, avoiding the large MUX delay problem caused by the increase in FIFO depth in traditional designs, and performing a beat operation according to the target data through the register to read through the data read interface, alleviating the timing bottleneck of the downstream long combinational logic, and further improving the overall operation speed and performance of the system.

[0089] In one embodiment, a computer device is provided, the internal structure diagram of which can be as follows: Figure 3As shown. The computer device includes a processor, a memory, a network interface and a database connected via a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a multi-port synchronous FIFO data reading method as described above is implemented. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the multi-port synchronous FIFO data reading method as described above is implemented.

[0090] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above multi-port synchronous FIFO data reading method can be implemented.

[0091] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0092] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0093] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0094] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0095] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0096] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A multi-port synchronous FIFO data reading method, characterized in that: The multi-port synchronous FIFO data reading method comprises: When multiple read ports trigger corresponding data read requests in parallel, obtain a read enable signal corresponding to each of the read ports and current status information of the FIFO; the read enable signal is used to indicate whether the read port performs a read operation; For each of the read ports, a target address is determined according to the read enable signal and the current state information of the FIFO; the target address is used to represent an identifier of a data read address; According to the target address, target data is selected from the register file or the write port data through a multiplexer; the write port data refers to the data currently being written into the FIFO; The target data is input into the register through the input port to perform a beat operation and a read operation is performed through the data read interface corresponding to the FIFO.

2. The method according to claim 1, characterized in that: Determining a target address according to the read enable signal and current status information of the FIFO, comprising: When the current status information of the FIFO is in a full state, generating a corresponding current read address according to the read enable signal, and using the current read address as the target address; When the current status information of the FIFO is in an empty state and a data write request corresponding to the write port is detected to be triggered, the write port address is determined according to the read enable signal and is used as the target address.

3. The method according to claim 2, characterized in that When the current state information of the FIFO is in an empty state and a data write request corresponding to the write port is detected to be triggered, a corresponding target address is generated according to the read enable signal, including: When the current state information of the FIFO is an empty state, a data read request corresponding to the read port and a data write request corresponding to the write port occur simultaneously, and the number of the read ports and the number of the write ports are the same, determining the current read address of each of the read ports according to the read enable signal; Obtain the current write data address of the FIFO; According to the comparison logic judgment between the current read address of each read port and the write data address, the target address is selected from the data of all write ports; the write data address is used to represent the current data address of the FIFO.

4. The method according to claim 3, characterized in that According to the comparison logic judgment between the current read address of each read port and the write data address, the target address is selected from the data of all write ports, including: Compare the current read address of each read port with the write data address bit by bit to obtain a comparison result; the comparison result is used to indicate whether the current read address is consistent with the write data address; If the read address is consistent with the write data address, the write data address is used as the target address.

5. The method according to claim 3, characterized in that: According to the target address, target data is selected from a register file or write port data through a multiplexer, including: When the target address is the current read address, selecting the current read register stack data corresponding to each read port from the register stack as the target data; When the target address is the write data address, data corresponding to the write data address is selected from the write port data as the target data.

6. The method according to claim 1, characterized in that The register includes a plurality of input ports, and the method further includes: When the FIFO is in an empty state and there is a valid write enable signal, the data of each write port is assigned as the target data to each input port of the register respectively; When there is a stored data in the FIFO and a read enable signal is valid, the data of each write port is assigned as the target data to each input port of the register; When there are two stored data in the FIFO and a read enable signal is valid, the data read from the FIFO is assigned as target data to the first input port in the register, and the data of other write ports are assigned as target data to the remaining input ports of the register in sequence; the other write ports refer to the write ports except the first write port among all the write ports; When there are n stored data in the FIFO and the read enable signal is valid, the data read from the FIFO is assigned as the target data to the first n-1 input ports in the register in sequence, and the data of the write port is assigned as the target data to the last input port of the register, n≥1.

7. A multi-port synchronous FIFO data reading device, characterized in that: The multi-port synchronous FIFO data reading device comprises: An acquisition module, used for acquiring a read enable signal corresponding to each read port and current status information of the FIFO when multiple read ports trigger corresponding data read requests in parallel; the read enable signal is used to indicate whether the read port performs a read operation; A determination module, used for determining a target address for each of the read ports according to the read enable signal and the current state information of the FIFO; the target address is used to represent an identifier of a data read address; A selection module, used for selecting target data from a register file or write port data through a multiplexer according to the target address; the write port data refers to data currently being written into the FIFO; The reading module is used to perform a beat operation on the target data through a register and to perform a read operation through the multi-port synchronous FIFO data reading interface.

8. A multi-port synchronous FIFO data reading system, characterized in that: The multi-port synchronous FIFO data reading system comprises: a register stack, a plurality of multiplexers, a plurality of registers, a plurality of read pointers, a plurality of read ports and a data reading interface, each of the multiplexers establishes a communication connection with the corresponding register, and the data reading interface establishes a communication connection with each of the registers and each of the read pointers respectively; Each of the read pointers is used to: when multiple read ports trigger corresponding data read requests in parallel, obtain the read enable signal corresponding to the read port and the current state information of the FIFO and send them to the corresponding multiplexer; the read enable signal is used to indicate whether the read port performs a read operation; Each of the multiplexers is used to: for each of the read ports, determine a target address according to the read enable signal and the current state information of the FIFO; select target data from a register stack or write port data according to the target address; the target address is used to represent the identifier of the data read address; the write port data refers to the data currently being written into the FIFO; Each of the registers is used to: perform a beat operation on the target data and transmit the target data to the data reading interface; The data reading interface is used to perform a reading operation on the target data.

9. A computer device comprising: A memory and a processor, wherein the memory stores a computer program, wherein the processor implements the steps of the multi-port synchronous FIFO data reading method according to any one of claims 1 to 6 when executing the computer program.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the multi-port synchronous FIFO data reading method according to any one of claims 1 to 6 are implemented.

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