A memory and task allocation method

Abstract

The application provides a memory and a task allocation method. The memory comprises: a master control module, configured to receive host tasks; a plurality of cache units, configured to execute host tasks in corresponding task queues; and a cache management module, configured to acquire working states of the corresponding task queues according to types of the host tasks, and allocate the host tasks according to the working states of the task queues. The memory and the task allocation method provided by the application can improve cache utilization of the memory.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of storage, in particular to a memory and a task allocation method. BACKGROUND

[0002] With the wide application of the memory in the smart TV, set-top box, mobile terminal and other consumer electronic devices, the memory needs to achieve a balance among data reliability, stability and running efficiency. The memory adopts a collaborative architecture of the ARM architecture master control and the NAND flash module, and realizes core functions such as bad block management, garbage collection and performance optimization through firmware. The highly integrated characteristics of the memory lead to a complex system environment with multiple modules operating in parallel.

[0003] The current technical bottleneck is that each functional module (such as a data verification module and a cache module) in the memory is configured with an independent cache unit. However, in the existing architecture, the cache resources adopt a static allocation mechanism, and each cache unit only serves the corresponding host task. Due to the significant differences in capacity, access speed and data retention characteristics between different cache units, this single mapping cache management mode leads to two prominent problems: on the one hand, high-load modules are prone to performance bottlenecks due to insufficient exclusive cache resources; on the other hand, the idle cache of low-load modules cannot be dynamically called by the system, resulting in low overall utilization of storage resources. Therefore, there is room for improvement. SUMMARY

[0004] The purpose of the present application is to provide a memory and a task allocation method, which can improve the cache utilization of the memory.

[0005] To solve the above technical problems, the present application is realized by the following technical scheme:

[0006] The present application provides a memory, comprising:

[0007] a master control module, configured to receive a host task;

[0008] a plurality of cache units, configured to execute the host task in a corresponding task queue;

[0009] a cache management module, configured to obtain the working state of the corresponding task queue according to the type of the host task, and allocate the host task according to the working state of the task queue.

[0010] In an embodiment of the present application, the cache management module comprises:

[0011] a cache monitoring unit, configured to obtain the working state of the corresponding task queue according to the type of the host task;

[0012] The task allocation unit is configured to judge the working state of the task queue, and when the task queue is in an idle state, allocate the host task to the corresponding task queue until the task queue is in a full state; and when the task queue is in the full state, allocate the unallocated host task to the task queue of another cache unit.

[0013] In an embodiment of the present application, the task allocation unit allocates the unallocated host task according to the following steps:

[0014] When the task queue is in the full state, judge the working state of the task queue of another cache unit:

[0015] When there is at least one task queue in an idle state, allocate the unallocated host task to the same task queue.

[0016] In an embodiment of the present application, the task allocation unit allocates the unallocated host task to the same task queue according to the following steps:

[0017] Sort the idle capacities of all the task queues in the idle state to obtain the task queue with the largest idle capacity;

[0018] Allocate the unallocated host task to the task queue with the largest idle capacity.

[0019] In an embodiment of the present application, the task allocation unit allocates the unallocated host task according to the following steps:

[0020] Judge the number of the unallocated host task and the largest idle capacity:

[0021] When the number of the unallocated host task is less than or equal to the largest idle capacity, allocate all the unallocated host task to the task queue with the largest idle capacity;

[0022] When the number of the unallocated host task is greater than the largest idle capacity, allocate part of the unallocated host task to the task queue with the largest idle capacity until the task queue with the largest idle capacity is in a full state.

[0023] In an embodiment of the present application, the task allocation unit allocates the unallocated host task according to the following steps:

[0024] When the task queue of a cache unit is in a full state, judge the working state of the task queue of another cache unit:

[0025] When there is at least one task queue in an idle state, allocate the unallocated host task to different task queues.

[0026] In an embodiment of the present application, the task allocation unit allocates the unallocated host tasks to different task queues according to the following steps:

[0027] obtaining the idle capacity, total capacity, current throughput and average throughput of the task queues in the idle state; wherein the current throughput represents the number of host tasks processed by the cache unit in its task queue per unit time, and the average throughput represents the average value of the number of host tasks processed by all cache units in their task queues per unit time;

[0028] calculating the ratio of the idle capacity to the total capacity and the ratio of the current throughput to the average throughput of each of the task queues in the idle state, denoted as the first ratio and the second ratio respectively;

[0029] calculating the sum of the product of the first ratio and the corresponding adjustment coefficient and the product of the second ratio and the corresponding adjustment coefficient, denoted as the dynamic weight value;

[0030] splitting the unallocated host tasks according to the dynamic weight values of all the task queues in the idle state to obtain a plurality of task sets; each task set includes at least one unallocated host task;

[0031] allocating the task set to the corresponding task queue in the idle state.

[0032] In an embodiment of the present application, the cache management module further comprises a task queue unit for caching unallocated host tasks.

[0033] In an embodiment of the present application, the task allocation unit allocates the host tasks cached by the task queue unit according to the following steps:

[0034] judging the working state of the corresponding task queue according to the task type of the cached host tasks:

[0035] when the task queue is in the idle state, sequentially allocating the cached host tasks to the corresponding task queue until the task queue is in the full state.

[0036] The present application also provides a task allocation method of a memory, wherein the memory comprises a master module, a cache management module and a plurality of cache units; the task allocation method comprises:

[0037] receiving host tasks through the master module;

[0038] The cache management module obtains the working state of the corresponding task queue according to the type of the host task, and allocates the host task according to the working state of the task queue;

[0039] The host task in the corresponding task queue is executed by the cache unit.

[0040] As described above, the present application provides a memory and a task allocation method, by breaking the static binding relationship between cache resources and functional modules in the traditional storage architecture, a global dynamic scheduling system is constructed, effectively solving the efficiency bottleneck problem caused by rigid resource allocation of the storage system, realizing intelligent collaboration of cache resources across modules and tasks, and significantly improving the overall system performance and resource utilization. According to real-time task requirements, idle cache resources are automatically allocated to high-load modules, eliminating the resource waste phenomenon of "uneven busy and idle" in the traditional architecture. In the single-core scenario, cache resources are allocated based on task priority to avoid resource contention when a single core processes multiple tasks; in the multi-core scenario, cache resource sharing and task parallel scheduling across cores are implemented to achieve linear expansion capability.

[0041] Of course, implementing any product of the present application does not necessarily need to achieve all the advantages described above at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0043] Figure 1 The schematic diagram of the memory in an embodiment of the present application;

[0044] Figure 2 The schematic diagram of the cache management module in an embodiment of the present application.

[0045] In the figure: 10, power module; 20, first interface module; 30, master control module; 40, read-only storage module; 50, random cache unit; 60, mapping cache unit; 70, second interface module; 71, output cache unit; 72, input cache unit; 80, data verification module; 81, verification cache unit; 90, cache module; 91, write cache unit; 92, read cache unit; 100, flash memory module; 110, cache management module; 111, configuration management unit; 112, task queue unit; 113, state management unit; 114, cache monitoring unit; 115, task allocation unit; 116, interrupt processing unit. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0047] Please refer to Figure 1 The present application provides a memory, which can be an Embedded MultiMedia Card (eMMC) or a Universal Flash Storage (UFS). The memory can communicate with an electronic device through a CMD line and DATA0-7 lines, and execute reading, writing, erasing and other operations by receiving instructions from the electronic device. The electronic device can send instructions through the CMD line and transmit data through the DATA0-7 lines. The communication protocol between the memory and the electronic device can comply with the JEDEC protocol. The memory can include a power module 10, a first interface module 20, a master control module 30, a read-only storage module 40, a random cache unit 50, a mapping cache unit 60, a second interface module 70, a data verification module 80, a cache module 90, a flash memory module 100, a cache management module 110, etc.

[0048] In some embodiments, the power module 10 can be a power supply of the memory. The power module 10 can be used to receive power from an external electronic device and provide power supply to various modules inside the memory.

[0049] In some embodiments, the first interface module 20 (Universal Asynchronous Receiver / Transmitter, UART) can output log information of the memory when it is running. A developer can obtain the running state information log of the memory in real time without affecting the normal operation of the memory.

[0050] In some embodiments, the master module 30 can be a microcontroller unit (MCU). The master module 30 can be used to perform specific control tasks, such as reading data, processing instructions from the electronic device, etc. The CPU core of the master module 30 can be designed based on the RISC-V architecture to perform various control and computation tasks. The master module 30 can have one CPU core or multiple CPU cores. A CPU core is a basic unit in the master module 30 that executes instructions and performs operations. Each CPU core can independently perform tasks, and each CPU core has its own registers, ALU (arithmetic logic unit), and cache.

[0051] In some embodiments, the read-only storage module 40 can be a non-volatile memory (ROM) that stores data for a long time. The read-only storage module 40 can store programs such as firmware, which can be a set of pre-written instructions that guide the master module 30 on how to start and run. These instructions include device initialization, peripheral configuration, and possibly a bootloader. The bootloader can be used to load updated programs or operating systems, etc.

[0052] In some embodiments, the random cache unit 50 can be a volatile memory (RAM) that temporarily stores data and program code. The random cache unit 50 can be used to temporarily store data. When the master module 30 executes a program, the program code can be loaded from the read-only storage module 40 into the random cache unit 50 for execution.

[0053] In some embodiments, the memory mapping table module 60 can be used to manage the mapping relationship between virtual memory and physical memory. The memory mapping table module 60 converts virtual addresses (used by programs) to physical addresses (used by hardware) by maintaining a mapping table, thereby achieving efficient management and protection of memory. The mapping table can be a hierarchical structure (such as a page table) that records the correspondence between virtual addresses and physical addresses. For example, in the paging mechanism, virtual addresses are divided into page numbers and offsets within pages. The mapping table looks up the corresponding physical page frame through the page number. When a program accesses a virtual address, the master module 30 queries the mapping table to find the corresponding physical address. If there is no corresponding entry in the mapping table (i.e., a page fault), a page fault exception is triggered, and the master module 30 is responsible for loading the required data from the disk to the physical memory and updating the mapping table.

[0054] In some embodiments, the second interface module 70 can be a transmission interface between the memory and the electronic device. The second interface module 70 can receive instructions from the electronic device and return data or status information to the electronic device. The second interface module 70 can receive instructions from the electronic device through the CMD line and return the result data or execution status to the electronic device through the DATA line.

[0055] In some embodiments, the second interface module 70 can include an output buffer unit 71 and an input buffer unit 72. The output buffer unit 71 can be used to temporarily store data prepared by the host module to be sent to the external device (such as data written to the flash memory module 100). The input buffer unit 72 can be used to temporarily store data received from the external device (such as the electronic device).

[0056] In some embodiments, the data checking module 80 (Error Checking and Correction Unit, ECCU) refers to a module in the memory for detecting and correcting data transmission errors. The data checking module 80 can implement data checking (Error Detection), error correction (Error Correction), data integrity protection, etc. Data checking refers to checking whether errors (such as bit flips) occur in the data during transmission or storage. Error correction refers to automatically repairing data (such as single-bit error correction, multi-bit error detection) if errors are found. Data integrity protection refers to ensuring that the data written / read is consistent with the original data, improving the reliability of the storage system. Since the data checking module 80 needs time to calculate, the data cannot be directly streamed, and the checking buffer unit 81 can be configured in the data checking module 80. The checking buffer unit 81 can be used to temporarily store data to be checked, and avoid waiting for the host module 30 or the flash memory module 100 when calculating the check code or correcting errors.

[0057] In some embodiments, the buffer module 90 can include a write buffer unit 91 and a read buffer unit 92. The write buffer unit 91 and the read buffer unit 92 can be used as a high-speed temporary storage area between the host module 30 and the flash memory module 100, for storing data and instructions frequently accessed by the host module 30. The write buffer unit 91 is mainly to improve the efficiency of data writing and optimize the performance of the write operation. The read buffer unit 92 is mainly to improve the speed of data reading and reduce the access to the flash memory module 100.

[0058] In some embodiments, the flash module 100 can be a physical unit (nand) in the memory for storing data. The flash module 100 can be composed of multiple storage blocks. Each storage block can contain multiple pages. Each page is the minimum unit of read / write operation, while the block is the minimum unit of erase operation. Data is usually read / written in page units, while the entire block needs to be erased when erasing.

[0059] Referring to Figure 1 In some embodiments, in the conventional memory architecture, each buffer unit (such as the random buffer unit 50, the mapping buffer unit 60, the output buffer unit 71, the input buffer unit 72, the check buffer unit 81, the write buffer unit 91, the read buffer unit 92, etc.) is usually statically assigned to a specific functional module, resulting in low resource utilization. For example, the buffer units of some modules can be idle, while the buffer units of other modules are insufficient (such as when the host module 30 is under high load). The memory buffer management unit (MBMU) 110 integrates the originally dispersed buffer units into a unified resource pool through a global scheduling and flexible allocation mechanism, realizing on-demand allocation and load balancing. For example, the memory buffer management unit 110 can dynamically allocate the resources of the buffer units according to the real-time host task demand (such as the high-load module can temporarily occupy the idle buffer units of other modules).

[0060] Referring to Figure 1 and Figure 2 In some embodiments, the host module 30 can be used to receive host tasks issued by external devices. Each buffer unit can correspond to an independent task queue, and the task queue can store the host tasks and related data to be processed. The memory buffer management unit 110 can be used to track the working status of the task queue of each buffer unit. The memory buffer management unit 110 can obtain the working status of the corresponding task queue according to the type of the host task, and allocate the host task according to the working status of the task queue. For example, the memory buffer management unit 110 can allocate write tasks to the write buffer queue. The memory buffer management unit 110 can include a configuration management unit 111, a task queue unit 112, a status management unit 113, a buffer monitoring unit 114, a task allocation unit 115, and an interrupt processing unit 116.

[0061] In some embodiments, the configuration management unit 111 can be used to configure the buffer units, and connect all the buffer units to realize the interaction between different buffer units. Specifically, the configuration management unit 111 can be used to establish a communication link between the buffer units to support cross-buffer unit data interaction (for example, temporarily using the ECC buffer as a write buffer).

[0062] In some embodiments, the task queue unit 112 can be configured to store all the task queues corresponding to the cache units, and the host tasks that are not assigned. Specifically, the task queue unit 112 can be configured to maintain an independent task queue (e.g., a write queue, a read queue, etc.) for each cache unit. The task queue unit 112 can also temporarily store the host tasks that cannot be immediately assigned due to a full state of a certain task queue, and wait for subsequent scheduling.

[0063] In some embodiments, the status management unit 113 can be configured to obtain the working status of the task queues. Specifically, the status management unit 113 can be configured to obtain real-time information (e.g., queue depth, processing progress, etc.) from the task queues of the cache units. The status management unit 113 can also synchronize the real-time information to the cache monitoring unit 114 and the task assignment unit 115.

[0064] In some embodiments, the cache monitoring unit 114 can be configured to monitor the working status of each cache unit and the task queues. Specifically, the cache monitoring unit 114 can monitor how many host tasks in each cache unit are being executed, how much idle capacity in each cache unit can be used to cache other host tasks, the total capacity of each cache unit, etc.

[0065] In some embodiments, the task assignment unit 115 can be configured to determine the working status of the task queues: when the task queues are in an idle state, assign the host tasks to the corresponding task queues according to the types until the task queues are in a full state; when the task queues are in a full state, assign the unassigned host tasks to the task queues of other cache units.

[0066] In some embodiments, the interrupt processing unit 116 can be configured to issue the corresponding interrupt status bit after each cache unit completes each host task, and notify the firmware to perform corresponding processing. Specifically, when a cache unit completes a host task, the corresponding interrupt signal (e.g., "write completion" or "ECC check failure") can be generated. Subsequently, the interrupt processing unit 116 can encode the interrupt type (e.g., success, error, timeout) into the interrupt status bit to notify the firmware to process.

[0067] In some embodiments, when the host module 30 has one CPU core, and a certain task queue is in a full state and cannot assign the remaining unassigned host tasks to the task queue, the task assignment unit 115 can determine the working status of the task queues of other cache units: when there is at least one task queue in an idle state, assign the unassigned host tasks to the same task queue.

[0068] In some embodiments, when the task allocation unit 115 finds that a certain task queue is in a full state (e.g., the write queue cannot receive new host tasks), the task allocation unit 115 can check the task queue state of other cache units (e.g., whether the ECC queue is idle) and allocate the unassigned host tasks to the available queue (e.g., store the write tasks in the ECC queue) for processing. By re-allocating, the host tasks can be immediately allocated to the available queue without waiting, and the idle cache unit (e.g., the ECC queue) can be fully utilized, reducing resource waste.

[0069] In some embodiments, when the task allocation unit 115 allocates unassigned host tasks to the same task queue, the idle capacities of all idle task queues can be sorted to obtain the task queue with the largest idle capacity, and the unassigned host tasks can be allocated to the task queue with the largest idle capacity. Specifically, the task allocation unit 115 can monitor the states of the task queues of all cache units in real time, sort the idle capacities of all idle task queues in descending order to generate a priority list, and then select the task queue with the largest idle capacity as the preferred allocation target. For example, task queue A (remaining 80%), task queue B (remaining 50%), and task queue C (remaining 30%), at which time task queue A can be selected as the preferred allocation target.

[0070] In some embodiments, the task allocation unit 115 can also determine the number of unassigned host tasks and the largest idle capacity: when the number of unassigned host tasks is less than or equal to the largest idle capacity, all unassigned host tasks can be allocated to the task queue with the largest idle capacity; and when the number of unassigned host tasks is greater than the largest idle capacity, part of the unassigned host tasks can be allocated to the task queue with the largest idle capacity until the task queue with the largest idle capacity is in a full state. For example, task queue A (remaining 80%, cacheable 12 host tasks), when the number of unassigned host tasks reaches 20, the first 12 unassigned host tasks can be sequentially allocated to task queue A, and the remaining 8 unassigned host tasks can be temporarily stored in the task queue unit 112 for subsequent processing.

[0071] In some embodiments, when the host module 30 has multiple CPU cores and a certain task queue is in a full state and cannot allocate the remaining unassigned host tasks to the task queue, the task allocation unit 115 can determine the working state of the task queues of other cache units: when at least one task queue is in an idle state, the unassigned host tasks can be allocated to different task queues.

[0072] In some embodiments, when the master module 30 adopts a multi-core CPU design (e.g., a 4-core / 8-core processor), the core challenges faced by the memory include task allocation efficiency, resource contention avoidance, and load balancing. Among them, the task allocation efficiency refers to how to utilize the parallelism of multiple CPU cores to accelerate task scheduling. The resource contention avoidance refers to avoiding conflicts caused by multiple CPU cores operating the same cache unit at the same time. The load balancing refers to ensuring the collaborative work of all multiple CPU cores and cache units. For example, the first CPU core can bind the task queue of the random cache unit 50 and the mapped cache unit 60, and the second CPU core can bind the task queue of the output cache unit 71 and the input cache unit 72.

[0073] In some embodiments, the task allocation unit 115 can adopt a multi-dimensional weighted dynamic allocation algorithm to achieve intelligent load balancing by comprehensively evaluating the static resource capacity and dynamic processing efficiency of the task queue. The multi-dimensional weighted dynamic allocation algorithm can break through the allocation limit of traditional single dimension (such as idle capacity) and ensure the optimal performance of the system in high-throughput and high-concurrency scenarios. Among them, the idle capacity / total capacity can reflect the proportion of the remaining resources of the task queue (space dimension), and the current throughput / average throughput can reflect the processing efficiency of the task queue (time dimension). Specifically, when the task allocation unit 115 allocates unallocated host tasks to different task queues, the task allocation unit 115 can obtain the idle capacity, total capacity, current throughput, and average throughput of the task queue in the idle state. Among them, the current throughput represents the number of host tasks processed by the cache unit in its task queue per unit time, and the average throughput represents the average value of the number of host tasks processed by all cache units in their task queues per unit time.

[0074] In some embodiments, the task allocation unit 115 can calculate the ratio of the idle capacity to the total capacity and the ratio of the current throughput to the average throughput of each idle task queue, denoted as the first ratio and the second ratio, respectively. For example, a certain task queue can be allocated 100 host tasks, at this time, 20 host tasks have been allocated in the task queue, and 80 host tasks can be allocated, so the first ratio can be 0.8. In a unit of time, the task queue can be processed 12 host tasks, and the average value of the host tasks that can be processed by all task queues can be 10, so the second ratio can be 1.2.

[0075] In some embodiments, the task allocation unit 115 can calculate the sum of the product of the first ratio and the corresponding adjustment coefficient and the product of the second ratio and the corresponding adjustment coefficient, denoted as a dynamic weight value. The size of the adjustment coefficient corresponding to the first ratio can be unlimited, for example, it can be 0.6; the size of the adjustment coefficient corresponding to the second ratio can be unlimited, for example, it can be 0.4; wherein the sum of the two adjustment coefficients needs to be set to 1.

[0076] In some embodiments, the task allocation unit 115 can split the unallocated host tasks according to the dynamic weight values of all task queues in the idle state, to obtain multiple groups of task sets; a task set can include at least one unallocated host task. For example, the number of unallocated host tasks is 100, and the dynamic weight values of the task queues in the idle state are 0.8, 0.7, and 0.5 respectively, then the 100 unallocated host tasks need to be split according to the proportion of the dynamic weight values to obtain multiple groups of task sets. The first group of task sets can include 40 host tasks, the second group of task sets can include 35 host tasks, and the third group of task sets can include 25 host tasks.

[0077] In some embodiments, the task allocation unit 115 can allocate the task set to the corresponding task queue in the idle state. Through the multi-dimensional weighted dynamic allocation algorithm, the real-time service capability of each task queue can be quantitatively evaluated to perform task allocation.

[0078] In some embodiments, when the task allocation unit 115 allocates part of the unallocated host tasks to the task queue with the maximum idle capacity, and allocates the task set to the corresponding task queue in the idle state, there can be part of the unallocated host tasks, which can be temporarily stored in the task queue unit 112, at this time, the host tasks temporarily stored in the task queue unit 112 need to be allocated.

[0079] In some embodiments, the task allocation unit 115 can determine the working state of the corresponding task queue according to the task type of the host tasks buffered in the task queue unit 112: when the task queue is in the idle state, the buffered host tasks are sequentially allocated to the corresponding task queue until the task queue is in the full state. By introducing a two-level buffer architecture, the problem of task retention in a high-concurrency scenario is solved. When the first allocation cannot completely consume the tasks, secondary allocation is realized through dynamic state monitoring, ensuring the optimal balance between system throughput and resource utilization.

[0080] As can be seen, the above solution effectively solves the efficiency bottleneck caused by rigid resource allocation in storage systems by breaking the static binding relationship between cache resources and functional modules in traditional storage architectures and constructing a global dynamic scheduling system. This achieves intelligent collaboration of cache resources across modules and tasks, significantly improving overall system performance and resource utilization. Based on real-time task requirements, idle cache resources are automatically and dynamically allocated to high-load modules, eliminating the resource waste caused by uneven workloads in traditional architectures. In single-core scenarios, cache resources are dynamically allocated based on task priority, avoiding resource contention when a single core processes multiple tasks. In multi-core scenarios, linear scalability is achieved through cross-core cache resource sharing and parallel task scheduling.

[0081] The present invention also provides a task allocation method for a memory, which can be applied to the aforementioned memory, and the task allocation method includes:

[0082] Receive host tasks through the main control module;

[0083] The cache management module obtains the working status of the corresponding task queue based on the type of the host task, and allocates host tasks according to the working status of the task queue.

[0084] The host tasks in the corresponding task queue are executed through the cache unit.

[0085] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A memory, characterized in that, include: The main control module is used to receive tasks from the host computer. Multiple cache units are used to execute host tasks in corresponding task queues; each cache unit corresponds to an independent task queue. The cache management module is used to dynamically allocate cache unit resources according to the needs of the host task; The cache management module includes: A configuration management unit is used to configure and manage the cache units so that different cache units can interact. A cache monitoring unit is used to obtain the working status of the corresponding task queue according to the type of the host task. The task allocation unit is used to allocate host tasks according to the working status of the task queue; Task queue units are used to cache unassigned host tasks; When a task queue is fully loaded, the task allocation unit is also used to allocate the unallocated host tasks corresponding to the fully loaded task queue to other idle task queues. When allocating the unallocated host tasks, the task allocation unit is further configured to: obtain the idle capacity, total capacity, current throughput, and average throughput of the idle task queues; wherein, the current throughput represents the number of host tasks processed by a cache unit in its task queue per unit time, and the average throughput represents the average number of host tasks processed by all cache units in their task queues per unit time; calculate the ratio of the idle capacity to the total capacity and the ratio of the current throughput to the average throughput of each idle task queue, denoted as the first ratio and the second ratio, respectively; calculate the sum of the product of the first ratio and the corresponding adjustment coefficient and the product of the second ratio and the corresponding adjustment coefficient, expressed as a dynamic weight value; split the unallocated host tasks according to the dynamic weight values ​​of all idle task queues to obtain multiple task sets; each task set includes at least one unallocated host task; and allocate the task sets to the corresponding idle task queues. When allocating host tasks cached in the task queue unit, the task allocation unit is further configured to: determine the working status of the corresponding task queue based on the task type of the cached host tasks; when the task queue is in an idle state, allocate the cached host tasks to the corresponding task queues in sequence until the task queues are in a full-load state.

2. The memory according to claim 1, characterized in that, The task allocation unit is used to determine the working status of the task queue: when the task queue is idle, the host task is allocated to the corresponding task queue until the task queue is full; when the task queue is full, the unallocated host task is allocated to the task queue of other cache units.

3. The memory according to claim 2, characterized in that, The task allocation unit allocates unallocated host tasks according to the following steps: When the task queue is full, determine the working status of the task queues of other cache units: When at least one task queue is idle, the unassigned host tasks are assigned to the same task queue.

4. The memory according to claim 3, characterized in that, The task allocation unit assigns the unassigned host tasks to the same task queue according to the following steps: Sort all idle task queues by their available capacity and obtain the task queue with the largest available capacity. The unassigned host tasks are assigned to the task queue with the maximum available capacity.

5. The memory according to claim 4, characterized in that, The task allocation unit will allocate the unallocated host tasks according to the following steps: Determine the number of unassigned host tasks and the maximum free capacity: When the number of unassigned host tasks is less than or equal to the maximum free capacity, all the unassigned host tasks are assigned to the task queue with the maximum free capacity. When the number of unassigned host tasks exceeds the maximum free capacity, some of the unassigned host tasks are assigned to the task queue with the maximum free capacity until the task queue with the maximum free capacity is fully loaded.

6. The memory according to claim 2, characterized in that, The task allocation unit allocates the unallocated host tasks according to the following steps: When the task queue of a cache unit is full, determine the working status of the task queues of other cache units: When at least one task queue is idle, the unassigned host tasks are assigned to different task queues.

7. A method for task allocation in a memory, characterized in that, Applied in a memory as described in any one of claims 1 to 6, the memory includes a main control module, a cache management module, and multiple cache units; the task allocation method includes: The main control module receives host tasks. The cache management module obtains the working status of the corresponding task queue according to the type of the host task, and allocates the host task according to the working status of the task queue. The host task in the corresponding task queue is executed through the cache unit.

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