A cache line redirection system
Through the coordinated work of cache and registers, the index offset value is determined based on the address information and index identification of the target request, the number of groups with reference identification in the index range is counted, and the second set of index identification is updated to achieve efficient redirection of cache lines, which solves the problems of low hardware resource utilization efficiency and large latency, and realizes low-latency cache redirection.
Patent Information
- Application Number
- CN202510521453.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-24
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2045-04-24
AI Technical Summary
When there are bad points in the in-chip cache, the prior art cannot effectively redirect without increasing hardware costs, resulting in low hardware resource utilization efficiency and large transmission delay and bandwidth consumption across cache levels.
Through the cooperation of cache, group identification registers and range identification registers, the index offset value is determined based on the address information and index identification of the target request, the number of groups with reference identification in the index range is counted, and the second set of index identifications is updated to achieve redirection and avoid cross-level transmission.
Without increasing hardware costs, the efficiency of cache redirection is improved, the redirection delay is reduced, and the existing cache structure is efficiently utilized.
Smart Images
Figure CN120045471B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of storage management, and particularly to a cache line redirection system. Background Art
[0002] When there are bad points in the tag array or data array in the on-chip cache (Cache), and they cannot be repaired using the Error-Correcting Code (ECC) algorithm, it will cause the entire cache, and even the entire chip, to become unusable. The reason is that it is difficult to determine which specific request will be allocated to the damaged group in the cache.
[0003] In response to the above problems, various processing methods have been proposed in the prior art. One processing method is to increase redundant cache lines. The redundant cache lines are initially in an idle state. When a request is allocated to a damaged group, it is redirected to the redundant cache lines. However, this method increases the hardware cost of the cache and reduces the utilization efficiency of hardware resources. Another processing method is that in a multi-level cache scenario, when a request is allocated to a damaged group, it is redirected to cache lines at other levels. However, this method will introduce delays and bandwidth consumption caused by cross-cache level data transmission, reducing the efficiency of data access. Another processing method is to change the page table to change the physical address of the request when the request is allocated to a damaged group. However, this method requires a large number of complex operations at the operating system or software level and will also introduce a large amount of additional delay. Another processing method is to back up the data to a secure storage area before it is stored in the cache line. When the request is allocated to a damaged group, the software restores the data from the backup area to a new cache line. However, this method also increases the hardware cost of the cache and reduces the utilization efficiency of hardware resources.
[0004] Therefore, how to improve the efficiency of cache redirection without increasing the hardware cost has become an urgent problem to be solved. Summary of the Invention
[0005] In response to the above technical problems, the technical solution adopted by the present invention is as follows:
[0006] A cache line redirection system, the system includes: a cache, a group identification register, a range identification register, a processor, and a memory storing a computer program. Among them, the cache includes M groups, each group contains N ways, and both M and N are integers greater than one. The range identification register is configured with a range identification value. When the computer program is executed by the processor, the following steps are implemented:
[0007] S101, obtain the groups in the cache that need to be redirected, and record the group identifications corresponding to each group to be redirected as reference identifications in the group identification register.
[0008] S102. Obtain a target request and determine a first set of index identifiers according to the address information corresponding to the target request.
[0009] S103. If there is a reference identifier in the group identifier register that is the same as the first set of index identifiers, execute step S104; otherwise, execute step S109.
[0010] S104. Determine an index offset value according to the address information corresponding to the target request and the range identifier value in the range identifier register.
[0011] S105. Determine a second set of index identifiers according to the address information corresponding to the target request, the first set of index identifiers, and the index offset value.
[0012] S106. Determine an index range according to the first set of index identifiers and the second set of index identifiers.
[0013] S107. Count the number P of all groups corresponding to reference identifiers in the index range.
[0014] S108. Update the second set of index identifiers according to P and execute step S110.
[0015] S109. Determine the first set of index identifiers as the second set of index identifiers.
[0016] S110. Determine the redirection result corresponding to the target request according to the second set of index identifiers.
[0017] Compared with the prior art, the present invention has obvious beneficial effects. By means of the above technical solutions, a cache line redirection system provided by the present invention can achieve quite remarkable technical progressiveness and practicality, and has wide industrial utilization value. It has at least the following beneficial effects:
[0018] The present invention provides a cache line redirection system, which includes a cache, a group identification register, a range identification register, a processor, and a memory storing a computer program. Wherein, the cache includes M groups, each group contains N ways, and both M and N are integers greater than one. The range identification register is configured with a range identification value. When the computer program is executed by the processor, the following steps are implemented: S101, obtain the groups in the cache that need to be redirected, and record the group identification corresponding to each redirected group as a reference identification in the group identification register; S102, obtain a target request, and determine a first group index identification according to the address information corresponding to the target request; S103, if there is a reference identification in the group identification register that is the same as the first group index identification, then execute step S104, otherwise, execute step S109; S104, determine an index offset value according to the address information corresponding to the target request and the range identification value in the range identification register; S105, determine a second group index identification according to the address information corresponding to the target request, the first group index identification, and the index offset value; S106, determine an index range according to the first group index identification and the second group index identification; S107, count the number P of all groups corresponding to the reference identification in the index range; S108, update the second group index identification according to P, and execute step S110; S109, determine the first group index identification as the second group index identification; S110, determine the redirection result corresponding to the target request according to the second group index identification.
[0019] It can be seen that according to the address information corresponding to the target request and the range identification value in the range identification register, an index offset value is determined. Then, according to the address information corresponding to the target request, the first group index identification, and the index offset value, a second group index identification is determined, and the number of all groups corresponding to the reference identification in the index range is counted to update the second group index identification, so as to determine the redirection result. This can efficiently utilize the existing cache structure, without increasing additional hardware costs, and perform redirection at the same cache level, with a lower redirection latency, improving the efficiency of cache redirection. Description of the Drawings
[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0021] Figure 1 It is a schematic flowchart of the process when the computer program in a cache line redirection system provided by an embodiment of the present invention is executed by a processor. Detailed Embodiments
[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.
[0023] This embodiment provides a cache line redirection system. Refer to Figure 1 , which is a schematic flowchart of a computer program executed by a processor in a cache line redirection system provided by an embodiment of the present invention. The system includes: a cache, a set identification register, a range identification register, a processor, and a memory storing a computer program. Among them, the cache includes M sets, each set contains N ways, and both M and N are integers greater than one. The range identification register is configured with a range identification value. When the computer program is executed by the processor, the following steps are implemented:
[0024] S101, obtain the set to be redirected in the cache, and record the set identification corresponding to each set to be redirected as a reference identification in the set identification register;
[0025] S102, obtain a target request, and determine a first set index identification according to the address information corresponding to the target request;
[0026] S103, if there is a reference identification in the set identification register that is the same as the first set index identification, execute step S104; otherwise, execute step S109;
[0027] S104, determine an index offset value according to the address information corresponding to the target request and the range identification value in the range identification register;
[0028] S105, determine a second set index identification according to the address information corresponding to the target request, the first set index identification, and the index offset value;
[0029] S106, determine an index range according to the first set index identification and the second set index identification;
[0030] S107, count the number P of all sets corresponding to the reference identification in the index range;
[0031] S108, update the second set index identification according to P, and execute step S110;
[0032] S109, determine the first set index identification as the second set index identification;
[0033] S110. Determine the redirection result corresponding to the target request according to the second set of index identifiers.
[0034] Among them, the cache can be located in the chip. Usually, the chip can include multiple levels of caches, such as L1 cache, L2 cache, L3 cache, etc. In this embodiment, the cache line redirection is performed with a single cache as the object, and the processing of different levels of caches is not involved. Therefore, only a single cache is used as the object for description, and the cache described in this embodiment can belong to any cache level.
[0035] The cache is divided into multiple groups. The group is used to determine the location range of data storage, and the way can be used to determine the cache line within a single group.
[0036] The range identification value can be used to determine the redirection offset range. The group identification register can be used to record the group to be redirected by referring to the identifier. The group identification register can include several sub-registers, and each sub-register records a reference identifier. Correspondingly, when determining whether there is a reference identifier in the group identification register that is the same as the first set of index identifiers, the first set of index identifiers is compared with the reference identifiers corresponding to each sub-register respectively.
[0037] The first set of index identifiers can refer to the group index determined based on the address information corresponding to the target request. If there is no corresponding reference identifier for the first set of index identifiers, it means that the group corresponding to the first set of index identifiers is not damaged and does not need to be redirected. Therefore, step S109 can be executed. Otherwise, redirection processing needs to be performed, that is, steps S104 to S108.
[0038] The index offset value can determine the second set of index identifiers. The second set of index identifiers is used to indicate which group near the group corresponding to the first set of index identifiers is redirected to. The index range can refer to the groups covered between the first set of index identifiers and the second set of index identifiers.
[0039] It should be noted that this embodiment describes the group to be redirected in the cache. The group to be redirected usually refers to the damaged group. However, in the actual application process, if the implementer needs some groups to perform special functions and does not want these groups to be replaced, the group identifiers corresponding to these groups can also be recorded as reference identifiers in the group identification register.
[0040] In a specific implementation manner, step S101 includes the following steps:
[0041] S1011. Obtain the damaged groups in the cache during the factory test as the groups to be redirected, and use the group identifiers corresponding to each group to be redirected as reference identifiers;
[0042] S1012. For any group in the cache, obtain the corruption flag bit information of the first return data corresponding to each historical request after the group sends several historical requests to a lower-level object during a historical time period.
[0043] S1013. If the corruption flag bit information of the first return data corresponding to any historical request is a first preset value, obtain the verification information of the second return data returned by the group to a higher-level object corresponding to the historical request.
[0044] S1014. Count the number A of historical requests with verification information indicating verification errors.
[0045] S1015. If A is greater than a preset quantity threshold, determine that the group is a damaged group, determine that the group is a group to be redirected, and use the group identifier corresponding to the group as a reference identifier.
[0046] Among them, in the chip factory test session, groups with bad points in the cache can be detected. However, there will also be groups to be redirected that are damaged only during the chip usage session.
[0047] The historical time period can refer to the time period determined from a historical time point to the current time point. The historical time point can be set by the implementer himself. The historical request can refer to a request whose group index corresponding to the address information during the historical time period is the group. According to the level of the cache, its lower-level object can be a lower-level cache or memory, and its higher-level object can be a higher-level cache or a core unit.
[0048] The corruption flag bit information can refer to the ECC flag bit. The corruption flag bit information is carried by the first return data. The first preset value can be 0. When the corruption flag bit information of the first return data corresponding to a historical request is the first preset value, it can indicate that the first return data is not damaged. Otherwise, it can indicate that the first return data is damaged.
[0049] The verification information can refer to the verification result of the second return data. The verification information includes verification error and verification correct. In this embodiment, only historical requests with the first return data not damaged are used for counting verification information, and historical requests with verification information indicating verification errors are counted. Such historical requests can be considered as errors in the group. To avoid misjudgment, a preset quantity threshold is set in this embodiment to determine whether the group is a damaged group, that is, to determine whether the group is a group to be redirected.
[0050] In an implementation manner, the number E of consecutive historical requests with verification information indicating verification errors can also be counted. According to the comparison result between E and the preset quantity threshold, determine whether the group is a group to be redirected. Correspondingly, the implementer can adjust the value of the preset quantity threshold according to the actual situation.
[0051] In a specific embodiment, step S104 includes the following steps:
[0052] S1041, when the range identification value C in the range identification register is 0, determine that the index offset value is 1;
[0053] S1042, when the range identification value C in the range identification register is greater than 0, determine the termination bit identification B2 according to the preset start bit identification B1 and the range identification value C in the range identification register;
[0054] S1043, determine the index offset value from the address segment of the B1th bit to the B2th bit in the address information corresponding to the target request.
[0055] Wherein, B2 = B1 + C - 1, and when C = 0, the index offset value is 1.
[0056] When C = 1, B2 = B1, and the index offset value is determined by adding 1 to the corresponding value of the address of the B1th bit in the address information; when C = 2, B2 = B1 + 1, and the index offset value is determined by adding 1 to the corresponding value of the address segment of the B1th bit to the B2th bit in the address information; when C = 3, B2 = B1 + 2, and the index offset value is determined by adding 1 to the corresponding value of the address segment of the B1th bit to the B2th bit in the address information, and so on.
[0057] For example, when C = 2 and B1 = 1, the index offset value is determined by adding 1 to the corresponding value of the address segment of the 1st bit to the 2nd bit in the address information; when C = 3 and B1 = 1, the index offset value is determined by adding 1 to the corresponding value of the address segment of the 1st bit to the 3rd bit in the address information.
[0058] In a specific embodiment, step S105 includes the following steps:
[0059] S1051, determine the Dth bit as the direction identification value from the address information corresponding to the target request according to the preset reference bit identification D;
[0060] S1052, when the direction identification value is 0, subtract the first group of index identifications from the index offset value to obtain a first intermediate index;
[0061] S1053, if the first intermediate index is less than 0, use the sum of the first intermediate index and M as the second group of index identifications, otherwise, use the first intermediate index as the second group of index identifications;
[0062] S1054, when the direction identification value is 1, add the first group of index identifications to the index offset value to obtain a second intermediate index;
[0063] S1055. If the second intermediate index is greater than or equal to M, then use the difference between the second intermediate index and M as the second group index identifier; otherwise, use the second intermediate index as the second group index identifier.
[0064] Among them, the direction identification value can be used to represent whether the first group index identifier is offset in the positive direction or the negative direction.
[0065] Specifically, in this embodiment, the index identifier range corresponding to each group is [0, M - 1]. When exceeding this index identifier range, correction is required to ensure that there is a corresponding group for the second group index identifier.
[0066] In a specific implementation manner, step S106 includes the following steps:
[0067] S1061. If the direction identification value is 0 and the first intermediate index is less than 0, then use 0 to the first group index identifier as the first sub - range, and use the second group index identifier to M - 1 as the second sub - range. The index range is formed by the first sub - range and the second sub - range.
[0068] S1062. If the direction identification value is 1 and the second intermediate index is greater than or equal to M, then use the first group index identifier to M - 1 as the third sub - range, and use 0 to the second group index identifier as the fourth sub - range. The index range is formed by the third sub - range and the fourth sub - range.
[0069] S1063. If the direction identification value is 0 and the first intermediate index is greater than or equal to 0, then use the second group index identifier to the first group index identifier as the index range.
[0070] S1064. If the direction identification value is 1 and the second intermediate index is less than M, then use the first group index identifier to the second group index identifier as the index range.
[0071] Among them, in order to avoid the second group index identifier corresponding to the group to be redirected, the index range is determined for subsequent update of the second group index identifier.
[0072] In a specific implementation manner, step S108 includes the following steps:
[0073] S1081. Add P and the second group index identifier, and update the second group index identifier with the addition result.
[0074] S1082. If the updated second group index identifier is greater than or equal to M, then update the second group index identifier again with the difference between the updated second group index identifier and M.
[0075] S1083. Otherwise, do not update the updated second group of index identifiers again.
[0076] In a specific embodiment, step S110 includes the following steps:
[0077] S1101. According to the second group of index identifiers and a preset cache replacement algorithm, determine the path corresponding to the target request from the group corresponding to the second group of index identifiers as the redirection result, where the redirection result is used to store the data corresponding to the target request and the request identifier information.
[0078] Among them, the cache replacement algorithm can refer to the least recently used algorithm, the least recently used algorithm, the first-in first-out algorithm, etc. After determining the group corresponding to the second group of index identifiers, according to the cache replacement algorithm, determine the path corresponding to the target request from the group corresponding to the second group of index identifiers as the redirection result, that is, determine the corresponding cache line as the redirection result.
[0079] The request identifier information can be used to determine the request corresponding to the data in the corresponding cache line.
[0080] In a specific embodiment, the address information corresponding to the target request includes a first address segment and a second address segment;
[0081] The request identifier information includes the first address segment and the second address segment in the address information corresponding to the target request.
[0082] Among them, in the prior art, if the address mapping method is used to process the address information to obtain the group index, the second address segments corresponding to the same group are the same, then only the first address segment needs to be stored. However, if the hash calculation method is used to process the address information to obtain the group index, then the first address segment and the second address segment need to be stored.
[0083] However, in the redirection scenario, the second address segments corresponding to the same group may be different, that is, it may be directly located to the group, or it may be redirected to the group. In order to effectively record the request corresponding to the data in the cache line, different from the prior art where only the first address segment is stored when using the address mapping method to process the address information to obtain the group index, in this embodiment, regardless of the method of obtaining the group index by processing the address information, the request identifier information includes the first address segment and the second address segment in the address information corresponding to the target request.
[0084] It can be seen that in this embodiment, according to the address information corresponding to the target request and the range identification value in the range identification register, the index offset value is determined. Then, according to the address information corresponding to the target request, the first set of index identifiers, and the index offset value, the second set of index identifiers is determined, and the number of all groups corresponding to the reference identifiers in the index range is counted to update the second set of index identifiers, thereby determining the redirection result. This can efficiently utilize the existing cache structure, without adding additional hardware costs, and perform redirection at the same cache level, with a lower redirection latency, improving the efficiency of cache redirection.
[0085] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and not for limiting the scope of the present invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.
Claims
1. A cache line redirection system, characterized in that The system includes: a cache, a group identification register, a range identification register, a processor, and a memory storing a computer program, wherein the cache includes M groups, each group contains N ways, and both M and N are integers greater than one. The range identification register is configured with a range identification value, and the range identification value is used to determine the redirection offset range. When the computer program is executed by the processor, the following steps are implemented: S101. Obtain the groups to be redirected in the cache, and record the group identifications corresponding to the groups to be redirected as reference identifications in the group identification register; S102. Obtain a target request, and determine a first group index identification according to the address information corresponding to the target request; S103. If there is a reference identification in the group identification register that is the same as the first group index identification, execute step S104; otherwise, execute step S109; S104. Determine an index offset value corresponding to the first group index identification according to the address information corresponding to the target request and the range identification value in the range identification register. Wherein, step S104 includes the following steps: S1041. When the range identification value C in the range identification register is 0, determine that the index offset value is 1; S1042. When the range identification value C in the range identification register is greater than 0, determine a termination bit identification B2 according to a preset start bit identification B1 and the range identification value C in the range identification register; S1043. Determine the index offset value from the address segment of the B1-th bit to the B2-th bit in the address information corresponding to the target request; S105. Determine a second group index identification according to the address information corresponding to the target request, the first group index identification, and the index offset value; S106. Determine an index range according to the first group index identification and the second group index identification; S107. Count the number P of all groups corresponding to reference identifications in the index range; S108. Update the second group index identification according to P, and execute step S110; S109. Determine the first group index identification as the second group index identification; S110. Determine the redirection result corresponding to the target request according to the second group index identification.
2. The cache line redirection system according to claim 1, wherein Step S101 includes the following steps: S1011. Obtain the groups with damage in the cache during factory testing as the groups to be redirected, and use the group identifications corresponding to the groups to be redirected as reference identifications; S1012. For any group in the cache, obtain the damage flag bit information of the first return data corresponding to each historical request after the group sends several historical requests to a lower-level object during a historical time period, wherein the lower-level object is a lower-level cache or a memory; S1013. If the damage flag bit information of the first return data corresponding to any historical request is a first preset value, obtain the verification information of the second return data returned by the group to a higher-level object corresponding to the historical request, wherein the higher-level object is a higher-level cache or a core unit; S1014, count the number A of historical requests with verification errors in all verification information; S1015, if A is greater than a preset quantity threshold, determine that this group is a damaged group, determine that this group is a group to be redirected, and use the group identifier corresponding to this group as a reference identifier.
3. The cache line redirection system according to claim 1, wherein Step S105 includes the following steps: S1051, according to a preset reference bit identifier D, determine the D-th bit from the address information corresponding to the target request as a direction identifier value; S1052, when the direction identifier value is 0, subtract the first group index identifier from the index offset value to obtain a first intermediate index; S1053, if the first intermediate index is less than 0, use the sum of the first intermediate index and M as the second group index identifier, otherwise, use the first intermediate index as the second group index identifier; S1054, when the direction identifier value is 1, add the first group index identifier to the index offset value to obtain a second intermediate index; S1055, if the second intermediate index is greater than or equal to M, use the difference between the second intermediate index and M as the second group index identifier, otherwise, use the second intermediate index as the second group index identifier.
4. The cache line redirection system according to claim 3, wherein Step S106 includes the following steps: S1061, if the direction identifier value is 0 and the first intermediate index is less than 0, use 0 to the first group index identifier as a first sub-range, use the second group index identifier to M - 1 as a second sub-range, and form the index range from the first sub-range and the second sub-range; S1062, if the direction identifier value is 1 and the second intermediate index is greater than or equal to M, use the first group index identifier to M - 1 as a third sub-range, use 0 to the second group index identifier as a fourth sub-range, and form the index range from the third sub-range and the fourth sub-range; S1063, if the direction identifier value is 0 and the first intermediate index is greater than or equal to 0, use the second group index identifier to the first group index identifier as the index range; S1064, if the direction identifier value is 1 and the second intermediate index is less than M, use the first group index identifier to the second group index identifier as the index range.
5. The cache line redirection system according to claim 2, wherein Step S108 includes the following steps: S1081, add P to the second group index identifier, and update the second group index identifier with the addition result; S1082, if the updated second group index identifier is greater than or equal to M, update the second group index identifier again with the difference between the updated second group index identifier and M; S1083, otherwise, do not update the updated second group index identifier again.
6. The cache line redirection system according to claim 1, wherein Step S110 includes the following steps: S1101, according to the second group index identifier and a preset cache replacement algorithm, determine the path corresponding to the target request from the group corresponding to the second group index identifier as the redirection result, and the redirection result is used to store the data and request identifier information corresponding to the target request.
7. The cache line redirection system according to claim 6, wherein The address information corresponding to the target request includes a first address segment and a second address segment; The request identification information includes a first address segment and a second address segment in the address information corresponding to the target request.
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