Apb-based peripheral access system, access method, storage medium and chip

Abstract

The application discloses an APB-based peripheral access system and method, a storage medium and a chip, and belongs to the chip technical field. A Cross-Bar forwards an access request of a target host to a target APB DEMUX; the target APB DEMUX converts the access request into a shared signal and a PSEL signal and a PENABLE signal of each peripheral, sends the shared signal to a gating unit of each peripheral, and sends the PSEL signal and the PENABLE signal of each peripheral to the peripheral; the gating unit sends the shared signal to a target peripheral when the corresponding peripheral is the target peripheral; the gating unit masks the shared signal when the corresponding peripheral is not the target peripheral; and the target peripheral communicates with the target host according to the PSEL signal, the PENABLE signal and the shared signal. The application can avoid unnecessary flip-flops of a combination logic unit in a non-target peripheral caused by a shared signal flip-flop, and can save power consumption.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a peripheral access system, access method, storage medium and chip based on APB. Background Technology

[0002] Advanced Peripheral Bus (APB) peripherals have an internal configuration register array. The host reads and writes configuration registers through the APB bus to complete information exchange between the processor and the peripheral. For example... Figure 1 As shown, the information exchange between multiple hosts and multiple peripherals is mainly achieved using a cascaded method of cross-bar and APB demultiplexer (DEMUX). Specifically, APB DEMUX decodes and splits a set of APB buses into multiple sets of APB buses according to specific address blocks to realize time-division multiplexing control and interaction between the host and peripherals. This reduces the design complexity of cross-bar and achieves a balance between area and performance.

[0003] like Figure 2 As shown, the address decoding unit in APB DEMUX obtains the host's access requirements for different peripherals, generates different PSEL and PENABLE signals for different peripherals based on the address decoding results generated by the access requirements, and shares other signals (such as PADDR, PWDATA, etc.) with all peripherals except for PSEL and PENABLE signals.

[0004] While sharing a common access path among multiple peripherals via time-division multiplexing can effectively reduce the design complexity of a cross-bar, it can introduce a broadcast effect on shared signals (such as PADDR and PWDATA). For example, when the host writes data 0x55 to address 0xaa of peripheral 1, even though the host is not accessing other peripherals at that moment, because these shared signals are shared, other peripherals can still see the shared signal toggling (except for PSEL and PENABLE). This toggling of shared signals leads to unnecessary power consumption by the peripherals. Summary of the Invention

[0005] This application provides a peripheral access system, access method, storage medium, and chip based on APB, to solve the problem that when a host accesses peripherals through APB DEMUX, other peripherals besides the accessed peripheral are affected by the toggling shared signal, resulting in unnecessary power consumption waste. The technical solution is as follows:

[0006] According to a first aspect of this application, an APB-based peripheral access system is provided, the peripheral access system including multiple hosts, a cross-bar switch matrix and at least one peripheral access group, the peripheral access group including an APB demultiplexer DEMUX and at least one peripheral;

[0007] Each host is connected to one input of the Cross-Bar, and each output of the Cross-Bar is connected to the address decoding unit of the APB DEMUX in a peripheral access group. The address decoding unit is connected to a peripheral in the same group through each gating unit.

[0008] The target host is used to send an access request to the target peripheral device to the Cross-Bar;

[0009] The Cross-Bar is used to determine the target APB DEMUX corresponding to the target peripheral based on the access request, and forward the access request to the target APB DEMUX through the APB bus;

[0010] The target APB DEMUX is used to convert the access request into a shared signal and the PSEL and PENABLE signals of each peripheral through the address decoding unit, send the shared signal to the gating unit of each peripheral, and send the PSEL and PENABLE signals of each peripheral to the corresponding peripheral; wherein, the PSEL and PENABLE signals corresponding to the target peripheral are high-level signals, and the PSEL and PENABLE signals corresponding to other peripherals are low-level signals;

[0011] Each gating unit is used to send the shared signal to the target peripheral when the corresponding peripheral is the target peripheral; and to shield the shared signal from the peripheral when the corresponding peripheral is not the target peripheral.

[0012] The target peripheral is used to communicate with the target host based on the PSEL signal, the PENABLE signal, and the sharing signal.

[0013] In one possible implementation, the target APB DEMUX is further configured to send a control signal to each gating unit, the control signal being either the PSEL signal or the PENABLE signal;

[0014] The gating unit is used to send the shared signal to the target peripheral when the control signal is a high-level signal, and to shield the shared signal from the peripheral when the control signal is a low-level signal.

[0015] In one possible implementation, the gating unit is located in the APB DEMUX, and the address decoding unit in an APB DEMUX is connected to each gating unit in the same group, and each gating unit is connected to a corresponding peripheral.

[0016] In one possible implementation, where the gating unit is located within the peripheral, an address decoding unit in an APB DEMUX is connected to the gating unit in each peripheral in the same group.

[0017] In one possible implementation, the peripheral device further includes a configuration register array, each configuration register being connected to a combinational logic unit, and each combinational logic unit being connected to a corresponding gating unit and the address decoding unit;

[0018] The gating unit is used to send the shared signal to the combinational logic unit corresponding to the target peripheral;

[0019] The address decoding unit is used to send the PSEL signal and the PENABLE signal to the combinational logic unit corresponding to the target peripheral.

[0020] The combinational logic unit is used to perform logical operations on the PSEL signal, the PENABLE signal and the shared signal, and send the operation results to the corresponding configuration register for corresponding read and write operations, so as to realize the communication between the target peripheral and the target host.

[0021] According to a second aspect of this application, an APB-based peripheral access method is provided for use in the peripheral access system described above, the method comprising:

[0022] The target host sends an access request to the target peripheral device to the Cross-Bar;

[0023] The Cross-Bar determines the target APB DEMUX corresponding to the target peripheral based on the access request, and forwards the access request to the target APB DEMUX through the APB bus;

[0024] The target APB DEMUX converts the access request into a shared signal and the PSEL and PENABLE signals of each peripheral through the address decoding unit. The shared signal is sent to the gating unit of each peripheral, and the PSEL and PENABLE signals of each peripheral are sent to the corresponding peripheral. The PSEL and PENABLE signals of the target peripheral are high-level signals, while the PSEL and PENABLE signals of other peripherals are low-level signals.

[0025] Each gating unit sends the shared signal to the target peripheral when the corresponding peripheral is the target peripheral; and blocks the shared signal to the peripheral when the corresponding peripheral is not the target peripheral.

[0026] The target peripheral communicates with the host based on the PSEL signal, the PENABLE signal, and the sharing signal.

[0027] In one possible implementation, the method further includes: the target APB DEMUX sending a control signal to each gating unit, the control signal being either the PSEL signal or the PENABLE signal;

[0028] Each gating unit sends the shared signal to the target peripheral when the corresponding peripheral is the target peripheral; and blocks the shared signal from the peripheral when the corresponding peripheral is not the target peripheral, including:

[0029] Each gating unit sends the shared signal to the target peripheral when the control signal is high; and blocks the shared signal from the peripheral when the control signal is low.

[0030] In one possible implementation, the method further includes:

[0031] When the peripheral device also includes a configuration register array, the gating unit sends the shared signal to the combinational logic unit corresponding to the target peripheral device;

[0032] The address decoding unit sends the PSEL signal and the PENABLE signal to the combinational logic unit corresponding to the target peripheral.

[0033] The combinational logic unit performs logical operations on the PSEL signal, the PENABLE signal, and the shared signal, and sends the operation results to the corresponding configuration registers for corresponding read and write operations, so as to realize the communication between the target peripheral and the target host.

[0034] According to a third aspect of this application, a computer-readable storage medium is provided, wherein at least one instruction is stored therein, the at least one instruction being loaded and executed by a processor to implement the APB-based peripheral access method as described above.

[0035] According to a fourth aspect of this application, a chip is provided that includes the aforementioned APB-based peripheral access system.

[0036] The beneficial effects of the technical solution provided in this application include at least the following:

[0037] By setting a gating unit between the APB DEMUX and each peripheral, the transmission of shared signals can be controlled by the gating unit. That is, when the peripheral is a target peripheral that the target host needs to access, the gating unit controls the shared signals to be visible to the peripheral; when the peripheral is not a target peripheral that the target host needs to access, the gating unit controls the shared signals to be invisible to the peripheral. This can avoid unnecessary switching of combinational logic units in non-target peripherals due to the switching of shared signals, thereby saving power consumption. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram illustrating a peripheral access structure based on APB, according to relevant technologies.

[0040] Figure 2 This is a schematic diagram illustrating the connection between an APB DEMUX and a peripheral device, based on relevant technologies.

[0041] Figure 3 This is a schematic diagram illustrating the connection of a register array and combinational logic unit in a peripheral device, based on relevant technologies.

[0042] Figure 4 This is a structural diagram of a peripheral access system based on APB provided in one embodiment of this application;

[0043] Figure 5 This is a schematic diagram illustrating the connection between an APB DEMUX and a peripheral device according to one embodiment of this application;

[0044] Figure 6 This is a schematic diagram illustrating the connection of a configuration register array and combinational logic unit in a peripheral device according to one embodiment of this application;

[0045] Figure 7 This is a flowchart of an APB-based peripheral access method provided in one embodiment of this application. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0047] The APB DEMUX connects to multiple peripherals, each containing a configuration register array. This array includes multiple configuration registers, which the host can access via the APB bus. Each configuration register's D pin is connected to a corresponding combinational logic unit, which includes combinations of logic devices such as AND gates, NOT gates, and OR gates. The appropriate combinational logic unit can be designed to meet the specific needs of each configuration register.

[0048] like Figure 3 As shown, a combinational logic unit including comb1 and comb2 is used as an example. Shared signals (such as PADDR / PWDATA / PWRITE / PSTRB / PPROT / PUSER, etc.) are input to comb1, while the PSEL and PENABLE signals are input to comb2. When the shared signal toggles, but the PSEL and PENABLE signals do not, comb1 will still perform logic operations on the shared signal, causing unnecessary toggling of the combinational logic unit and resulting in wasted power.

[0049] The PSEL (Peripheral Select) signal is the peripheral selection signal, which can be used to activate the peripheral. The PENABLE signal is the enable signal, notifying the peripheral to begin data transmission. Shared signals are a set of signals shared by multiple peripherals, and may include, but are not limited to: PADDR, PWDATA, PWRITE, PSTRB, PPROT, and PUSER. PADDR is the address signal, PWDATA is the write data signal, PWRITE is the write signal, PSTRB is the write pulse signal, PPROT is the protection type signal, and PUSER is a user-defined signal. In practical applications, the types of shared signals can be added or removed as needed; this embodiment does not impose any limitations.

[0050] To address this technical problem, this application adds a gating unit between the APB DEMUX and each peripheral device. The gating unit determines whether to shield the shared signal from the peripheral device. Specifically, when the host accesses a peripheral device, the gating unit removes the shielding from that peripheral device, making the shared signal visible to it. For other peripheral devices that are not accessed, the gating unit shields them, making the shared signal invisible to them.

[0051] like Figure 4The diagram illustrates a structural block diagram of an APB-based peripheral access system according to an embodiment of this application. The APB-based peripheral access system includes: multiple hosts 410, a Cross-Bar 420, and at least one peripheral access group 430. Each peripheral access group 430 includes an APB DEMUX 431 and at least one peripheral 432. The number of peripherals 432 in each peripheral access group 430 can be the same or different.

[0052] In this embodiment, each host 410 is connected to one input terminal of Cross-Bar 420, and each output terminal of Cross-Bar 420 is connected to the address decoding unit of APB DEMUX 431 in a peripheral access group 430. The address decoding unit is connected to a peripheral 432 in the same group through each gating unit.

[0053] In one implementation, the gating unit is located in the APB DEMUX431. An address decoding unit in the APB DEMUX431 is connected to each gating unit in the same group, and each gating unit is connected to a corresponding peripheral 432. For example... Figure 4 As shown, if a peripheral access group 430 includes m peripherals, then the APB DEMUX431 includes m gating units, and the address decoding unit is connected to each of the m gating units; if another peripheral access group 430 includes n peripherals, then the APB DEMUX431 includes n gating units, and the address decoding unit is connected to each of the n gating units.

[0054] like Figure 5 As shown, a peripheral access group 430 includes an APB DEMUX431 and three peripherals 432. The address decoding unit in the APB DEMUX431 is connected to the three gating units respectively. The gating unit of peripheral 1 is connected to peripheral 1, the gating unit of peripheral 2 is connected to peripheral 2, and the gating unit of peripheral 3 is connected to peripheral 3.

[0055] In another implementation, the gating unit is located in peripheral 432, and the address decoding unit in one APB DEMUX431 is connected to the gating unit in each peripheral 432 in the same group. That is, each peripheral 432 contains one gating unit, and the address decoding unit in the APB DEMUX431 is connected to the gating unit in each peripheral 432. Figure 4 Not shown in the image.

[0056] The following describes the access process for the peripheral access system.

[0057] (1) The target host 410 is used to send an access request to the target peripheral 432 to the Cross-Bar 420.

[0058] Each host 410 communicates with the Cross-Bar 420 via an Advanced eXtensible Interface (AXI) or an Advanced High-performance Bus (AHB).

[0059] In this embodiment, the host that accesses the peripheral is called the target host, and the peripheral to be accessed is called the target peripheral. The target host 410 can generate an access request based on the address of the target peripheral 432 and its read / write requirements, and send the access request to the Cross-Bar 420 through the AXI bus or AHB bus.

[0060] (2) Cross-Bar420 is used to determine the target APB DEMUX431 corresponding to the target peripheral 432 according to the access request, and forwards the access request to the target APB DEMUX431 through the APB bus.

[0061] Cross-Bar420 communicates with each APB DEMUX431 via the APB bus.

[0062] In this embodiment, the APB DEMUX corresponding to the target peripheral is referred to as the target APB DEMUX. Cross-Bar 420 can determine the target APB DEMUX 431 corresponding to the target peripheral 432 and send the access request to the target APB DEMUX 431 through the APB bus.

[0063] (3) The target APB DEMUX431 is used to convert the access request into a shared signal and the PSEL and PENABLE signals of each peripheral 432 through the address decoding unit, send the shared signal to the gating unit of each peripheral 432, and send the PSEL and PENABLE signals of each peripheral 432 to the corresponding peripheral 432; wherein, the PSEL and PENABLE signals corresponding to the target peripheral 432 are high-level signals, and the PSEL and PENABLE signals corresponding to other peripherals 432 are low-level signals.

[0064] In this embodiment, each peripheral 432 in a peripheral access group 430 corresponds to a set of PSEL and PENABLE signals, and all peripherals 432 correspond to a set of shared signals. For example... Figure 5As shown, peripheral 1 corresponds to psel_out[0] and penable_out[0], peripheral 2 corresponds to psel_out[1] and penable_out[1], peripheral 3 corresponds to psel_out[2] and penable_out[2], and peripherals 1-3 all correspond to pwrite[31:0] and paddr[31:0].

[0065] Assuming that the target peripheral 432 that the target host 410 needs to access is peripheral 1, then psel_out[0] and penable_out[0] are high-level signals, and psel_out[1] and penable_out[1], psel_out[2] and penable_out[2] are low-level signals.

[0066] (4) Each gate unit is used to send a shared signal to the target peripheral 432 when the corresponding peripheral 432 is the target peripheral 432; and to shield the shared signal to the peripheral 432 when the corresponding peripheral 432 is not the target peripheral 432.

[0067] In this embodiment, the gating unit can be controlled by a control signal. Specifically, the target APB DEMUX431 is also used to send a control signal to each gating unit, where the control signal is a PSEL signal or a PENABLE signal; the gating unit is used to send a shared signal to the target peripheral 432 when the control signal is a high-level signal, and to shield the shared signal from the peripheral 432 when the control signal is a low-level signal.

[0068] Assuming that the target peripheral 432 that the target host 410 needs to access is peripheral 1, then psel_out[0] and penable_out[0] are high-level signals, that is, the control signals are high-level signals, which can control the gating unit to send the shared signal to peripheral 1; psel_out[1] and penable_out[1], psel_out[2] and penable_out[2] are low-level signals, that is, the control signals are low-level signals, which can control the two gating units to shield the shared signal to peripheral 2 and peripheral 3 respectively.

[0069] (5) The target peripheral 432 is used to communicate with the target host 410 based on the PSEL signal, the PENABLE signal and the sharing signal.

[0070] The target peripheral 432 can write the data sent by the target host 410 into the configuration register to perform a write operation; or, the target peripheral 432 can send the data in the configuration register to the target host 410 to perform a read operation.

[0071] In this embodiment, peripheral 432 further includes a configuration register array, each configuration register being connected to a combinational logic unit, and each combinational logic unit being connected to a corresponding gating unit and address decoding unit. The gating unit is used to send a shared signal to the combinational logic unit corresponding to the target peripheral 432. The address decoding unit is used to send the PSEL signal and the PENABLE signal to the combinational logic unit corresponding to the target peripheral 432. The combinational logic unit is used to perform logical operations on the PSEL signal, the PENABLE signal, and the shared signal, and send the operation result to the corresponding configuration register for corresponding read and write operations, so as to realize the communication between the target peripheral 432 and the target host 410.

[0072] like Figure 6 As shown, taking combinational logic units including comb1 and comb2 as an example, shared signals (such as PADDR / PWDATA / PWRITE / PSTRB / PPROT / PUSER, etc.) are input to the gating unit, while PSEL and PENABLE signals are input to the gating unit and comb2. Only when the PSEL and PENABLE signals input to the gating unit toggle (becoming high-level signals) will the gating unit output the shared signal to comb1. Comb1 and comb2 then perform logical operations on the PSEL, PENABLE, and shared signals, thereby controlling the combinational logic unit to toggle and enabling read / write operations on the configuration register. When the PSEL and PENABLE signals input to the gating unit do not toggle (becoming low-level signals), the gating unit shields the shared signal from comb1. Comb1 and comb2 do not perform logical operations on the shared signal, thus preventing unnecessary toggling of the combinational logic unit and saving power.

[0073] For the asynchronous APB bus, the PSEL and PENABLE signals are in the same clock domain (CLK domain) as peripheral 432, while the shared signals belong to another source clock domain. Static Timing Analysis (STA) can only guarantee that the PSEL and PENABLE signals in the clock domain have stable outputs without glitch phenomena, but it cannot guarantee that the shared signals in the source clock domain will not have glitch phenomena. Therefore, for peripheral 432 that is not accessed, shielding the shared signals through the gating unit can avoid glitch phenomena in peripheral 432 caused by the shared signals.

[0074] In summary, the peripheral access system based on APB provided in this application, by setting a gating unit between the APB DEMUX and each peripheral, can realize the transmission of shared signals controlled by the gating unit. That is, when the peripheral is a target peripheral that the target host needs to access, the gating unit controls the shared signals to be visible to the peripheral; when the peripheral is not a target peripheral that the target host needs to access, the gating unit controls the shared signals to be invisible to the peripheral. This can avoid unnecessary switching of combinational logic units in non-target peripherals due to the switching of shared signals, thereby saving power consumption.

[0075] like Figure 7 The diagram illustrates a flowchart of an APB-based peripheral access method according to an embodiment of this application. This APB-based peripheral access method can be applied to a chip. The APB-based peripheral access method may include:

[0076] Step 701: The target host sends an access request to the target peripheral to the Cross-Bar.

[0077] In this embodiment, the host that accesses the peripheral is called the target host, and the peripheral to be accessed is called the target peripheral. The target host can generate an access request based on the address of the target peripheral and its read / write requirements, and send the access request to the Cross-Bar through the AXI bus or AHB bus.

[0078] Step 702: Cross-Bar determines the target APB DEMUX corresponding to the target peripheral based on the access request, and forwards the access request to the target APB DEMUX through the APB bus.

[0079] In this embodiment, the APB DEMUX corresponding to the target peripheral is referred to as the target APB DEMUX. The Cross-Bar can then determine the target APB DEMUX corresponding to the target peripheral and send the access request to the target APB DEMUX through the APB bus.

[0080] Step 703: The target APB DEMUX converts the access request into a shared signal and the PSEL and PENABLE signals of each peripheral through the address decoding unit. It sends the shared signal to the gating unit of each peripheral and sends the PSEL and PENABLE signals of each peripheral to the corresponding peripheral. The PSEL and PENABLE signals of the target peripheral are high-level signals, while the PSEL and PENABLE signals of other peripherals are low-level signals.

[0081] In this embodiment, each peripheral in a peripheral access group corresponds to a set of PSEL and PENABLE signals, and all peripherals correspond to a set of shared signals. For example... Figure 5 As shown, peripheral 1 corresponds to psel_out[0] and penable_out[0], peripheral 2 corresponds to psel_out[1] and penable_out[1], peripheral 3 corresponds to psel_out[2] and penable_out[2], and peripherals 1-3 all correspond to pwrite[31:0] and paddr[31:0].

[0082] Assuming the target peripheral that the target host needs to access is peripheral 1, then psel_out[0] and penable_out[0] are high-level signals, and psel_out[1] and penable_out[1], psel_out[2] and penable_out[2] are low-level signals.

[0083] Step 704: When the corresponding peripheral is the target peripheral, each gating unit sends a shared signal to the target peripheral; when the corresponding peripheral is not the target peripheral, it blocks the shared signal from the peripheral.

[0084] In this embodiment, the gating units can be controlled by control signals. Specifically, the target APB DEMUX sends control signals to each gating unit. The control signals are either PSEL or PENABLE signals. When the control signal is high, each gating unit sends a shared signal to the target peripheral; when the control signal is low, it blocks the shared signal from reaching the peripheral.

[0085] Assuming the target peripheral that the target host needs to access is peripheral 1, then psel_out[0] and penable_out[0] are high-level signals, that is, the control signals are high-level signals, which can control the gating unit to send the shared signal to peripheral 1; psel_out[1] and penable_out[1], psel_out[2] and penable_out[2] are low-level signals, that is, the control signals are low-level signals, which can control the two gating units to shield the shared signal to peripheral 2 and peripheral 3 respectively.

[0086] Step 705: The target peripheral communicates with the host based on the PSEL signal, PENABLE signal and sharing signal.

[0087] The target peripheral can write data sent by the target host into the configuration register to perform a write operation; or, the target peripheral can send data in the configuration register to the target host to perform a read operation.

[0088] In this embodiment, when the peripheral device also includes a configuration register array, the gating unit sends the shared signal to the combinational logic unit corresponding to the target peripheral device; the address decoding unit sends the PSEL signal and the PENABLE signal to the combinational logic unit corresponding to the target peripheral device; the combinational logic unit performs logical operations on the PSEL signal, the PENABLE signal and the shared signal, and sends the operation result to the corresponding configuration register for corresponding read and write operations, so as to realize the communication between the target peripheral device and the target host.

[0089] like Figure 6 As shown, taking combinational logic units including comb1 and comb2 as an example, shared signals (such as PADDR / PWDATA / PWRITE / PSTRB / PPROT / PUSER, etc.) are input to the gating unit, while PSEL and PENABLE signals are input to the gating unit and comb2. Only when the PSEL and PENABLE signals input to the gating unit toggle (becoming high-level signals) will the gating unit output the shared signal to comb1. Comb1 and comb2 then perform logical operations on the PSEL, PENABLE, and shared signals, thereby controlling the combinational logic unit to toggle and enabling read / write operations on the configuration register. When the PSEL and PENABLE signals input to the gating unit do not toggle (becoming low-level signals), the gating unit shields the shared signal from comb1. Comb1 and comb2 do not perform logical operations on the shared signal, thus preventing unnecessary toggling of the combinational logic unit and saving power.

[0090] For asynchronous APB buses, the PSEL and PENABLE signals are in the same clock domain (CLKDomain) as the peripherals, while the shared signals belong to another source clock domain. Static Timing Analysis (STA) can only guarantee that the PSEL and PENABLE signals in the clock domain have stable outputs without glitch phenomena, but it cannot guarantee that the shared signals in the source clock domain will not exhibit glitch phenomena. Therefore, for unaccessed peripherals, shielding the shared signals through a gating unit can prevent glitch phenomena caused by the shared signals from occurring in the peripherals.

[0091] In summary, the peripheral access method based on APB provided in this application, by setting a gating unit between the APB DEMUX and each peripheral, can realize the transmission of shared signals controlled by the gating unit. That is, when the peripheral is a target peripheral that the target host needs to access, the gating unit controls the shared signals to be visible to the peripheral; when the peripheral is not a target peripheral that the target host needs to access, the gating unit controls the shared signals to be invisible to the peripheral. This can avoid unnecessary switching of combinational logic units in the non-target peripheral due to the switching of shared signals, thereby saving power consumption.

[0092] One embodiment of this application provides a computer-readable storage medium storing at least one instruction, which is loaded and executed by a processor to implement the APB-based peripheral access method as described above.

[0093] One embodiment of this application provides a chip that includes any of the aforementioned APB-based peripheral access systems.

[0094] It should be noted that the peripheral access system based on APB provided in the above embodiments is only illustrated by the division of the above functional modules when performing peripheral access based on APB. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the peripheral access system based on APB can be divided into different functional modules to complete all or part of the functions described above. In addition, the peripheral access system based on APB provided in the above embodiments and the peripheral access method embodiments based on APB belong to the same concept, and the specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0095] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0096] The above description is not intended to limit the embodiments of this application. Any adjustments, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A peripheral access system based on APB, characterized in that, The peripheral access system includes multiple hosts, a crossbar switch matrix, and at least one peripheral access group, wherein the peripheral access group includes an APB demultiplexer DEMUX and at least one peripheral. Each host is connected to one input of the Cross-Bar, and each output of the Cross-Bar is connected to the address decoding unit of the APB DEMUX in a peripheral access group. The address decoding unit is connected to a peripheral in the same group through each gating unit. The target host is used to send an access request to the target peripheral device to the Cross-Bar; The Cross-Bar is used to determine the target APB DEMUX corresponding to the target peripheral based on the access request, and forward the access request to the target APB DEMUX through the APB bus; The target APB DEMUX is used to convert the access request into a shared signal and the PSEL and PENABLE signals of each peripheral through the address decoding unit, send the shared signal to the gating unit of each peripheral, and send the PSEL and PENABLE signals of each peripheral to the corresponding peripheral; wherein, the PSEL and PENABLE signals corresponding to the target peripheral are high-level signals, and the PSEL and PENABLE signals corresponding to other peripherals are low-level signals; Each gating unit is used to send the shared signal to the target peripheral when the corresponding peripheral is the target peripheral; and to shield the shared signal from the peripheral when the corresponding peripheral is not the target peripheral. The target peripheral is used to communicate with the target host based on the PSEL signal, the PENABLE signal, and the sharing signal.

2. The peripheral access system based on APB according to claim 1, characterized in that, The target APB DEMUX is also used to send control signals to each gating unit, wherein the control signals are the PSEL signal or the PENABLE signal; The gating unit is used to send the shared signal to the target peripheral when the control signal is a high-level signal, and to shield the shared signal from the peripheral when the control signal is a low-level signal.

3. The peripheral access system based on APB according to claim 1, characterized in that, If the gating unit is located in the APB DEMUX, then the address decoding unit in an APB DEMUX is connected to each gating unit in the same group, and each gating unit is connected to a corresponding peripheral.

4. The peripheral access system based on APB according to claim 1, characterized in that, If the gating unit is located in the peripheral device, then the address decoding unit in an APB DEMUX is connected to the gating unit in each peripheral device in the same group.

5. The peripheral access system based on APB according to any one of claims 1 to 4, characterized in that, The peripheral device also includes a configuration register array, each configuration register being connected to a combinational logic unit, and each combinational logic unit being connected to a corresponding gating unit and the address decoding unit; The gating unit is used to send the shared signal to the combinational logic unit corresponding to the target peripheral; The address decoding unit is used to send the PSEL signal and the PENABLE signal to the combinational logic unit corresponding to the target peripheral. The combinational logic unit is used to perform logical operations on the PSEL signal, the PENABLE signal and the shared signal, and send the operation results to the corresponding configuration register for corresponding read and write operations, so as to realize the communication between the target peripheral and the target host.

6. A peripheral access method based on APB, characterized in that, For use in a peripheral access system as described in any one of claims 1 to 5, the method comprises: The target host sends an access request to the target peripheral device to the Cross-Bar; The Cross-Bar determines the target APB DEMUX corresponding to the target peripheral based on the access request, and forwards the access request to the target APB DEMUX through the APB bus; The target APB DEMUX converts the access request into a shared signal and the PSEL and PENABLE signals of each peripheral through the address decoding unit. The shared signal is sent to the gating unit of each peripheral, and the PSEL and PENABLE signals of each peripheral are sent to the corresponding peripheral. The PSEL and PENABLE signals of the target peripheral are high-level signals, while the PSEL and PENABLE signals of other peripherals are low-level signals. Each gating unit sends the shared signal to the target peripheral when the corresponding peripheral is the target peripheral; and blocks the shared signal to the peripheral when the corresponding peripheral is not the target peripheral. The target peripheral communicates with the host based on the PSEL signal, the PENABLE signal, and the sharing signal.

7. The peripheral access method based on APB according to claim 6, characterized in that, The method further includes: the target APB DEMUX sending a control signal to each gating unit, wherein the control signal is the PSEL signal or the PENABLE signal; Each gating unit sends the shared signal to the target peripheral when the corresponding peripheral is the target peripheral; and blocks the shared signal from the peripheral when the corresponding peripheral is not the target peripheral, including: Each gating unit sends the shared signal to the target peripheral when the control signal is high; and blocks the shared signal from the peripheral when the control signal is low.

8. The peripheral access method based on APB according to claim 6, characterized in that, The method further includes: When the peripheral device also includes a configuration register array, the gating unit sends the shared signal to the combinational logic unit corresponding to the target peripheral device; The address decoding unit sends the PSEL signal and the PENABLE signal to the combinational logic unit corresponding to the target peripheral. The combinational logic unit performs logical operations on the PSEL signal, the PENABLE signal, and the shared signal, and sends the operation results to the corresponding configuration registers for corresponding read and write operations, so as to realize the communication between the target peripheral and the target host.

9. A computer-readable storage medium, characterized in that, The storage medium stores at least one instruction, which is loaded and executed by a processor to implement the APB-based peripheral access method as described in any one of claims 6 to 8.

10. A chip, characterized in that, The chip includes: an APB-based peripheral access system as described in any one of claims 1 to 5.

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