SPI slave communication method and device, readable storage medium and computer program product

Abstract

The invention discloses an SPI (Serial Peripheral Interface) slave communication method and device, a readable storage medium and a computer program product, relates to the field of SPI communication of an embedded ARM (Advanced RISC Machines), and is mainly applied to the field of SPI communication of the embedded ARM. The method comprises the following steps: (1) configuring an SPI communication mode of the ARM as slave communication; (2) configuring an SPI (Serial Peripheral Interface) as a sending mode based on DMA (Direct Memory Access (3) triggering rising edge interruption through a chip selection signal line of the host; and (4) the SPI slave is reset, data to be sent are prepared, the sent data comprise frame header and frame tail verification, a DMA sending buffer area is updated in a double-buffer mode, and reliable communication of the SPI slave is achieved in the mode.

Description

Technical Field

[0001] The present invention relates to a communication method for an SPI slave, and particularly to a communication method, device, readable storage medium, and computer program product for an SPI slave, which are mainly used in the SPI communication field of embedded ARM. Background Art

[0002] As the requirements for the domestic production level of product components in the project are getting higher and higher, there are certain limitations in the hardware selection of the product. Considering indicators such as power consumption, stability, and cost, the general ARM chip has a low main frequency and no dedicated floating-point data processing unit, resulting in more time-consuming when processing floating-point data. As a slave device, within a fixed data acquisition cycle, the data processing of itself and the SPI communication with the host are prone to timing conflicts, leading to a relatively high error rate of communication data frames.

[0003] The SPI slave device can only passively wait for the host device to perform chip selection on it in the communication link, and then communicate with the host. If the current communication fails, the SPI slave will have a communication timing disorder and cannot recover the communication failure. Summary of the Invention

[0004] The technical problem solved by this application is: overcoming the deficiencies of the prior art, providing a communication method, device, readable storage medium, and computer program product for an SPI slave, and solving the problem of poor communication reliability caused by the conflict between the data processing of the SPI slave device itself and the SPI communication with the host.

[0005] The technical solution provided by this application is as follows:

[0006] The SPI slave communication method includes:

[0007] S1: Configure the ARM as a slave, and configure the communication method between the slave and the host as SPI communication. Define a double buffer flag bit and a periodic processing data flag bit in the slave. The double buffer flag bit includes 0 and 1;

[0008] S2: Configure the slave as a DMA memory-based transmission mode, configure the DMA memory address as the address of the data storage area to be sent by the slave. The address of the data storage area to be sent includes SendData0 and SendData1. If the double buffer flag bit is 0, configure the DMA memory address as SendData0. If the double buffer flag bit is 1, configure the DMA memory address as SendData1;

[0009] S3: The slave receives the chip select signal sent by the host. The chip select signal triggers a rising edge interrupt, and determines whether the chip select signal is high level or low level. If the chip select signal is detected as low level, set the periodic processing data flag bit to 0. If the chip select signal is detected as high level, set the periodic processing data flag bit to 1;

[0010] S4: The slave device processes the data flag bit according to the period, and determines whether it is a correct communication initiation. When the data flag bit processed according to the period is 0, it is determined that it is not a correct communication initiation, and the slave device does not prepare the data to be sent and does not communicate with the master device;

[0011] When the data flag bit processed according to the period is 1, it is determined that it is a correct communication initiation, the double buffer flag bit is switched, the data flag bit processed according to the period is set to 0, and steps S1 and S2 are re-performed according to the switched double buffer flag bit. Re-performing steps S1 and S2 includes: reconfiguring the SPI communication mode and the DMA memory, resetting the SPI and the DMA, and simultaneously updating the DMA memory address; according to the switched double buffer flag bit, the slave device places the data to be sent into SendData0 or SendData1, waits for the master device to read the data, and completes the communication with the master device.

[0012] In the above step S4, the function of re-executing steps S1 and S2 is to prevent communication interruption and reset the communication again. This process is part of the reliability, avoiding the inability to restore communication after a communication failure with the master device once. At the same time, the data flag bits processed according to the period are different for two adjacent times, making the DMA memory addresses of the slave device different for two adjacent times, improving the communication reliability.

[0013] The initial value of the double buffer flag bit is 0.

[0014] The switching of the double buffer flag bit includes making txBufPingPong = 1 - txBufPingPong, where txBufPingPong is the double buffer flag bit, that is, assigning 1 - txBufPingPong to txBufPingPong.

[0015] The configuration mode of the SPI communication mode is as follows:

[0016] Configure the clock signal pin of the slave device, the master output / slave input pin, and the master input / slave output pin;

[0017] Configure the slave device as a two-wire full-duplex mode;

[0018] Configure the slave device as a slave working mode;

[0019] Configure the data frame length of the slave device;

[0020] According to the requirements of the master device, configure the communication mode of the SPI slave device. The slave device and the master device need to work in the same mode to communicate normally;

[0021] Configure the SPI data sending mode of the slave device to be high-bit first;

[0022] Disable the CRC check of SPI;

[0023] Enable the SPI function.

[0024] After the rising edge interrupt is triggered by the chip select signal, the high and low levels of the signal are detected in real time within 5 μs, and the influence of the glitch level on the interrupt is eliminated.

[0025] When the rising edge interrupt is triggered by the chip select signal, the host does not select the slave for communication at this time. The chip select signal serves as the data processing clock signal for the slave. That is, when the slave receives the chip select signal, it determines that a correct communication is initiated, and performs the switching of the double buffer flag bit, the reset of SPI and DMA, and subsequent data communication.

[0026] The communication format of the data to be sent is a combination of a frame header and a frame tail.

[0027] A computer device includes a memory, a processor, and a computer program stored in the memory. The processor executes the computer program to implement the steps of any one of the above methods.

[0028] A computer-readable storage medium stores a computer program / instructions. When the computer program / instructions are executed by a processor, the steps of any one of the above methods are implemented.

[0029] A computer program product includes a computer program / instructions. When the computer program / instructions are executed by a processor, the steps of any one of the above methods are implemented.

[0030] In summary, the present application at least includes the following beneficial technical effects:

[0031] (1) In the prior art, a single buffer sending method is mostly used for SPI slave communication. For products with high requirements for communication speed, there is a risk that when the host communicates with the slave within a limited time, the data to be sent by the slave is not written into the buffer in time, or a conflict occurs between updating the buffer and the host fetching data, resulting in the failure to update two consecutive frames of data or data frame errors. The present invention designs a dual buffer for SPI sending, and switches the sending buffer within each communication cycle, which can solve the problem of the conflict between SPI slave data update and host communication timing, and improve the reliability.

[0032] (2) In the prior art, the SPI slave is not reset regularly, which may cause a communication anomaly and lead to a failure where subsequent communication cannot be restored. The present invention regularly resets the SPI slave when the slave device is not selected, which can ensure that the SPI slave can resume normal communication in the next cycle after an abnormal communication.

[0033] (3) The design method of the present invention is general and reliable, which helps to directly transplant and use in SPI slave communication design projects, and reduces subsequent maintenance work. Description of the Drawings

[0034] Figure 1 This is the flowchart for configuring SPI in the present invention;

[0035] Figure 2 This is the flowchart for configuring DMA in the present invention;

[0036] Figure 3 This is the flowchart for the rising edge interrupt in the present invention;

[0037] Figure 4 This is the flowchart for resetting SPI and data transmission in the present invention. Detailed Embodiment

[0038] To make the objectives, technical solutions and advantages of the present invention clearer, the following will further describe in detail the disclosed embodiments of the present invention with reference to the accompanying drawings.

[0039] An embodiment of this application discloses an SPI slave communication method, as Figure 1 shown, including the following steps:

[0040] S1: Configure the SPI communication mode of the ARM as slave communication;

[0041] The configuration mode of the SPI communication mode is:

[0042] (1) Configure the clock signal pin, host output / slave input pin, and host input / slave output pin of the SPI;

[0043] (2) Configure the SPI as a dual-line full-duplex mode;

[0044] (3) Configure the SPI as a slave working mode;

[0045] (4) Configure the SPI data frame length to 8 bits;

[0046] (5) According to the requirements of the host, configure the communication mode of the SPI slave. The slave and the host need to work in the same mode to communicate normally;

[0047] (6) Configure the SPI data transmission method as high-order first;

[0048] (7) Disable the CRC check of the SPI;

[0049] (8) Enable the SPI function.

[0050] S2: Configure the slave SPI as a transmission mode based on the DMA peripheral;

[0051] The configuration mode of the DMA peripheral is:

[0052] (1) Select the corresponding DMA channel for SPI transmission (the DMA memory has multiple channels, and one of them is used to configure the SPI transmission mode);

[0053] (2) Configure the DMA peripheral address as the SPI data register address;

[0054] (3) Define a variable in the slave device. This variable is a double-buffer flag bit named txBufPingPong; define a variable in the slave device. This variable is a periodic data processing flag bit; according to the double-buffer flag bit, configure the DMA memory address as the address of the data storage area to be sent (the data storage area to be sent is an array variable defined in the slave device), and the size of the data storage area to be sent is determined according to the number of communication bytes. The initial value of the double-buffer flag bit is 0; if the double-buffer flag bit is 0, then configure the DMA memory address as SendData0, otherwise configure it as SendData1; (SendData0 and SendData1 are two defined data storage areas to be sent, and according to the double-buffer flag bit, switch the configuration as the DMA memory address);

[0055] (4) Configure the DMA transfer direction as from DMA memory to DMA peripheral;

[0056] (5) Configure the DMA transfer quantity as the size of the buffer variable described in (3);

[0057] (6) Disable the automatic increment of the DMA peripheral address;

[0058] (7) Enable the automatic increment of the DMA memory address;

[0059] (8) Configure the DMA peripheral data width as 8 bits;

[0060] (9) Configure the DMA memory data width as 8 bits;

[0061] (10) Configure the DMA transfer mode as circular transfer;

[0062] (11) Enable the DMA function.

[0063] S3: Trigger a rising-edge interrupt through the chip select signal line of the host;

[0064] Trigger a rising-edge interrupt through the chip select signal line of the host. At this time, the host does not select the slave device for communication (the chip select signal is high, indicating that the host does not select the slave device for communication), which can be used as the data processing clock signal of the slave device;

[0065] After triggering the rising-edge interrupt (that is, after entering the rising-edge interrupt function), detect the high and low levels of this signal in real time within 5 μs to eliminate the influence of the glitch level on the interrupt. The specific operations are as follows:

[0066] (1) If the detection signal of the chip select signal is at a high level, it is determined as a correct external interrupt signal, the cycle processing data flag bit (start) is set to 1, and at the same time, the double buffer flag bit is switched, that is, txBufPingPong = 1 - txBufPingPong. If the double buffer flag bit is 0 at this time, it is switched to 1, otherwise it is switched to 0;

[0067] (2) If the detection signal is at a low level, the cycle processing data flag bit (start) is set to 0, it is determined that it is not a correct communication initiation, and the slave does not prepare the data to be sent and does not communicate with the master.

[0068] S4: Reset the SPI slave, prepare the data to be sent. The data to be sent includes frame header, frame tail and checksum. Update the DMA transmit buffer in a double buffer mode. Through this method, reliable communication of the SPI slave is achieved. The specific process is as follows:

[0069] (4.1) Judge whether the cycle processing data flag bit is set (start is 1). If it is set, clear the flag bit (that is, start is 0), reset the SPI slave (re - execute the configurations in steps 1 and 2), and perform data processing (data processing is to obtain the data to be sent); Reset the SPI slave to re - execute the configured SPI communication mode in (1) and the configured DMA peripheral in (2), and update the DMA memory address according to the double buffer flag bit.

[0070] (4.2) Prepare the data to be sent. The sent data includes frame header, frame tail and checksum;

[0071] (4.3) Update the DMA transmit buffer in a double buffer mode. Judge the double buffer flag bit in this cycle. If the flag bit is 0, store the data to be sent in SendData1, otherwise store the data to be sent in SendData0.

[0072] The implementation principle of this application is as follows:

[0073] Within a communication cycle, the master sends a chip select signal, and the slave receives the chip select signal, triggering a rising - edge interrupt;

[0074] After triggering the rising - edge interrupt, if the chip select signal is detected as low level within 5 us, set the cycle processing data flag bit to 0, determine that it is not a correct communication initiation, and the slave does not prepare the data to be sent and does not communicate with the master;

[0075] After the rising edge interrupt is triggered, if the chip select signal is detected as high level within 5 us, it is determined that a correct communication is initiated at this time. The double buffer flag bit is switched, and the periodic processing data flag bit is set to 1; when the periodic processing data flag bit is 1, the periodic processing data flag bit is set to 0, and steps S1 and S2 are performed again, and the data to be sent is prepared; and the slave device places the data to be sent into the buffer variable storage area SendData0 or SendData1 according to the switched double buffer flag bit, waits for the host device to read the data, and completes the communication.

[0076] In any two adjacent communication cycles, due to the operation of switching the double buffer flag bit, in the latter communication cycle of two adjacent communication cycles, the data to be sent by the slave device is stored in a DMA memory address different from that of the previous communication cycle. When updating the DMA memory address in the previous communication cycle of two adjacent communication cycles, the host device is set to fetch data from another DMA memory address, avoiding the failure of data processing of the slave device conflicting with the host communication.

[0077] Designing the SPI transmission double buffer can solve the problem of incorrect data update of the SPI slave device and improve the reliability of the transmitted data. Switch the data storage area to be sent within each communication cycle. When updating the data storage area to be sent within this cycle, the host device is set to fetch data from another data storage area to be sent, effectively avoiding the failure of data processing of the slave device conflicting with the host communication.

[0078] Timing resetting the SPI slave device can avoid the failure of not being able to restore normal communication after an exception. When the slave device is not selected, timing resetting the SPI slave device can ensure that the SPI slave device can restore normal communication in the next cycle after abnormal communication.

[0079] In the solution provided by the embodiment of the present application, taking the STM32F1 series as an example, the following steps are included:

[0080] (1) Configure the SPI communication mode of the ARM as slave communication. The configuration information is as Figure 1 shown, and the example is as follows:

[0081] (1.1) The host can correspond to multiple slave devices, and one of the slave devices is slave SPI2; configure the clock signal pin GPIOB_13 of SPI2 as floating input, the host output / slave input pin GPIOB_15 as floating input, and the host input / slave output pin GPIOB_14 as multiplexed push-pull output; the chip select pin of slave SPI2 is GPIOB_12;

[0082] (1.2) Configure SPI2 as a dual-line full-duplex mode;

[0083] (1.3) Configure SPI2 as a slave working mode;

[0084] (1.4) Configure the SPI2 data frame length to 8 bits;

[0085] (1.5) Configure the communication mode of the SPI2 slave to Mode 1, with the SCK clock low during idle time and the sampling moment at the even edge;

[0086] (1.6) Configure the SPI2 data transmission method to transmit the high bits first;

[0087] (1.7) Disable the CRC check of SPI2;

[0088] (1.8) Enable the SPI2 function.

[0089] (2) Configure the slave SPI to the transmission mode based on the DMA peripheral. The configuration information is as Figure 2 shown, and the example is as follows:

[0090] (2.1) Select the corresponding DMA channel for SPI2 transmission as DMA1_Channel5;

[0091] (2.2) Configure the DMA peripheral address as the data register address of SPI2;

[0092] (2.3) According to the double-buffer flag bit, configure the DMA memory address as the start address of the buffer variable storage area, and set the buffer variable size to 40 bytes; if txBufPingPong (the initial value of txBufPingPong is 0) is 0, then configure the DMA memory address as SendData0, otherwise configure it as SendData1;

[0093] (2.4) Configure the DMA transfer direction as from memory to peripheral;

[0094] (2.5) Configure the DMA transfer quantity to 40;

[0095] (2.6) Prohibit the automatic increment of the DMA peripheral address;

[0096] (2.7) Enable the automatic increment of the DMA memory address;

[0097] (2.8) Configure the DMA peripheral data width to 8 bits;

[0098] (2.9) Configure the DMA memory data width to 8 bits;

[0099] (2.10) Configure the DMA transfer mode as circular transfer;

[0100] (2.11) Enable the DMA function.

[0101] (3) Trigger a rising-edge interruption through the chip select signal line of the host. The interruption process is as shown in Figure 3 shown below. The example is as follows:

[0102] (3.1) Set GPIOB_12 to trigger on the external rising edge interruption;

[0103] (3.2) If an interruption is triggered, then after entering the interruption, clear the external interruption EXTI_Line12 flag bit; start Timer 1 and detect the high and low levels of GPIOB_12 in real time within 5 μs; if the status of GPIOB_12 remains high, then set the periodic processing data flag bit (start) to 1, and at the same time set txBufPingPong = 1 - txBufPingPong; if the detected signal is low, then do not perform any operation and exit the interruption.

[0104] (4) Reset the SPI slave, prepare the data to be sent. The sent data includes the frame header, frame tail, and checksum, and update the DMA transmission buffer in a double-buffer mode. Through this method, reliable communication of the SPI slave is achieved.

[0105] The sending process is as shown in Figure 4 shown below. The example is as follows:

[0106] (4.1) In the main loop, judge whether the periodic processing data flag bit start is 1. If start is 1, then enter the main process, clear start to 0, re-initialize SPI2 and DMA, and then perform corresponding data processing; prepare the data to be sent arrData. The sent data arrData is a combination of the frame header 0xAA + 0x5A and the CRC frame tail checksum;

[0107] (4.2) Update the DMA transmission buffer in a double-buffer mode. If txBufPingPong is 0, then store arrData in SendData1, otherwise store it in SendData0.

[0108] The above has introduced in detail a SPI slave communication method provided by the present invention. For those of ordinary skill in the art, there will be changes in accordance with the specific implementation process and application scope of the present invention. In summary, the content of this specification should not be construed as a limitation to the present invention.

[0109] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, then this application is also intended to include these modifications and variations.

[0110] The content not described in detail in the specification of the present invention belongs to the well-known technology of those skilled in the art.

Claims

1. SPI slave communication method, characterized in that: include: S1: Configure ARM as a slave, and configure the communication mode between the slave and the host as SPI communication. Define the double buffer flag and the periodic processing data flag in the slave. The double buffer flag includes 0 and 1. S2: Configure the slave to the DMA memory-based sending mode, configure the DMA memory address to be the address of the slave's data storage area to be sent, the address of the data storage area to be sent includes SendData0 and SendData1, if the double buffer flag is 0, configure the DMA memory address to SendData0, if the double buffer flag is 1, configure the DMA memory address to SendData1; S3: The slave receives the chip select signal sent by the host, and the chip select signal triggers a rising edge interrupt, and determines whether the chip select signal is high or low. If the chip select signal is detected as a low level, the periodic processing data flag is set to 0; if the chip select signal is detected as a high level, the periodic processing data flag is set to 1; S4: The slave determines whether the communication is initiated correctly according to the periodic processing data flag. When the periodic processing data flag is 0, it is determined that the communication is not initiated correctly, and the slave is not ready to send data and does not communicate with the host. When the periodic processing data flag is 1, it is determined that the communication is correctly initiated, the double buffer flag is switched, the periodic processing data flag is set to 0, and steps S1 and S2 are repeated according to the switched double buffer flag, and steps S1 and S2 are repeated, including: reconfiguring the SPI communication mode and the DMA memory, resetting the SPI and DMA, and updating the DMA memory address; The slave puts the data to be sent into SendData0 or SendData1 according to the switched double buffer flag, waits for the host to read the data, and completes the communication with the host.

2. The SPI slave communication method according to claim 1, wherein: The initial value of the double buffer flag is 0.

3. The SPI slave communication method according to claim 1, wherein: The switching double buffer flag includes: Let txBufPingPong=1-txBufPingPong, txBufPingPong is the double buffer flag, that is, 1-txBufPingPong is assigned to txBufPingPong.

4. The SPI slave communication method according to claim 1, characterized in that: The configuration mode of the SPI communication method is: Configure the slave's clock signal pin, master output / slave input pin, and master input / slave output pin; configure the slave to two-wire full-duplex mode; Configure the slave to slave working mode; Configure the data frame length of the slave; Configure the communication mode of the SPI slave according to the host's requirements. The slave and the host need to work in the same mode to communicate normally. Configure the slave's SPI data transmission mode to high bit first; Disable SPI CRC check; Enable SPI function.

5. The SPI slave communication method according to claim 1, wherein: After the chip select signal triggers the rising edge interrupt, the high and low levels of the signal are detected in real time within 5 μs, and the influence of the burr level on the interrupt is eliminated.

6. The SPI slave communication method according to claim 1, wherein: The chip select signal triggers a rising edge interrupt. At this time, the host has not selected the slave for communication. The chip select signal serves as the data processing clock signal of the slave. That is, when the slave receives the chip select signal, it is determined that the correct communication is initiated, and the double buffer flag is switched, the SPI and DMA are reset, and subsequent data communication is performed.

7. The SPI slave communication method according to claim 1, wherein: The communication format of the data to be sent is a combination of a frame header and a frame trailer.

8. A computer device comprising a memory, a processor and the memory, and processing a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of any one of claims 1-7.

9. A computer-readable storage medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instruction is executed by a processor, the steps of any method described in claims 1-7 are implemented.

10. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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