High-speed serial communication interface, chip and clock distribution method

Abstract

The invention provides a high-speed serial communication interface, a chip and a clock distribution method. The high-speed serial communication interface comprises an internal and external interconnection module, at least one internal reference clock buffer module and an external reference clock buffer module, the external reference clock buffer module is connected with the internal and external interconnection module, and the internal and external interconnection module is connected with at least one internal reference clock buffer module; the external reference clock buffer module is used for receiving a clock signal of an external clock source and outputting the clock signal to the internal and external interconnection module; the at least one internal reference clock buffer module is used for receiving clock signals from other high-speed serial communication interfaces and outputting the clock signals to the internal and external interconnection module, or outputting the clock signals received from the internal and external interconnection module to other high-speed serial communication interfaces; and the internal and external interconnection module is used for taking a clock signal received from the external reference clock buffer module or a clock signal received from at least one internal reference clock buffer module as a reference clock of the high-speed serial communication interface.

Description

Technical Field

[0001] This application belongs to the field of chip technology, and particularly relates to a high-speed serial communication interface, a chip, and a clock distribution method. Background Art

[0002] High-speed network switching chips play a crucial role in modern communication and data centers. These chips usually contain multiple SerDes ports. In large-scale and ultra-large-scale switching chips, there can be hundreds of SerDes, and the number of lanes can reach several hundred, as Figure 1 shown.

[0003] Each SerDes requires a high-speed differential clock signal to ensure correct output and reception of data. The CML (Current Mode Logic) level is a commonly used high-speed differential clock signal level standard. The differential clock with the CML level standard is usually used as the reference clock for Serdes, and its frequency is usually 100MHz, 156.25MHz, etc. Summary of the Invention

[0004] The purpose of this application is to provide a high-speed serial communication interface, a chip, and a clock distribution method, aiming to solve the problems of high difficulty and high cost in processing the differential clock network at the top layer during chip integration and packaging in related technologies.

[0005] According to the first aspect of this application, a high-speed serial communication interface is provided, including: an internal and external interconnection module, at least one internal reference clock buffer module, and an external reference clock buffer module; the external reference clock buffer module is connected to the internal and external interconnection module, and the internal and external interconnection module is connected to the at least one internal reference clock buffer module;

[0006] The external reference clock buffer module is used to receive the clock signal from the external clock source and output it to the internal and external interconnection module;

[0007] The at least one internal reference clock buffer module is used to receive the clock signal from other high-speed serial communication interfaces and output it to the internal and external interconnection module, or output the clock signal received from the internal and external interconnection module to other high-speed serial communication interfaces;

[0008] The internal and external interconnection module is used to use the clock signal received from the external reference clock buffer module, or the clock signal received from the at least one internal reference clock buffer module as the reference clock of the high-speed serial communication interface.

[0009] In an optional implementation manner, the internal and external interconnection module also outputs the received clock signal to one or more of the at least one internal reference clock buffer module.

[0010] In an alternative embodiment, under the control of a first enable signal, the external reference clock buffer module receives a clock signal from an external clock source and outputs it to the internal and external interconnection module; under the control of a second enable signal, the at least one internal reference clock buffer module receives a clock signal from other high-speed serial communication interfaces and outputs it to the internal and external interconnection module, or outputs the clock signal received from the internal and external interconnection module to other high-speed serial communication interfaces.

[0011] In an alternative embodiment, after the high-speed serial communication interface is integrated and packaged in the chip, the top layer of the chip packages external pins electrically connected to the external reference clock buffer module.

[0012] In an alternative embodiment, when there are multiple internal reference clock buffer modules, the multiple internal reference clock buffer modules are distributed in different directions on the edge of the high-speed serial communication interface.

[0013] According to a second aspect of the present application, there is provided a chip including one or more high-speed serial communication interfaces as described in the first aspect.

[0014] In an alternative embodiment, the high-speed serial communication interface includes at least one first high-speed serial communication interface and at least one second high-speed serial communication interface; after the first high-speed serial communication interface is packaged in the chip, it is electrically connected to the external pins packaged on the top layer of the chip, and after the second high-speed serial communication interface is packaged in the chip, the clock signal line of the second high-speed serial communication interface is not electrically connected to the external pins packaged on the top layer of the chip.

[0015] In an alternative embodiment, at least one internal reference clock buffer module of the first high-speed serial communication interface is connected to at least one of the second high-speed serial communication interfaces;

[0016] The external reference clock buffer module of the first high-speed serial communication interface receives a clock signal from the external pin and outputs the clock signal to the internal and external interconnection module;

[0017] The at least one internal reference clock buffer module of the first high-speed serial communication interface receives the clock signal from the internal and external interconnection module and outputs the clock signal to the connected second high-speed serial communication interface.

[0018] In an alternative embodiment, the same second high-speed serial communication interface is connected to one of the first high-speed serial communication interfaces or to other second high-speed serial communication interfaces; wherein, the second high-speed serial communication interface connected to other second high-speed serial communication interfaces receives a clock signal from the other second high-speed serial communication interfaces.

[0019] In an alternative embodiment, it further includes: a control and management unit; the control and management unit is configured to output a first enable signal and / or a second enable signal to one or more of the high-speed serial communication interfaces;

[0020] Wherein, the control and management unit controls the high-speed serial communication interface to receive a clock signal from an external pin through the external reference clock buffer module under the control of the first enable signal or to receive a clock signal from another high-speed serial communication interface through the internal reference clock buffer module under the control of the second enable signal by using the first enable signal and the second enable signal, and / or the control and management unit further controls some of the high-speed serial communication interfaces to output a clock signal to other high-speed serial communication interfaces through the internal reference clock buffer module by using the second enable signal.

[0021] According to a third aspect of the present application, there is provided a clock distribution method, which is implemented on the chip described in the second aspect, and includes:

[0022] Outputting a first enable signal and a second enable signal to the high-speed serial communication interfaces on the chip;

[0023] Wherein, the first enable signal and the second enable signal cooperate to enable the high-speed serial communication interface to receive a clock signal from an external pin through the external reference clock buffer module under the control of the first enable signal or to receive a clock signal from another high-speed serial communication interface through the internal reference clock buffer module under the control of the second enable signal, and / or some of the high-speed serial communication interfaces further output a clock signal to other high-speed serial communication interfaces through the internal reference clock buffer module under the control of the second enable signal.

[0024] Compared with the related art, the technical solution of the present application has at least the following advantages:

[0025] The chip architecture of the solution of the present application is more flexible, and it is convenient to adjust the clock signal distribution scheme. The top-level integration of the chip design is simple, and only differential clock wiring needs to be completed between SerDes and simple control is required. In terms of implementation, the buffer is built into the SerDes, and its position depends on the package layout of the SerDes. It does not occupy the top-level wiring resources, the area is more optimized, and it will not affect the surrounding layout. It is especially suitable for chips with tight top-level routing resources and ultra-large scale, and there is no need to process the differential clock network at the top level, which can reduce the physical implementation difficulty and greatly shorten the development cycle.

[0026] Other features and advantages of the present application will be described in the subsequent specification, and will be partially apparent from the specification, or will be understood by implementing the present application. The objectives and other advantages of the present application can be achieved and obtained through the structures and processes indicated in the specification and the accompanying drawings. Brief Description of the Drawings

[0027] To more clearly illustrate the technical solutions in the embodiments of the present application or in the related art, the following will briefly introduce the drawings required for use in the description of the embodiments or the related art. Obviously, the drawings in the following description are certain embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0028] Figure 1 is a schematic diagram of the chip layout structure of a multi-Serdes interface in the related art.

[0029] Figure 2 is a schematic diagram of the centralized clock distribution network structure in a chip with a multi-Serdes interface in the related art.

[0030] Figure 3 is a schematic diagram of the distributed clock distribution network structure in a chip with a multi-Serdes interface in the related art.

[0031] Figure 4 is a schematic diagram of the structure of a high-speed serial communication interface according to an exemplary embodiment of the present application.

[0032] Figure 5 is a schematic diagram of the chip structure of multiple high-speed serial communication interfaces according to an exemplary embodiment of the present application.

[0033] Figure 6 is a schematic diagram of the simplified chip structure of multiple high-speed serial communication interfaces according to an exemplary embodiment of the present application. Detailed Embodiments

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts fall within the scope of protection of the present application.

[0035] In a multi-port SerDes system, the distribution of high-speed differential clocks faces the following problems: clock jitter, complexity of clock distribution, power consumption and area, difficulty of engineering implementation, etc. There are mainly two related differential clock distribution technologies, namely:

[0036] Centralized: Share a differential clock source and distribute signals to each SerDes port through a global clock tree network.

[0037] Distributed: Multiple differential clock sources are locally shared by SerDes to reduce the length of the clock tree network.

[0038] The structure of the centralized differential clock distribution network is shown in Figure 2 as follows, including: a central clock source, a branch network from the clock source starting point to each end SerDes, and differential buffers located at different positions in the network. The advantages of the centralized differential clock are simple structure, while the disadvantages are reflected in three aspects: clock quality, resource consumption, and complexity. In terms of clock quality, due to the large clock tree length and many branch points, the delay and jitter become larger; in terms of resources, more buffers are required to optimize the delay and jitter; in terms of complexity, the clock tree needs to be laid out and routed on the top layer of the chip, and the tree structure, the number and position of buffers need to be carefully evaluated, and the physical implementation is difficult and the development cycle is long.

[0039] The structure of the distributed differential clock distribution network is shown in Figure 3 as follows, which includes multiple clock sources, multiple SerDes sharing the clock source within a local range, and differential buffers located within the local network. Compared with the centralized one, the clock network of the distributed differential clock is divided into multiple small blocks, the clock tree length becomes shorter, and the jitter and delay are better. The disadvantage of the distributed differential clock is reflected in the complexity. Since the clock tree still needs to be laid out and routed on the top layer of the chip, the tree structure, the number and position of buffers need to be carefully evaluated, and the physical implementation is difficult and the cycle is long.

[0040] Whether it is a centralized or a common distributed scheme, the differential clock network structure still needs to be determined on the top layer, and the planning of the number and position of buffers needs to be completed, occupying routing resources. In large-scale and ultra-large-scale switching chips, the number of SerDes can reach dozens or hundreds, and the number of channels can reach several hundred levels, which makes the difficulty and cost of processing the differential clock network on the top layer more prominent.

[0041] To this end, the present application proposes a solution. In this solution, the buffer of CMLCLK is placed inside the SerDes as a standard component of the SerDes, and the supporting logic is used to achieve clock interconnection in four directions. Then, the SerDes itself can be used as a transit node for the reference clock to receive and forward the reference clock. Further, by adding a small number of configuration signals for the serdes reference clock interconnection in the top CCU, the reference clock interconnection configuration of each serdes is realized. In this solution, in terms of chip top-level integration, only the wiring interconnection of the reference clock needs to be carried out among the serdes according to the clock network distribution architecture, which can not only reduce the chip design and physical implementation difficulty, optimize resources, but also make the architecture more flexible and facilitate rapid iterative adjustment.

[0042] See Figure 4 As shown, the present application exemplarily proposes a high-speed serial communication interface, including: an internal and external interconnection module, at least one internal reference clock buffer module, and an external reference clock buffer module; the external reference clock buffer module is connected to the internal and external interconnection module, and the internal and external interconnection module is connected to at least one internal reference clock buffer module;

[0043] The external reference clock buffer module is used to receive the clock signal of the external clock source and output it to the internal and external interconnection module;

[0044] At least one internal reference clock buffer module is used to receive the clock signal from other high-speed serial communication interfaces and output it to the internal and external interconnection module, or output the clock signal received from the internal and external interconnection module to other high-speed serial communication interfaces;

[0045] The internal and external interconnection module is used to use the clock signal received from the external reference clock buffer module or the clock signal received from at least one internal reference clock buffer module as the reference clock of the high-speed serial communication interface.

[0046] Exemplarily, the high-speed serial communication interface Serdes may include one or more internal reference clock buffer modules B-E that output or receive clock signals in different directions. These different directions can be understood as different wiring directions after the high-speed serial communication interface is laid out on the chip. The internal reference clock buffer module is bidirectional, that is, it can not only receive the clock signals int_ref_clk_* (shown as int_ref_clk_north, int_ref_clk_sorth, int_ref_clk_west, int_ref_clk_east in the figure) from other high-speed serial communication interfaces in different wiring directions on the chip, but also output the clock signals int_ref_clk_* to other high-speed serial communication interfaces in different wiring directions on the chip.

[0047] Exemplarily, the external reference clock buffer module A only receives the clock signal Ext_ref_clk from an external clock source, which can be understood as a clock source outside the chip after the high-speed serial communication interface is encapsulated on the chip. It should be noted that the same high-speed serial communication interface either receives the clock signal of the external clock source through the external reference clock buffer module or receives the clock signal of other high-speed serial communication interfaces through the internal reference clock buffer module. And in the case of multiple internal reference clock buffer modules, only one of the internal reference clock buffer modules receives the clock signal, and the other internal reference clock buffer modules output or do not output the clock signal to other high-speed serial communication interfaces.

[0048] Exemplarily, the clock signals received by the external reference clock buffer module and the internal reference clock buffer module are both output to the internal and external interconnection module F. If the internal and external interconnection module F receives the clock signal of the external reference clock buffer module, it takes this clock signal as the clock of this high-speed serial communication interface and also outputs this clock signal to the internal reference clock buffer module. If the internal and external interconnection module F receives the clock signal of the internal reference clock buffer module, it takes this clock signal as the clock of this high-speed serial communication interface and also outputs this clock signal to other internal reference clock buffer modules except the internal reference clock buffer module that receives the clock signal.

[0049] Exemplarily, the internal and external interconnection module can selectively output the clock signal to some of the internal reference clock buffer modules. The internal and external interconnection module can also output the clock signal to all the internal reference clock buffer modules. Whether the internal reference clock buffer module receives the clock signal from other high-speed serial communication interfaces or outputs the clock signal to other high-speed serial communication interfaces can be controlled by a dedicated control and management unit.

[0050] In some alternative embodiments, the internal and external interconnection module also outputs the received clock signal to one or more of at least one internal reference clock buffer module.

[0051] Exemplarily, both the external reference clock buffer module and the internal reference clock buffer module output the received clock signal to the internal and external interconnection module, and the internal and external interconnection module outputs the received clock signal to other internal reference clock buffer modules regardless of whether it receives the clock signal from the external reference clock buffer module or the internal reference clock buffer module. It should be noted that if the clock signal is received from the external reference clock buffer module, the internal and external interconnection module outputs the clock signal to all internal reference clock buffer modules; if the clock signal is received from one of the internal reference clock buffer modules, it outputs the clock signal to the remaining internal reference clock buffer modules. It can be understood that the internal and external interconnection module either receives the clock signal from the external reference clock buffer module or from one of the internal reference clock buffer modules. Of course, the internal and external interconnection module may also not output the clock signal to any internal reference clock buffer module.

[0052] In some alternative embodiments, under the control of the first enable signal, the external reference clock buffer module receives the clock signal from the external clock source and outputs it to the internal and external interconnection module; under the control of the second enable signal, at least one internal reference clock buffer module receives the clock signal from other high-speed serial communication interfaces and outputs it to the internal and external interconnection module, or outputs the clock signal received from the internal and external interconnection module to other high-speed serial communication interfaces.

[0053] Exemplarily, a high-speed serial communication interface can receive a first enable signal aa and at least one second enable signal bb-dd from an external clock source. The second enable signals correspond one-to-one with internal reference clock buffer modules. The first enable signal is used to control whether the external reference clock buffer module receives a clock signal from the external clock source. If the external reference clock buffer module receives a clock signal from the external under the control of the first enable signal, the external reference clock buffer module will output the received clock signal from the external to the internal and external interconnection module. The second enable signal is used to control whether the corresponding internal reference clock buffer module is connected to other high-speed serial communication interfaces. In the case of being connected to other high-speed serial communication interfaces, the second enable signal is further used to control the signal direction of the corresponding internal reference clock buffer module, that is, to output a clock signal to other high-speed serial communication interfaces or to receive a clock signal from other high-speed serial communication interfaces. It should be noted that when the high-speed serial communication interface receives a clock signal from the external clock source through the external reference clock buffer module, it no longer receives the clock signal of other high-speed serial communication interfaces from any internal reference clock buffer module; and if the high-speed serial communication interface receives a clock signal through the internal reference clock buffer module, it cannot receive the clock signal of the external clock source through the external reference clock buffer module, and only one internal reference clock buffer module can receive the clock signal of other high-speed serial communication interfaces, while other internal reference clock buffer modules either output a clock signal to other high-speed serial communication interfaces or neither receive nor output a clock signal.

[0054] In some alternative embodiments, after the high-speed serial communication interface is integrally packaged in a chip, external pins electrically connected to the external reference clock buffer module are packaged on the top layer of the chip.

[0055] Exemplarily, when the high-speed serial communication interface is packaged in a chip, external pins can be packaged on the top layer of the integrated chip. The external pins are electrically connected to the external reference clock buffer module of the high-speed serial communication interface. When using this chip, the external pins can be connected to an external clock source, so that a clock signal can be provided to the high-speed serial communication interface through the external clock source. Of course, it can be understood that the high-speed serial communication interface may not package external pins during chip integration, but receive a clock signal from other high-speed serial communication interfaces through the internal reference clock buffer module.

[0056] In some alternative embodiments, when there are multiple internal reference clock buffer modules, the multiple internal reference clock buffer modules are distributed in different directions on the edge of the high-speed serial communication interface.

[0057] Exemplarily, when there are multiple internal reference clock buffer modules, these multiple internal reference clock buffer modules can be arranged in different wiring directions inside the high-speed serial communication interface. For example, taking the center of the high-speed serial communication interface as a reference point, four internal reference clock buffer modules are set in each of the four directions of up, down, left, and right. The internal reference clock buffer modules in these four directions can receive or output clock signals from other high-speed serial communication interfaces around the high-speed serial communication interface through wiring design. It should be noted that in order to simplify chip design and implementation logic, the high-speed serial communication interface only outputs clock signals to other adjacent high-speed serial communication interfaces in layout.

[0058] For the above high-speed serial communication interface proposed in this application, the CMLCLKbuffer (external reference clock buffer module) is built into the high-speed serial communication interface. The reference clock can be directly input into the high-speed serial communication interface from the external bump, or input from other high-speed serial communication interfaces in one of multiple directions (up, down, left, and right). At the same time, with the cooperation of the external enable signal, clock signals can also be output in the four directions of up, down, left, and right.

[0059] Correspondingly, referring to Figure 5 As shown, this application exemplarily proposes a chip, which includes one or more high-speed serial communication interfaces as described above.

[0060] The relevant details of the high-speed serial communication interface included in this chip can be referred to the description of the high-speed serial communication interface above, and will not be elaborated here.

[0061] In some alternative embodiments, the high-speed serial communication interface includes at least one first high-speed serial communication interface and at least one second high-speed serial communication interface; after the first high-speed serial communication interface is encapsulated in the chip, it is electrically connected to the external pins encapsulated on the top layer of the chip. After the second high-speed serial communication interface is encapsulated in the chip, the clock signal line of the second high-speed serial communication interface is not electrically connected to the external pins encapsulated on the top layer of the chip.

[0062] Exemplarily, as Figure 6As shown, the high-speed serial communication interface can be divided into two types. One is the high-speed serial communication interface that receives the clock signal from an external clock source through an external reference clock buffer module. For the convenience of description, this is referred to as the first high-speed serial communication interface in this article. The other is the module that receives the clock signal through an internal reference clock buffer module. For the convenience of description, this is referred to as the second high-speed serial communication interface in this article. Since the first high-speed serial communication interface needs to receive the clock signal from an external clock source, when the chip is integrated and packaged, an external pin bump is packaged on the top layer so that the external clock source can input the clock signal to the external reference clock buffer module of the first high-speed serial communication interface through this external pin. The second high-speed serial communication interface receives the clock signal from other high-speed serial communication interfaces (which can be the first high-speed serial communication interface or other second high-speed serial communication interfaces) through the internal reference clock buffer module, rather than from an external clock source. Therefore, it is not necessary to package the clock signal line of the second high-speed serial communication interface out of the external pin.

[0063] In some optional embodiments, at least one internal reference clock buffer module of the first high-speed serial communication interface is connected to at least one second high-speed serial communication interface;

[0064] The external reference clock buffer module of the first high-speed serial communication interface receives the clock signal from the external pin and outputs the clock signal to the internal and external interconnection module;

[0065] At least one internal reference clock buffer module of the first high-speed serial communication interface receives the clock signal from the internal and external interconnection module and outputs the clock signal to the connected second high-speed serial communication interface.

[0066] Exemplarily, the first high-speed serial communication interface can directly receive the clock signal from an external clock source, and this clock signal can be provided to the surrounding second high-speed serial communication interfaces through the internal reference clock buffer module. In this way, the design and physical implementation difficulty of the chip can be reduced.

[0067] Exemplarily, after the external reference clock buffer module of the first high-speed serial communication interface receives the clock signal from the external clock source, it uses it as its own reference clock. At the same time, it also outputs this clock signal to the internal and external interconnection module, and the internal and external interconnection module provides this clock signal to each internal reference clock buffer module. Thus, under the control of the enable signal, the corresponding internal reference clock buffer module provides this clock signal to the surrounding second high-speed serial communication interfaces.

[0068] After receiving the clock signal from the first high-speed serial communication interface in the periphery, the second high-speed serial communication interface can use it as its own reference clock and can further provide the clock signal to other second high-speed serial communication interfaces through the internal reference clock buffer module. It should be noted that the first high-speed serial communication interface only receives the clock signal from an external clock source, and the second high-speed serial communication interface receives the clock signal of other high-speed serial communication interfaces through one of the internal reference clock buffer modules. Moreover, the first high-speed serial communication interface or the second high-speed serial communication interface can output the clock signal to one or more other second high-speed serial communication interfaces.

[0069] In some alternative embodiments, the same second high-speed serial communication interface is connected to one of the first high-speed serial communication interfaces or to other second high-speed serial communication interfaces; among them, the second high-speed serial communication interface connected to other second high-speed serial communication interfaces receives the clock signal from other second high-speed serial communication interfaces.

[0070] Exemplarily, the same second high-speed serial communication interface either receives the clock signal from one of the first high-speed serial communication interfaces or receives the clock signal from one of the second high-speed serial communication interfaces.

[0071] In some alternative embodiments, there is a control and management unit; the control and management unit is configured to output a first enable signal and / or a second enable signal to one or more of the high-speed serial communication interfaces;

[0072] Among them, the control and management unit, through the first enable signal and the second enable signal, controls the high-speed serial communication interface to receive the clock signal from an external pin through the external reference clock buffer module under the control of the first enable signal or to receive the clock signal from other high-speed serial communication interfaces through the internal reference clock buffer module under the control of the second enable signal, and / or the control and management unit also controls some of the high-speed serial communication interfaces to output the clock signal to other high-speed serial communication interfaces through the internal reference clock buffer module through the second enable signal.

[0073] Exemplarily, it can be understood that the clock signal lines of some or all of the high-speed serial communication interfaces on the chip can be packaged into external pin bumps, and whether to receive the clock signal from an external clock source can also be controlled by the control and management unit. That is to say, by configuring the first enable signal and the second enable signal output by the control and management unit, it is possible to control some of the high-speed serial communication interfaces to receive the clock signal from the external clock source through the external reference clock buffer module, and control this part of the high-speed serial communication interfaces to transmit the clock signal to other high-speed serial communication interfaces through the internal reference clock buffer module; in addition, the control and management unit can also control this part of the high-speed serial communication interfaces that receive the clock signal through the internal reference clock buffer module to further output the clock signal to the high-speed serial communication interfaces that do not receive the clock signal from the external clock source through other internal reference clock buffer modules.

[0074] In the highly flexible integration solution proposed in this application, the external reference clock buffer module of each SerDes can be packaged into an external pin bump on the top layer of the chip. At the same time, it is possible to freely select which external pins of the SerDes are used as the input of the external clock source at the board level, so that the number of external clock sources can be freely selected. Inside the chip, the clock transfer relationship between the SerDes can also be freely configured through the control of the control and management unit topCCU.

[0075] Exemplarily, please refer to Figure 6 As shown, a simplified solution of this application is that some SerDes are packaged with external pins on the top layer of the chip (shown as Ball type in the figure), and the remaining SerDes are not packaged with external pins on the top layer of the chip, and the SerDes are connected through the internal reference clock buffer module in a fixed direction. Each SerDes only uses the internal reference clock buffer module in the up and down directions. In this simplified solution, the enable signal of the control and management unit topCCU is not necessary, and the first enable signal and the second enable signal can be set to fixed values.

[0076] In the above simplified solution, only the external reference clock buffer modules of some SerDes are packaged with external pins on the top layer of the chip. Then, at the board level, the clock signal of the external clock source is only input on the external pins of the fixed SerDes, and the clock transfer relationship between the SerDes inside the chip can also be fixed. As Figure 6 shown, the SerDes that receive the clock signal from the external clock source only output the clock signal to the adjacent SerDes in the up and down directions. In this way, the enable signal of each SerDes can also be fixed. Therefore, the control and management unit can be not used, and the enable signal can be set to a fixed value.

[0077] The solution of this application has at least the following advantages compared with the related art:

[0078] The chip architecture of the solution of this application is more flexible, which can facilitate the adjustment of the clock signal distribution scheme. The top-level integration of chip design is simple. It only needs to complete the differential clock connection between SerDes and perform simple control. In implementation, the buffer is built into the SerDes, and its position depends on the package layout of the SerDes. It does not occupy the top-level wiring resources, the area is more optimized, and it will not affect the surrounding layout. It is especially suitable for chips with tight top-level routing resources and ultra-large scale, and there is no need to process the differential clock network at the top level, which can reduce the physical implementation difficulty and significantly shorten the development cycle.

[0079] Correspondingly, this application also exemplarily proposes a clock distribution method, which is implemented on the chip described in the above embodiments, including:

[0080] Output a first enable signal and a second enable signal to the high-speed serial communication interface on the chip;

[0081] Among them, the first enable signal and the second enable signal cooperate so that the high-speed serial communication interface receives a clock signal from an external pin through an external reference clock buffer module under the control of the first enable signal or receives a clock signal from other high-speed serial communication interfaces through an internal reference clock buffer module under the control of the second enable signal, and / or some high-speed serial communication interfaces also output a clock signal to other high-speed serial communication interfaces through the internal reference clock buffer module under the control of the second enable signal.

[0082] The above method can be implemented by the chip provided in the above embodiments. The specific implementation method can refer to the description of the chip in the above embodiments and will not be elaborated here.

[0083] It can be understood that the circuit structures, names, and parameters described in the above embodiments are only examples. Those skilled in the art can also easily combine and adjust the structural features of the above multiple embodiments according to actual needs, and should not limit the concept of this application to the specific details of the above examples.

[0084] Although this application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A high-speed serial communication interface, characterized in that: include: An internal-external interconnection module, at least one internal reference clock buffer module and an external reference clock buffer module; the external reference clock buffer module is connected to the internal-external interconnection module, and the internal-external interconnection module is connected to the at least one internal reference clock buffer module; The external reference clock buffer module is used to receive the clock signal of the external clock source and output it to the internal and external interconnection module; The at least one internal reference clock buffer module is used to receive a clock signal from other high-speed serial communication interfaces and output it to the internal and external interconnection module, or output the clock signal received from the internal and external interconnection module to other high-speed serial communication interfaces; The internal-external interconnection module is used to use the clock signal received from the external reference clock buffer module, or the clock signal received from the at least one internal reference clock buffer module as a reference clock of the high-speed serial communication interface.

2. The high-speed serial communication interface according to claim 1, characterized in that: The internal-external interconnection module also outputs the received clock signal to one or more of the at least one internal reference clock buffer module.

3. The high-speed serial communication interface according to claim 1 or 2, characterized in that: Under the control of the first enable signal, the external reference clock buffer module receives a clock signal from an external clock source and outputs it to the internal and external interconnection module; Under the control of the second enable signal, the at least one internal reference clock buffer module receives a clock signal from other high-speed serial communication interfaces and outputs it to the internal-external interconnection module, or outputs the clock signal received from the internal-external interconnection module to other high-speed serial communication interfaces.

4. The high-speed serial communication interface according to claim 1 or 2, characterized in that: After the high-speed serial communication interface is integrated and packaged in a chip, the top layer of the chip packages out external pins electrically connected to the external reference clock buffer module.

5. The high-speed serial communication interface according to claim 1 or 2, characterized in that: When there are multiple internal reference clock buffer modules, the multiple internal reference clock buffer modules are distributed in different directions of the edge of the high-speed serial communication interface.

6. A chip, characterized in that: Comprising one or more high-speed serial communication interfaces as described in any one of claims 1-5.

7. The chip according to claim 6, characterized in that: The high-speed serial communication interface includes at least one first high-speed serial communication interface and at least one second high-speed serial communication interface; after the first high-speed serial communication interface is packaged in the chip, it is electrically connected to the external pins packaged on the top layer of the chip; after the second high-speed serial communication interface is packaged in the chip, the clock signal line of the second high-speed serial communication interface is not electrically connected to the external pins packaged on the top layer of the chip.

8. The chip according to claim 7, characterized in that: At least one internal reference clock buffer module of the first high-speed serial communication interface is connected to at least one of the second high-speed serial communication interfaces; The external reference clock buffer module of the first high-speed serial communication interface receives a clock signal from the external pin, and outputs the clock signal to the internal-external interconnection module; The at least one internal reference clock buffer module of the first high-speed serial communication interface receives the clock signal from the internal-external interconnection module, and outputs the clock signal to the connected second high-speed serial communication interface.

9. The chip according to claim 8, characterized in that: The same second high-speed serial communication interface is connected to one of the first high-speed serial communication interfaces or to other second high-speed serial communication interfaces; wherein the second high-speed serial communication interface connected to other second high-speed serial communication interfaces receives a clock signal from the other second high-speed serial communication interfaces.

10. The chip according to any one of claims 6 to 9, characterized in that: Also includes: A control management unit; the control management unit is used to output a first enable signal and / or a second enable signal to one or more of the high-speed serial communication interfaces; Among them, the control management unit controls the high-speed serial communication interface through the first enable signal and the second enable signal to receive the clock signal from the external pin through the external reference clock buffer module under the control of the first enable signal, or to receive the clock signal from other high-speed serial communication interfaces through the internal reference clock buffer module under the control of the second enable signal, and / or the control management unit also controls part of the high-speed serial communication interface to output the clock signal to other high-speed serial communication interfaces through the internal reference clock buffer module through the second enable signal.

11. A clock distribution method, characterized in that: The method is implemented on the chip according to any one of claims 6 to 10, comprising: Outputting a first enable signal and a second enable signal to a high-speed serial communication interface on the chip; Among them, the first enable signal and the second enable signal cooperate so that the high-speed serial communication interface receives a clock signal from an external pin through the external reference clock buffer module under the control of the first enable signal, or receives a clock signal from other high-speed serial communication interfaces through the internal reference clock buffer module under the control of the second enable signal, and / or part of the high-speed serial communication interface also outputs a clock signal to other high-speed serial communication interfaces through the internal reference clock buffer module under the control of the second enable signal.

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