Memristive neural network circuit with partially enhanced operational conditioned reflex

Abstract

The invention discloses a memristive neural network circuit with partially enhanced operational conditioned reflex. The memristive neural network circuit comprises a pressing module, a satiety module, an award module and a synaptic module, the synapse module is connected with the reward module, and the reward module comprises a pressing module and a satiety module. By adopting the technical scheme of the invention, the control of the enhancement rate and the inhibition rate of the behavior by rewards with different frequencies in the operational conditioned reflex of the circuit is realized, and meanwhile, the circuit has certain adaptability to multiple reward stimulation in the behavior enhancement and behavior inhibition process.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit design, and particularly relates to a memristive neural network circuit with partially enhanced operant conditioning. Background Art

[0002] In recent years, with the rapid development of artificial neural network technology, the research on neuromorphic circuits has gradually become an important direction for simulating the neuron and synapse structures of the human brain. Traditional artificial neural network circuits constructed based on CMOS technology have many problems such as low integration and high energy consumption. As a new type of electronic component, the memristor has gradually become an important part of current neural network research due to its remarkable advantages of memory, low power consumption, and good integration.

[0003] The memristor has characteristics highly similar to biological synapses, such as non-volatility, non-linearity, low power consumption, and good scalability, which makes it show great potential in simulating biological synapses. Therefore, the memristor is widely used in many research fields such as memristive neural networks and associative memory circuits. With the continuous development of memristor technology, its application prospects in neural networks are also becoming more and more extensive, becoming an important research direction for promoting neuromorphic computing and brain-like computing.

[0004] Associative memory is a process of associating information together for memory according to the relevance between things. It can be divided into two categories, one is classical conditioning, and the other is operant conditioning. Operant conditioning was proposed by psychologist Skinner to explain the learning process of behavior. It emphasizes that by strengthening or punishing the consequences of behavior, the occurrence frequency of behavior can be affected. Currently, operant conditioning is one of the research hotspots in artificial neural networks.

[0005] At present, many operant conditioning circuits based on memristors have been proposed. Publication No.: CN202410956651 only considers simple operant conditioning, does not add the function of partial reinforcement, and does not consider the different effects of different interval durations on the maintenance rate of pressing the lever. Currently, for operant conditioning circuits, the behavior maintenance rate is affected by changing the reward intensity or reward type, lacking consideration of the impact of the intermittency of rewards on the behavior maintenance rate. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a memristive neural network circuit with partially enhanced operant conditioning.

[0007] To achieve the above object, the present invention adopts the following technical solutions: A memristive neural network circuit with partially enhanced operant conditioning, comprising: a pressing module, a satiety module, a reward module, and a synaptic module; the synaptic module is connected to the reward module, and the reward module includes: the pressing module and the satiety module; wherein, The pressing module is composed of a first capacitor C1, a second capacitor C2, a third capacitor C3, a first comparator OP1, a second comparator OP2, a third comparator OP3, a first 555 timer TIMER1, a thirteenth resistor R13, and a fourteenth resistor R14; wherein, the analog pressing signal N1 is connected to the inverting input terminal of the first comparator OP1, the output terminal of the first comparator OP1 is connected to the input terminal of the third capacitor C3, the output terminal of the third capacitor C3 is connected to the inverting input port of the second comparator and the input terminal of the thirteenth resistor R13, the output terminal of the thirteenth resistor R13 is connected to the input terminals of the first capacitor C1, the second capacitor C2, and the 1 port of the first 555 timer TIMER1, the output terminal of the second comparator is connected to the 2 port of the first 555 timer TIMER1, and the 3 port of the first 555 timer TIMER1 is connected to the non-inverting input terminal of the third comparator; The satiety module is composed of a third NOT gate NOT3, a first NMOS transistor T1, a second adder SUM2, a first memristor M1, a fifth operational amplifier OP5, a first memristor R1, a first digital arithmetic unit ABM1, and a first voltage-controlled switch S1; wherein, the output terminal of the third NOT gate NOT3 is connected to the G pole of the first NMOS transistor T1, the D pole of the first NMOS transistor T1 is connected to the input terminal of the second adder SUM2, the output terminal of the second adder SUM2 is connected to the input terminal of the first memristor M1 and the 2 input terminal of the first digital arithmetic unit ABM1, the reverse segment of the first memristor M1 is connected to the inverting input terminal of the fifth operational amplifier OP5, the output terminal of the fifth operational amplifier OP5 is connected to the 1 input terminal of the first digital arithmetic unit ABM1, and the output terminal of the first digital arithmetic unit ABM1 is connected to the input terminal of the first voltage-controlled switch; The reward module is composed of a second AND gate AND2, a third AND gate AND3, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a fourth adder OP4; wherein, the output terminal of the second AND gate AND2 is connected to the output terminal of the second resistor R2, the output terminal of the third AND gate AND3 is connected to the input terminal of the third resistor R3, and the output terminal of the second resistor R2 is connected to the non-inverting input terminal of the fourth adder OP4; The synaptic module consists of a first NOT gate NOT1, a second NOT gate NOT2, a first AND gate AND1, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a sixth adder OP6, a seventh operational amplifier OP7, a second memristor M2, and a second digital arithmetic unit ABM2. Among them, the input terminal of the first NOT gate is connected to the signal N2 indicating that a reward appears after pressing twice, the input terminal of the second NOT gate is connected to the signal N3 indicating that a reward appears after pressing four times. The output terminals of the first NOT gate NOT1 and the second NOT gate NOT2 are respectively connected to the two input terminals of the first AND gate AND1. The output terminal of the first AND gate AND1 is connected to the input terminal of the seventh resistor R7. The output terminal of the seventh resistor R7 is connected to the positive input terminal of the sixth adder OP6. The output terminal of the sixth adder OP6 is connected to the input terminal of the memristor M2. The output terminal of the memristor M2 is connected to the negative input terminal of the seventh operational amplifier OP7. The output terminal of the seventh operational amplifier OP7 is connected to the 1 input terminal of the second digital arithmetic unit ABM2. The output terminal of the sixth adder OP6 is connected to the 2 input terminal of the second digital arithmetic unit ABM2. The output terminal of the second digital arithmetic unit is connected to the maintenance rate signal N4.

[0008] Preferably, in the pressing module, when the pressing signal N1 is at a high level and simultaneously N1 > 1V, the output of OP1 changes from a high level to a low level. At this time, C3 and R13 generate a falling-edge voltage, and at the same time, OP2 generates a rising-edge voltage. And the monostable flip-flop is triggered by the falling edge. The 3 port of the 555 timer outputs a low level. After passing through the comparator OP3, the signal VOP3 output by the comparator OP3 outputs a low level. When N1 changes from a high level to a low level, this is a falling-edge level. OP1 outputs a high level, and OP2 outputs a low level. At this time, the PIN3 pin of the monostable flip-flop outputs a high level, and the duration of the high level is determined by the magnitudes of R14 and C1.

[0009] Preferably, in the satiety module, whenever the signal N2 indicating that a reward appears after pressing twice or the signal N3 indicating that a reward appears after pressing four times appears, the voltage-controlled switch S1 conducts. And this voltage, after passing through SUM1 and SUM2, acts on the memristor M1 and ABM1. The voltage signal VOP5 output by the operational amplifier OP5 acts on the digital arithmetic circuit ABM1 to represent the resistance value of M1 by the output of ABM1. When both N2 and N3 are at a low level, there is no food reward at this time. NOT3 conducts and outputs a high-level voltage to act on the gate of the NMOS. At this time, the MOS transistor conducts and outputs a voltage. This voltage causes the memristance value of M1 to continuously increase and gradually return to the initial value, and VABM1 continuously increases, and the satiety gradually returns to the initial state.

[0010] Preferably, in the reward module, the reward signal N2 represents that a food reward is generated every two presses of the lever, and a high-level pulse is output; the reward signal N3 represents that a food reward is generated every four presses, and a high-level pulse is output; when the output signal VOP3 of the comparator OP3 and the reward signal N2 are at a high level, AND2 conducts and outputs a 10V voltage, and the reward voltage is output through the adder; when the output signal VOP3 of the pressing module and the reward signal N3 are at a high level, at this time AND3 outputs a 4V voltage, and this voltage also passes through the adder OP4 and is output as the reward voltage.

[0011] Preferably, in the synapse module, when the voltage signal VOP4 output by the adder OP4 is input to OP6, at this time the output of OP6 causes the memristance value of M2 to decrease, and the voltage value output after passing through OP7 and ABM2 continuously decreases, indicating that the pressing frequency of the mouse is continuously increasing.

[0012] Based on the psychological phenomenon of "partial reinforcement" and other factors, the memristive neural network circuit of the present invention realizes the control of the reinforcement rate and inhibition rate of different frequencies of rewards on behavior in operant conditioning. In addition, a satiety circuit is applied to this circuit, enabling the circuit to have a certain adaptability to multiple reward stimuli during the processes of behavior reinforcement and behavior inhibition. The circuit is closer to actual applications, more in line with biological characteristics, and can adapt to more complex scenarios, providing more references for the further development of neural networks for operant conditioning. Description of the Drawings

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to the provided drawings.

[0014] Figure 1 It is a graph of the change in memristance value under different voltages; Figure 2 It is a schematic structural diagram of the memristive neural network circuit of the present invention with operant conditioning of partial reinforcement; Figure 3 It is a simulation process diagram of operant conditioning where an electric shock punishment is received every two presses; Figure 4 It is a simulation process diagram of operant conditioning where an electric shock punishment is received every four presses. Detailed Embodiments

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0016] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] Embodiment 1: As Figure 1 shown, Figure 1 It is a curve graph of the selected memristors M1 and M2 under different voltages. It can be seen from the graph that the greater the voltage input to the memristor, the faster the resistance value of the memristor decreases. If a reverse voltage is applied, the resistance value of the memristor will increase.

[0018] As Figure 2 shown, the embodiment of the present invention provides a memristive neural network circuit with partially enhanced operant conditioning, including: a pressing module, a satiety module, a reward module, and a synaptic module; the synaptic module is connected to the reward module, and the reward module includes: a pressing module and a satiety module. Among them, As an implementation manner of the embodiment of the present invention, the pressing module is composed of a first capacitor C1, a second capacitor C2, a third capacitor C3, a first comparator OP1, a second comparator OP2, a third comparator OP3, a first 555 timer TIMER1, a thirteenth resistor R13, and a fourteenth resistor R14; wherein, the analog pressing signal N1 is connected to the inverting input terminal of the first comparator OP1, the output terminal of the first comparator OP1 is connected to the input terminal of the third capacitor C3, the output terminal of the third capacitor C3 is connected to the inverting input port of the second comparator and the input terminal of the thirteenth resistor R13, the output terminal of the thirteenth resistor R13 is connected to the input terminals of the first capacitor C1, the second capacitor C2, and the 1 port of the first 555 timer TIMER1, the output terminal of the second comparator is connected to the 2 port of the first 555 timer TIMER1, and the 3 port of the first 555 timer TIMER1 is connected to the non-inverting input terminal of the third comparator; The satiety module is composed of a third NOT gate NOT3, a first NMOS transistor T1, a second adder SUM2, a first memristor M1, a fifth operational amplifier OP5, a first memristor R1, a first digital arithmetic unit ABM1, and a first voltage-controlled switch S1. Among them, the output terminal of the third NOT gate NOT3 is connected to the G pole of the first NMOS transistor T1, the D pole of the first NMOS transistor T1 is connected to the input terminal of the second adder SUM2, the output terminal of the second adder SUM2 is connected to the input terminal of the first memristor M1 and the 2 input terminal of the first digital arithmetic unit ABM1, the reverse segment of the first memristor M1 is connected to the reverse input terminal of the fifth operational amplifier OP5, the output terminal of the fifth operational amplifier OP5 is connected to the 1 input terminal of the first digital arithmetic unit ABM1, and the output terminal of the first digital arithmetic unit ABM1 is connected to the input terminal of the first voltage-controlled switch. The reward module is composed of a second AND gate AND2, a third AND gate AND3, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a fourth adder OP4. Among them, the output terminal of the second AND gate AND2 is connected to the output terminal of the second resistor R2, the output terminal of the third AND gate AND3 is connected to the input terminal of the third resistor R3, and the output terminal of the second resistor R2 is connected to the positive input terminal of the fourth adder OP4. The synaptic module is composed of a first NOT gate NOT1, a second NOT gate NOT2, a first AND gate AND1, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a sixth adder OP6, a seventh operational amplifier OP7, a second memristor M2, and a second digital arithmetic unit ABM2. Among them, the input terminal of the first NOT gate is connected to the signal N2 indicating that a reward appears after pressing twice, the input terminal of the second NOT gate is connected to the signal N3 indicating that a reward appears after pressing four times, the output terminals of the first NOT gate NOT1 and the second NOT gate NOT2 are respectively connected to the two input terminals of the first AND gate AND1, the output terminal of the first AND gate AND1 is connected to the input terminal of the seventh resistor R7, the output terminal of the seventh resistor R7 is connected to the positive input terminal of the sixth adder OP6, the output terminal of the sixth adder OP6 is connected to the input terminal of the memristor M2, the output terminal of the memristor M2 is connected to the reverse input terminal of the seventh operational amplifier OP7, the output terminal of the seventh operational amplifier OP7 is connected to the 1 input terminal of the second digital arithmetic unit ABM2, the output terminal of the sixth adder OP6 is connected to the 2 input terminal of the second digital arithmetic unit ABM2, and the output terminal of the second digital arithmetic unit is connected to the maintenance rate signal N4.

[0019] As an implementation manner of the embodiment of the present invention, in the pressing module, when the pressing signal N1 is at a high level, since N1 > Vth1 = 1V, the output of OP1 changes from a high level to a low level. At this time, C3 and R13 generate a falling-edge voltage, and at the same time, OP2 generates a rising-edge voltage. Since the monostable flip-flop is triggered by a falling edge, the output of the 3-port of the 555 timer is at a low level. After passing through the comparator OP3, the signal VOP3 output by the comparator OP3 is at a low level. When N1 changes from a high level to a low level, this is a falling-edge level. OP1 outputs a high level, and OP2 outputs a low level. At this time, the PIN3 pin of the monostable flip-flop outputs a high level, and the duration of the high level is determined by the sizes of R14 and C1.

[0020] In the satiety module, whenever the reward signal N2 that appears when pressing 2 times or the reward signal N3 that appears when pressing 4 times appears, the voltage-controlled switch S1 conducts, and this voltage acts on the memristor M1 and ABM1 after passing through SUM1 and SUM2. The voltage signal VOP5 output by the operational amplifier OP5 acts on the digital arithmetic circuit ABM1, and the output of ABM1 represents the resistance value of M1. For example, when M1 is 1KΩ, the output voltage is 1V at this time. As the output signal of SUM2 continuously acts on the memristor M1, the memristance value of M1 continuously decreases, and VABM1 also continuously decreases. At this time, it means that the stimulation degree of food reward to the mouse is continuously decreasing. The voltage output by ABM1 is output as the reward voltage. When both N2 and N3 are at a low level, there is no food reward at this time, NOT3 conducts, and outputs a high-level voltage to act on the gate of the NMOS. At this time, the MOS transistor conducts and outputs a voltage, and the voltage makes the memristance value of M1 continuously increase and gradually return to the initial value, VABM1 continuously increases, and the satiety also gradually returns to the initial state.

[0021] In the reward module, the reward signal N2 represents that a food reward is generated every time the lever is pressed twice, and a high-level pulse is output. The reward signal N3 represents that a food reward is generated every time the lever is pressed four times, and a high-level pulse is output. When the signal VOP3 output by the comparator OP3 and the reward signal N2 are at a high level, AND2 conducts and outputs a 10V voltage, and the reward voltage is output through the adder. When the signal VOP3 output by the comparator OP3 and the reward signal N3 are at a high level, at this time AND3 outputs a 4V voltage, and this voltage also passes through the adder OP4 and is output as the reward voltage. The voltages output by AND2 and AND3 with different amplitudes respectively indicate that the stimulation degrees of different reward frequencies to the mouse are different, and at the same time, it also reflects some psychological phenomena of behavior.

[0022] In the synaptic module, when the voltage signal VOP4 output by the adder OP4 is input to OP6, the output of OP6 at this time causes the memristance value of M2 to decrease. The voltage value output after passing through OP7 and ABM2 also continuously decreases, indicating that the pressing frequency of the mouse continuously increases.

[0023] In addition, the embodiment of the present invention also considers its own adaptive regulation, such as the influence of satiety level on food reward stimulation. During the process of giving food rewards, the intensity of positive feedback is also affected by satiety. When the reward signals N2 and N3 generate a positive pulse once, the voltage-controlled switch S1 conducts and acts on the memristor M1. The resistance value of the memristor M1 continuously decreases, and the output of VABM1 also continuously decreases, thereby achieving an inhibitory effect.

[0024] By simulating the reward signals N2 and N3, that is, when the reward signal N2 or the reward signal N3 is at a high level, AND2 or AND3 is at a high level, and different voltage magnitudes are output to act on OP4 to achieve a strengthening function.

[0025] By controlling the changes in the resistance values of the memristors M1 and M2 to control the output situation of the entire circuit, thereby achieving the self-adaptive regulation of the circuit, such as the influence of satiety level on food reward stimulation, and realizing the psychological effect of partial reinforcement.

[0026] The present invention will conduct an example analysis on two scenarios: the simulation of operant conditioning where the mouse is electrically stimulated every two presses and the simulation of operant conditioning where the mouse is electrically stimulated every four presses.

[0027] As Figure 3 shown, it is the process diagram of the simulation of operant conditioning where the mouse is electrically stimulated every two presses. The specific process is as follows: Behavior reinforcement stage with electrical stimulation after pressing twice: From 0 to 48 s is the process of reinforcing the behavior of the mouse pressing the lever. When the lever is pressed, N1 generates a high-level pulse of 5 V. At the same time, after the lever is pressed, OP3 is also activated and generates a high-level voltage, which indicates that the neuron is active after the mouse presses the lever. At this time, giving a reward signal will have a certain impact on the mouse's behavior. N2 is the reward signal 1, and this signal will generate a food reward every time the lever is pressed twice. When N2 and OP3 are both at a high level, OP6 generates a reward voltage, which is output to the synaptic module, causing the memory resistance value of M2 to decrease. Since the voltage output by ABM2 is proportional to M2, the output voltage VOUT of ABM2 is the maintenance rate of the mouse pressing the lever. The smaller the output voltage, the higher the maintenance rate of the mouse pressing the lever. In this simulation process, the output of VOUT finally decreases to about 3.0 V. At the same time, after the mouse receives the food reward, the mouse will have a certain sense of satiety. Therefore, after receiving the food reward, the memory resistance value of M1 will continuously decrease, and at this time, the satiety voltage is also decreasing. Therefore, after receiving the food reward, due to the influence of satiety, the output of OP6 will also decrease. When the mouse does not receive the food reward, the memory resistance value of M1 will continuously increase, and the mouse's satiety will gradually recover.

[0028] Behavior inhibition stage with electrical stimulation after pressing twice: From 48 to 70 s is the behavior inhibition stage of the mouse. This stage is a natural inhibition stage where no reward is generated when the mouse presses the lever. When N1 is activated, OP3 generates a high-level voltage, and the neuron is active. Since the reward signal N2 is in an inactive state, the mouse's behavior is also inhibited. At this time, the punishment voltage output by OP6 is -2 V, which is output to the synaptic module, causing the resistance value of the memristor M2 to continuously increase, and VOUT also continuously increases, and the frequency of the mouse pressing the lever continuously decreases. At the same time, since the mouse has not received the food reward all the time, the mouse's satiety decreases, and the sensitivity to the food reward will continuously increase and gradually return to the initial state.

[0029] As Figure 4 shown, it is a simulation process diagram of operant conditioning with electrical stimulation punishment every four presses. The specific process is as follows: Behavior reinforcement stage with four presses under electrical stimulation: From 0 to 48 s is the process of positive reinforcement for the behavior of the mouse pressing the lever. In this process, the mouse receives food rewards every 4 times it presses the lever. When N1 is activated, OP3 generates a high level, and the neuron is in an active state. After N1 generates 4 pulses, N3 is activated and generates high-level pulses, indicating the generation of food rewards. At the same time, OP6 generates a reward voltage and outputs it to the synaptic module, acting on the memristor M2, causing the memristance value of M2 to continuously decrease. Since the output voltage VOUT of ABM2 is proportional to the memristance value of M2, the output voltage VOUT also continuously decreases, indicating that the maintenance rate of the mouse's behavior of pressing the lever is continuously increasing. At 48 s, VOUT decreases to about 2.5 V. Due to the influence of the psychological effect of partial reinforcement, intermittent rewards often cause the mouse to exhibit stronger and more persistent behavior. Therefore, compared with the reinforcement effect of the mouse receiving food rewards for pressing the lever twice, the reward stimulus generated by pressing the lever four times is greater. Therefore, the output voltage of OP6 is smaller. A smaller reward voltage will cause M2 to decrease more rapidly, and at the same time, the behavior maintenance rate VOUT will also decrease more rapidly. The value of VOUT at 48 s is 2.5 V, and this voltage value indicates that the mouse will press the lever more frequently, which also corresponds to the psychological phenomenon of partial reinforcement. When the mouse receives food rewards, the satiety module will also be activated, causing the memristance value of M1 to decrease and the satiety voltage to decrease, indicating that the degree of stimulation of the mouse by food rewards is also decreasing.

[0030] Behavior inhibition stage with four presses under electrical stimulation: From 48 to 70 s is the simulation process of behavior inhibition. When the mouse presses the lever, N1 is activated, and the mouse neuron is in an active state. At this time, OP3 also generates a high-level voltage, but since N3 does not generate a reward signal, the mouse undergoes natural behavior inhibition, causing the memristance value of M2 to continuously increase and the output voltage of VOUT to also continuously increase. At this time, the behavior frequency continuously decreases, achieving the effect of behavior inhibition.

[0031] The present invention separately sets up experimental environments where the mouse gets food when pressing the lever twice and when pressing the lever four times. The present invention introduces the regulation of satiety, making the circuit more in line with biological characteristics and also more adaptable to different environments. The present invention can not only simulate and achieve adaptive regulation but also achieve the partial reinforcement function, and can effectively simulate the different effects of different interval durations on the maintenance rate of lever pressing. Taking the two-interval and four-interval as examples, the present invention has a simple structure and perfect functions, and is of great significance for the research of memristor bionic circuits.

[0032] The embodiments described above are only descriptions of the preferred embodiments of the present invention, and do not limit the scope of the present invention. Without departing from the design spirit of the present invention, various deformations and improvements made by those of ordinary skill in the art to the technical solutions of the present invention shall fall within the protection scope determined by the claims of the present invention.

Claims

1. A memristor neural network circuit with partially enhanced operant conditioning, characterized in that: include: Press module, satiety module, reward module and synapse module; The synapse module is connected to the reward module, which includes a pressing module and a satiety module; wherein, The pressing module is composed of a first capacitor C1, a second capacitor C2, a third capacitor C3, a first comparator OP1, a second comparator OP2, a third comparator OP3, a first 555 timer TIMER1, a thirteenth resistor R13, and a fourteenth resistor R14; wherein the analog pressing signal N1 is connected to the reverse input terminal of the first comparator OP1, the output terminal of the first comparator OP1 is connected to the input terminal of the third capacitor C3, the output terminal of the third capacitor C3 is connected to the reverse input port of the second comparator and the input terminal of the thirteenth resistor R13, the output terminal of the thirteenth resistor R13 is connected to the input terminals of the first capacitor C1, the second capacitor C2 and the 1st port of the first 555 timer TIMER1, the output terminal of the second comparator is connected to the 2nd port of the first 555 timer TIMER1, and the 3rd port of the first 555 timer TIMER1 is connected to the positive input terminal of the third comparator; The satiety module is composed of a third NOT gate NOT3, a first NMOS tube T1, a second adder SUM2, a first memristor M1, a fifth operational amplifier OP5, a first memristor R1, a first digital operation unit ABM1, and a first voltage-controlled switch S1; wherein the output end of the third NOT gate NOT3 is connected to the G pole of the first NMOS tube T1, the D pole of the first NMOS tube T1 is connected to the input end of the second adder SUM2, the output end of the second adder SUM2 is connected to the input end of the first memristor M1 and the 2 input end of the first digital operation unit ABM1, the reverse segment of the first memristor M1 is connected to the reverse input end of the fifth operational amplifier OP5, the output end of the fifth operational amplifier OP5 is connected to the 1 input end of the ABM1 of the first digital operation unit, and the output end of the first digital operation unit ABM1 is connected to the input end of the first voltage-controlled switch; The reward module is composed of a second AND gate AND2, a third AND gate AND3, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a fourth adder OP4; wherein the output end of the second AND gate AND2 is connected to the output end of the second resistor R2, the output end of the third AND gate AND3 is connected to the input end of the third resistor R3, and the output end of the second resistor R2 is connected to the positive input end of the fourth adder OP4; The synaptic module is composed of a first NOT gate NOT1, a second NOT gate NOT2, a first AND gate AND1, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a sixth adder OP6, a seventh operational amplifier OP7, a second memristor M2, and a second digital operation unit ABM2; wherein, the input end of the first NOT gate is connected to a signal N2 indicating a reward appears when pressing twice, the input end of the second NOT gate is connected to a signal N3 indicating a reward appears when pressing four times, and the output ends of the first NOT gate NOT1 and the second NOT gate NOT2 are connected to the respective Two input terminals of the first AND gate AND1 and an output terminal of the first AND gate AND1 are connected to an input terminal of the seventh resistor R7, an output terminal of the seventh resistor R7 is connected to a positive input terminal of the sixth adder OP6, an output terminal of the sixth adder OP6 is connected to an input terminal of the memristor M2, an output terminal of the memristor M2 is connected to a reverse input terminal of the seventh operational amplifier OP7, an output terminal of the seventh operational amplifier OP7 is connected to an input terminal 1 of the second digital operation unit ABM2, an output terminal of the sixth adder OP6 is connected to an input terminal 2 of the second digital operation unit ABM2, and an output terminal of the second digital operation unit is connected to a maintenance rate signal N4.

2. The memristor neural network circuit with partially enhanced operant conditioning as claimed in claim 1, characterized in that: In the pressing module, when the pressing signal N1 is at a high level and N1>1V, the output of OP1 changes from a high level to a low level. At this time, C3 and R13 generate a falling edge voltage, and OP2 generates a rising edge voltage, and the monostable trigger is triggered by a falling edge. Port 3 of the 555 timer outputs a low level. After passing through the comparator OP3, the signal VOP3 output by the comparator OP3 outputs a low level. When N1 changes from a high level to a low level, it is a falling edge level. OP1 outputs a high level and OP2 outputs a low level. At this time, the monostable trigger PIN3 pin outputs a high level, and the duration of the high level is determined by the size of R14 and C1.

3. The memristor neural network circuit with partially enhanced operant conditioning as claimed in claim 2, characterized in that: In the satiety module, whenever the reward signal N2 appears when pressing twice or the reward signal N3 appears when pressing four times, the voltage-controlled switch S1 is turned on, and the voltage acts on the memristor M1 and ABM1 after passing through SUM1 and SUM2. The voltage signal VOP5 output by the operational amplifier OP5 acts on the digital operation circuit ABM1, and the output of ABM1 represents the resistance value of M1; when N2 and N3 are both low levels, there is no food reward at this time, NOT3 is turned on, and a high-level voltage is output to act on the gate of NMOS. At this time, the MOS tube is turned on and outputs a voltage. The voltage causes the memristor value of M1 to increase continuously and gradually recover to the initial value, VABM1 increases continuously, and the satiety gradually recovers to the initial state.

4. The memristor neural network circuit with partially enhanced operant conditioning as claimed in claim 3, characterized in that: In the reward module, the reward signal N2 represents that a food reward is generated every time the lever is pressed twice, and a high-level pulse is output; the reward signal N3 represents that a food reward is generated every time the lever is pressed four times, and a high-level pulse is output; when the output signal VOP3 of the comparator OP3 and the reward signal N2 are at a high level, AND2 is turned on and outputs a 10V voltage, and outputs the reward voltage through the adder; when the output signal VOP3 of the pressing module and the reward signal N3 are at a high level, AND3 outputs a 4V voltage, which also passes through the adder OP4 and is output as a reward voltage.

5. The memristor neural network circuit with partially enhanced operant conditioning as claimed in claim 4, characterized in that: In the synaptic module, when the voltage signal VOP4 output by the adder OP4 is input to OP6, the output of OP6 reduces the memristor value of M2, and the output voltage value after passing through OP7 and ABM2 continues to decrease, which means that the pressing frequency of the mouse continues to increase.

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