Covalently functionalized mxene artificial synapse and method of making the same

Abstract

The application discloses a kind of covalent functionalization MXene artificial synapse and preparation method thereof, it is related to the technical field of artificial intelligence, the present application aims at solving how to enrich the overall characteristics of brain-like neural chip, promote artificial intelligence technology problem, the present application includes including following steps: selecting substrate;Utilize photoetching process on the substrate on gate, source and drain are patterned and are handled, in utilizing electron beam evaporation deposition metal layer and stripping obtains metal electrode pattern;Utilize photoetching process on the substrate on channel region is patterned and is handled;MAX phase material is obtained by in-situ acid etching combined with mechanical stripping few-layer T X MXene;Form uniform T i3C2T X MXene film on the substrate by coating process, and obtain channel region pattern by stripping;Preparation of iodonium salt solution, prepared device is immersed in iodonium salt solution so that it is completed covalent functionalization;Preparation of electrolyte solution, on T i3C2T X MXene channel layer, gate and exposed substrate drop casting electrolyte.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence technology, specifically to a covalently functionalized MXene artificial synapse and its preparation method. Background Technology

[0002] With the rapid development of artificial intelligence, the demand for various intelligent tasks, from real-time big data and motion control to visual and auditory recognition, is exploding worldwide. However, the traditional von Neumann architecture currently in use has become a bottleneck because of its limited parallel computing capabilities and high power consumption when processing big data. This is due to the need for data transfer between physically separated processing units and memory via a data bus. Therefore, to successfully perform big data analysis, a new neuromorphic computing architecture has been developed. The key idea of ​​the new architecture is to compute data in memory without data transfer (or small-scale data movement), thereby reducing power consumption and suppressing latency through parallel data processing capabilities.

[0003] In the field of neuromorphic computing, specially designed hardware such as neuromorphic chips can mimic the functions of neurons and synapses in the human brain, enabling efficient parallel information processing and learning. Both two-terminal memristors and three-terminal neuromorphic transistors are suitable as simulation elements for artificial synapses and neurons. Artificial synapses driven by three-terminal electrolyte-gated transistors stand out due to their precise controllable conductance, fast response time, and stable electrical properties. They support synchronous learning processes, updating synaptic weights even as data transmission continues. MXene materials, as channel materials, offer advantages for the development of high-performance neuromorphic computing devices due to their low migration barrier, tunable surface properties, open interlayer structure, and ease of fabrication, foreshadowing widespread applications in simulating human brain intelligence.

[0004] However, current electrolyte-gated synaptic transistors based on MXene channel materials exhibit high postsynaptic currents and low synaptic plasticity. Therefore, opening the MXene bandgap and improving ion storage capacity by covalently functionalizing and grafting strong electron-withdrawing groups has become a way to improve the performance of MXene synaptic transistors. This is expected to greatly enrich the overall characteristics of neuromorphic chips and promote the development of artificial intelligence technology. Summary of the Invention

[0005] This invention proposes a covalently functionalized MXene artificial synapse, comprising, from bottom to top, a substrate layer, a source-gate-drain electrode layer, a channel layer, and an electrolyte layer; the channel layer is a covalently functionalized Ti3C2T iodomonium salt. X MXene.

[0006] This invention also proposes a method for preparing covalently functionalized MXene artificial synapses as described above, comprising the following steps:

[0007] S1: Select a substrate and clean the substrate;

[0008] S2: The gate, source and drain electrodes are patterned on the substrate using photolithography, and a metal layer is deposited by electron beam evaporation and then stripped to obtain the metal electrode pattern.

[0009] S3: The channel region is patterned on the substrate using photolithography and then hydrophilicized.

[0010] S4: Few-layer Ti3C2T was obtained by in-situ acid etching combined with mechanical exfoliation of MAX phase material. X MXene;

[0011] S5: A uniform Ti3C2T coating process is used to form a uniform Ti3C2T coating on the substrate. X MXene film, and obtained channel region pattern by peeling;

[0012] S6: Prepare an iodonium salt solution, immerse the device prepared in step S5 into the iodonium salt solution to complete covalent functionalization; after covalent functionalization, rinse the device repeatedly with acetonitrile and methanol solution, and then dry it with a nitrogen gun; finally, heat-treat it in a vacuum drying oven at 90℃ for 20 minutes to remove unevaporated solvent.

[0013] S7: Prepare electrolyte solution in Ti3C2T X An electrolyte is drop-cast onto the MXene channel layer, gate, and exposed substrate, with the electrolyte covering the channel layer cake and connecting to the gate, to construct a Ti3C2T. X MXene synaptic transistor.

[0014] A further provision of the present invention is that the substrate in step S1 is one of silicon oxide, glass, silicon carbide, or gallium nitride.

[0015] A further feature of the present invention is that the source, gate, and drain electrodes in step S2 are made of Cr / Au or Cr / Pt, with a thickness of 35nm-65nm.

[0016] A further provision of the present invention is that the hydrophilic treatment in step S3 is performed using ultraviolet ozone or oxygen plasma treatment.

[0017] A further configuration of the present invention is: the Ti3C2T in step S4 X The concentration of MXene is 1-20 mg / ml.

[0018] A further provision of the present invention is that the coating process in step S5 is one of spin coating, spray coating, or dip coating, forming Ti3C2T XThe thickness of MXene films ranges from 1 to 20 nm.

[0019] A further setting of the present invention is as follows: the iodonium salt in step S6 is any one of (perfluoropropyl)phenyliodonium trifluoromethanesulfonate, bis(3-(trifluoromethyl)phenyl)iodonium trifluoromethanesulfonate, 3,3'-dinitrodiphenyliodohexafluorophosphate, and (4-cyanophenyl)(trimethylmethyl)iodonium trifluoromethanesulfonate; the provided strong electron-withdrawing group is any one of perfluoropropyl group, trifluoromethylphenyl group, nitro group, and cyano group; the concentration of the iodonium salt solution is 5-15 mg / ml; and the immersion time is 30-90 min.

[0020] A further setting of the present invention is: the electrolyte in step S7 is PEO / LiClO4, PEO / LiClO4 is used as the lithium ion supply layer, and the mass ratio of PEO to LiClO4 is 2.5-5:1.

[0021] The beneficial effects of this invention are as follows:

[0022] 1. The method for covalent functionalization of iodonium salts provided by this invention involves a nucleophilic reaction in Ti3C2T X Introducing strong electron-withdrawing groups into the MXene surface opens up Ti3C2T X The band gap of Ti3C2T X Its electrical conductivity changes from that of a metalloid to that of a semiconductor.

[0023] 2. This invention modulates the channel current by controlling the migration behavior of lithium ions driven by an electric field, which can simulate the pulse quantity-dependent plasticity and pulse frequency-dependent plasticity of neural synapses, thereby achieving electrolyte-gated neural synapse biomimicry. Attached Figure Description

[0024] Figure 1 The Ti3C2T prepared according to the present invention is shown. X A schematic diagram of the MXene synaptic transistor.

[0025] Figure 2 The modified Ti3C2T prepared according to the present invention is shown. X REELS map.

[0026] Figure 3 The Ti3C2T prepared according to the present invention is shown. X The transfer characteristic curve of a synaptic transistor.

[0027] Figure 4 The Ti3C2T constructed according to the present invention is shown. X Excitatory postsynaptic current (EPSC) response and decay behavior when a single pulse is applied to a synaptic transistor.

[0028] Figure 5 The Ti3C2T constructed according to the present invention is shown. X The relationship between long-term boost (LTP) of synaptic transistors and gate pulse number.

[0029] Figure 6 The Ti3C2T constructed according to the present invention is shown. X The relationship between long duration enhancement (LTP) of synaptic transistors and gate pulse interval. Detailed Implementation

[0030] Those skilled in the art can refer to the content of this document and appropriately improve the process parameters to achieve the desired results. It should be particularly noted that all similar substitutions and modifications are obvious to those skilled in the art and are considered to be included in this invention. The methods and applications of this invention have been described through preferred embodiments. Those skilled in the art can make modifications or appropriate alterations and combinations to the methods and applications described herein without departing from the content, spirit, and scope of this invention to implement and apply the technology of this invention.

[0031] Example 1

[0032] This embodiment proposes a covalently functionalized MXene artificial synapse, which, from top to bottom, includes a substrate layer, a source-gate-drain electrode layer, a channel layer, and an electrolyte layer. The channel layer is covalently functionalized Ti3C2T. X MXene.

[0033] Example 2

[0034] This embodiment provides a method for preparing covalently functionalized MXene artificial synapses as described in Embodiment 1, comprising the following steps:

[0035] S1: Select a substrate and clean the substrate;

[0036] S2: The gate, source, and drain electrodes are patterned on the substrate using photolithography, and a metal layer is deposited by electron beam evaporation and then stripped to obtain the metal electrode pattern;

[0037] S3: The channel region is patterned on the substrate using photolithography and then hydrophilicated.

[0038] S4: Few-layer Ti3C2T was obtained by in-situ acid etching combined with mechanical exfoliation of MAX phase material. X MXene;

[0039] S5: A uniform Ti3C2T coating process is used to form a uniform Ti3C2T coating on the substrate. X MXene film, and the channel region pattern was obtained by peeling;

[0040] S6: Prepare an iodonium salt solution. Immerse the device prepared in step S5 into the iodonium salt solution to complete covalent functionalization. After covalent functionalization, rinse the device repeatedly with acetonitrile and methanol solution, and then dry it with a nitrogen gun. Finally, heat-treat it in a vacuum drying oven at 90°C for 20 minutes to remove unevaporated solvent.

[0041] S7: Prepare electrolyte solution in Ti3C2T X An electrolyte is drop-cast onto the MXene channel layer, gate, and exposed substrate, with the electrolyte covering the channel layer and connecting to the gate, to construct a Ti3C2T. X MXene synaptic transistor.

[0042] In step S1, the substrate can be any one of silicon oxide, glass, silicon carbide, or gallium nitride.

[0043] In step S2, the source, gate, and drain are made of Cr / Au or Cr / Pt materials, and their thickness is 35nm-65nm.

[0044] The hydrophilic treatment in step S3 uses ultraviolet ozone or oxygen plasma treatment.

[0045] The Ti3C2T in step S4 X MXene concentrations range from 1 to 20 mg / ml.

[0046] The coating process in step S5 can be any one of spin coating, spray coating, or dip coating, forming Ti3C2T X The thickness of MXene films ranges from 5 to 20 nm.

[0047] The iodonium salt in step S6 is any one of (perfluoropropyl)phenyliodonium trifluoromethanesulfonate, bis(3-(trifluoromethyl)phenyl)iodonium trifluoromethanesulfonate, 3,3'-dinitrodiphenyliodohexafluorophosphate, and (4-cyanophenyl)(trimethylmethyl)iodonium trifluoromethanesulfonate. The provided strong electron-withdrawing group is any one of perfluoropropyl group, trifluoromethylphenyl group, nitro group, and cyano group. The concentration of the iodonium salt solution is 5-15 mg / ml, and the immersion time is 30-90 min.

[0048] In step S7, the drop-cast electrolyte is PEO / LiClO4, with PEO / LiClO4 serving as the lithium-ion supply layer, and the mass ratio of PEO to LiClO4 is 2.5-5:1.

[0049] Example 3

[0050] like Figure 1 As shown, based on Ti3C2T XMXene's synaptic transistor has a side-gate structure, including a substrate, source (S), drain (D), gate (G), and Ti3C2T. X Channel layer and electrolyte layer, Ti3C2T X The channel layer is grafted with perfluoropropyl groups via a nucleophilic reaction.

[0051] The preparation method described in Example 2 specifically includes the following steps:

[0052] S1: Select a silicon oxide wafer as the substrate. Clean the 2×2cm silicon oxide wafer sequentially with acetone, isopropanol, and deionized water for 5 minutes each to remove contaminants from the substrate surface, and then dry it with nitrogen gas.

[0053] S2: Gate, source, and drain patterning;

[0054] S2-1: The source, gate, and drain electrodes are patterned on the substrate through steps such as spin-coating photoresist negative, pre-baking, ultraviolet exposure, post-baking, development, and fixing. The channel spacing between the source and drain electrodes is 5 μm, and the length is 100 μm.

[0055] S2-2: A Cr / Au metal layer is deposited on a substrate by electron beam evaporation, wherein the thickness of Cr is 5nm and the thickness of Au is 50nm.

[0056] S2-3: Immerse the substrate with the deposited metal layer in acetone at 95°C for 15 min, then in isopropanol for 1 min, and peel off to obtain a patterned metal electrode pattern.

[0057] S3: Patterning of the channel layer region;

[0058] S3-1: The channel region is patterned on the substrate by spin-coating photoresist positive resist, pre-baking, ultraviolet exposure, post-baking, development and fixing, wherein the area of ​​the channel region is 100μm×100μm.

[0059] S3-2: Place the substrate in an ultraviolet ozone generator for 20 minutes and perform hydrophilic treatment;

[0060] S4: Preparation of few-layer Ti3C2T X MXene;

[0061] S4-1: Weigh 1.6g LiF and add it to 20ml 9M HCl, then stir in a polytetrafluoroethylene beaker for 5min;

[0062] S4-2: Slowly add 1g of Ti3AlC2 powder to the above solution, place the polytetrafluoroethylene beaker in an oil bath at 40℃, and stir continuously for 30h;

[0063] S4-3: After the reaction is complete, the reaction mixture is washed 5-6 times with deionized water (centrifuged at 5000 rpm for 5 min), and the pH is adjusted to 6. The final precipitate with obvious swelling at the bottom is a multilayer Ti3C2T. X ;

[0064] S4-4: Add the above precipitate to 30 ml of deionized water, shake manually for 10 min, then pour into a gas washing bottle. Connect the long end to an inert gas, and sonicate for 50 min under aeration and flowing water conditions. Centrifuge the solution at 3500 rpm for 30 min to obtain a few-layer Ti3C2T. X MXene dispersion;

[0065] S5: Channel region Ti3C2T X Thin film preparation;

[0066] S5-1: A few layers of Ti3C2T X The MXene dispersion was diluted to 5 mg / ml;

[0067] S5-2: Set the spin coating parameters of the spin coater to spin coat at 1000 rpm for 10 seconds and at 3000 rpm for 30 seconds.

[0068] S5-3: After spin coating, place the device in a vacuum drying oven at 90°C for 20 minutes to evaporate the remaining solvent;

[0069] S5-4: Spin-coated Ti3C2T X The substrate of the thin film was immersed in acetone at 95°C for 15 min, followed by isopropanol for 1 min, and then peeled off to obtain patterned Ti3C2T. X Ditch area.

[0070] S6: Covalent functionalization of iodonium salts;

[0071] S6-1: Prepare a 10 mg / ml acetonitrile / methanol solution of (perfluoropropyl)phenyliodonium trifluoromethane sulfonate in a glove box;

[0072] S6-2: Immerse the device prepared in step S5 in the solution prepared in step S6-1 for 50 minutes;

[0073] S6-3: After the reaction is complete, rinse the substrate repeatedly with acetonitrile and methanol, and then dry it with nitrogen gas;

[0074] S6-4: Place the device on a 90°C hot plate in a glove box and heat for 20 minutes;

[0075] S7: Building Ti3C2T X MXene synaptic transistor;

[0076] S7-1: Weigh 250mg of polyethylene oxide and 100mg of lithium perchlorate, add them to 10ml of anhydrous acetonitrile, and stir overnight at 60℃ until the solution becomes transparent;

[0077] S7-2: Use a pipette to drop 2 μL of electrolyte solution onto the channel layer, gate, and exposed substrate. The electrolyte layer covers the channel layer and connects to the gate.

[0078] S7-3: Place the device in a vacuum drying oven and heat it at 90°C for 20 minutes to remove unvolatile acetonitrile.

[0079] The reactive electron energy loss spectrum (REELS) of this embodiment was tested using X-ray photoelectron spectroscopy, such as... Figure 2 As shown, Ti3C2T grafted with perfluoropropyl groups X The band gap is 2.82 eV. The transfer curve of the artificial synapse based on the electrolyte gate transistor obtained in this embodiment was tested using a semiconductor analyzer. The counterclockwise hysteresis can be used as an information storage window for artificial synapse simulation.

[0080] Example 4

[0081] Based on Ti3C2T X MXene's synaptic transistor has a side-gate structure, including a substrate, source (S), drain (D), gate (G), and Ti3C2T. X Channel layer and electrolyte layer, Ti3C2T X The channel layer is grafted with perfluoropropyl groups via a nucleophilic reaction.

[0082] The preparation method described in Example 2 specifically includes the following steps:

[0083] S1: Select a glass slide as the substrate. Clean the 2×2cm glass slide sequentially with acetone, isopropanol, and deionized water for 5 minutes each to remove contaminants from the substrate surface, and then dry it with nitrogen gas.

[0084] S2: Gate, source, and drain patterning;

[0085] S2-1: The source, gate, and drain electrodes are patterned on the substrate through steps such as spin-coating photoresist negative, pre-baking, ultraviolet exposure, post-baking, development, and fixing. The channel spacing between the source and drain electrodes is 5 μm, and the length is 100 μm.

[0086] S2-2: A Cr / Au metal layer is deposited on a substrate by electron beam evaporation, wherein the thickness of Cr is 5nm and the thickness of Au is 60nm.

[0087] S2-3: Immerse the substrate with the deposited metal layer in acetone at 95°C for 15 min, then in isopropanol for 1 min, and peel off to obtain a patterned metal electrode pattern.

[0088] S3: Patterning of the channel layer region;

[0089] S3-1: The channel region is patterned on the substrate by spin-coating photoresist positive resist, pre-baking, ultraviolet exposure, post-baking, development and fixing, wherein the area of ​​the channel region is 100μm×100μm.

[0090] S3-2: Place the substrate in an ultraviolet ozone generator for 20 minutes and perform hydrophilic treatment;

[0091] S4: Preparation of few-layer Ti3C2T X MXene;

[0092] S4-1: Weigh 1.6g LiF and add it to 20ml 9M HCl, then stir in a polytetrafluoroethylene beaker for 5min;

[0093] S4-2: Slowly add 1g of Ti3AlC2 powder to the above solution, place the polytetrafluoroethylene beaker in an oil bath at 40℃, and stir continuously for 30h;

[0094] S4-3: After the reaction is complete, the reaction mixture is washed 5-6 times with deionized water (centrifuged at 5000 rpm for 5 min), and the pH is adjusted to 6. The final precipitate with obvious swelling at the bottom is a multilayer Ti3C2T. X ;

[0095] S4-4: Add the above precipitate to 30 ml of deionized water, shake manually for 10 min, then pour into a gas washing bottle. Connect the long end to an inert gas, and sonicate for 50 min under aeration and flowing water conditions. Centrifuge the solution at 3500 rpm for 30 min to obtain a few-layer Ti3C2T. X MXene dispersion;

[0096] S5: Channel region Ti3C2T X Thin film preparation;

[0097] S5-1: A few layers of Ti3C2T X The MXene dispersion was diluted to 1 mg / ml;

[0098] S5-2: Set the parameters of the dip coating machine: running speed 20mm / min, immersion time 3s, coating times 15 times;

[0099] S5-3: After coating, place the device in a vacuum drying oven at 90°C for 20 minutes to evaporate the remaining solvent;

[0100] S5-4: Complete the Ti3C2T coating. X The substrate of the thin film was immersed in acetone at 95°C for 15 min, followed by isopropanol for 1 min, and then peeled off to obtain patterned Ti3C2T. X Ditch area.

[0101] S6: Covalent functionalization of iodonium salts;

[0102] S6-1: Prepare a 5 mg / ml acetonitrile / methanol solution of 3,3'-dinitrodiphenyliodohexafluorophosphate in a glove box;

[0103] S6-2: Immerse the device prepared in step S5 in the solution prepared in step S6-1 for 75 minutes;

[0104] S6-3: After the reaction is complete, rinse the substrate repeatedly with acetonitrile and methanol, and then dry it with nitrogen gas;

[0105] S6-4: Place the device on a 90°C hot plate in a glove box and heat for 20 minutes;

[0106] S7: Building Ti3C2T X MXene synaptic transistor;

[0107] S7-1: Weigh 250mg of polyethylene oxide and 62.5mg of lithium perchlorate, add them to 15ml of anhydrous acetonitrile, and stir overnight at 60℃ until the solution becomes transparent;

[0108] S7-2: Use a pipette to drop 2 μL of electrolyte solution onto the channel layer, gate, and exposed substrate. The electrolyte layer covers the channel layer and connects to the gate.

[0109] S7-3: Place the device in a vacuum drying oven and heat it at 90°C for 20 minutes to remove unvolatile acetonitrile.

[0110] like Figure 4 As shown, the artificial synapse obtained in this embodiment was subjected to a single-pulse test using a semiconductor analyzer. Under the condition of electrical excitation with a single pulse amplitude, the artificial synapse generated a corresponding excitatory postsynaptic current, indicating that the device successfully simulated the functional behavior of biological synapses.

[0111] Example 5

[0112] Based on Ti3C2T X MXene's synaptic transistor has a side-gate structure, including a substrate, source (S), drain (D), gate (G), and Ti3C2T. X Channel layer and electrolyte layer, Ti3C2T X The channel layer is grafted with trifluoromethylphenyl groups via a nucleophilic reaction.

[0113] The preparation method described in Example 2 specifically includes the following steps:

[0114] S1: Select a silicon carbide wafer as the substrate. Clean the 2×2cm silicon carbide wafer sequentially with acetone, isopropanol, and deionized water for 5 minutes each to remove contaminants from the substrate surface, and then dry it with nitrogen gas.

[0115] S2: Gate, source, and drain patterning;

[0116] S2-1: The source, gate, and drain electrodes are patterned on the substrate through steps such as spin-coating photoresist negative, pre-baking, ultraviolet exposure, post-baking, development, and fixing. The channel spacing between the source and drain electrodes is 5 μm, and the length is 100 μm.

[0117] S2-2: A Cr / Au metal layer is deposited on a substrate by electron beam evaporation, wherein the thickness of Cr is 5 nm and the thickness of Au is 45 nm.

[0118] S2-3: Immerse the substrate with the deposited metal layer in acetone at 95°C for 15 min, then in isopropanol for 1 min, and peel off to obtain a patterned metal electrode pattern.

[0119] S3: Patterning of the channel layer region;

[0120] S3-1: The channel region is patterned on the substrate by spin-coating photoresist positive resist, pre-baking, ultraviolet exposure, post-baking, development and fixing, wherein the area of ​​the channel region is 100μm×100μm.

[0121] S3-2: Pre-treat the cleaned substrate with oxygen plasma for 15 min;

[0122] S4: Preparation of few-layer Ti3C2T X MXene;

[0123] S4-1: Weigh 1.6g LiF and add it to 20ml 9M HCl, then stir in a polytetrafluoroethylene beaker for 5min;

[0124] S4-2: Slowly add 1g of Ti3AlC2 powder to the above solution, place the polytetrafluoroethylene beaker in an oil bath at 40℃, and stir continuously for 30h;

[0125] S4-3: After the reaction is complete, the reaction mixture is washed 5-6 times with deionized water (centrifuged at 5000 rpm for 5 min), and the pH is adjusted to 6. The final precipitate with obvious swelling at the bottom is a multilayer Ti3C2T. X ;

[0126] S4-4: Add the above precipitate to 30 ml of deionized water, shake manually for 10 min, then pour into a gas washing bottle. Connect the long end to an inert gas, and sonicate for 50 min under aeration and flowing water conditions. Centrifuge the solution at 3500 rpm for 30 min to obtain a few-layer Ti3C2T. X MXene dispersion;

[0127] S5: Channel region Ti3C2T X Thin film preparation;

[0128] S5-1: A few layers of Ti3C2T X The MXene dispersion was diluted to 5 mg / ml;

[0129] S5-2: Set the spraying equipment pressure to 22 PSI, flow rate to 7 L / min, nozzle diameter to 0.2 m, and spraying time to 10 s;

[0130] S5-3: After the spraying is completed, place the device in a vacuum drying oven at 90°C for 20 minutes to evaporate the remaining solvent;

[0131] S5-4: After spraying Ti3C2T X The substrate of the thin film was immersed in acetone at 95°C for 15 min, followed by isopropanol for 1 min, and then peeled off to obtain patterned Ti3C2T. X Ditch area.

[0132] S6: Covalent functionalization of iodonium salts;

[0133] S6-1: Prepare a 15 mg / ml acetonitrile / methanol solution of bis(3-(trifluoromethyl)phenyl)iodonium trifluoromethanesulfonate in a glove box;

[0134] S6-2: Immerse the device prepared in step S5 in the solution prepared in step S6-1 for 30 minutes;

[0135] S6-3: After the reaction is complete, rinse the substrate repeatedly with acetonitrile and methanol, and then dry it with nitrogen gas;

[0136] S6-4: Place the device on a 90°C hot plate in a glove box and heat for 20 minutes;

[0137] S7: Building Ti3C2T X MXene synaptic transistor;

[0138] S7-1: Weigh 250mg of polyethylene oxide and 50mg of lithium perchlorate, add them to 15ml of anhydrous acetonitrile, and stir overnight at 60℃ until the solution becomes transparent;

[0139] S7-2: Use a pipette to drop 2 μL of electrolyte solution onto the channel layer, gate, and exposed substrate. The electrolyte layer covers the channel layer and connects to the gate.

[0140] S7-3: Place the device in a vacuum drying oven and heat it at 90°C for 20 minutes to remove unvolatile acetonitrile.

[0141] like Figure 5 As shown, the response characteristics of this artificial synapse under different numbers of 50ms voltage pulses are... Figure 6 The figure shows the response characteristics of the artificial synapse under 10 50ms voltage pulses at different frequencies. The more pulses there are and the lower the voltage pulse frequency, the more obvious the change in the channel current of the device, which simulates the frequency-dependent plasticity of the neural synapse.

[0142] Example 6

[0143] Based on Ti3C2T X MXene's synaptic transistor has a side-gate structure, including a substrate, source (S), drain (D), gate (G), and Ti3C2T. X Channel layer and electrolyte layer, Ti3C2T X The channel layer is grafted with cyano groups through a nucleophilic reaction.

[0144] The preparation method described in Example 2 specifically includes the following steps:

[0145] S1: Select a gallium nitride (GaN) wafer as the substrate. Clean the 2×2cm GaN wafer sequentially with acetone, isopropanol, and deionized water using ultrasonic cleaning for 5 minutes each to remove contaminants from the substrate surface. Then, dry the substrate with nitrogen gas.

[0146] S2: Gate, source, and drain patterning;

[0147] S2-1: The source, gate, and drain electrodes are patterned on the substrate through steps such as spin-coating photoresist negative, pre-baking, ultraviolet exposure, post-baking, development, and fixing. The channel spacing between the source and drain electrodes is 5 μm, and the length is 100 μm.

[0148] S2-2: A Cr / Au metal layer is deposited on a substrate by electron beam evaporation, wherein the thickness of Cr is 5nm and the thickness of Au is 60nm.

[0149] S2-3: Immerse the substrate with the deposited metal layer in acetone at 95°C for 15 min, then in isopropanol for 1 min, and peel off to obtain a patterned metal electrode pattern.

[0150] S3: Patterning of the channel layer region;

[0151] S3-1: The channel region is patterned on the substrate by spin-coating photoresist positive resist, pre-baking, ultraviolet exposure, post-baking, development and fixing, wherein the area of ​​the channel region is 100μm×100μm.

[0152] S3-2: Pre-treat the cleaned substrate with oxygen plasma for 15 min;

[0153] S4: Preparation of few-layer Ti3C2T X MXene;

[0154] S4-1: Weigh 1.6g LiF and add it to 20ml 9M HCl, then stir in a polytetrafluoroethylene beaker for 5min;

[0155] S4-2: Slowly add 1g of Ti3AlC2 powder to the above solution, place the polytetrafluoroethylene beaker in an oil bath at 40℃, and stir continuously for 30h;

[0156] S4-3: After the reaction is complete, the reaction mixture is washed 5-6 times with deionized water (centrifuged at 5000 rpm for 5 min), and the pH is adjusted to 6. The final precipitate with obvious swelling at the bottom is a multilayer Ti3C2T. X ;

[0157] S4-4: Add the above precipitate to 30 ml of deionized water, shake manually for 10 min, then pour into a gas washing bottle. Connect the long end to an inert gas, and sonicate for 50 min under aeration and flowing water conditions. Centrifuge the solution at 3500 rpm for 30 min to obtain a few-layer Ti3C2T. X MXene dispersion;

[0158] S5: Channel region Ti3C2T X Thin film preparation;

[0159] S5-1: A few layers of Ti3C2T X The MXene dispersion was diluted to 15 mg / ml;

[0160] S5-2: Set the spin coating parameters of the spin coater to spin coat at 1000 rpm for 10 seconds and at 3000 rpm for 30 seconds.

[0161] S5-3: After spin coating, place the device in a vacuum drying oven at 90°C for 20 minutes to evaporate the remaining solvent;

[0162] S5-4: Spin-coated Ti3C2T X The substrate of the thin film was immersed in acetone at 95°C for 15 min, followed by isopropanol for 1 min, and then peeled off to obtain patterned Ti3C2T. X Ditch area.

[0163] S6: Covalent functionalization of iodonium salts;

[0164] S6-1: Prepare a 5 mg / ml acetonitrile / methanol solution of (4-cyanophenyl)(trimethylmethyl)iodonium trifluoromethanesulfonate in a glove box;

[0165] S6-2: Immerse the device prepared in step S5 in the solution prepared in step S6-1 for 90 minutes;

[0166] S6-3: After the reaction is complete, rinse the substrate repeatedly with acetonitrile and methanol, and then dry it with nitrogen gas;

[0167] S6-4: Place the device on a 90°C hot plate in a glove box and heat for 20 minutes;

[0168] S7: Building Ti3C2T X MXene synaptic transistor;

[0169] S7-1: Weigh 250mg of polyethylene oxide and 100mg of lithium perchlorate, add them to 10ml of anhydrous acetonitrile, and stir overnight at 60℃ until the solution becomes transparent;

[0170] S7-2: Use a pipette to drop 2 μL of electrolyte solution onto the channel layer, gate, and exposed substrate. The electrolyte layer covers the channel layer and connects to the gate.

[0171] S7-3: Place the device in a vacuum drying oven and heat it at 90°C for 20 minutes to remove unvolatile acetonitrile.

[0172] In summary, the method for covalent functionalization of iodonium salts provided by this invention utilizes nucleophilic reactions in Ti3C2T X Introducing strong electron-withdrawing groups into the MXene surface opens up Ti3C2T X The band gap of Ti3C2T X The conductivity of the lithium ions changes from metalloid to semiconductor. This invention modulates the channel current by controlling the migration behavior of lithium ions driven by an electric field, which can simulate the pulse quantity-dependent plasticity and pulse frequency-dependent plasticity of neural synapses, thus achieving electrolyte-gated biomimetic neural synapses.

[0173] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be within the scope of protection of the present invention.

Claims

1. A covalently functionalized MXene artificial synapse, characterized in that, From bottom to top, it includes a substrate layer, a source-gate-drain electrode layer, a channel layer, and an electrolyte layer; the channel layer is a Ti3C2T covalently functionalized iodonium salt. X MXene.

2. A method for preparing covalently functionalized MXene artificial synapses as described in claim 1, characterized in that, It includes the following steps: S1: Select a substrate and clean the substrate; S2: The gate, source and drain electrodes are patterned on the substrate using photolithography, and a metal layer is deposited by electron beam evaporation and then stripped to obtain the metal electrode pattern. S3: The channel region is patterned on the substrate using photolithography and then hydrophilicized. S4: Few-layer Ti3C2T was obtained by in-situ acid etching combined with mechanical exfoliation of MAX phase material. X MXene; S5: A uniform Ti3C2T coating process is used to form a uniform Ti3C2T coating on the substrate. X MXene film, and obtained channel region pattern by peeling; S6: Prepare an iodonium salt solution, immerse the device prepared in step S5 into the iodonium salt solution to complete covalent functionalization; after covalent functionalization, rinse the device repeatedly with acetonitrile and methanol solution, and then dry it with a nitrogen gun; finally, heat-treat it in a vacuum drying oven at 90℃ for 20 minutes to remove unevaporated solvent. S7: Prepare electrolyte solution in Ti3C2T X An electrolyte is drop-cast onto the MXene channel layer, gate, and exposed substrate, with the electrolyte covering the channel layer and connecting to the gate, to construct a Ti3C2T. X MXene synaptic transistor.

3. The method for preparing covalently functionalized MXene artificial synapses according to claim 2, characterized in that, The substrate in step S1 is one of silicon oxide, glass, silicon carbide, or gallium nitride.

4. The method for preparing covalently functionalized MXene artificial synapses according to claim 2, characterized in that, The source, gate, and drain electrodes in step S2 are made of Cr / Au or Cr / Pt, with a thickness of 35nm-65nm.

5. The method for preparing covalently functionalized MXene artificial synapses according to claim 2, characterized in that, The hydrophilic treatment in step S3 is performed using ultraviolet ozone or oxygen plasma treatment.

6. The method for preparing covalently functionalized MXene artificial synapses according to claim 2, characterized in that, The Ti3C2T in step S4 X The concentration of MXene is 1-20 mg / ml.

7. The method for preparing covalently functionalized MXene artificial synapses according to claim 2, characterized in that, The coating process in step S5 is one of spin coating, spray coating, or dip coating, forming Ti3C2T X The thickness of MXene films ranges from 5 to 20 nm.

8. The method for preparing covalently functionalized MXene artificial synapses according to claim 2, characterized in that, The iodonium salt in step S6 is any one of (perfluoropropyl)phenyliodonium trifluoromethanesulfonate, bis(3-(trifluoromethyl)phenyl)iodonium trifluoromethanesulfonate, 3,3'-dinitrodiphenyliodohexafluorophosphate, and (4-cyanophenyl)(trimethylmethyl)iodonium trifluoromethanesulfonate. The provided strong electron-withdrawing group is any one of perfluoropropyl group, trifluoromethylphenyl group, nitro group, and cyano group. The concentration of the iodonium salt solution is 5-15 mg / ml, and the immersion time is 30-90 min.

9. The method for preparing covalently functionalized MXene artificial synapses according to claim 2, characterized in that, The drop-cast electrolyte in step S7 is PEO / LiClO4, with PEO / LiClO4 serving as the lithium-ion supply layer, and the mass ratio of PEO to LiClO4 is 2.5-5:1.

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