Display driving framework and method and display device

Abstract

The invention provides a display driving framework and method and a display device. The display driving framework comprises a controller, a first gate driving circuit and a second gate driving circuit, wherein the first gate driving circuit and the second gate driving circuit are arranged on the two sides of a display panel; the controller adjusts working modes of the first gate driving circuit and the second gate driving circuit according to the temperature or the frequency, and the working modes comprise a driving mode and a sleep mode; the first gate driving circuit comprises a plurality of first gate driving units, and each first gate driving unit comprises a first output transistor for outputting a gate driving signal; the second gate driving circuit comprises a plurality of second gate driving units, and each second gate driving unit comprises a second output transistor for outputting a gate driving signal; the size parameter of the first output transistor is greater than that of the second output transistor; two ends of each gate line are respectively connected with a first output transistor and a second output transistor. According to the invention, the antenna can meet the requirements of a wider environment temperature range or a wider frequency range.

Description

Technical Field

[0001] The present invention relates to the technical field of display driving, and particularly to a display driving architecture, method and display device. Background Art

[0002] Display devices, such as liquid crystal display (LCD) devices, have gradually replaced traditional cathode ray tube displays due to many advantages such as being thin, light, energy-saving, and radiation-free, and are widely used in electronic devices such as high-definition digital TVs, desktop computers, personal digital assistants, laptop computers, mobile phones, digital cameras, etc. A display device can adopt a display driving architecture, and the display driving architecture includes a gate driving circuit and a source driving circuit, etc. Among them, the gate driving circuit is used to output a gate driving signal to scan the gate lines row by row, and sequentially turn on the thin film transistors (TFTs, Thin Film Transistors) of each row of the display panel; the source driving circuit outputs a data signal to the data lines, and charges the pixel units of an entire row to their respective required voltages through the turned-on thin film transistors.

[0003] However, when the display device is under working conditions such as a wide temperature range of -40°C to 85°C or a wide frequency range, it is very difficult to ensure normal operation at each temperature or each frequency. For example, when it works normally at low temperature, abnormal phenomena such as screen flashing may occur at high temperature, and when it works normally at high temperature, it may not be able to start normally at low temperature. The main reason is that the transistors in the gate driving circuit, especially the output transistors with the largest size and connected to the gate lines for outputting gate driving signals, have changes in their working characteristics due to temperature and frequency changes. For example, at low temperature, the electron mobility of the transistor is low and the conductivity decreases, which may lead to a slower switching speed and affect the pixel charging efficiency. However, at high temperature, the electron mobility becomes higher and the leakage current becomes larger, which may cause the circuit not to maintain a low level well during the holding stage and result in abnormal display.

[0004] Therefore, it is necessary to provide improved technical solutions to overcome the above technical problems existing in the prior art. Summary of the Invention

[0005] In view of this, the present invention provides a display driving architecture, method and display device, which can be applicable to a wider ambient temperature range or a wider frequency range requirement, and improve the reliability of the product.

[0006] An embodiment of the present invention provides a display driving architecture, including a controller, a first gate driving circuit and a second gate driving circuit disposed on both sides of a display panel; the controller adjusts operating modes of the first gate driving circuit and the second gate driving circuit according to temperature or frequency, and the operating modes include a driving mode and a sleep mode; the first gate driving circuit includes a plurality of cascaded first gate driving units, and each first gate driving unit includes a first output transistor for outputting a gate driving signal; the second gate driving circuit includes a plurality of cascaded second gate driving units, and each second gate driving unit includes a second output transistor for outputting a gate driving signal; a size parameter of the first output transistor is greater than that of the second output transistor; two ends of each gate line of the display panel are respectively connected to one first output transistor and one second output transistor.

[0007] Specifically, when the temperature detected by the controller is lower than a first temperature threshold, the controller controls the first gate driving circuit to enter the driving mode and controls the second gate driving circuit to enter the driving mode; when the temperature is between the first temperature threshold and a second temperature threshold, the controller controls the first gate driving circuit to enter the driving mode and controls the second gate driving circuit to enter the sleep mode; when the temperature is higher than the second temperature threshold, the controller controls the first gate driving circuit to enter the sleep mode and controls the second gate driving circuit to enter the driving mode; the first temperature threshold is lower than the second temperature threshold.

[0008] Specifically, when the frequency detected by the controller is higher than a first frequency threshold, the controller controls the first gate driving circuit to enter the driving mode and controls the second gate driving circuit to enter the driving mode; when the frequency is between the first frequency threshold and a second frequency threshold, the controller controls the first gate driving circuit to enter the driving mode and controls the second gate driving circuit to enter the sleep mode; when the frequency is lower than the second frequency threshold, the controller controls the first gate driving circuit to enter the sleep mode and controls the second gate driving circuit to enter the driving mode; the first frequency threshold is higher than the second frequency threshold.

[0009] Specifically, for the first gate driving circuit or the second gate driving circuit in the sleep mode, the controller only provides a second low-level signal to the corresponding gate driving unit to pull down the potential of the internal node.

[0010] Specifically, the controller is the first gate driving circuit or the second gate driving circuit in the sleep mode, and only provides a second low-level signal to the corresponding gate driving unit during the display period of one frame for pulling down the potential of the internal node; and during the non-display period of one frame, replaces the second low-level signal with a high-level signal.

[0011] An embodiment of the present invention further provides a driving method for a display driving architecture. The display driving architecture includes a first gate driving circuit and a second gate driving circuit arranged on both sides of a display panel; the first gate driving circuit includes a plurality of cascaded first gate driving units, and the first gate driving unit includes a first output transistor for outputting a gate driving signal; the second gate driving circuit includes a plurality of cascaded second gate driving units, and the second gate driving unit includes a second output transistor for outputting a gate driving signal; the size parameter of the first output transistor is greater than the size parameter of the second output transistor; both ends of each gate line of the display panel are respectively connected to one of the first output transistors and one of the second output transistors. The driving method includes: obtaining temperature or frequency; according to the temperature or the frequency, adjusting the working modes of the first gate driving circuit and the second gate driving circuit, and the working modes include a driving mode and a sleep mode.

[0012] Specifically, the adjusting the working modes of the first gate driving circuit and the second gate driving circuit according to the temperature or the frequency includes: when the temperature is lower than a first temperature threshold, controlling the first gate driving circuit to enter the driving mode and controlling the second gate driving circuit to enter the driving mode; when the temperature is between the first temperature threshold and a second temperature threshold, controlling the first gate driving circuit to enter the driving mode and controlling the second gate driving circuit to enter the sleep mode; when the temperature is higher than the second temperature threshold, controlling the first gate driving circuit to enter the sleep mode and controlling the second gate driving circuit to enter the driving mode; the first temperature threshold is lower than the second temperature threshold.

[0013] Specifically, the first gate driving unit further includes a plurality of other transistors, and the plurality of other transistors of the first gate driving unit are provided with size parameters matching the first output transistor, and / or, the second gate driving unit further includes a plurality of other transistors, and the plurality of other transistors of the second gate driving unit are provided with size parameters matching the second output transistor.

[0014] Specifically, adjusting the operating modes of the first gate driving circuit and the second gate driving circuit according to the temperature or the frequency includes: when the frequency is higher than a first frequency threshold, controlling the first gate driving circuit to enter the driving mode and controlling the second gate driving circuit to enter the driving mode; when the frequency is between the second frequency threshold and the first frequency threshold, controlling the first gate driving circuit to enter the driving mode and controlling the second gate driving circuit to enter the sleep mode; when the frequency is lower than the second frequency threshold, controlling the first gate driving circuit to enter the sleep mode and controlling the second gate driving circuit to enter the driving mode; the first frequency threshold is higher than the second frequency threshold.

[0015] An embodiment of the present invention further provides a display device, including the above-mentioned display driving architecture.

[0016] The display driving architecture, method and display device of the present invention are provided with a first gate driving circuit and a second gate driving circuit on both sides of the display panel; the first gate driving circuit includes a plurality of cascaded first gate driving units, and each first gate driving unit includes a first output transistor for outputting a gate driving signal; the second gate driving circuit includes a plurality of cascaded second gate driving units, and each second gate driving unit includes a second output transistor for outputting a gate driving signal; the size parameter of the first output transistor is greater than that of the second output transistor; both ends of each gate line of the display panel are respectively connected to a first output transistor and a second output transistor; during driving, the operating modes of the first gate driving circuit and the second gate driving circuit are adjusted according to the temperature or the frequency, and the operating modes include a driving mode and a sleep mode; thus, the first gate driving circuit and the second gate driving circuit can cooperate with each other to ensure the normal output of the gate driving signal, and can be applicable to a wider ambient temperature range or a wider frequency requirement, improving the reliability of the product.

[0017] To make the above and other objects, features and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, details are described as follows. Description of the Drawings

[0018] Figure 1 is a schematic structural diagram of a display driving architecture according to an embodiment of the present invention.

[0019] Figure 2 is a schematic structural diagram of a first gate driving unit of a display driving architecture according to an embodiment of the present invention in the driving mode.

[0020] Figure 3 is Figure 2 a timing schematic diagram of

[0021] Figure 4It is a schematic structural diagram of a first gate driving unit of a display driving architecture according to an embodiment of the present invention in a sleep mode.

[0022] Figure 5 is Figure 4 a timing schematic diagram of.

[0023] Figure 6 It is a schematic flowchart of a driving method of a display driving architecture according to an embodiment of the present invention. Detailed Embodiments

[0024] To further elaborate on the technical means and effects adopted by the present invention to achieve the expected purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific embodiments, methods, steps, structures, features, and effects of the display driving architecture, method, and display device proposed according to the present invention.

[0025] Figure 1 It is a schematic structural diagram of a display driving architecture according to an embodiment of the present invention. Please refer to Figure 1 , the display driving architecture of this embodiment includes a controller ( Figure 1 not shown in the figure) and a first gate driving circuit 100 and a second gate driving circuit 200 disposed on both sides of the display panel 300. The controller adjusts the working modes of the first gate driving circuit 100 and the second gate driving circuit 200 according to temperature or frequency, and the working modes include a driving mode and a sleep mode. The first gate driving circuit 100 includes a plurality of cascaded first gate driving units 110, and the first gate driving unit 110 includes a first output transistor for outputting a gate driving signal; the second gate driving circuit 200 includes a plurality of cascaded second gate driving units 210, and the second gate driving unit 210 includes a second output transistor for outputting a gate driving signal; the size parameter of the first output transistor is greater than that of the second output transistor. Both ends of each gate line of the display panel 300 are respectively connected to a first output transistor and a second output transistor.

[0026] In an embodiment of the present invention, the display driving architecture includes a temperature sensor used in conjunction with the display panel 300, and the temperature sensor is connected to the controller for the controller to determine the magnitude of the temperature. However, the present invention is not limited thereto, and the controller can also obtain the default or previously set temperature or frequency from the storage, or obtain the temperature or frequency according to an external input, which all fall within the protection scope of the present invention.

[0027] Specifically, in Figure 1In the exemplary display driving architecture, the two sides of the display panel 300 are the left side and the right side. The first gate driving circuit 100 is arranged on the left side, and the second gate driving circuit 200 is arranged on the right side. The first gate driving circuit 100 includes a plurality of cascaded first gate driving units 110, and the first gate driving unit 110 includes a first output transistor for outputting a gate driving signal. The second gate driving circuit 200 includes a plurality of cascaded second gate driving units 210, and the second gate driving unit 210 includes a second output transistor for outputting a gate driving signal. If the size parameter of the first output transistor is greater than that of the second output transistor, their operating characteristics may be the same or different at the same temperature or frequency. Both ends of each gate line of the display panel 300 are respectively connected to a first output transistor and a second output transistor. Then, at least one of the first gate driving circuit 100 and the second gate driving circuit 200 can provide a gate driving signal to each gate line for the display of the display panel 300. The controller adjusts the operating modes of the first gate driving circuit 100 and the second gate driving circuit 200 according to the temperature or frequency. The operating modes include a driving mode and a sleep mode. That is to say, according to the temperature or frequency, the operating characteristics of output transistors with different size parameters can be matched. Accordingly, at least one of the first gate driving circuit 100 and the second gate driving circuit 200 is selected and adjusted to the driving mode to output a gate driving signal to the gate line, or the corresponding gate driving circuit can be adjusted to the sleep mode to avoid outputting an abnormal gate driving signal to the gate line. Thus, the first gate driving circuit 100 and the second gate driving circuit 200 can cooperate with each other to ensure the normal output of the gate driving signals G1, G2, G3, G4…Gn-1, Gn, and can be applicable to a wider ambient temperature range or a wider frequency requirement, improving the reliability of the product.

[0028] Those skilled in the art can understand that Figure 1 the display driving architecture in

[0029] In an embodiment of the present invention, the controller controls the first gate driving circuit 100 to enter the driving mode and controls the second gate driving circuit 200 to enter the driving mode according to the temperature being lower than the first temperature threshold; the controller controls the first gate driving circuit 100 to enter the driving mode and controls the second gate driving circuit 200 to enter the sleep mode according to the temperature being between the first temperature threshold and the second temperature threshold; the controller controls the first gate driving circuit 100 to enter the sleep mode and controls the second gate driving circuit 200 to enter the driving mode according to the temperature being higher than the second temperature threshold. As shown in Table 1: Table 1:

[0030] Specifically, in a wide temperature range such as -40°C to 85°C, the controller can first obtain the temperature through a temperature sensor or the like, and then can set the working modes of the first gate driving circuit 100 and the second gate driving circuit 200 according to the temperature. For example, when the controller determines that the temperature is lower than the first temperature threshold, the value range of the first temperature threshold can be -20°C to 0°C. The controller controls the first gate driving circuit 100 to enter the driving mode and also controls the second gate driving circuit 200 to enter the driving mode, which can better cope with the decrease in driving ability of the first output transistor and the second output transistor due to the reduction of carrier mobility and the drift of threshold voltage at this temperature. For example, when the controller determines that the temperature is between the first temperature threshold and the second temperature threshold, the first temperature threshold is lower than the second temperature threshold, and the value range of the second temperature threshold can be 50°C to 70°C. The controller controls the first gate driving circuit 100 to enter the driving mode and controls the second gate driving circuit 200 to enter the sleep mode because the size parameter of the first output transistor is relatively large, so a wider channel width can be set at this temperature, and it has a stronger driving ability, which can avoid smear or response delay caused by the second output transistor. For example, when the controller determines that the temperature is higher than the second temperature threshold, the controller controls the first gate driving circuit 100 to enter the sleep mode and controls the second gate driving circuit 200 to enter the driving mode because the size parameter of the second output transistor is relatively small, so at this temperature, due to the smaller channel area, lower parasitic capacitance, and limited leakage path, the leakage current is relatively small, which can avoid the increase in leakage current caused by the first output transistor resulting in the inability to maintain a low level and display abnormalities.

[0031] It should be noted that the specific temperature value of the above temperature threshold usually needs to be set according to the actual measurement during product debugging. In addition, the present invention is not limited to the mode setting of three temperature ranges in Table 1 above, and can be set to at least two temperature ranges according to needs. For example, if the temperature range only includes below the first temperature threshold and between the first temperature threshold and the second temperature threshold, then only the mode setting of these two temperature ranges below the first temperature threshold and between the first temperature threshold and the second temperature threshold belongs to the protection scope of the present invention.

[0032] In an embodiment of the present invention, the first gate driving unit 110 further includes a plurality of other transistors. The plurality of other transistors of the first gate driving unit 110 are set with size parameters matching the first output transistor, and / or, the second gate driving unit 120 further includes a plurality of other transistors. The plurality of other transistors of the second gate driving unit 120 are set with size parameters matching the second output transistor. That is to say, when the size parameter of the first output transistor is relatively large, in order to make the plurality of other transistors of the first gate driving unit 110 match the first output transistor during operation, the plurality of other transistors of the first gate driving unit 110 can be set with corresponding large size parameters (related to factors such as device characteristic parameters, resolution, and RC load); similarly, when the size parameter of the second output transistor is relatively small, in order to make the plurality of other transistors of the second gate driving unit 120 match the second output transistor during operation, the plurality of other transistors of the second gate driving unit 120 can be set with corresponding small size parameters (related to factors such as device characteristic parameters, resolution, and RC load). In an embodiment, the plurality of other transistors of the first gate driving unit 110 can be set with large size parameters corresponding to the first output transistor, and the plurality of other transistors of the second gate driving unit 120 can be set with small size parameters corresponding to the second output transistor, which can make both the first gate driving unit and the second gate driving unit have better circuit performance, as shown in Table 2: Table 2:

[0033] In an embodiment of the present invention, the controller controls the first gate driving circuit 100 to enter the driving mode and controls the second gate driving circuit 200 to enter the driving mode according to a frequency higher than the first frequency threshold; the controller controls the first gate driving circuit 100 to enter the driving mode and controls the second gate driving circuit 200 to enter the sleep mode according to a frequency between the second frequency threshold and the first frequency threshold; the controller controls the first gate driving circuit 100 to enter the sleep mode and controls the second gate driving circuit 200 to enter the driving mode according to a frequency lower than the second frequency threshold. And in an embodiment, the first gate driving unit 110 further includes a plurality of other transistors, the plurality of other transistors of the first gate driving unit 110 are provided with size parameters matching the first output transistor, the second gate driving unit 120 further includes a plurality of other transistors, and the plurality of other transistors of the second gate driving unit 120 are provided with size parameters matching the second output transistor, as shown in Table 3: Table 3:

[0034] Specifically, in the case of wide frequency band, the controller can obtain the frequency according to the display refresh rate, etc., and then can set the working modes of the first gate driving circuit 100 and the second gate driving circuit 200 according to the frequency. For example, when the frequency is higher than the first frequency threshold, the value range of the first frequency threshold can be 90 hz to 120 hz, the controller controls the first gate driving circuit 100 to enter the driving mode, and also controls the second gate driving circuit 200 to enter the driving mode, which can better cope with the display abnormality of insufficient charge and discharge caused by too fast driving switching of the first output transistor and the second output transistor at this frequency. For example, when the frequency is between the first frequency threshold and the second frequency threshold, the first frequency threshold is higher than the second frequency threshold, and the value range of the second frequency threshold can be 40 hz to 60 hz, the controller controls the first gate driving circuit 100 to enter the driving mode and controls the second gate driving circuit 200 to enter the sleep mode, because the size parameter of the first output transistor is relatively large, so at this frequency, a wider channel width can be set, and it has stronger driving ability, which can shorten the charging time and avoid smear or response delay. For example, when the frequency is lower than the second frequency threshold, the controller controls the first gate driving circuit 100 to enter the sleep mode and controls the second gate driving circuit 200 to enter the driving mode, because the size parameter of the second output transistor is relatively small, so at this frequency, the channel area is smaller, the parasitic capacitance is lower, and the output signal is relatively stable, which can avoid the significant increase of the parasitic capacitance caused by the large size of the first output transistor, and correspondingly avoid signal delay and coupling interference, as well as the possible gate voltage overshoot or mis-triggering. Moreover, a plurality of other transistors of the first gate driving unit 110 are provided with large size parameters corresponding to the first output transistor, and a plurality of other transistors of the second gate driving unit 120 are provided with small size parameters corresponding to the second output transistor, which can make both the first gate driving unit and the second gate driving unit have better circuit performance.

[0035] It should be noted that the specific frequency values of the above frequency thresholds usually need to be set according to the actual measurement of product debugging. In addition, the present invention is not limited to the mode setting of three frequency ranges in Table 3 above, and at least two frequency ranges can be set according to needs. For example, if the frequency range only includes higher than the first temperature threshold and between the first frequency threshold and the second frequency threshold, then only the mode setting of these two frequency ranges higher than the first temperature threshold and between the first frequency threshold and the second frequency threshold belongs to the protection scope of the present invention.

[0036] In an embodiment of the present invention, the controller is the first gate driving circuit 100 or the second gate driving circuit 200 in the sleep mode, and only provides the second low-level signal VGL+ to the corresponding gate driving unit for pulling down the potential of the internal node.

[0037] In an embodiment of the present invention, the controller is the first gate driving circuit 100 or the second gate driving circuit 200 in the sleep mode, and only provides the second low-level signal VGL+ to the corresponding gate driving unit during the display period of one frame for pulling down the potential of the internal node; and replaces the second low-level signal VGL+ with a high-level signal during the non-display period of one frame.

[0038] Specifically, please refer to Figures 2 to 5 , which respectively gives the connection and timing diagrams of the first gate driving circuit 100 in the driving mode and the sleep mode. Taking the first gate driving circuit 100 as an example, the working processes of the first gate driving circuit 100 and the second gate driving circuit 200 in the driving mode and the sleep mode are described below.

[0039] As Figure 2As shown, in the driving mode, the first gate driving circuit 100. The first gate driving unit 110 in the first gate driving circuit 100 includes, for example, 16 switching elements and 1 capacitor C1. The 16 switching elements include a first switching element M1 to a sixteenth switching element M16. The second switching element M2 among them is the first output transistor for outputting a gate driving signal. The first control terminal of the first switching element M1 receives a pre-stage transfer signal Zn-2. The first path terminal of the first switching element M1 receives a pre-stage gate signal Gn-2. The second path terminal of the first switching element M1 is connected to a first node Qn. The second control terminal of the second switching element M2 is connected to the first node Qn. The third path terminal of the second switching element M2 receives a first clock signal CLK1. The fourth path terminal of the second switching element M2 is connected to a first output terminal for outputting a stage gate driving signal Gn. The fourteenth control terminal of the fourteenth switching element M14 is connected to the first node Qn. The twenty-seventh path terminal of the fourteenth switching element M14 receives the first clock signal CLK1. The twenty-eighth path terminal of the fourteenth switching element M14 is connected to a second output terminal for outputting a stage transfer signal Zn. The third control terminal of the third switching element M3 receives a post-stage gate signal Gn+2. The fifth path terminal of the third switching element M3 is connected to the first node Qn. The sixth path terminal of the third switching element M3 receives a second clock signal CLK2. The eighth control terminal of the eighth switching element M8 receives a first control signal V1. The fifteenth path terminal of the eighth switching element M8 is connected to the tenth control terminal of the tenth switching element M10. The sixteenth path terminal of the eighth switching element M8 is connected to a second node QB1. The tenth control terminal of the tenth switching element M10 is connected to the fifteenth path terminal of the eighth switching element M8 and receives the first control signal V1. The nineteenth path terminal of the tenth switching element M10 receives a first low-level signal VGL. The twentieth path terminal of the tenth switching element M10 is connected to a third node QB2. The ninth control terminal of the ninth switching element M9 receives a second control signal V2. The seventeenth path terminal of the ninth switching element M9 is connected to the third node QB2. The eighteenth path terminal of the ninth switching element M9 is connected to the eleventh control terminal of the eleventh switching element M11. The eleventh control terminal of the eleventh switching element M11 is connected to the eighteenth path terminal of the ninth switching element M9 and receives the second control signal V2. The twenty-first path terminal of the eleventh switching element M11 is connected to the second node QB1. The twenty-second path terminal of the eleventh switching element M11 receives the first low-level signal VGL. The twelfth control terminal of the twelfth switching element M12 is connected to the first node Qn. The twenty-third path terminal of the twelfth switching element M12 receives the first low-level signal VGL. The twenty-fourth path terminal of the twelfth switching element M12 is connected to the second node QB1.The thirteenth control terminal of the thirteenth switching element M13 is connected to the first node Qn. The twenty-fifth path terminal of the thirteenth switching element M13 is connected to the twenty-third path terminal of the twelfth switching element M12, and receives the first low-level signal VGL. The twenty-sixth path terminal of the thirteenth switching element M13 is connected to the third node QB2. The fourth control terminal of the fourth switching element M4 is connected to the second node QB1. The seventh path terminal of the fourth switching element M4 is connected to the first node Qn. The eighth path terminal of the fourth switching element M4 receives the first low-level signal VGL. The fifth control terminal of the fifth switching element M5 is connected to the third node QB2. The ninth path terminal of the fifth switching element M5 is connected to the eighth path terminal of the fourth switching element M4 and receives the first low-level signal VGL. The tenth path terminal of the fifth switching element M5 is connected to the first node Qn. The sixth control terminal of the sixth switching element M6 is connected to the second node QB1. The eleventh path terminal of the sixth switching element M6 is connected to the first output terminal. The twelfth path terminal of the sixth switching element M6 receives the first low-level signal VGL. The seventh control terminal of the seventh switching element M7 is connected to the third node QB2. The thirteenth path terminal of the seventh switching element M7 is connected to the twelfth path terminal of the sixth switching element M6 and receives the first low-level signal VGL. The fourteenth path terminal of the seventh switching element M7 is connected to the first output terminal. The fifteenth control terminal of the fifteenth switching element M15 is connected to the second node QB1. The twenty-ninth path terminal of the fifteenth switching element M15 is connected to the second output terminal. The thirtieth path terminal of the fifteenth switching element M15 receives the first low-level signal VGL. The sixteenth control terminal of the sixteenth switching element M16 is connected to the third node QB2. The thirty-first path terminal of the sixteenth switching element M16 is connected to the thirtieth path terminal of the fifteenth switching element M15 and receives the first low-level signal VGL. The thirty-second path terminal of the sixteenth switching element M16 is connected to the second output terminal. The first control signal V1 and the second control signal V2 are low-frequency clock signals (i.e., their frequencies are lower than the frequency of the clock signal), and the first control signal V1 and the second control signal V2 alternately become high level.

[0040] As Figure 3 shown, in the driving mode, the first gate driving circuit 100 receives a plurality of timing signals provided by the driver, such as the start signal STV, the clock signals CLK1 to CLK4, the first control signal V1, the second control signal V2, and the first low-level signal VGL. Sixteen switching elements in the plurality of first gate driving units 110 of the first gate driving circuit 100 are correspondingly turned on or off, and the voltages of the first node Qn, the second node QB1, and the third node QB2 are changed. A plurality of first output transistors sequentially output a plurality of gate driving signals G1, G2... and can simultaneously output a plurality of transfer signals Z1, Z2... ( Figure 3 not shown).

[0041] As Figure 4 and Figure 5 shown, in the sleep mode, the first gate driving circuit 100 stops receiving a plurality of timing signals, such as a start signal STV, clock signals CLK1 to CLK4, a first control signal V1, a second control signal V2, and a first low-level signal VGL. Then, the sixth path terminal of the third switching element M3 no longer receives the second clock signal CLK2. The controller provides only the second low-level signal VGL+ to the sixth path terminal of the third switching element M3 of the first gate driving unit 110 for the first gate driving circuit 100 in the sleep mode, so as to pull down the potential of the internal node, that is, the first node Qn. Since both ends of each gate line of the display panel 300 are respectively connected to a first output transistor and a second output transistor, even when the first gate driving circuit 100 is in the sleep mode, it can still receive the gate driving signal output by the second output transistor in the driving mode through the gate line of the display panel 300. Then, the first gate driving unit 110 can receive the subsequent gate driving signal Gn+2 through the third control terminal of the third switching element M3, so that the internal node, that is, the first node Qn, receives the second low-level signal VGL+ through the third switching element M3 and the potential is pulled down, which can prevent the potential of the first node Qn from rising and causing the first output transistor to turn on, and prevent abnormal phenomena such as leakage of the gate line due to the turned-on first output transistor. Optionally, the controller provides only the second low-level signal VGL+ to the sixth path terminal of the third switching element M3 of the first gate driving unit 110 for the first gate driving circuit 100 in the sleep mode during the display period of one frame, so as to pull down the potential of the internal node, that is, the first node Qn; and replaces the second low-level signal VGL+ with a high-level signal during the non-display period blank of one frame, which can prevent the first output transistor and the fourteenth switching element M14 from being abnormal due to receiving a low level for a long time at the gate.

[0042] Figure 6 is a flowchart of a driving method of a display driving architecture according to an embodiment of the present invention. Based on the same inventive concept, an embodiment of the present invention further provides a driving method of a display driving architecture. The display driving architecture includes a first gate driving circuit 100 and a second gate driving circuit 200 disposed on both sides of a display panel 300; the first gate driving circuit 100 includes a plurality of cascaded first gate driving units 110, and the first gate driving unit 110 includes a first output transistor for outputting a gate driving signal; the second gate driving circuit 200 includes a plurality of cascaded second gate driving units 210, and the second gate driving unit 210 includes a second output transistor for outputting a gate driving signal; the size parameter of the first output transistor is greater than that of the second output transistor; both ends of each gate line of the display panel 300 are respectively connected to a first output transistor and a second output transistor, and the driving method includes: S1. Obtain the temperature or frequency; S2. Adjust the operating modes of the first gate driving circuit 100 and the second gate driving circuit 200 according to the temperature or frequency. The operating modes include a driving mode and a sleep mode.

[0043] In an embodiment of the present invention, adjusting the operating modes of the first gate driving circuit 100 and the second gate driving circuit 200 according to the temperature or frequency includes: when the temperature is lower than the first temperature threshold, controlling the first gate driving circuit 100 to enter the driving mode and controlling the second gate driving circuit 200 to enter the driving mode; when the temperature is between the first temperature threshold and the second temperature threshold, controlling the first gate driving circuit 100 to enter the driving mode and controlling the second gate driving circuit 200 to enter the sleep mode; when the temperature is higher than the second temperature threshold, controlling the first gate driving circuit 100 to enter the sleep mode and controlling the second gate driving circuit 200 to enter the driving mode.

[0044] In an embodiment of the present invention, adjusting the operating modes of the first gate driving circuit 100 and the second gate driving circuit 200 according to the temperature or frequency includes: when the frequency is higher than the first frequency threshold, controlling the first gate driving circuit 100 to enter the driving mode and controlling the second gate driving circuit 200 to enter the driving mode; when the frequency is between the second frequency threshold and the first frequency threshold, controlling the first gate driving circuit 100 to enter the driving mode and controlling the second gate driving circuit 200 to enter the sleep mode; when the frequency is lower than the second frequency threshold, controlling the first gate driving circuit 100 to enter the sleep mode and controlling the second gate driving circuit 200 to enter the driving mode.

[0045] For the implementation of the driving method of this display driving architecture, reference can be made to the embodiments of the above display driving architecture, and the repeated parts will not be elaborated.

[0046] Based on the same inventive concept, an embodiment of the present invention further provides a display device, which includes the display driving architecture provided in the above embodiment. For the implementation of this display device, reference can be made to the embodiments of the above display driving architecture, and the repeated parts will not be elaborated.

[0047] The display driving architecture, method and display device of the present invention are provided with a first gate driving circuit 100 and a second gate driving circuit 200 on both sides of a display panel 300; the first gate driving circuit 100 includes a plurality of cascaded first gate driving units 110, and the first gate driving unit 110 includes a first output transistor for outputting a gate driving signal; the second gate driving circuit 200 includes a plurality of cascaded second gate driving units 210, and the second gate driving unit 210 includes a second output transistor for outputting a gate driving signal; the size parameter of the first output transistor is greater than that of the second output transistor; both ends of each gate line of the display panel 300 are respectively connected to a first output transistor and a second output transistor; during driving, according to the temperature or frequency, the working modes of the first gate driving circuit 100 and the second gate driving circuit 200 are adjusted, and the working modes include a driving mode and a sleep mode; thus, the first gate driving circuit 100 and the second gate driving circuit 200 can cooperate with each other to ensure the normal output of the gate driving signal, can be applicable to a wider ambient temperature range or a wider frequency requirement, and improve the reliability of the product.

[0048] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make some changes or modifications to the equivalent embodiments by using the above-disclosed technical content within the scope of the technical solution of the invention. However, as long as it does not depart from the content of the technical solution of the invention, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the invention still fall within the scope of the technical solution of the present invention.

Claims

1. A display driver architecture, characterized in that: The invention comprises a controller and a first gate driving circuit (100) and a second gate driving circuit (200) arranged on both sides of a display panel (300); the controller adjusts the working modes of the first gate driving circuit (100) and the second gate driving circuit (200) according to temperature or frequency, and the working modes include a driving mode and a sleep mode; the first gate driving circuit (100) comprises a plurality of cascaded first gate driving units (110), and the first gate driving unit (110) comprises a first output transistor for outputting a gate driving signal; the second gate driving circuit (200) comprises a plurality of cascaded second gate driving units (210), and the second gate driving unit (210) comprises a second output transistor for outputting a gate driving signal; the size parameter of the first output transistor is greater than the size parameter of the second output transistor; and the two ends of each gate line of the display panel (300) are respectively connected to a first output transistor and a second output transistor.

2. The display driver architecture according to claim 1, characterized in that: The controller controls the first gate drive circuit (100) to enter the drive mode and the second gate drive circuit (200) to enter the drive mode according to the temperature being lower than a first temperature threshold; the controller controls the first gate drive circuit (100) to enter the drive mode and the second gate drive circuit (200) to enter the sleep mode according to the temperature being between the first temperature threshold and the second temperature threshold; the controller controls the first gate drive circuit (100) to enter the sleep mode and the second gate drive circuit (200) to enter the drive mode according to the temperature being higher than the second temperature threshold; the first temperature threshold is lower than the second temperature threshold.

3. The display driver architecture according to claim 1, characterized in that: The first gate driving unit (110) further includes a plurality of other transistors, wherein the plurality of other transistors of the first gate driving unit (110) are provided with size parameters matching the first output transistor, and / or the second gate driving unit (120) further includes a plurality of other transistors, wherein the plurality of other transistors of the second gate driving unit (120) are provided with size parameters matching the second output transistor.

4. The display driver architecture according to claim 1, characterized in that: The controller controls the first gate drive circuit (100) to enter the drive mode and the second gate drive circuit (200) to enter the drive mode according to the frequency being higher than a first frequency threshold; the controller controls the first gate drive circuit (100) to enter the drive mode and the second gate drive circuit (200) to enter the sleep mode according to the frequency being between the first frequency threshold and the second frequency threshold; the controller controls the first gate drive circuit (100) to enter the sleep mode and the second gate drive circuit (200) to enter the drive mode according to the frequency being lower than the second frequency threshold; the first frequency threshold is higher than the second frequency threshold.

5. The display driver architecture according to claim 1, characterized in that: The controller is the first gate driving circuit (100) or the second gate driving circuit (200) in the sleep mode, and only provides a second low level signal (VGL+) to the corresponding gate driving unit for pulling down the potential of the internal node.

6. The display driver architecture according to claim 1, characterized in that: The controller is the first gate driving circuit (100) or the second gate driving circuit (200) in the sleep mode, and only provides a second low-level signal (VGL+) to the corresponding gate driving unit in a display time period of a frame for pulling down the potential of an internal node; and replaces the second low-level signal (VGL+) with a high-level signal in a non-display time period of a frame.

7. A driving method for a display driving architecture, characterized in that: The display driving architecture comprises a first gate driving circuit (100) and a second gate driving circuit (200) arranged on both sides of a display panel (300); the first gate driving circuit (100) comprises a plurality of cascaded first gate driving units (110), the first gate driving unit (110) comprising a first output transistor for outputting a gate driving signal; the second gate driving circuit (200) comprises a plurality of cascaded second gate driving units (210), the second gate driving unit (210) comprising a second output transistor for outputting a gate driving signal; a size parameter of the first output transistor is greater than a size parameter of the second output transistor; Two ends of each gate line of the display panel (300) are respectively connected to a first output transistor and a second output transistor, and the driving method comprises: Get temperature or frequency; According to the temperature or the frequency, the working modes of the first gate driving circuit (100) and the second gate driving circuit (200) are adjusted, and the working modes include a driving mode and a sleep mode.

8. The driving method of the display driving architecture according to claim 7, characterized in that: The step of adjusting the working modes of the first gate driving circuit (100) and the second gate driving circuit (200) according to the temperature or the frequency comprises: According to the temperature being lower than a first temperature threshold, the first gate drive circuit (100) is controlled to enter the drive mode, and the second gate drive circuit (200) is controlled to enter the drive mode; according to the temperature being between the first temperature threshold and the second temperature threshold, the first gate drive circuit (100) is controlled to enter the drive mode, and the second gate drive circuit (200) is controlled to enter the sleep mode; according to the temperature being higher than the second temperature threshold, the first gate drive circuit (100) is controlled to enter the sleep mode, and the second gate drive circuit (200) is controlled to enter the drive mode; the first temperature threshold is lower than the second temperature threshold.

9. The driving method of the display driving architecture according to claim 7, characterized in that: The step of adjusting the working modes of the first gate driving circuit (100) and the second gate driving circuit (200) according to the temperature or the frequency comprises: According to the frequency being higher than a first frequency threshold, the first gate drive circuit (100) is controlled to enter the drive mode, and the second gate drive circuit (200) is controlled to enter the drive mode; according to the frequency being between the first frequency threshold and the second frequency threshold, the first gate drive circuit (100) is controlled to enter the drive mode, and the second gate drive circuit (200) is controlled to enter the sleep mode; according to the frequency being lower than the second frequency threshold, the first gate drive circuit (100) is controlled to enter the sleep mode, and the second gate drive circuit (200) is controlled to enter the drive mode; the first frequency threshold is higher than the second frequency threshold.

10. A display device, characterized in that: The display device comprises the display driving architecture according to any one of claims 1 to 6.

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