Driving circuit, memory device and operating method thereof

Abstract

The invention provides a driving circuit, a memory device and an operating method thereof. The driving circuit comprises a control unit, a switch unit and a sampling unit. The control unit is connected with a first voltage source and a second voltage source, receives a first control signal from the first voltage source, receives a second control signal from the second voltage source, is switched on or switched off according to the first control signal, and applies the second control signal to a first node during switching on; the switch unit is connected with the control unit, a third voltage source and the output end, is switched on or off according to the level of the first node, and is switched on to apply a first operation voltage received from the third voltage source to the output end when the level of the first node is a second control signal; and the sampling unit is connected with the output end, the third voltage source and the switch unit, is switched on or switched off according to the feedback voltage of the output end, and applies the first operation voltage to the first node during switching on, so that the switch unit is switched off when the level of the first node is the first operation voltage. The driving circuit can reduce power consumption.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a driving circuit, a memory device, and an operation method thereof. Background Art

[0002] A resistive random access memory (RRAM) is a non-volatile device that can adjust its conductance state by applying an external excitation, and can record and store data information based on resistance value changes, with characteristics such as high speed, low power consumption, and small size. Resistive random access memory devices have good application prospects in the fields of artificial intelligence, neural networks, and memories, and have received increasing attention from the academic and industrial communities. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a driving circuit, which includes: a control unit, a switching unit, and a sampling unit. The control unit is connected to a first voltage source and a second voltage source, and is configured to receive a first control signal from the first voltage source, receive a second control signal from the second voltage source, and conduct or cut off according to the first control signal, and apply the second control signal to a first node when conducting; the switching unit is connected to the control unit, a third voltage source, and an output terminal, and is configured to conduct or cut off according to the level of the first node, and conduct when the level of the first node is the second control signal to apply a first operating voltage received from the third voltage source to the output terminal; the sampling unit is connected to the output terminal, the third voltage source, and the switching unit, and is configured to conduct or cut off according to the feedback voltage of the output terminal, and apply the first operating voltage to the first node when conducting, so that the switching unit cuts off when the level of the first node is the first operating voltage.

[0004] For example, in the driving circuit provided by at least one embodiment of the present disclosure, the control unit includes a first transistor, a control electrode of the first transistor is connected to the first voltage source, a first pole of the first transistor is connected to the second voltage source, and a second pole of the first transistor is connected to the first node; the switching unit includes a second transistor, a control electrode of the second transistor is connected to the first node, a first pole of the second transistor is connected to the third voltage source, and a second pole of the second transistor is connected to the output terminal; the sampling unit includes a third transistor, a control electrode of the third transistor is connected to the output terminal, a first pole of the third transistor is connected to the third voltage source, and a second pole of the third transistor is connected to the first node.

[0005] For example, in the driving circuit provided by at least one embodiment of the present disclosure, the first transistor, the second transistor, and the third transistor are P-type transistors.

[0006] At least one embodiment of the present disclosure further provides a memory device, which includes: the driving circuit of any embodiment of the present disclosure; a resistive random access memory (RRAM) device, a first end of the RRAM device is connected to the output end of the driving circuit, and a second end of the RRAM device is connected to a fourth voltage source.

[0007] At least one embodiment of the present disclosure further provides an operation method of a memory device, and the operation method includes: receiving, by the control unit, the first control signal from the first voltage source and the second control signal from the second voltage source; turning on the control unit according to the first control signal, and applying the second control signal to the first node to turn on the switching unit; receiving, by the switching unit, the first operation voltage from the third voltage source, and applying the first operation voltage to the RRAM device connected to the output end when the switching unit is turned on; turning on the sampling unit according to the feedback voltage at the output end, and applying the first operation voltage to the first node to turn off the switching unit.

[0008] For example, in the operation method provided by at least one embodiment of the present disclosure, the first operation voltage includes an initialization voltage or a set voltage for the RRAM device.

[0009] For example, the operation method provided by at least one embodiment of the present disclosure further includes: changing a resistance value of the RRAM device according to the first operation voltage.

[0010] For example, in the operation method provided by at least one embodiment of the present disclosure, the feedback voltage changes corresponding to a change in the resistance value of the RRAM device, and when the resistance value of the RRAM device reaches a target resistance value, the feedback voltage reaches a first threshold voltage to turn on the sampling unit.

[0011] For example, the operation method provided by at least one embodiment of the present disclosure further includes: determining a magnitude of a current-limiting voltage of the second control signal according to the target resistance value of the RRAM device.

[0012] At least one embodiment of the present disclosure further provides a memory device, which includes: a memory array including a plurality of rows and columns of memory cells arranged in multiple rows and columns, word lines corresponding to each row in the memory array, bit lines corresponding to each row in the memory array, and source lines corresponding to each column in the memory array. Each memory cell includes a transistor and a resistive memory device. The gate of the transistor is connected to the word line corresponding to the row where the memory cell is located, the first pole of the transistor is connected to the source line corresponding to the column where the memory cell is located, the second pole of the transistor is connected to the first end of the resistive memory device, and the second end of the resistive memory device is connected to the bit line corresponding to the row where the memory cell is located; at least one driving circuit as described in any one of the present disclosure, and each driving circuit is coupled to one of the bit lines of the memory array. Description of the Drawings

[0013] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0014] Figure 1 Schematic structural diagram of an exemplary resistive memory device provided by at least one embodiment of the present disclosure;

[0015] Figure 2 Schematic structural diagram of an exemplary memory cell provided by at least one embodiment of the present disclosure;

[0016] Figure 3 Schematic block diagram of a driving circuit provided by at least one embodiment of the present disclosure;

[0017] Figure 4 Schematic structural diagram of an exemplary driving circuit provided by at least one embodiment of the present disclosure;

[0018] Figure 5 Schematic diagram of a memory device provided by at least one embodiment of the present disclosure; and

[0019] Figure 6 Schematic diagram of a memory device provided by at least one embodiment of the present disclosure. Detailed Description of the Embodiments

[0020] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Apparently, the described embodiments are only a part rather than all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0021] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "include" or "comprise" mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items. The terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left", and "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0022] The present disclosure will be described below through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, the detailed descriptions of known functions and known components (elements) may be omitted. When any component (element) of the embodiments of the present disclosure appears in more than one drawing, the component (element) is denoted by the same or similar reference numerals in each drawing.

[0023] Resistive random access memory (RRAM) devices are considered a promising new type of non-volatile memory due to their fast read / write speeds, simple structures, and good compatibility with CMOS processes, and have been widely used in fields such as information storage, logic operations, and neural network computing.

[0024] Figure 1 The structural schematic diagram of an exemplary resistive random access memory (RRAM) device is shown. As Figure 1As shown, the resistive random access memory device R1 includes a resistive switching layer 111 and upper electrode 113 and lower electrode 114 on both sides, and may further include a functional layer 112 in at least one example. The functional layer 112 is an optional layer, and whether to add it can be determined according to the optimization direction of the performance of the resistive random access memory device R1, and corresponding design can be carried out thereon. The resistive switching layer 111 can be, for example, a single layer, including a single type of binary metal oxide (such as NiO, AlOx, etc.), graphene oxide, multi-element perovskite oxide (such as STO, SZO, PCMO, etc.), or can be a multi-layer, such as any optional stack of the above materials, for example, a stack of TixN and AlOx.

[0025] The resistive random access memory device can store data based on the resistive switching characteristic. The resistive switching characteristic of the resistive random access memory device is related to the conductive filament. By applying a set voltage or a reset voltage between the upper and lower electrodes of the resistive random access memory device, the conductive filament inside the resistive random access memory device can be restored or broken. When the conductive filament is connected, the resistive random access memory device exhibits a low resistance state (LRS), and at this time, the resistive random access memory device can be used to store data 0, for example; when the conductive filament is broken, the resistive random access memory device exhibits a high resistance state (HRS), and at this time, the resistive random access memory device can be used to store data 1, for example.

[0026] For example, after a conductive filament is formed inside the resistive random access memory device R1, the resistive random access memory device R1 has an operating threshold voltage. When the amplitude of the input voltage applied between the upper electrode 113 and the lower electrode 114 of the resistive random access memory device R1 is less than the operating threshold voltage of the resistive random access memory device R1, the resistance value (or conductance value) of the resistive random access memory device R1 will not change. In this case, the current stored value of the resistive random access memory device can be read by applying a read voltage to the resistive random access memory device. The current stored value of the resistive random access memory device can be, for example, the resistance value of the resistive random access memory device. The read voltage is less than the operating threshold voltage of the resistive random access memory device.

[0027] When the amplitude of the input voltage applied between the upper electrode 113 and the lower electrode 114 of the resistive random access memory device R1 is greater than the operating threshold voltage of the resistive random access memory device R1, the resistance value (or conductance value) of the resistive random access memory device R1 can be changed according to the set voltage or the reset voltage applied between the upper electrode 113 and the lower electrode 114 of the resistive random access memory device R1. For example, the set voltage is a positive voltage pulse, and the reset voltage is a negative voltage pulse. In the embodiments of the present disclosure, applying a set voltage to the resistive random access memory device is called a set operation, and applying a reset voltage to the resistive random access memory device is called a reset operation. One set operation or one reset operation can be used as one write operation.

[0028] The following is combined withFigure 2 The structure of the memory cell and the write operation are described in detail.

[0029] Figure 2 FIG. shows a schematic structural diagram of an exemplary memory cell. The memory cell includes a transistor M1 and a resistive random access memory device R1. For example, when the transistor M1 is an N-type transistor, its gate is connected to the word line WL. For example, when a high level is input to the word line WL, the transistor M1 is turned on; the first pole of the transistor M1 can be the source and is configured to be connected to the source line SL. For example, the transistor M1 can receive a reset voltage through the source line SL; the second pole of the transistor M1 can be the drain and is configured to be connected to the second pole (for example, the negative pole) of the resistive random access memory device R1, and the first pole (for example, the positive pole) of the resistive random access memory device R1 is connected to the bit line BL. For example, the resistive random access memory device R1 can receive a set voltage through the bit line BL. For example, when the transistor M1 is a P-type transistor, its gate is connected to the word line WL. For example, when a low level is input to the word line WL, the transistor M1 is turned on; the first pole of the transistor M1 can be the source and is configured to be connected to the source line SL. For example, the transistor M1 can receive a reset voltage through the source line SL; the second pole of the transistor M1 can be the drain and is configured to be connected to the second pole (for example, the negative pole) of the resistive random access memory device R1, and the first pole (for example, the positive pole) of the resistive random access memory device R1 is connected to the bit line BL. For example, the resistive random access memory device R1 can receive a set voltage through the bit line BL. It should be noted that the structure of the memory cell can also be implemented as other structures, such as a structure in which the second pole of the resistive random access memory device R1 is connected to the source line SL. The embodiments of the present disclosure do not limit this.

[0030] Taking the case where M1 is an N-type transistor as an example, the function of the word line WL is to apply a corresponding voltage to the gate of the transistor M1 to control the transistor M1 to be turned on or off. When performing a write operation on the resistive random access memory device R1, for example, a set operation or a reset operation, the transistor M1 needs to be turned on first, that is, a conduction voltage needs to be applied to the gate of the transistor M1 through the word line WL. After the transistor M1 is turned on, for example, a voltage can be applied to the resistive random access memory device R1 by the source line SL and the bit line BL to change the resistance state of the resistive random access memory device R1. For example, a set voltage can be applied through the bit line BL to make the resistive random access memory device R1 in a low resistance state; for another example, a reset voltage can be applied through the source line SL to make the resistive random access memory device R1 in a high resistance state. For example, the resistance value of the high resistance state is more than one hundred times, for example, more than one thousand times, the resistance value of the low resistance state.

[0031] Embodiments of the present disclosure have no restrictions on the type, structure, etc. of the storage unit. The structure of the storage unit can be 1T1R (including one transistor and one resistive random access memory device), 2T2R (including two transistors and two resistive random access memory devices), or other possible structures. It should be noted that the transistors used in the embodiments of the present disclosure can all be thin film transistors or field effect transistors (such as MOS field effect transistors) or other switching devices with the same characteristics. The source and drain of the transistors used here can be symmetric in structure, so there is no difference between them in structure. The embodiments of the present disclosure do not limit the type of transistors used.

[0032] Since there is no conductive filament inside the resistive random access memory device when it is fabricated, compared with other types of storage devices, the resistive random access memory device needs to undergo an additional initialization (Forming) process to obtain the resistive switching characteristics. The initialization process refers to applying a high voltage pulse across the two electrodes of the resistive random access memory device to induce the formation of a conductive filament inside the resistive random access memory device. After the conductive filament is formed inside the resistive random access memory device, the resistive random access memory device can become a low resistance at the set voltage or a high resistance at the reset voltage.

[0033] The initialization operation usually only needs to be performed once during the life cycle of the resistive random access memory device. However, since a very high voltage pulse (usually greater than the set voltage and the reset voltage) needs to be applied to the resistive random access memory device during initialization, and the differences of the resistive random access memory devices themselves are relatively large when they are just fabricated, the pulse time required for each resistive random access memory device to complete initialization is not necessarily the same. If the same pulse voltage time is applied to each resistive random access memory device, it may cause the initialization of some resistive random access memory devices to fail, thus affecting the performance of the storage unit. Therefore, after the initialization operation of the resistive random access memory device, it is usually necessary to perform multiple verification operations on the resistive random access memory device to check whether the resistive random access memory device has been successfully initialized.

[0034] A verification operation refers to obtaining the resistance value of a resistive random access memory (RRAM) device after applying an initialization voltage through a read operation, and checking whether the resistance value of the RRAM device has reached a target resistance value. For example, in the current initialization process, it is necessary to first apply an initialization voltage pulse with a preset time and a preset amplitude to an RRAM device, and then apply a read voltage to read the current resistance value of the RRAM device. If the current resistance value of this RRAM device does not reach the target resistance value, it means that this RRAM device has not been initialized yet. Then, it is necessary to change the amplitude of the initialization voltage pulse, or change the pulse time applied to the RRAM device, and then perform the initialization operation and verification operation on the RRAM device again until it is determined that the RRAM device has been successfully initialized. After initializing one RRAM device, repeat the above operations for the next RRAM device until all RRAM devices are successfully initialized. However, multiple verifications make the initialization process very time-consuming, greatly increasing the time costs of production and testing.

[0035] An effective solution to the above problems is parallel initialization. Parallel initialization refers to simultaneously applying the same initialization voltage pulse to multiple RRAM devices in a row, and the time of this initialization voltage pulse is set long enough so that any one of the RRAM devices can complete the initialization. That is to say, parallel initialization shortens the total time for initializing multiple RRAM devices as a whole by extending the time of a single initialization operation. However, parallel initialization operations cannot take into account the differences of the RRAM devices themselves, and the large current brought by parallel initialization operations also poses new challenges to circuit design.

[0036] On the one hand, too large a current on the bus will cause serious voltage drop (IR Drop) problems, which in turn limits the number of RRAM devices initialized in parallel. Here, voltage drop refers to the fact that due to the existence of wire resistance, when a large current flows through a long wire, there will be a voltage difference V = I * R between the proximal and distal ends of the wire. The voltage drop problem will cause the voltage obtained by the RRAM devices at the distal end of the bus to be much smaller than the preset initialization voltage. For example, since the word lines in a memory array are often very long (in the millimeter range), if the initialization current for each column is dozens of microamperes, then when one thousand columns are initialized simultaneously, the current on the bus will reach dozens of milliamperes, which will cause a very large voltage drop. The existence of voltage drop makes the RRAM devices at the distal end of the bus unable to receive a high enough initialization voltage, resulting in the RRAM devices at the distal end of the bus not being successfully initialized. Therefore, the number of columns in the memory array has to be limited within a certain range.

[0037] On the other hand, parallel initialization may also degrade the performance of the resistive memory device. During parallel initialization, in order to ensure that all the resistive memory devices in a row can be successfully initialized during initialization, the pulse time of the initialization voltage needs to be set relatively long to ensure sufficient margin. However, during the period when the initialization voltage pulse persists, current will continuously flow through the resistive memory device. Even with current-limiting protection measures, applying a high voltage to the resistive memory device for a long time may result in poor consistency or over-initialization of the resistive memory device. Therefore, the performance of the resistive memory device initialized in parallel is often inferior to that of the resistive memory device initialized one by one. In addition, the large current on the bus for a long time will also increase the power consumption.

[0038] At least one embodiment of the present disclosure provides a driving circuit, a memory device, and an operation method thereof. The driving circuit includes a control unit, a switching unit, and a sampling unit. The control unit is connected to a first voltage source and a second voltage source, and is configured to receive a first control signal from the first voltage source, receive a second control signal from the second voltage source, and conduct or cut off according to the first control signal, and apply the second control signal to a first node when conducting; the switching unit is connected to the control unit, a third voltage source, and an output terminal, and is configured to conduct or cut off according to the level of the first node, and conduct when the level of the first node is the second control signal to apply a first operating voltage received from the third voltage source to the output terminal; the sampling unit is connected to the output terminal, the third voltage source, and the switching unit, and is configured to conduct or cut off according to the feedback voltage of the output terminal, and apply the first operating voltage to the first node when conducting, so that the switching unit cuts off when the level of the first node is the first operating voltage.

[0039] The driving circuit provided by the above embodiment of the present disclosure can limit the value of the voltage at the output terminal according to the second control signal of the control unit, and automatically turn off the switching unit by the sampling unit according to the feedback voltage of the output terminal, thereby effectively controlling the voltage at the output terminal, realizing the function of self-stopping driving, and reducing the power consumption.

[0040] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, the present disclosure is not limited to these specific embodiments.

[0041] Figure 3 It is a schematic block diagram of a driving circuit provided by at least one embodiment of the present disclosure. As Figure 3 shown, the driving circuit 10 provided by at least one embodiment of the present disclosure includes a control unit, a switching unit, and a sampling unit.

[0042] The control unit is connected to the first voltage source U1 and the second voltage source U2, and is configured to receive a first control signal FORM from the first voltage source U1, receive a second control signal VFORM_I from the second voltage source U2, and conduct or cut off according to the first control signal FORM. When conducting, the second control signal VFORM_I is applied to the first node V1. That is, the first control signal FORM is used to turn on or off the control unit, and the second control signal VFORM_I is used to turn on or off the switching unit.

[0043] The switching unit is connected to the control unit, the third voltage source U3 and the output terminal OUT, and is configured to conduct or cut off according to the level of the first node V1, and conduct when the level of the first node V1 is the second control signal VFORM_I to apply the first operating voltage VFORM received from the third voltage source U3 to the output terminal OUT.

[0044] The second control signal VFORM_I and the first operating voltage VFORM can jointly adjust the voltage of the output terminal OUT. For example, the output terminal OUT is connected to a load. When the switching unit is turned on, the first operating voltage VFORM is provided to the load. The load can be, for example, a voltage-modulated device, including but not limited to a resistive random access memory device. The second control signal VFORM_I is used to limit the threshold value that the voltage of the output terminal OUT can reach. This threshold value can be, for example, the voltage value just enough to realize the function of the load.

[0045] The sampling unit is connected to the output terminal OUT, the third voltage source U3 and the switching unit, and is configured to conduct or cut off according to the feedback voltage VBL of the output terminal OUT, and apply the first operating voltage VFORM to the first node V1 when conducting, so that the switching unit cuts off when the level of the first node V1 is the first operating voltage VFORM.

[0046] When the driving circuit 10 operates, a first control signal FORM is applied to the control unit to turn on the control unit. The control unit applies the received second control signal VFORM_I to the switching unit to turn on the switching unit. After the switching unit is turned on, the first operating voltage VFORM is applied to the output terminal OUT. At the same time, the sampling unit can receive the feedback voltage VBL returned from the output terminal OUT and convert it into a signal for controlling the switching unit. When the feedback voltage VBL changes to the threshold voltage, the sampling unit turns off the switching unit, thereby blocking the path between the first operating voltage VFORM and the output terminal, and automatically stopping applying the driving voltage to the load at the output terminal.

[0047] Figure 4 Schematic diagram of the structure of an exemplary driving circuit provided by at least one embodiment of the present disclosure. As Figure 4As shown, in at least one embodiment of the present disclosure, the control unit includes a first transistor T1. The control electrode (e.g., gate) of the first transistor T1 is connected to a first voltage source U1. The first electrode (e.g., source) of the first transistor T1 is connected to a second voltage source U2. The second electrode (e.g., drain) of the first transistor T1 is connected to a first node V1.

[0048] For example, the switching unit includes a second transistor T2. The control electrode (e.g., gate) of the second transistor T2 is connected to the first node V1. The first electrode (e.g., source) of the second transistor T2 is connected to a third voltage source U3. The second electrode (e.g., drain) of the second transistor T2 is connected to the output terminal OUT.

[0049] For example, the sampling unit includes a third transistor T3. The control electrode (e.g., gate) of the third transistor T3 is connected to the output terminal OUT. The first electrode (e.g., source) of the third transistor T3 is connected to the third voltage source U3. The second electrode (e.g., drain) of the third transistor T3 is connected to the first node V1.

[0050] For example, in some embodiments of the present disclosure, the first transistor T1, the second transistor T2, and the third transistor T3 are P-type transistors. For example, the first transistor T1, the second transistor T2, and the third transistor T3 may all be PMOS transistors.

[0051] For example, in some other embodiments of the present disclosure, the first transistor T1, the second transistor T2, and the third transistor T3 are N-type transistors. For example, the first transistor T1, the second transistor T2, and the third transistor T3 may all be NMOS transistors.

[0052] For example, in still some other embodiments of the present disclosure, the functions of the control unit, the switching unit, and the sampling unit may also be implemented by other switching devices or circuit structures with the same transistor characteristics. The embodiments of the present disclosure do not limit the specific circuit elements and circuit structures in the control unit, the switching unit, and the sampling unit.

[0053] Figure 5 Schematic diagram of a memory device 100 provided by at least one embodiment of the present disclosure. As Figure 5 shown, the memory device 100 provided by at least one embodiment of the present disclosure includes a driving circuit 10 and a resistive random access memory device R1.

[0054] For example, the first end of the resistive random access memory device R1 is connected to the output terminal OUT of the driving circuit 10. The second end of the resistive random access memory device R1 is connected to a fourth voltage source U4. For example, the fourth voltage source U4 is grounded.

[0055] For example, the driving circuit 10 can be used for the resistive random access memory device R1 in a high-resistance state, such as a resistive random access memory device R1 that has just been fabricated and in which no conductive filaments have been formed internally. For example, the driving circuit 10 can convert the resistive random access memory device R1 from a high-resistance state to a low-resistance state, and automatically turn off when the resistive random access memory device R1 reaches the expected low-resistance state to stop providing the driving voltage. That is, when the resistive random access memory device R1 reaches the expected resistance state, the driving circuit 10 no longer continues to provide the first operating voltage VFORM to the resistive random access memory device R1, thereby effectively preventing over-initialization of the resistive random access memory device R1 and reducing power consumption to a certain extent.

[0056] At least one embodiment of the present disclosure further provides an operation method for a memory device. The operation method includes: receiving a first control signal from a first voltage source and a second control signal from a second voltage source through a control unit; turning on the control unit according to the first control signal, and applying the second control signal to a first node to turn on a switching unit; receiving a first operating voltage from a third voltage source through the switching unit, and applying the first operating voltage to a resistive random access memory device connected to an output terminal when the switching unit is turned on; turning on a sampling unit according to a feedback voltage at the output terminal, and applying the first operating voltage to the first node to turn off the switching unit.

[0057] For example, in some embodiments of the present disclosure, the first operating voltage includes an initialization voltage for the resistive random access memory device.

[0058] For example, in some embodiments of the present disclosure, the operation method further includes: changing a resistance value of the resistive random access memory device according to the first operating voltage.

[0059] For example, in some embodiments of the present disclosure, the feedback voltage changes corresponding to a change in the resistance value of the resistive random access memory device. When the resistance value of the resistive random access memory device reaches a target resistance value, the feedback voltage reaches a first threshold voltage to turn on the sampling unit.

[0060] For example, in some embodiments of the present disclosure, the operation method further includes: determining a magnitude of a current-limiting voltage of the second control signal according to a target resistance value of the resistive random access memory device.

[0061] The memory device and its operation method can control an initialization process of the resistive random access memory device, limit a lowest resistance that the resistive random access memory device can reach through a second control signal of the control unit, and automatically stop the initialization process of the resistive random access memory device and stop continuing to apply the initialization voltage to the resistive random access memory device when the resistance of the resistive random access memory device reaches the lowest resistance, thereby effectively preventing over-initialization of the resistive random access memory device and reducing power consumption.

[0062] The following Figure 5 illustrates the operation method in detail with reference to the memory device 100 shown.

[0063] For example, in one example of the embodiments of the present disclosure, the resistive random access memory device R1 is initialized by the driving circuit 10 as shown below. The control unit, the switching unit, and the sampling unit in the driving circuit 10 are respectively a P-type first transistor T1, a second transistor T2, and a third transistor T3. Figure 4 Shown below is the driving circuit 10 for initializing the resistive random access memory device R1. The control unit, the switching unit, and the sampling unit in the driving circuit 10 are respectively a P-type first transistor T1, a second transistor T2, and a third transistor T3.

[0064] First, the driving circuit 10 needs to be turned on. For example, a low-level pulse signal is applied to the first transistor T1 as a first control signal FORM to turn on the first transistor T1, so that a second control signal VFORM_I is provided to the second transistor T2. The level of the second control signal VFORM_I is less than the difference between the first operating voltage VFORM (for example, the initialization voltage) and the threshold voltage VGT3 of the second transistor T2, that is, VFORM_I < VFORM - VGT3. The magnitude of the current-limiting voltage of the second control signal VFORM_I can be determined according to the target resistance value of the resistive random access memory device R1. For example, if it is not desired that the resistance value of the resistive random access memory device R1 after initialization is too low, the current-limiting voltage of the second control signal VFORM_I can be set to be smaller, so that the degree of turning on of the second transistor T2 becomes smaller, thereby preventing the resistive random access memory device R1 from being over-initialized.

[0065] Since the resistance value of the original resistive random access memory device R1 is very large, the second transistor T2 is in the linear region and can provide the first operating voltage VFORM to the resistive random access memory device R1 with almost no loss, and the third transistor T3 is in the off state.

[0066] As the first operating voltage VFORM is applied to the resistive random access memory device R1, the resistance value of the resistive random access memory device R1 gradually decreases. When the resistance value of the resistive random access memory device R1 decreases to the target resistance value, it indicates that the resistive random access memory device R1 has been successfully initialized. At this time, the first operating voltage VFORM does not need to be applied to the resistive random access memory device R1 any more. Continuing to apply the first operating voltage VFORM may cause the resistance value of the resistive random access memory device R1 to be too low, resulting in over-initialization, which is not conducive to the performance of the resistive random access memory device.

[0067] In this case, the sampling unit in the driving circuit 10 starts to function. Since the resistance value of the resistive random access memory device R1 is low at this time, the current flowing through the second transistor T2 becomes high, and the feedback voltage VBL at the output terminal OUT decreases. When the feedback voltage VBL is less than the difference between the first operating voltage VFORM and the threshold voltage VGT2 of the third transistor (VBL < VFORM - VGT2), the third transistor T3 conducts. That is to say, the feedback voltage VBL can change corresponding to the change in the resistance value of the resistive random access memory device R1. When the resistance value of the resistive random access memory device R1 reaches the target resistance value, the feedback voltage VBL reaches the threshold to turn on the third transistor T3.

[0068] After the third transistor T3 conducts, the first operating voltage VFORM is transmitted to the first node V1, that is, the first operating voltage VFORM is transmitted to the gate of the second transistor T2, causing the second transistor T2 to quickly turn off, thereby turning off the conduction path between the third voltage source U3 and the output terminal OUT, and stopping applying the first operating voltage VFORM to the resistive random access memory device R1.

[0069] After the second transistor T2 turns off, the output terminal OUT is floating, and the charge on the bit line (BL) where the resistive random access memory device R1 is located can be gradually discharged through the gate capacitance of the third transistor T3. Therefore, the bit line returns to the low level, and the initialization process of the resistive random access memory device R1 ends.

[0070] For example, in some embodiments of the present disclosure, the first transistor T1, the second transistor T2, and the third transistor T3 can also be NMOS transistors. In this embodiment, the first transistor T1 conducts when the first control signal FORM is at a high level; the level of the second control signal VFORM_I should be greater than the difference between the first operating voltage VFORM and the threshold voltage VGT3 of the second transistor, that is, VFORM_I > VFORM - VGT3; when the feedback voltage VBL is greater than the difference between the first operating voltage VFORM and the threshold voltage VGT2 of the third transistor (VBL > VFORM - VGT2), the third transistor T3 conducts. The change processes of other operation steps and circuit elements except for the above differences are similar to those described above, and will not be elaborated here.

[0071] For example, in some embodiments of the present disclosure, the first operating voltage can also be a set voltage for the resistive random access memory device. For example, this driving circuit can accurately control the resistance value of the resistive random access memory device during the write operation, so that the verification operation after the write operation can be omitted, reducing the time cost. The method of using the driving circuit for the set operation of the resistive random access memory device can refer to the description of the initialization operation in the above embodiments, and will not be elaborated here.

[0072] At least one embodiment of the present disclosure further provides a memory device. The memory device includes a memory array and at least one driving circuit. The memory array includes a plurality of memory cells arranged in multiple rows and columns, word lines corresponding to each row in the memory array, bit lines corresponding to each row in the memory array, and source lines corresponding to each column in the memory array. Wherein, each memory cell includes a transistor and a resistive memory device. The gate of the transistor is connected to the word line corresponding to the row where the memory cell is located. The first pole of the transistor is connected to the source line corresponding to the column where the memory cell is located. The second pole of the transistor is connected to the first end of the resistive memory device. The second end of the resistive memory device is connected to the bit line corresponding to the row where the memory cell is located; each driving circuit is coupled to a bit line of the memory array.

[0073] The memory device can perform parallel initialization on the memory array through the driving circuit. And during the parallel initialization process, for the resistive memory devices that have completed initialization, the initialization voltage applied to them is automatically stopped, thereby effectively alleviating the voltage drop problem, shortening the initialization time, improving the uniformity and reliability of multiple resistive memory devices during parallel initialization, and reducing power consumption.

[0074] Figure 6 It is a schematic diagram of a memory device 200 provided by at least one embodiment of the present disclosure. As Figure 6 shown, the memory device 100 includes a memory array 20 and a plurality of driving circuits 10. For example, the plurality of driving circuits 10 are used as an initialization module to perform an initialization operation on the resistive memory devices in the memory array 20.

[0075] For example, the memory array 20 includes a plurality of memory cells, and the plurality of memory cells form an array of M rows and N columns, where both M and N are positive integers. For example, each memory cell includes a switching element (such as a transistor) and a resistive memory device. In Figure 6 it, WL[1], WL[2]... WL[m] respectively represent the word lines of the first row, the second row... the Mth row. The control poles (such as the gates of transistors) of the switching elements in the memory cells in each row are connected to the corresponding word lines of that row; BL[1], BL[2]... BL[n] respectively represent the bit lines of the first column, the second column... the Nth column. One end of the resistive memory device in the memory cells in each column is connected to the corresponding bit line of that column (and the other end is connected to, for example, the drain of the switching element in the memory cell); SL[1], SL[2]... SL[n] respectively represent the source lines of the first column, the second column... the Nth column. For example, the sources of the transistors in the memory cells in each column are connected to the corresponding source lines of that column. It should be noted that in the embodiments of the present disclosure, the directions of rows and columns are not limited to the situations in the figure, but can be determined as needed. The embodiments of the present disclosure do not limit the structure of the memory array 20.

[0076] For example, the output terminals of multiple driving circuits 10 are respectively coupled to multiple bit lines of the memory array 20, so that when the resistive memory devices in the memory array 20 are initialized in parallel, the initialization degree of the resistive memory devices in each column can be automatically controlled.

[0077] For example, multiple driving circuits 10 are connected to the bus of the initialization voltage to receive the first operating voltage VFORM. For example, multiple driving circuits 10 can receive the same second control voltage VFORM_I, so that the resistance values of the multiple resistive memory devices after initialization are substantially the same.

[0078] The process of the driving circuit 10 initializing each resistive memory device can refer to the detailed description of the operation method of self-stopping initialization in the foregoing embodiments, and will not be elaborated here.

[0079] In general, when the parallel initialization operation starts, the current on the VFORM bus increases rapidly. Since there is no voltage drop problem at the proximal end of the bus due to the small wire resistance, the resistive memory devices in the columns at the proximal end of the bus can receive the maximum voltage VFORM and start the initialization process under the regulation of this voltage. When the resistance of the resistive memory devices in this column drops to a certain value, the initialization of this column automatically stops and the current drops to 0. As more and more branches (columns) are turned off, the total current on the VFORM bus will gradually decrease, making the total current smaller, so the voltage drop problem at the distal end of the bus is alleviated. Therefore, the memory array 10 can gradually complete the initialization process from the proximal end to the distal end of the bus.

[0080] By using the operation method of self-stopping initialization provided by the foregoing embodiments of the present disclosure, when initializing multiple resistive memory devices in a certain row of the memory array 20, when the resistance of the resistive memory devices in a column drops below a certain value, the driving circuit 10 of this column can automatically stop the initialization process, thereby automatically "turning off" this branch. In this way, the uniformity and reliability of the resistive memory devices can be improved after the initialization operation of multiple storage units is performed simultaneously, while avoiding the voltage drop problem, reducing the current on the bus, and lowering the power consumption.

[0081] It should be noted that, from the perspective of statistical distribution, during parallel initialization, the resistive random access memory (RRAM) devices closer to the bus in the memory array 10 may complete initialization faster, while those farther from the bus may complete initialization slower. However, due to the differences in the RRAM devices themselves, the order in which multiple RRAM devices complete initialization is usually random. Additionally, during parallel initialization, the initialization times of multiple RRAM devices in a row are not necessarily the same, but the resistance values of the multiple RRAM devices after initialization can be controlled within a target range by the driving circuit. Therefore, the driving circuit, memory device, and its operation method provided by at least one embodiment of the present disclosure can also improve the accuracy of RRAM device initialization, and do not require additional verification operations, which can greatly shorten the initialization time and reduce production costs.

[0082] Although the present disclosure has been described in detail above using general descriptions and specific embodiments, based on the embodiments of the present disclosure, some modifications or improvements can be made, which are obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present disclosure all fall within the scope of protection required by the present disclosure.

[0083] The following points also need to be explained regarding the present disclosure:

[0084] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the usual designs.

[0085] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of the layers or regions is enlarged or reduced, that is, these drawings are not drawn according to the actual scale.

[0086] (3) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0087] As described above, the above are only the specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A driving circuit, comprising: a control unit, a switching unit, and a sampling unit, wherein the control unit is connected to a first voltage source and a second voltage source, and is configured to receive a first control signal from the first voltage source, receive a second control signal from the second voltage source, and conduct or cut off according to the first control signal, and when conducting, apply the second control signal to a first node; the switching unit is connected to the control unit, a third voltage source, and an output terminal, and is configured to conduct or cut off according to the level of the first node, and conduct when the level of the first node is the second control signal to apply a first operating voltage received from the third voltage source to the output terminal; the sampling unit is connected to the output terminal, the third voltage source, and the switching unit, and is configured to conduct or cut off according to a feedback voltage of the output terminal, and when conducting, apply the first operating voltage to the first node so that the switching unit cuts off when the level of the first node is the first operating voltage.

2. The driving circuit according to claim 1, wherein, the control unit includes a first transistor, a control electrode of the first transistor is connected to the first voltage source, a first pole of the first transistor is connected to the second voltage source, and a second pole of the first transistor is connected to the first node; the switching unit includes a second transistor, a control electrode of the second transistor is connected to the first node, a first pole of the second transistor is connected to the third voltage source, and a second pole of the second transistor is connected to the output terminal; the sampling unit includes a third transistor, a control electrode of the third transistor is connected to the output terminal, a first pole of the third transistor is connected to the third voltage source, and a second pole of the third transistor is connected to the first node.

3. The driving circuit according to claim 2, wherein, the first transistor, the second transistor, and the third transistor are P-type transistors.

4. A memory device, comprising: the driving circuit according to claim 1; a resistive random access memory (RRAM) device, a first end of the RRAM device is connected to the output terminal of the driving circuit, and a second end of the RRAM device is connected to a fourth voltage source.

5. An operation method of the memory device according to claim 4, comprising: receiving the first control signal from the first voltage source and the second control signal from the second voltage source through the control unit; conducting the control unit according to the first control signal, and applying the second control signal to the first node to conduct the switching unit; receiving the first operating voltage from the third voltage source through the switching unit, and applying the first operating voltage to the RRAM device connected to the output terminal when the switching unit is conducting; conducting the sampling unit according to the feedback voltage of the output terminal, and applying the first operating voltage to the first node to cut off the switching unit.

6. The operation method according to claim 5, wherein, The first operating voltage includes an initialization voltage or a set voltage for the resistive memory device.

7. The operating method according to claim 5 or 6, further comprises: changing a resistance value of the resistive memory device according to the first operating voltage.

8. The operating method according to claim 5 or 6, wherein the feedback voltage varies corresponding to a change in the resistance value of the resistive memory device, when the resistance value of the resistive memory device reaches a target resistance value, the feedback voltage reaches a first threshold voltage to turn on the sampling unit.

9. The operating method according to claim 5 or 6, further comprises: determining a magnitude of a current-limiting voltage of the second control signal according to the target resistance value of the resistive memory device.

10. A memory device, comprising: a memory array including a plurality of rows and columns of memory cells arranged in a plurality of rows and columns, word lines corresponding to respective rows in the memory array, bit lines corresponding to respective rows in the memory array, and source lines corresponding to respective columns in the memory array, wherein each memory cell includes a transistor and a resistive memory device, a gate of the transistor is connected to the word line corresponding to the row where the memory cell is located, a first pole of the transistor is connected to the source line corresponding to the column where the memory cell is located, a second pole of the transistor is connected to a first end of the resistive memory device, and a second end of the resistive memory device is connected to the bit line corresponding to the row where the memory cell is located; at least one driving circuit as claimed in claim 1, each of the driving circuits being coupled to one of the bit lines of the memory array.

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