Logic chip, memory chip, chip stacking structure and memory

Abstract

The invention provides a logic chip, a memory chip, a chip stacking structure and a memory, the logic chip is provided with a plurality of channel signal areas, a conductive through hole is divided into a plurality of repair unit groups, each repair unit group comprises four repair units, a first repair unit and a second repair unit are symmetrical along a first axis, and the first repair unit and the second repair unit are symmetrical along a second axis. The third repairing unit and the fourth repairing unit are symmetrical along the first axis, and the first repairing unit and the fourth repairing unit are symmetrical along the second axis.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a logic chip, a memory chip, a chip stacking structure, and a memory. Background Art

[0002] With the development of integrated circuit technology, significant progress has been made in the production process of semiconductor devices. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, limits of existing lithography technology, and limits of storage electron density, etc. Against this background, in order to solve the difficulties encountered by two-dimensional semiconductor devices and pursue a lower production cost per unit storage cell, multiple chips can be stacked using bonding processes (such as: Hybrid bonding, Bumping, Wire bonding) to form three-dimensional semiconductor devices. However, for three-dimensional semiconductor devices, there are still problems such as large parasitic capacitance and large parasitic resistance in the connection structure between different chips, which affect the signal transmission quality. Summary of the Invention

[0003] Embodiments of the present disclosure provide a logic chip, a memory chip, a chip stacking structure, and a memory.

[0004] In a first aspect, embodiments of the present disclosure provide a logic chip. The logic chip includes m channel signal regions arranged in sequence along a first direction. The logic chip has a chip axis that extends along a second direction and passes through the center of the logic chip. The m channel signal regions are symmetric about the chip axis; m is a positive integer. Each of the channel signal regions has a first axis and a second axis. The first axis extends along the first direction or the second direction, and the second axis is perpendicular to the first axis and intersects at the center of the corresponding channel signal region. Each of the channel signal regions is penetrated by a plurality of conductive vias along a third direction. The first direction, the second direction, and the third direction are perpendicular to each other pairwise. The first direction and the second direction are parallel to the top surface of the logic chip, and the third direction is perpendicular to the top surface of the logic chip. For each of the channel signal regions, the plurality of conductive vias therein are divided into a plurality of repair unit groups. Each repair unit group includes a first repair unit, a second repair unit, a third repair unit, and a fourth repair unit. The first repair unit and the second repair unit are symmetric about the first axis of the corresponding channel signal region. The third repair unit and the fourth repair unit are symmetric about the first axis of the corresponding channel signal region. The first repair unit and the fourth repair unit are symmetric about the second axis of the corresponding channel signal region. Each repair unit includes at least one redundant conductive via and at least one normal conductive via. When any one of the normal conductive vias is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset signal switching direction. Any conductive via in any one of the repair units is electrically connected to the internal circuit of the logic chip when used to transmit an effective signal. The normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit are in one-to-one correspondence and symmetric about the first axis of the corresponding channel signal region. The normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit are in one-to-one correspondence and symmetric about the first axis of the corresponding channel signal region. The normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit are in one-to-one correspondence and symmetric about the second axis of the corresponding channel signal region.

[0005] In some embodiments, for each of the repair unit groups, the preset switching direction of the conductive vias in the first repair unit and the preset switching direction of the conductive vias in the second repair unit are symmetric about the first axis of the channel signal region; the preset switching direction of the conductive vias in the third repair unit and the preset switching direction of the conductive vias in the fourth repair unit are symmetric about the first axis of the channel signal region; the preset switching direction of the conductive vias in the first repair unit and the preset switching direction of the conductive vias in the fourth repair unit are symmetric about the second axis of the channel signal region; the preset switching direction of the conductive vias in the second repair unit and the preset switching direction of the conductive vias in the third repair unit are symmetric about the second axis of the channel signal region.

[0006] In some embodiments, each of the channel signal regions is divided into 2×2 signal regions, and the conductive vias in each signal region are divided into n conductive via groups with the same distribution positions, where n is a positive integer; in the same channel signal region, the conductive via groups in the first signal region and the conductive via groups in the second signal region correspond one by one and are symmetric about the first axis of the channel signal region to which they belong, the conductive via groups in the third signal region and the conductive via groups in the fourth signal region correspond one by one and are symmetric about the first axis of the channel signal region to which they belong, and the conductive via groups in the first signal region and the conductive via groups in the fourth signal region correspond one by one and are symmetric about the second axis of the channel signal region to which they belong; each conductive via group includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via; in the same channel signal region, the overall formed by the first conductive via in a conductive via group in the first signal region, the second conductive via in the corresponding conductive via group in the second signal region, the third conductive via in the corresponding conductive via group in the third signal region, and the fourth conductive via in the corresponding conductive via group in the fourth signal region is symmetric about the first axis and symmetric about the second axis; in the same channel signal region, the overall formed by the second conductive via in a conductive via group in the first signal region, the first conductive via in the corresponding conductive via group in the second signal region, the fourth conductive via in the corresponding conductive via group in the third signal region, and the third conductive via in the corresponding conductive via group in the fourth signal region is symmetric about the first axis and symmetric about the second axis; in the same channel signal region, the overall formed by the third conductive via in a conductive via group in the first signal region, the fourth conductive via in the corresponding conductive via group in the second signal region, the first conductive via in the corresponding conductive via group in the third signal region, and the second conductive via in the corresponding conductive via group in the fourth signal region is symmetric about the first axis and symmetric about the second axis; in the same channel signal region, the overall formed by the fourth conductive via in a conductive via group in the first signal region, the third conductive via in the corresponding conductive via group in the second signal region, the second conductive via in the corresponding conductive via group in the third signal region, and the first conductive via in the corresponding conductive via group in the fourth signal region is symmetric about the first axis and symmetric about the second axis.

[0007] In some embodiments, B conductive via groups in each of the signal regions are referred to as 1 conductive via combination. The overall structure formed by the conductive via groups b in the corresponding conductive via combinations in all signal regions is symmetric along the first axis and symmetric along the second axis. B is a positive integer less than or equal to n, and b is a natural number less than B. In each of the signal regions in the same channel signal region, 1 corresponding conductive via combination in each signal region together constitute 4 repair unit groups: For the 1st repair unit group, the first repair unit therein includes: the first conductive vias of all the conductive via groups in the conductive via combination in the first signal region; the second repair unit therein includes: the second conductive vias of all the conductive via groups in the conductive via combination in the second signal region; the third repair unit therein includes: the third conductive vias of all the conductive via groups in the conductive via combination in the third signal region; the fourth repair unit therein includes: the fourth conductive vias of all the conductive via groups in the conductive via combination in the fourth signal region; For the 2nd repair unit group, the first repair unit therein includes: the first conductive vias of all the conductive via groups in the conductive via combination in the second signal region; the second repair unit therein includes: the second conductive vias of all the conductive via groups in the conductive via combination in the first signal region; the third repair unit therein includes: the third conductive vias of all the conductive via groups in the conductive via combination in the fourth signal region; the fourth repair unit therein includes: the fourth conductive vias of all the conductive via groups in the conductive via combination in the third signal region; For the 3rd repair unit group, the first repair unit therein includes: the first conductive vias of all the conductive via groups in the conductive via combination in the third signal region; the second repair unit therein includes: the second conductive vias of all the conductive via groups in the conductive via combination in the fourth signal region; the third repair unit therein includes: the third conductive vias of all the conductive via groups in the conductive via combination in the first signal region; the fourth repair unit therein includes: the fourth conductive vias of all the conductive via groups in the conductive via combination in the second signal region; For the 4th repair unit group, the first repair unit therein includes: the first conductive vias of all the conductive via groups in the conductive via combination in the fourth signal region; the second repair unit therein includes: the second conductive vias of all the conductive via groups in the conductive via combination in the third signal region; the fourth repair unit therein includes: the third conductive vias of all the conductive via groups in the conductive via combination in the second signal region;The fourth repair unit therein includes: the fourth conductive vias of each of the conductive via groups in the conductive via group combination in the first signal region.

[0008] In some embodiments, when B = 3, b can take values of 0, 1, or 2; all the conductive vias in the conductive via group 0 are normal conductive vias; the preset switching direction of the conductive vias in the Xth repair unit is: the Xth conductive via in the conductive via group 0 therein is allowed to be switched to the Xth conductive via in the conductive via group 1 in the same signal region, and the Xth conductive via in the conductive via group 1 is allowed to be switched to the Xth conductive via in the conductive via group 2 in the same signal region; X takes one, two, three, or four.

[0009] In some embodiments, when B = 6, b can take values of 0, 1, 2, 3, 4, or 5; all the conductive vias in the conductive via group 2 of all signal regions are normal conductive vias; the preset switching direction of the conductive vias in the Xth repair unit is: the Xth conductive via in the conductive via group 2 is allowed to be switched to the Xth conductive via in the conductive via group 3 in the same signal region, the Xth conductive via in the conductive via group 3 is allowed to be switched to the Xth conductive via in the conductive via group 4 in the same signal region, the Xth conductive via in the conductive via group 4 is allowed to be switched to the Xth conductive via in the conductive via group 1 in the same signal region; the Xth conductive via in the conductive via group 1 is allowed to be switched to the Xth conductive via in the conductive via group 0 in the same signal region; the Xth conductive via in the conductive via group 0 is allowed to be switched to the Xth conductive via in the conductive via group 5 in the same signal region.

[0010] In some embodiments, in each signal region, the conductive via group 0, the conductive via group 1, and the conductive via group 2 are aligned along the first direction; the conductive via group 3, the conductive via group 4, and the conductive via group 5 are aligned along the first direction; the conductive via group 0 and the conductive via group 5 are aligned along the second direction, the conductive via group 1 and the conductive via group 4 are aligned along the second direction, and the conductive via group 2 and the conductive via group 3 are aligned along the second direction.

[0011] In some embodiments, the conductive vias are prepared by any one or more of the processes of via - first process, via - middle process, via - last process, and back side via - last process; different conductive vias in the same logic chip are electrically isolated.

[0012] In a second aspect, embodiments of the present disclosure provide a storage chip, the storage chip includes m channels, the m channels are arranged in sequence along a first direction, the storage chip has a chip axis extending along a second direction and passing through the center of the storage chip, and the m channels are symmetric about the chip axis; each of the channels includes a first storage array region, a channel signal region, and a second storage array region that are sequentially distributed along the second direction, and the center of each channel signal region coincides with the center of the corresponding channel, where m is a positive integer; each channel signal region has a first axis and a second axis, the first axis extends along the first direction or the second direction, the second axis and the first axis are perpendicular to each other and intersect at the center of the corresponding channel signal region; each channel signal region is penetrated by a plurality of conductive vias along a third direction, the first direction, the second direction, and the third direction are perpendicular to each other pairwise, the first direction and the second direction are parallel to the top surface of the storage chip, and the third direction is perpendicular to the top surface of the storage chip; for each channel signal region, the plurality of conductive vias therein are divided into a plurality of repair unit groups; each repair unit group includes a first repair unit, a second repair unit, a third repair unit, and a fourth repair unit; the first repair unit and the second repair unit are symmetric about the first axis of the corresponding channel signal region, the third repair unit and the fourth repair unit are symmetric about the first axis of the corresponding channel signal region, and the first repair unit and the fourth repair unit are symmetric about the second axis of the corresponding channel signal region; each repair unit includes at least one redundant conductive via and at least one normal conductive via, when any one of the normal conductive vias is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset signal switching direction; any conductive via in the first repair unit is electrically connected to the internal circuit of the storage chip when used to transmit an effective signal; the normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit are in one-to-one correspondence and symmetric about the first axis of the corresponding channel signal region, the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit are in one-to-one correspondence and symmetric about the first axis of the corresponding channel signal region, and the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit are in one-to-one correspondence and symmetric about the second axis of the corresponding channel signal region.

[0013] In some embodiments, for each of the repair unit groups, the preset switching direction of the conductive vias in the first repair unit and the preset switching direction of the conductive vias in the second repair unit are symmetric along the first axis of the channel signal region; the preset switching direction of the conductive vias in the third repair unit and the preset switching direction of the conductive vias in the fourth repair unit are symmetric along the first axis of the channel signal region; the preset switching direction of the conductive vias in the first repair unit and the preset switching direction of the conductive vias in the fourth repair unit are symmetric along the second axis of the channel signal region; the preset switching direction of the conductive vias in the second repair unit and the preset switching direction of the conductive vias in the third repair unit are symmetric along the second axis of the channel signal region.

[0014] In some embodiments, each of the channel signal regions is divided into 2×2 signal regions, and the conductive vias in each signal region are divided into n conductive via groups with the same distribution positions, where n is a positive integer; in the same channel signal region, the conductive via groups in the first signal region and the conductive via groups in the second signal region correspond one by one and are symmetric along the first axis, the conductive via groups in the third signal region and the conductive via groups in the fourth signal region correspond one by one and are symmetric along the first axis, and the conductive via groups in the first signal region and the conductive via groups in the fourth signal region correspond one by one and are symmetric along the second axis; each conductive via group includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via; for the same channel signal region, the overall formed by the first conductive via in a conductive via group in the first signal region, the second conductive via in the corresponding conductive via group in the second signal region, the third conductive via in the corresponding conductive via group in the third signal region, and the fourth conductive via in the corresponding conductive via group in the fourth signal region is symmetric along the first axis and symmetric along the second axis; in the same channel signal region, the overall formed by the second conductive via in a conductive via group in the first signal region, the first conductive via in the corresponding conductive via group in the second signal region, the fourth conductive via in the corresponding conductive via group in the third signal region, and the third conductive via in the corresponding conductive via group in the fourth signal region is symmetric along the first axis and symmetric along the second axis; in the same channel signal region, the overall formed by the third conductive via in a conductive via group in the first signal region, the fourth conductive via in the corresponding conductive via group in the second signal region, the first conductive via in the corresponding conductive via group in the third signal region, and the second conductive via in the corresponding conductive via group in the fourth signal region is symmetric along the first axis and symmetric along the second axis; in the same channel signal region, the overall formed by the fourth conductive via in a conductive via group in the first signal region, the third conductive via in the corresponding conductive via group in the second signal region, the second conductive via in the corresponding conductive via group in the third signal region, and the first conductive via in the corresponding conductive via group in the fourth signal region is symmetric along the first axis and symmetric along the second axis.

[0015] In some embodiments, B conductive via groups in each of the signal regions are referred to as 1 conductive via combination. The overall structure formed by the conductive via groups b in the corresponding conductive via combinations in all the signal regions is symmetric along the first axis and symmetric along the second axis. B is a positive integer less than or equal to n, and b is a natural number less than B. In each of the signal regions in the same channel signal region, 1 corresponding conductive via combination in each signal region together constitutes 4 repair unit groups: For the first repair unit group, the first repair unit therein includes: the first conductive vias of all the conductive via groups in the conductive via combination in the first signal region; the second repair unit therein includes: the second conductive vias of all the conductive via groups in the conductive via combination in the second signal region; the third repair unit therein includes: the third conductive vias of all the conductive via groups in the conductive via combination in the third signal region; the fourth repair unit therein includes: the fourth conductive vias of all the conductive via groups in the conductive via combination in the fourth signal region; For the second repair unit group, the first repair unit therein includes: the first conductive vias of all the conductive via groups in the conductive via combination in the second signal region; the second repair unit therein includes: the second conductive vias of all the conductive via groups in the conductive via combination in the first signal region; the third repair unit therein includes: the third conductive vias of all the conductive via groups in the conductive via combination in the fourth signal region; the fourth repair unit therein includes: the fourth conductive vias of all the conductive via groups in the conductive via combination in the third signal region; For the third repair unit group, the first repair unit therein includes: the first conductive vias of all the conductive via groups in the conductive via combination in the third signal region; the second repair unit therein includes: the second conductive vias of all the conductive via groups in the conductive via combination in the fourth signal region; the third repair unit therein includes: the third conductive vias of all the conductive via groups in the conductive via combination in the first signal region; the fourth repair unit therein includes: the fourth conductive vias of all the conductive via groups in the conductive via combination in the second signal region; For the fourth repair unit group, the first repair unit therein includes: the first conductive vias of all the conductive via groups in the conductive via combination in the fourth signal region; the second repair unit therein includes: the second conductive vias of all the conductive via groups in the conductive via combination in the third signal region; the fourth repair unit therein includes: the third conductive vias of all the conductive via groups in the conductive via combination in the second signal region;The fourth repair unit therein includes: fourth conductive vias of each of the conductive via groups in the conductive via combination in the first signal region.

[0016] In some embodiments, when B = 3, the value of b is 0, 1, or 2; the conductive vias in the conductive via group 0 are all normal conductive vias; the preset switching direction of the conductive vias in any one of the first repair units is that: the first conductive via in the conductive via group 0 is allowed to be switched to the first conductive via in the conductive via group 1 in the same signal region, and the first conductive via in the conductive via group 1 is allowed to be switched to the first conductive via in the conductive via group 2 in the same signal region.

[0017] In some embodiments, when B = 6, the value of b is 0, 1, 2, 3, 4, or 5; the conductive vias in the conductive via group 0 of all signal regions are all normal conductive vias; the preset switching direction of the conductive vias in the first repair unit is that: the first conductive via in the conductive via group 2 is allowed to be switched to the first conductive via in the conductive via group 3 in the same signal region, the first conductive via in the conductive via group 3 is allowed to be switched to the first conductive via in the conductive via group 4 in the same signal region, the first conductive via in the conductive via group 4 is allowed to be switched to the first conductive via in the conductive via group 1 in the same signal region; the first conductive via in the conductive via group 1 is allowed to be switched to the first conductive via in the conductive via group 0 in the same signal region; the first conductive via in the conductive via group 0 is allowed to be switched to the first conductive via in the conductive via group 5 in the same signal region.

[0018] In a third aspect, an embodiment of the present disclosure provides a chip stacking structure, the chip stacking structure includes a logic chip as described in the first aspect and at least one stacking unit, and the logic chip and the at least one stacking unit are stacked in sequence along a third direction; each stacking unit includes a first storage chip, a second storage chip, a third storage chip, and a fourth storage chip stacked in sequence along the third direction, and the third direction is perpendicular to the top surface of each chip; the first storage chip, the second storage chip, the third storage chip, and the fourth storage chip are all storage chips as described in the second aspect; the first storage chip and the second storage chip are stacked face to face, the second storage chip and the third storage chip are stacked back to back, the third storage chip and the fourth storage chip are stacked face to face; the logic chip and the first storage chip are stacked back to back; or, the logic chip and the first storage chip are stacked face to back.

[0019] In some embodiments, the logic chip includes m channel signal regions arranged along a first direction. Each of the memory chips has m channels arranged along the first direction, and each of the channels includes a first memory array region, a channel signal region, and a second memory array region that are sequentially distributed along a second direction. The first direction, the second direction, and the third direction are perpendicular to each other in pairs, and the first direction and the second direction are parallel to the top surface of each chip. When the logic chip and the first memory chip are stacked back-to-back, and the first axes of the logic chip and each memory chip extend along the first direction, the (m - i)-th channel signal region in the logic chip is aligned with the channel signal region in the (i + 1)-th channel of the first memory chip, the channel signal region in the (i + 1)-th channel of the second memory chip, the channel signal region in the (m - i)-th channel of the third memory chip, and the channel signal region in the (m - i)-th channel of the fourth memory chip along the third direction, where i is a natural number less than m.

[0020] In some embodiments, the logic chip includes m channel signal regions arranged along a first direction. Each of the memory chips has m channels arranged along the first direction, and each of the channels includes a first memory array region, a channel signal region, and a second memory array region that are sequentially distributed along a second direction. When the logic chip and the first memory chip are stacked back-to-back, and the second axes of the logic chip and each memory chip extend along the first direction, the (i + 1)-th channel signal region in the logic chip is aligned with the channel signal region in the (i + 1)-th channel of the first memory chip, the channel signal region in the (m - i)-th channel of the second memory chip, the channel signal region in the (m - i)-th channel of the third memory chip, and the channel signal region in the (i + 1)-th channel of the fourth memory chip along the third direction, where i is a natural number less than m.

[0021] In some embodiments, the channel signal regions in each of the channels are each divided into 2×2 signal regions distributed in an array; only for a plurality of the channel signal regions aligned along the third direction: the fourth signal region belonging to the logic chip, the first signal region in the first memory chip, the second signal region in the second memory chip, the third signal region in the third memory chip, and the fourth signal region in the fourth memory chip are aligned along the third direction; the third signal region belonging to the logic chip, the second signal region in the first memory chip, the first signal region in the second memory chip, the fourth signal region in the third memory chip, and the third signal region in the fourth memory chip are aligned along the third direction; the second signal region belonging to the logic chip, the third signal region in the first memory chip, the fourth signal region in the second memory chip, the first signal region in the third memory chip, and the second signal region in the fourth memory chip are aligned along the third direction; the first signal region belonging to the logic chip, the fourth signal region in the first memory chip, the third signal region in the second memory chip, the second signal region in the third memory chip, and the first signal region in the fourth memory chip are aligned along the third direction.

[0022] In some embodiments, each of the signal regions includes n groups of conductive vias with the same distribution positions, and each group of conductive vias includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via; only for a plurality of the signal regions aligned along the third direction: the fourth conductive via belonging to the logic chip, the first conductive via belonging to the first memory chip, the second conductive via belonging to the second memory chip, the third conductive via belonging to the third memory chip, and the fourth conductive via belonging to the fourth memory chip are aligned along the third direction; the third conductive via belonging to the logic chip, the second conductive via belonging to the first memory chip, the first conductive via belonging to the second memory chip, the fourth conductive via belonging to the third memory chip, and the third conductive via belonging to the fourth memory chip are aligned along the third direction; the second conductive via belonging to the logic chip, the third conductive via belonging to the first memory chip, the fourth conductive via belonging to the second memory chip, the first conductive via belonging to the third memory chip, and the second conductive via belonging to the fourth memory chip are aligned along the third direction; the first conductive via belonging to the logic chip, the fourth conductive via belonging to the first memory chip, the third conductive via belonging to the second memory chip, the second conductive via belonging to the third memory chip, and the first conductive via belonging to the fourth memory chip are aligned along the third direction; wherein, a plurality of conductive vias aligned along the third direction are coupled to form a signal transmission channel.

[0023] In some embodiments, one of the fourth repair units in the logic chip, one of the first repair units in the first memory chip, one of the second repair units in the second memory chip, one of the third repair units in the third memory chip, and one of the fourth repair units in the fourth memory chip are aligned in the third direction and synchronously perform a conductive via switching operation; one of the third repair units in the logic chip, one of the second repair units in the first memory chip, one of the first repair units in the second memory chip, one of the fourth repair units in the third memory chip, and one of the third repair units in the fourth memory chip are aligned in the third direction and synchronously perform a conductive via switching operation; one of the second repair units in the logic chip, one of the third repair units in the first memory chip, one of the fourth repair units in the second memory chip, one of the first repair units in the third memory chip, and one of the second repair units in the fourth memory chip are aligned in the third direction and synchronously perform a conductive via switching operation; one of the first repair units in the logic chip, one of the fourth repair units in the first memory chip, one of the third repair units in the second memory chip, one of the second repair units in the third memory chip, and one of the first repair units in the fourth memory chip are aligned in the third direction and synchronously perform a conductive via switching operation.

[0024] In some embodiments, the logic chip includes m channel signal regions arranged in the first direction. Each memory chip has m channels arranged in the first direction, and each channel includes a first memory array region, a channel signal region, and a second memory array region that are sequentially distributed in the second direction. When the logic chip and the first memory chip are stacked back-to-back and the first axes of the logic chip and each memory chip extend in the first direction, the (i + 1)-th channel signal region in the logic chip is aligned with the channel signal region in the (i + 1)-th channel in the first memory chip, the channel signal region in the (i + 1)-th channel in the second memory chip, the channel signal region in the (m - i)-th channel in the third memory chip, and the channel signal region in the (m - i)-th channel in the fourth memory chip in the third direction; where i is a natural number less than m.

[0025] In some embodiments, the logic chip includes m channel signal regions arranged along a first direction. Each of the memory chips has m channels arranged along the first direction, and each of the channels includes a first memory array region, a channel signal region, and a second memory array region sequentially distributed along a second direction. When the logic chip and the first memory chip are stacked back-to-back, and the second axes of the logic chip and each of the memory chips extend along the first direction, the (m - i)-th channel signal region in the logic chip is aligned with the channel signal region in the (i + 1)-th channel of the first memory chip, the channel signal region in the (m - i)-th channel of the second memory chip, the channel signal region in the (m - i)-th channel of the third memory chip, and the channel signal region in the (i + 1)-th channel of the fourth memory chip along a third direction, where i is a natural number less than m.

[0026] In some embodiments, the channel signal region in each of the channels is divided into 2×2 signal regions arranged in an array. Only for the multiple channel signal regions aligned along the third direction: the second signal region belonging to the logic chip, the first signal region belonging to the first memory chip, the second signal region belonging to the second memory chip, the third signal region belonging to the third memory chip, and the fourth signal region belonging to the fourth memory chip are aligned along the third direction; the first signal region belonging to the logic chip, the second signal region belonging to the first memory chip, the first signal region belonging to the second memory chip, the fourth signal region belonging to the third memory chip, and the third signal region belonging to the fourth memory chip are aligned along the third direction; the fourth signal region belonging to the logic chip, the third signal region belonging to the first memory chip, the fourth signal region belonging to the second memory chip, the first signal region belonging to the third memory chip, and the second signal region belonging to the fourth memory chip are aligned along the third direction; the third signal region belonging to the logic chip, the fourth signal region belonging to the first memory chip, the third signal region belonging to the second memory chip, the second signal region belonging to the third memory chip, and the first signal region belonging to the fourth memory chip are aligned along the third direction.

[0027] In some embodiments, each of the signal regions includes n conductive via groups with the same distribution positions, and each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via; for a plurality of the signal regions aligned along a third direction: the second conductive vias belonging to the logic chip, the first conductive vias belonging to the first memory chip, the second conductive vias belonging to the second memory chip, the third conductive vias belonging to the third memory chip, and the fourth conductive vias belonging to the fourth memory chip are aligned along the third direction; the first conductive vias belonging to the logic chip, the second conductive vias belonging to the first memory chip, the first conductive vias belonging to the second memory chip, the fourth conductive vias belonging to the third memory chip, and the third conductive vias belonging to the fourth memory chip are aligned along the third direction; the fourth conductive vias belonging to the logic chip, the third conductive vias belonging to the first memory chip, the fourth conductive vias belonging to the second memory chip, the first conductive vias belonging to the third memory chip, and the second conductive vias belonging to the fourth memory chip are aligned along the third direction; the third conductive vias belonging to the logic chip, the fourth conductive vias belonging to the first memory chip, the third conductive vias belonging to the second memory chip, the second conductive vias belonging to the third memory chip, and the first conductive vias belonging to the fourth memory chip are aligned along the third direction; wherein, a plurality of conductive vias aligned along the third direction are coupled to form a signal transmission channel.

[0028] In some embodiments, one of the second repair units in the logic chip, one of the first repair units in the first memory chip, one of the second repair units in the second memory chip, one of the third repair units in the third memory chip, and one of the fourth repair units in the fourth memory chip are aligned in the third direction and synchronously perform a through-conductive via switching operation; one of the first repair units in the logic chip, one of the second repair units in the first memory chip, one of the first repair units in the second memory chip, one of the fourth repair units in the third memory chip, and one of the third repair units in the fourth memory chip are aligned in the third direction and synchronously perform a through-conductive via switching operation; one of the fourth repair units in the logic chip, one of the third repair units in the first memory chip, one of the fourth repair units in the second memory chip, one of the first repair units in the third memory chip, and one of the second repair units in the fourth memory chip are aligned in the third direction and synchronously perform a through-conductive via switching operation; one of the third repair units in the logic chip, one of the fourth repair units in the first memory chip, one of the third repair units in the second memory chip, one of the second repair units in the third memory chip, and one of the first repair units in the fourth memory chip are aligned in the third direction and synchronously perform a through-conductive via switching operation.

[0029] In some embodiments, for two chips connected face to face, the positions where the through-conductive vias in the two chips are aligned in the third direction are electrically connected through a hybrid bonding process; for two chips connected back to back or for two chips connected back to face, the positions where the through-conductive vias in the two chips are aligned in the third direction are electrically connected through a conductive bump bonding process; or, for two chips connected face to face or for two chips connected back to back or for two chips connected back to face, the positions where the through-conductive vias in the two chips are aligned in the third direction are all electrically connected through a hybrid bonding process; or, for two chips connected face to face or for two chips connected back to back or for two chips connected back to face, the positions where the through-conductive vias in the two chips are aligned in the third direction are all electrically connected through a conductive bump bonding process

[0030] Fourthly, an embodiment of the present disclosure provides a memory, and the memory includes a chip stacking structure as described in any one of the third aspects.

[0031] Embodiments of the present disclosure provide a logic chip, a memory chip, a chip stacking structure, and a memory. In each chip, there are multiple channel signal regions, and in each channel signal region, there are symmetrically arranged conductive vias, so that the chip stacking structure formed by the memory chip achieves a signal rotation transmission effect through the direct connection configuration of the conductive vias, and both the parasitic resistance and the parasitic capacitance are relatively small. At the same time, repair units are symmetrically divided in each channel signal region, which can realize the redundant repair function of the above chip stacking structure and improve the stability of the memory chip. Description of the Drawings

[0032] Figure 1 It is a schematic structural diagram of a chip;

[0033] Figure 2A It is a schematic diagram of the composition of a chip stacking structure Figure 1 ;

[0034] Figure 2B It is a schematic diagram of the composition of a chip stacking structure Figure 1 ;

[0035] Figure 3 It is a schematic diagram of a logic chip provided by an embodiment of the present disclosure;

[0036] Figure 4A / Figure 4B It is a schematic diagram of a logic chip provided by an embodiment of the present disclosure;

[0037] Figures 5 to 6D It is a schematic diagram of a repair unit in a logic chip provided by an embodiment of the present disclosure;

[0038] Figures 7 to 8D It is a schematic diagram of a repair unit in another logic chip provided by an embodiment of the present disclosure;

[0039] Figure 9 It is a schematic diagram of a memory chip provided by an embodiment of the present disclosure;

[0040] Figure 10A / Figure 10B It is a schematic diagram of a memory chip provided by an embodiment of the present disclosure;

[0041] Figures 11 to 12D It is a schematic diagram of a repair unit in a memory chip provided by an embodiment of the present disclosure;

[0042] Figures 13 to 14D It is a schematic diagram of a repair unit in another memory chip provided by an embodiment of the present disclosure;

[0043] Figure 15 It is a schematic diagram of the composition structure of a chip stacking structure provided by an embodiment of the present disclosure;

[0044] Figure 16A / Figure 16B Schematic diagram of the position of the repair unit in a chip stacking structure provided by an embodiment of the present disclosure;

[0045] Figure 17A / Figure 17B / Figure 17C Specific schematic diagram of the first chip stacking structure provided by an embodiment of the present disclosure;

[0046] Figure 18A / Figure 18B Specific schematic diagram of the second chip stacking structure provided by an embodiment of the present disclosure;

[0047] Figure 19A / Figure 19B Specific schematic diagram of the third chip stacking structure provided by an embodiment of the present disclosure;

[0048] Figure 20A / Figure 20B Specific schematic diagram of the fourth chip stacking structure provided by an embodiment of the present disclosure;

[0049] Figure 21 Schematic diagram of signal transmission of a chip stacking structure provided by an embodiment of the present disclosure;

[0050] Figure 22A / 22B Schematic diagram of the repair process of a chip stacking structure provided by an embodiment of the present disclosure;

[0051] Figure 23 Schematic diagram of signal transmission of another chip stacking structure provided by an embodiment of the present disclosure;

[0052] Figure 24A / 24B Schematic diagram of the repair process of another chip stacking structure provided by an embodiment of the present disclosure;

[0053] Figure 25 Schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Detailed implementation manners

[0054] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the related applications, rather than limiting the present disclosure. Additionally, it should be noted that for the convenience of description, only the parts related to the related applications are shown in the drawings.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0056] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

[0057] It should be noted that the terms "first / second / third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It is understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0058] Before introducing the embodiments of the present disclosure, three directions for describing three-dimensional structures that may be used in the following embodiments are defined. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0059] Please refer to Figure 1 , a semiconductor chip (specifically, a memory chip or a logic chip) may include a top surface on the front side and a bottom surface on the back side opposite to the front side; in the case of ignoring the flatness of the top surface and the bottom surface, the direction intersecting (e.g., perpendicular) with the top surface and the bottom surface of the semiconductor chip is defined as the third direction. On the top surface of the semiconductor chip, two mutually perpendicular directions are defined, namely the first direction and the second direction, and the first direction is perpendicular to one edge of the semiconductor chip, and the second direction is perpendicular to another edge of the semiconductor chip.

[0060] Please refer to Figure 1 , the semiconductor chip includes a substrate, and an active surface is formed on one side of the substrate for fabricating devices (such as transistors, capacitors, etc.). A plurality of metal layers, such as M1, M2, M3... are distributed between the substrate and the top surface. Figure 1 Also shown in are 2 types of conductive vias (e.g., through-silicon vias TSV), both of which are used to realize signal connections between different stacked chips.

[0061] As Figure 1 shown, for the type 1 conductive via, it penetrates the bottom surface and the top surface along the third direction, and the conductive via is connected to the internal circuit of the chip through the metal layer.

[0062] As Figure 1 shown, for the type 2 conductive via, it only penetrates the substrate along the third direction and needs to cooperate with a contact structure that penetrates the top surface along the third direction to jointly realize signal transmission; the contact structure and the conductive via are not directly electrically connected, but are indirectly electrically connected through the metal layer. For example: Figure 1The contact structure therein is connected to M4, and M4 is sequentially connected to M1 via M3 and M2, and M1 is connected to the conductive via. Of course, in other embodiments, the contact structure and the conductive via can also be designed to be directly electrically connected.

[0063] At the same time, the types of conductive vias are not limited to the above two, and the above are only examples. In particular, the diagrams presented in this disclosure do not mean actual views of any specific microelectronic device or its components, but are merely idealized representations for describing illustrative embodiments. Therefore, the diagrams are not necessarily to scale.

[0064] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0065] In one embodiment, a memory chip and a logic chip are provided. Both the memory chip / logic chip include a plurality of conductive vias penetrating the chip along the third direction. The conductive vias are used to realize signal transmission between different chips, and all the conductive vias can be located at any position. In particular, every 4 conductive vias can be regarded as a conductive via group in function, but the positions of these 4 conductive vias are not limited.

[0066] In a specific embodiment, 8 of the above-mentioned memory chips and 1 logic chip are stacked to form a 3D memory device. At the same time, the conductive vias of the 8 memory chips are aligned along the third direction, and 9 conductive vias in the aligned state along the third direction are connected to form an electrical path. Please refer to Figure 2A , which shows a signal transmission schematic diagram of a chip stacking structure. As Figure 2A shown, the chip stacking structure includes memory chips 0 to 7 and a logic chip. Figure 2A For each memory chip, only 4 conductive vias D0 to D3 are shown, and these 4 conductive vias D0 to D3 belong to the same conductive via group. At this time, the conductive vias D0 in the 8 memory chips and 1 logic chip are all aligned to form 1 electrical path, the conductive vias D1 in the 8 memory chips and 1 logic chip are all aligned to form 1 electrical path... The remaining conductive vias are similar.

[0067] At the same time, each memory chip and logic chip is also provided with a plurality of driving circuits ( Figure 2A only one driving circuit is shown by a dotted box in Figure 2AAmong mux0 to mux7), each conductive via group corresponds to one multiplexer, that is, all conductive vias in a conductive via group are connected to the data port of the multiplexer through their respective driving circuits. That is to say, the multiplexer can select which signal transmitted by the conductive via is output to the inside of the memory chip or which conductive via the signal output by the memory chip is output to.

[0068] For the overall memory device, different regions in different memory chips will be divided into different channels (for example: CH0, CH1, CH4, CH5) for management. The signal Signal_CH0 of channel CH0 is transmitted through the electrical path formed by "conductive via D0 in the logic chip, conductive via D0 in memory chip 0 - conductive via D0 in memory chip 1 - conductive via D0 in memory chip 2 - conductive via D0 in memory chip 3 - conductive via D0 in memory chip 4 - conductive via D0 in memory chip 5 - conductive via D0 in memory chip 6 - conductive via D0 in memory chip 7". The selection signals of the multiplexer mux0 in memory chip 0 and the multiplexer mux4 in memory chip 4 are both SEL_C0, that is, the signal Signal_CH0 can enter memory chip 0 and memory chip 4 through the aforementioned electrical path; the output process of the signal can be understood similarly.

[0069] As can be seen from the above, memory chip 0 only needs to obtain signals from conductive via D0, memory chip 1 only needs to obtain signals from conductive via D1... that is, each memory chip only needs to obtain signals from one of the conductive vias in a conductive via group. It should be noted that different memory chips may need to obtain signals from different conductive vias. However, since all memory chips need to be designed with exactly the same structure during the manufacturing process (so as to maximize cost and labor savings), all conductive vias in the memory chip need to be designed with corresponding driving structures and multiplexers to achieve structural consistency. Further, when adopting Figure 2A the shown chip stacking structure, each conductive via corresponds to a driving circuit; during the operation of this chip stacking structure, it is necessary to drive all the driving circuits in all memory chips in the same channel, with a large load and large parasitic capacitance, seriously affecting the performance of the chips therein, restricting the transmission efficiency and increasing power consumption, and also restricting the number of chip stacks in the three-dimensional device.

[0070] In another embodiment, please refer to Figure 2B , which shows the signal transmission schematic of another chip stacking structure. In particular, Figure 2B only some conductive vias are labeled (D0 to D3), and others are omitted, but for Figure 4AFor those, the identifiers of the conductive vias aligned in the third direction are the same. As Figure 2B shown, the chip stack structure also includes 8 memory chips and 1 logic chip aligned in the third direction. However, each conductive via in each memory chip is rotationally connected to another conductive via at a different position in another memory chip, achieving a spiral upward connection as a whole. That is, the signal Signal_CH0 of channel CH0 is transmitted through "the conductive via D0 in the logic chip - the conductive via D1 in memory chip 0 - the conductive via D2 in memory chip 1 - the conductive via D3 in memory chip 2 - the conductive via D0 in memory chip 3 - the conductive via D1 in memory chip 4 - the conductive via D2 in memory chip 5 - the conductive via D3 in memory chip 6 - the conductive via D0 in memory chip 7". The transmission of the remaining signals is similar.

[0071] In this way, memory chip 0 can obtain the signal Signal_CH0 through the output end of the conductive via D0 in the logic chip, memory chip 1 can obtain the signal Signal_CH1 through the input end of the conductive via D0 in memory chip 0, memory chip 2 can obtain the signal Signal_CH4 through the input end of the conductive via D0 in memory chip 1, memory chip 3 can obtain the signal Signal_CH5 through the input end of the conductive via D0 in memory chip 2... For each memory chip, only one conductive via in each conductive via group needs to be connected to the driving circuit, and there is no need to set a data selector, which can reduce the number of devices and thus reduce the parasitic capacitance. However, compared with Figure 2A the direct connection configuration of conductive vias, Figure 2B the process of rotational connection of conductive vias in Figure 2B is more complex. Specifically, Figure 2B in each memory chip in Figure 2B a horizontal interconnection structure needs to be set between adjacent conductive vias ( Figure 2B only one of them is marked with a five-pointed star in Figure 2B ). The signal interconnection structure can be a metal interconnection line, a conductive via, etc. In order to achieve the rotational connection of conductive vias, the input signal signal_CH0 from the conductive via D0 of the logic chip must first be transmitted upward to the interconnection structure below the conductive via D0 of memory chip 0 (not connected to the conductive via D0 of memory chip 0), and then horizontally transmitted from the interconnection structure below the conductive via D0 of memory chip 0 to the conductive via D1 of memory chip 0. That is: Figure 2B The structure shown in Figure 2B also needs to pass through the interconnection structure in each memory chip during the signal process, and the output signal is similar, which will inevitably lead to an increase in parasitic resistance and also increase the process complexity.

[0072] Especially, in Figure 2A and Figure 2BIn the chip stacking structure, all chips have their active surfaces facing up, that is, different memory chips are stacked back to back, and the memory chips and logic chips are also stacked back to back, namely, the bottom surface of the upper chip contacts the top surface of the lower chip.

[0073] Generally speaking, on the one hand, Figure 2A the chip stacking structure needs to set up more conductive vias to transmit corresponding signals. Coupled with the corresponding drive circuits and data selectors, the load and parasitic capacitance are relatively large. Figure 2B The chip stacking structure has a relatively large parasitic resistance due to the rotation configuration; on the other hand, Figure 2A and Figure 2B both stacking structures have certain problems and cannot be directly applied to the face-to-face stacking structure. Specifically, if you want to further implement the face-to-face chip stacking structure, one way is to use two sets of masks to make two different chips as the chips with the active surface facing up and the chips with the active surface facing down respectively. This way has a high process complexity and the cost is uncontrollable; another way is to make an additional set of conductive vias and connect both sets of conductive vias to the same drive circuit inside the memory chip. However, this will make the internal wiring of the memory chip complex, not only increasing the process complexity but also increasing the power consumption.

[0074] In an embodiment of the present disclosure, referring to Figure 3 , which shows a schematic diagram of the active surface in the logic chip 10. As Figure 3 shown, the logic chip 10 includes m channel signal regions arranged in sequence along the first direction ( Figure 3 illustrated with m = 4 as an example). The logic chip 10 has a chip axis YY' extending along the second direction and passing through the center of the logic chip 10, and the m channel signal regions are symmetric about the chip axis YY'.

[0075] As Figure 3 shown, the center and its adjacent regions of the active surface of the logic chip 10 are also defined as the global signal region. At this time, the first channel signal region 11, the second channel signal region 12, the global signal region, the third channel signal region 13, and the fourth channel signal region 14 are distributed in sequence along the first direction. Some logic control circuits of the stacked memory are distributed on the upper and lower sides of the channel signal region of the logic chip 10.

[0076] Figure 3Taking m = 4 as an example for illustration, the following also uses m = 4 as an example for explanation, but m can be any positive integer. Specifically, if m is an even number, then m / 2 channel signal regions are located on one side of the global signal region along the first direction, and the remaining m / 2 channel signal regions are located on the other side of the global signal region along the first direction; if m is an odd number, then the (m + 1) / 2-th channel signal region needs to be divided into two parts and located on both sides of the global signal region along the first direction respectively, while the other (m - 1) / 2 channel signal regions are located on one side of the global signal region along the first direction, and the remaining (m - 1) / 2 channel signal regions are located on the other side of the global signal region along the first direction.

[0077] It should be noted that during the chip manufacturing process, in order to distinguish different channel signal regions of the chip, a positioning structure can be made in the reference channel signal region (for example: the first channel signal region) of the logic chip 10, so that during subsequent packaging, the position of the reference channel can be identified through the positioning structure, and at the same time, other channels can be identified in combination with the orientation of the active surface of the chip.

[0078] It should be noted that both the global signal region and the channel signal region are penetrated by many conductive vias along the third direction, and the third direction is perpendicular to the active surface, that is, the first direction, the second direction, and the third direction are perpendicular to each other pairwise. Here, the conductive via can be a Through Silicon Via (TSV), specifically a vertical interconnection structure that penetrates the silicon wafer / chip. Or, in other embodiments, it can also be other conductive vias with conductive functions, and no specific limitation is made thereto. In addition, the conductive via can adopt the form of the aforementioned type 1 or the form of the aforementioned type 2.

[0079] For the global signal region, each conductive via is used to transmit the global signal, and the global signal is shared by all regions of the corresponding memory chip. The global signal includes but is not limited to: reset signal, power-on signal, stack identification signal SID / CID, power-related signal Voltage Monitor, timing-related signal Timing Aligner. In some cases, the global signal region can also refer to the pad region. The global signal can be a test signal for Design For Test (DFT). Through the global signal, the working condition of the internal circuit of the chip and the transmission condition of related signals can be known. In addition, because the pins of the DFT in the logic chip are generally located in the middle of the chip, the conductive vias of the global signals such as DFT are preferably located in the narrow region in the middle of the chip, that is, Figure 3 the position of the global signal region shown.

[0080] That is to say, the global signals transmitted by the global signal region are jointly used by m channels in all the memory chips in the subsequent stacked structure; while the channel control signals transmitted by each channel signal region are only used by a specific channel in all the memory chips in the subsequent stacked structure.

[0081] Please refer to Figure 4A , each channel signal region includes a first axis AA' and a second axis BB'. The first axis AA' extends along the first direction or the second direction, and the second axis BB' is perpendicular to the first axis AA' and intersects at the center of the corresponding channel signal region. For example, in Figure 3 , the first axis AA' extends along the first direction, and the second axis BB' extends along the second direction; in other embodiments, it is also possible that the first axis AA' extends along the second direction and the second axis BB' extends along the first direction. Figure 4A The global signal region is temporarily omitted. As Figure 4A shown, each channel signal region is penetrated by a plurality of conductive vias (D0, D1, D2, D3) along the third direction, and each conductive via is used to transmit the aforementioned channel control signals. The first direction, the second direction, and the third direction are perpendicular to each other pairwise, and the first direction and the second direction are parallel to the top surface of the logic chip 10, and the third direction is perpendicular to the top surface of the logic chip 10.

[0082] In the embodiments of the present disclosure, please refer to Figure 4B , for each channel signal region, (all or part of) the conductive vias therein are divided into a plurality of repair unit groups. Each repair unit group includes a first repair unit, a second repair unit, a third repair unit, and a fourth repair unit; the first repair unit and the second repair unit are symmetric about the first axis AA' of the corresponding channel signal region, the third repair unit and the fourth repair unit are symmetric about the first axis AA' of the corresponding channel signal region, and the first repair unit and the fourth repair unit are symmetric about the second axis BB' of the corresponding channel signal region. The above symmetry characteristics can be referred to as four-quadrant symmetry. In particular, Figure 4B the shapes of the repair unit groups in

[0083] Each repair unit (when not specified, the repair unit can be any one of the first repair unit, the second repair unit, the third repair unit, and the fourth repair unit) includes at least one redundant conductive via and at least one normal conductive via. Here, the normal conductive via refers to a conductive via that is designed to transmit valid signals from the beginning, and the redundant conductive via refers to a conductive via that is not designed to transmit any signals at the beginning. However, when any normal conductive via is damaged, the redundant conductive via can be changed to a normal conductive via to transmit valid signals, so that the memory can still work normally. That is to say, for the same repair unit, when any normal conductive via is damaged, the valid signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along the preset signal switching direction. Specifically: (1) If the next conductive via to be switched is a redundant conductive via, the repair ends, and at the same time, the redundant conductive via becomes a new normal conductive via; (2) If the next conductive via to be switched is another normal conductive via, the signal originally transmitted by the switched normal conductive via continues to be switched to its next conductive via along the preset switching direction until it is switched to a redundant conductive via.

[0084] Specifically, the logic chip 10 further includes a plurality of signal selection circuits (which may specifically include a data selector Mux and a driving unit). Taking signal output as an example, the signal to be transmitted generated inside the logic chip 10 is sent to the input end of the signal selection circuit, and the output ends of the signal selection circuit are respectively connected to a plurality of conductive vias; at this time, the signal selection circuit only sends the signal to be transmitted to one of the conductive vias. When the conductive via is damaged, the signal selection circuit can send the signal to be transmitted to another conductive via, thereby realizing the switching of the conductive via (that is, the switching of the signal transmission channel); the corresponding structure for signal input should be understood adaptively.

[0085] In this way, via the signal selection circuit, any conductive via in any repair unit is electrically connected to the internal circuit of the logic chip 10 when it is used to transmit valid signals, and any conductive via in any repair unit is electrically isolated from the internal circuit of the logic chip 10 when it does not transmit valid signals. Or it can be understood as: any conductive via in any repair unit is electrically connected to the internal circuit of the logic chip 10 when it is a normal conductive via, and any conductive via in any repair unit is electrically isolated from the internal circuit of the logic chip 10 when it is not a normal conductive via.

[0086] The number of redundant conductive vias and the number of normal conductive vias in each repair unit can be determined flexibly. Taking the example that each repair unit includes 4 different conductive vias, at this time, the number of normal conductive vias: the number of redundant conductive vias = 2:2, or the number of normal conductive vias: the number of redundant conductive vias = 1:3, or the number of normal conductive vias: the number of redundant conductive vias = 3:1, etc.; taking the example that each repair unit includes 6 different conductive vias, at this time, the number of normal conductive vias: the number of redundant conductive vias = 4:2, or the number of normal conductive vias: the number of redundant conductive vias = 3:3... It can be selected according to the actual application scenario.

[0087] In the embodiments of the present disclosure, the normal conductive vias in the repair unit have the following symmetry relationship: the normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit are in one-to-one correspondence and symmetric about the first axis AA' of the channel signal region to which they belong; the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit are in one-to-one correspondence and symmetric about the first axis AA' of the channel signal region to which they belong; the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit are in one-to-one correspondence and symmetric about the second axis BB' of the channel signal region to which they belong, that is, the positions of the normal conductive vias also have the characteristics of four-quadrant symmetry.

[0088] In this way, the repair units in the logic chip 10 have a four-quadrant symmetry relationship, and the normal conductive vias therein also have a four-quadrant symmetry relationship. Therefore, the chip stack structure formed by this logic chip and the memory chip (which also has the same characteristics) can achieve the signal rotation transmission effect through the direct connection configuration of the conductive vias, and the parasitic resistance and parasitic capacitance are relatively small. For details, please refer to the following description; at the same time, through the repair units arranged in four-quadrant symmetry, the redundant repair function of the above structure can also be realized, improving the stability of the chip; at the same time, the distribution of the conductive via groups and repair units in different channel signal regions is the same, and the same mask plate can be used.

[0089] In the implementation of the present disclosure, for each repair unit group, the preset switching direction of the conductive vias in the first repair unit and the preset switching direction of the conductive vias in the second repair unit are symmetric about the first axis AA' of the channel signal region to which they belong; the preset switching direction of the conductive vias in the third repair unit and the preset switching direction of the conductive vias in the fourth repair unit are symmetric about the first axis AA' of the channel signal region to which they belong; the preset switching direction of the conductive vias in the first repair unit and the preset switching direction of the conductive vias in the fourth repair unit are symmetric about the second axis BB' of the channel signal region to which they belong; the preset switching direction of the conductive vias in the second repair unit and the preset switching direction of the conductive vias in the third repair unit are symmetric about the second axis BB' of the channel signal region to which they belong.

[0090] Please refer toFigure 4A , each channel signal region 20 is divided into 2×2 signal areas, namely the first signal area 21, the second signal area 22, the third signal area 23, and the fourth signal area 24; (all or part of) the conductive vias in each signal area are divided into n conductive via groups with the same distribution positions, where n is a positive integer. Figure 4A Each dashed box in it is a conductive via group. As Figure 4A shown, the conductive via groups in the first signal area 21 and the conductive via groups in the second signal area 22 correspond one by one and are symmetric along the first axis AA' of the corresponding channel signal region. The conductive via groups in the third signal area 23 and the conductive via groups in the fourth signal area 24 correspond one by one and are symmetric along the first axis AA' of the corresponding channel signal region. The conductive via groups in the first signal area 21 and the conductive via groups in the fourth signal area 24 correspond one by one and are symmetric along the second axis BB' of the corresponding channel signal region, that is, the conductive via groups are also symmetric in four quadrants. Here, Figure 4A only 1 conductive via group is shown for each signal area, but in fact, the number of conductive via groups in each signal area is very large.

[0091] As Figure 4A shown, each conductive via group includes a first conductive via D0, a second conductive via D1, a third conductive via D2, and a fourth conductive via D3; and has the following symmetry relationships:

[0092] (1) In the same channel signal region, the whole formed by the first conductive via D0 in a conductive via group in the first signal area 21, the second conductive via D1 in the corresponding conductive via group in the second signal area 22, the third conductive via D2 in the corresponding conductive via group in the third signal area 23, and the fourth conductive via D3 in the corresponding conductive via group in the fourth signal area 24 is symmetric along the first axis AA' and symmetric along the second axis BB'.

[0093] (2) In the same channel signal region, the whole formed by the second conductive via D1 in a conductive via group in the first signal area 21, the first conductive via D0 in the corresponding conductive via group in the second signal area 22, the fourth conductive via D3 in the corresponding conductive via group in the third signal area 23, and the third conductive via D2 in the corresponding conductive via group in the fourth signal area 24 is symmetric along the first axis AA' and symmetric along the second axis BB'.

[0094] (3) In the same channel signal region, the overall structure formed by the third conductive via D2 in a conductive via group in the first signal region 21, the fourth conductive via D3 in the corresponding conductive via group in the second signal region 22, the first conductive via D0 in the corresponding conductive via group in the third signal region 23, and the second conductive via D1 in the corresponding conductive via group in the fourth signal region 24 is symmetric along the first axis AA' and symmetric along the second axis BB'.

[0095] (4) In the same channel signal region, the overall structure formed by the fourth conductive via D3 in a conductive via group in the first signal region 21, the third conductive via D2 in the corresponding conductive via group in the second signal region 22, the second conductive via D1 in the corresponding conductive via group in the third signal region 23, and the first conductive via D0 in the corresponding conductive via group in the fourth signal region 24 is symmetric along the first axis AA' and symmetric along the second axis BB'.

[0096] It should be understood that Figure 4A in, the 4 conductive vias in each conductive via group are arranged in a 2×2 array. However, in other embodiments, the 4 conductive vias in each conductive via group can be arbitrarily distributed as long as the above symmetry principle is followed.

[0097] Due to space limitations, the subsequent drawings only take one channel signal region as an example to illustrate the composition and principle of the repair unit group. In fact, the structures of all channel signal regions are the same, that is, the channel signal region in the drawings can be understood as any one of the channel signal regions 11, 12, 13, and 14.

[0098] In some embodiments, B conductive via groups in each signal region are referred to as 1 conductive via combination. The overall structure formed by the conductive via group b in the corresponding conductive via combinations in all signal regions is symmetric along the first axis AA' and symmetric along the second axis BB'. B is a positive integer less than or equal to n, and b is a natural number less than B.

[0099] In the same channel signal region, a total of 4 repair unit groups are formed by the corresponding 1 conductive via combination in each signal region:

[0100] (1) For the first repair unit group, the first repair unit therein includes: the first conductive vias D0 of each of all the conductive via groups in the conductive via combination in the first signal region 21; the second repair unit therein includes: the second conductive vias D1 of each of all the conductive via groups in the conductive via combination in the second signal region 22; the third repair unit therein includes: the third conductive vias D2 of each of all the conductive via groups in the conductive via combination in the third signal region 23; the fourth repair unit therein includes: the fourth conductive vias D3 of each of all the conductive via groups in the conductive via combination in the fourth signal region 24;

[0101] (2) For the second repair unit group, the first repair unit therein includes: the first conductive vias D0 of each of all the conductive via groups in the conductive via combination in the second signal region 22; the second repair unit therein includes: the second conductive vias D1 of each of all the conductive via groups in the conductive via combination in the first signal region 21; the third repair unit therein includes: the third conductive vias D2 of each of all the conductive via groups in the conductive via combination in the fourth signal region 24; the fourth repair unit therein includes: the fourth conductive vias D3 of each of all the conductive via groups in the conductive via combination in the third signal region 23;

[0102] (3) For the third repair unit group, the first repair unit therein includes: the first conductive vias D0 of each of all the conductive via groups in the conductive via combination in the third signal region 23; the second repair unit therein includes: the second conductive vias D1 of each of all the conductive via groups in the conductive via combination in the fourth signal region 24; the third repair unit therein includes: the third conductive vias D2 of each of all the conductive via groups in the conductive via combination in the first signal region 21; the fourth repair unit therein includes: the fourth conductive vias D3 of each of all the conductive via groups in the conductive via combination in the second signal region 22;

[0103] (4) For the fourth repair unit group, the first repair unit therein includes: the first conductive vias D0 of each of all the conductive via groups in the conductive via combination in the fourth signal region 24; the second repair unit therein includes: the second conductive vias D1 of each of all the conductive via groups in the conductive via combination in the third signal region 23; the third repair unit therein includes: the third conductive vias D2 of each of all the conductive via groups in the conductive via combination in the second signal region 22; the fourth repair unit therein includes: the fourth conductive vias D3 of each of all the conductive via groups in the conductive via combination in the first signal region 21.

[0104] It should be noted that for the same logic chip 10, B can have multiple values. For example, in the same logic chip 10, there is a conductive via combination composed of 4 conductive via groups, and there is also a conductive via combination composed of 6 conductive via groups, or there are more forms. However, no matter how many conductive via groups are included, each conductive via combination will surely form 4 repair unit groups.

[0105] In the first specific embodiment, please refer to Figure 5 , B = 3, and b takes 0, 1, or 2. That is to say, the whole formed by the conductive via group 0 in the first signal region 21, the conductive via group 0 in the second signal region 22, the conductive via group 0 in the third signal region 23, and the conductive via group 0 in the fourth signal region 24 is symmetric along the first axis AA' and symmetric along the second axis BB'; the whole formed by the conductive via group 1 in the first signal region 21, the conductive via group 1 in the second signal region 22, the conductive via group 1 in the third signal region 23, and the conductive via group 1 in the fourth signal region 24 is symmetric along the first axis AA' and symmetric along the second axis BB';...

[0106] The conductive via groups 0 to 2 in each signal region in the same channel signal region together form 4 repair unit groups:

[0107] Please refer to Figure 6A , for the first repair unit group _1: (1) The first repair unit _1 therein includes: the first conductive vias of the conductive via group 0, the conductive via group 1, and the conductive via group 2 in the first signal region 21, that is, D0 / 0, D0 / 1, and D0 / 2 in the first signal region 21; (2) The second repair unit _1 therein includes: the second conductive vias of the conductive via group 0, the conductive via group 1, and the conductive via group 2 in the second signal region 22, that is, D1 / 0, D1 / 1, and D1 / 2 in the second signal region 22; (3) The third repair unit _1 therein includes: the third conductive vias of the conductive via group 0, the conductive via group 1, and the conductive via group 2 in the third signal region 23, that is, D2 / 0, D2 / 1, and D2 / 2 in the third signal region 23; (4) The fourth repair unit _1 therein includes: the fourth conductive vias of the conductive via group 0, the conductive via group 1, and the conductive via group 2 in the fourth signal region 24, that is, D3 / 0, D3 / 1, and D3 / 2 in the fourth signal region 24.

[0108] Please refer to Figure 6B, for the second repair unit group _2, (1) the first repair unit _2 therein includes: the first conductive vias of the conductive via groups 0, 1, and 2 in the second signal region 22, that is, D0 / 0, D0 / 1, D0 / 2 in the second signal region 22; (2) the second repair unit _2 therein includes: the second conductive vias of the conductive via groups 0, 1, and 2 in the first signal region 21, that is, D1 / 0, D1 / 1, D1 / 2 in the first signal region 21; (3) the third repair unit _2 therein includes: the third conductive vias of the conductive via groups 0, 1, and 2 in the fourth signal region 24, that is, D2 / 0, D2 / 1, D2 / 2 in the fourth signal region 24; (4) the fourth repair unit _2 therein includes: the fourth conductive vias of the conductive via groups 0, 1, and 2 in the third signal region 23, that is, D3 / 0, D3 / 1, D3 / 2 in the third signal region 23.

[0109] Please refer to Figure 6C , for the third repair unit group _3, (1) the first repair unit _3 therein includes: the first conductive vias of the conductive via groups 0, 1, and 2 in the third signal region 23, that is, D0 / 0, D0 / 1, D0 / 2 in the third signal region 23; (2) the second repair unit _3 therein includes: the second conductive vias of the conductive via groups 0, 1, and 2 in the fourth signal region 24, that is, D1 / 0, D1 / 1, D1 / 2 in the fourth signal region 24; (3) the third repair unit _3 therein includes: the third conductive vias of the conductive via groups 0, 1, and 2 in the first signal region 21, that is, D2 / 0, D2 / 1, D2 / 2 in the first signal region 21; (4) the fourth repair unit _3 therein includes: the fourth conductive vias of the conductive via groups 0, 1, and 2 in the second signal region 22, that is, D3 / 0, D3 / 1, D3 / 2 in the second signal region 22.

[0110] Please refer to Figure 6D, for the 4th repair unit group _4, (1) the first repair unit _4 therein includes: the first conductive vias of the conductive via groups 0, 1, and 2 in the fourth signal region 24, that is, D0 / 0, D0 / 1, D0 / 2 in the fourth signal region 24; (2) the second repair unit _4 therein includes: the second conductive vias of the conductive via groups 0, 1, and 2 in the third signal region 23, that is, D2 / 0, D2 / 1, D2 / 2 in the third signal region 23; (3) the third repair unit _4 therein includes: the third conductive vias of the conductive via groups 0, 1, and 2 in the second signal region 22, that is, D2 / 0, D2 / 1, D2 / 2 in the second signal region 22; (4) the fourth repair unit _4 therein includes: the fourth conductive vias of the conductive via groups 0, 1, and 2 in the first signal region 21, that is, D3 / 0, D3 / 1, D3 / 2 in the first signal region 21.

[0111] It should be noted that: as Figure 6A shown, for the 1st repair unit group, the first repair unit _1 (D0 / 0, D0 / 1, D0 / 2 in the first signal region 21) and the second repair unit _1 (D1 / 0, D1 / 1, D1 / 2 in the first signal region 22) are symmetric along the first axis AA', the third repair unit _1 (D2 / 0, D2 / 1, D2 / 2 in the third signal region 23) and the fourth repair unit _1 (D3 / 0, D3 / 1, D3 / 2 in the fourth signal region 24) are symmetric along the first axis AA', the first repair unit _1 (D0 / 0, D0 / 1, D0 / 2 in the first signal region 21) and the fourth repair unit _1 (D3 / 0, D3 / 1, D3 / 2 in the fourth signal region 24) are symmetric along the second axis BB', and the second repair unit _1 (D1 / 0, D1 / 1, D1 / 2 in the first signal region 22) and the third repair unit _1 (D2 / 0, D2 / 1, D2 / 2 in the third signal region 23) are symmetric along the second axis BB'. At the same time, the 2nd to 4th repair unit groups also have similar characteristics.

[0112] The following provides an example of a preset switching direction for better understanding of the foregoing description, but the following example is not the only solution.

[0113] Assume that all the conductive vias in the conductive via group 0 are normal conductive vias; the preset switching direction of the conductive vias in the Xth repair unit is: the Xth conductive via in the conductive via group 0 is allowed to be switched to the Xth conductive via in the conductive via group 1 in the same signal region, and the Xth conductive via in the conductive via group 1 is allowed to be switched to the Xth conductive via in the conductive via group 2 in the same signal region; X takes one, two, three, or four.

[0114] That is to say, please refer toFigure 6A For the first repair unit group, the preset switching directions of the conductive vias in the first repair unit_1 are: D0 / 0 - D0 / 1 - D0 / 2 in the first signal region 21; the preset switching directions of the conductive vias in the second repair unit_1 are: D1 / 0 - D1 / 1 - D1 / 2 in the second signal region 22; the preset switching directions of the conductive vias in the third repair unit_1 are: D2 / 0 - D2 / 1 - D2 / 2 in the third signal region 23; the preset switching directions of the conductive vias in the fourth repair unit_1 are: D3 / 0 - D3 / 1 - D3 / 2 in the fourth signal region 24.

[0115] Please refer to Figure 6B For the second repair unit group, the preset switching directions of the conductive vias in the first repair unit_2 are: D0 / 0 - D0 / 1 - D0 / 2 in the second signal region 22; the preset switching directions of the conductive vias in the second repair unit_2 are: D1 / 0 - D1 / 1 - D1 / 2 in the first signal region 21; the preset switching directions of the conductive vias in the third repair unit_2 are: D2 / 0 - D2 / 1 - D2 / 2 in the fourth signal region 24; the preset switching directions of the conductive vias in the fourth repair unit_2 are: D3 / 0 - D3 / 1 - D3 / 2 in the third signal region 23.

[0116] Please refer to Figure 6C For the third repair unit group, the preset switching directions of the conductive vias in the first repair unit_3 are: D0 / 0 - D0 / 1 - D0 / 2 in the third signal region 23; the preset switching directions of the conductive vias in the second repair unit_3 are: D1 / 0 - D1 / 1 - D1 / 2 in the fourth signal region 22; the preset switching directions of the conductive vias in the third repair unit_3 are: D2 / 0 - D2 / 1 - D2 / 2 in the first signal region 21; the preset switching directions of the conductive vias in the fourth repair unit_3 are: D3 / 0 - D3 / 1 - D3 / 2 in the second signal region 22.

[0117] Please refer to Figure 6D For the fourth repair unit group, the preset switching directions of the conductive vias in the first repair unit_4 are: D0 / 0 - D0 / 1 - D0 / 2 in the fourth signal region 24; the preset switching directions of the conductive vias in the second repair unit_4 are: D1 / 0 - D1 / 1 - D1 / 2 in the third signal region 22; the preset switching directions of the conductive vias in the third repair unit_4 are: D2 / 0 - D2 / 1 - D2 / 2 in the second signal region 23; the preset switching directions of the conductive vias in the fourth repair unit_4 are: D3 / 0 - D3 / 1 - D3 / 2 in the second signal region 21.

[0118] It should be noted that for each of the above repair units, the ratio of the number of normal conductive vias to redundant conductive vias can be set arbitrarily, such as 1:2, 2:1, etc.

[0119] For the convenience of understanding, the following takes the repair ratio of normal conductive vias: redundant conductive vias = 2:1 as an example to provide a specific description of a signal switching related circuit. To implement the above switching process, please refer to Figure 6A 、 Figure 6B 、 Figure 6C and Figure 6D . The logic chip 10 further includes a plurality of signal selection circuits 100 for implementing the switching of the above conductive vias. Specifically, each signal selection circuit 100 is composed of a data selector and a plurality of driving units. The data selector in the signal selection circuit 100 is connected to a plurality of conductive via groups, and the driving circuit in the signal selection circuit 100 is connected to the internal circuit of the logic chip 10. Thus, through the signal selection circuit 100, a specified conductive via can be selected to be electrically connected to the internal circuit of the logic chip 10, so that the switching of the conductive vias can be performed.

[0120] Taking the first repair unit _1 of the first repair unit group (D0 / 0, D0 / 1, D0 / 2 in the first signal area 21) as an example, please refer to Figure 6A . D0 / 0 and D0 / 1 are connected to the first signal selection circuit 100, and the first signal selection circuit 100 connects D0 / 0 to the internal circuit of the logic circuit 10; D0 / 1 and D0 / 2 are connected to the second signal selection circuit 100, and the second signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10; then, if D0 / 0 is damaged, the first signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 0 will be transmitted by D0 / 1; at the same time, the second signal selection circuit 100 connects D0 / 2 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 1 will be transmitted by D0 / 2. The remaining repair units can be understood by reference.

[0121] It should be noted that Figures 6A to 6D This is only an example of the preset switching direction; the preset switching direction actually has very flexible options. Taking the first repair unit _1 as an example, it can currently switch in sequence along D0 / 0, D0 / 1, D0 / 2, or switch in the order of D0 / 2, D0 / 1, D0 / 0, or use D0 / 1 as the switching starting point, etc. Of course, the four repair units must follow the aforementioned symmetry characteristics, that is, if the first repair unit _1 adopts other switching forms and definitions of normal conductive vias, then the second repair unit _1, the third repair unit _1, and the fourth repair unit _1 must also adopt corresponding switching forms and definitions of normal vias.

[0122] In this way, the positions of the conductive vias and the preset switching directions of different repair units maintain the above-mentioned symmetrical relationship, so that the subsequent formed chip stack structure can realize the signal rotation transmission relationship through the direct connection configuration. For specific details, please refer to the subsequent description.

[0123] In the second specific embodiment, please refer to Figure 7 , B = 6, and b takes 0, 1, 2, 3, 4, or 5. At this time, the conductive via groups 0 to 5 in each signal area in the same channel signal area together constitute 4 repair unit groups:

[0124] The 6 conductive via groups in each signal area are respectively referred to as conductive via group 0 to conductive via group 5. The whole formed by the conductive via groups b in all signal areas is symmetric along the first axis AA' and symmetric along the second axis BB'; b ≤ 5; that is, the whole formed by conductive via group 0 in the first signal area 21, conductive via group 0 in the second signal area 22, conductive via group 0 in the third signal area 23, and conductive via group 0 in the fourth signal area 24 is symmetric along the first axis AA' and symmetric along the second axis BB'; the whole formed by conductive via group 1 in the first signal area 21, conductive via group 1 in the second signal area 22, conductive via group 1 in the third signal area 23, and conductive via group 1 in the fourth signal area 24 is symmetric along the first axis AA' and symmetric along the second axis BB';...

[0125] The conductive via groups 0 to 5 in each signal area in the same channel signal area together constitute 4 repair unit groups:

[0126] Please refer to Figure 8A , for the first repair unit group _A: (1) The first repair unit _A therein includes: the first conductive vias of the conductive via groups 0 to 5 in the first signal area 21 respectively, that is, D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the first signal area 21; (2) The second repair unit _A therein includes: the second conductive vias of the conductive via groups 0 to 5 in the second signal area 22 respectively, that is, D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the second signal area 22; (3) The third repair unit _A therein includes: the third conductive vias of the conductive via groups 0 to 5 in the third signal area 23 respectively, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the third signal area 23; (4) The fourth repair unit _A therein includes: the fourth conductive vias of the conductive via groups 0 to 5 in the fourth signal area 24 respectively, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the fourth signal area 24.

[0127] Please refer to Figure 8B , for the second repair unit group _B, (1) the first repair unit _B therein includes: the first conductive vias of each of the conductive via groups 0 to 5 in the second signal region 22, that is, D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the second signal region 22; (2) the second repair unit _B therein includes: the second conductive vias of each of the conductive via groups 0 to 5 in the first signal region 21, that is, D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the first signal region 21; (3) the third repair unit _B therein includes: the third conductive vias of each of the conductive via groups 0 to 5 in the fourth signal region 24, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the fourth signal region 24; (4) the fourth repair unit _B therein includes: the fourth conductive vias of each of the conductive via groups 0 to 5 in the third signal region 23, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the third signal region 23.

[0128] Please refer to Figure 8C , for the third repair unit group _C, (1) the first repair unit _C therein includes: the first conductive vias of each of the conductive via groups 0 to 5 in the third signal region 23, that is, D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the third signal region 23; (2) the second repair unit _C therein includes: the second conductive vias of each of the conductive via groups 0 to 5 in the fourth signal region 24, that is, D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the fourth signal region 24; (3) the third repair unit _C therein includes: the third conductive vias of each of the conductive via groups 0 to 5 in the first signal region 21, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the first signal region 21; (4) the fourth repair unit _C therein includes: the fourth conductive vias of each of the conductive via groups 0 to 5 in the second signal region 22, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the second signal region 22.

[0129] Please refer to Figure 8D, for the 4th repair unit group _D, the first repair unit therein includes: the first conductive vias of each of conductive via groups 0 to 5 in the fourth signal region 24, i.e., D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the fourth signal region 24; (2) the second repair unit _D therein includes: the second conductive vias of each of conductive via groups 0 to 5 in the third signal region 23, i.e., D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the third signal region 23; (3) the fourth repair unit _D therein includes: the third conductive vias of each of conductive via groups 0 to 5 in the second signal region 22, i.e., D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the second signal region 22; the fourth repair unit _D therein includes: the fourth conductive vias of each of conductive via groups 0 to 5 in the first signal region 21, i.e., D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the first signal region 21.

[0130] It should be noted that, as Figure 8A shown, the first repair unit _A (D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the first signal region 21) and the second repair unit _A (D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the second signal region 22) are symmetric along the first axis AA', the fourth repair unit _A (D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the fourth signal region 24) and the third repair unit _A (D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the third signal region 23) are symmetric along the first axis AA', the first repair unit _A (D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the first signal region 21) and the fourth repair unit _A (D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the fourth signal region 24) are symmetric along the second axis BB', and the second repair unit _A (D1 / 0, D1 / 1, D1 / 2, D1 / 3 in the second signal region 22) and the third repair unit _A (D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the third signal region 23) are symmetric along the second axis BB'. At the same time, the 2nd to 4th repair unit groups also have similar characteristics.

[0131] The following provides an example of a preset switching direction for better understanding of the foregoing description, but the following example is not the only solution.

[0132] Assume that all the conductive vias in the conductive via group 2 of all signal regions are normal conductive vias; the preset switching direction of the conductive vias in the Xth repair unit is as follows: the Xth conductive via in the conductive via group 2 is allowed to be switched to the Xth conductive via in the conductive via group 3 in the same signal region, the Xth conductive via in the conductive via group 3 is allowed to be switched to the Xth conductive via in the conductive via group 4 in the same signal region, the Xth conductive via in the conductive via group 4 is allowed to be switched to the Xth conductive via in the conductive via group 1 in the same signal region; the Xth conductive via in the conductive via group 1 is allowed to be switched to the Xth conductive via in the conductive via group 0 in the same signal region; the Xth conductive via in the conductive via group 0 is allowed to be switched to the Xth conductive via in the conductive via group 5 in the same signal region.

[0133] Please refer to Figure 8A , the description of the preset switching direction of the first repair unit group _A is as follows:

[0134] (a) The preset switching direction of the conductive vias in the first repair unit _A is: D0 / 2 - D0 / 3 - D0 / 4 - D0 / 1 - D0 / 0 - D0 / 5 in the first signal region 21; (b) The preset switching direction of the conductive vias in the second repair unit _A is: D1 / 2 - D1 / 3 - D1 / 4 - D1 / 1 - D1 / 0 - D1 / 5 in the second signal region 22; (c) The preset switching direction of the conductive vias in the third repair unit _A is: D2 / 2 - D2 / 3 - D2 / 4 - D2 / 1 - D2 / 0 - D2 / 5 in the third signal region 23; (d) The preset switching direction of the conductive vias in the fourth repair unit _A is: D3 / 2 - D3 / 3 - D3 / 4 - D3 / 1 - D3 / 0 - D3 / 5 in the fourth signal region 24;

[0135] Please refer to Figure 8B , the description of the preset switching direction of the second repair unit group _B is as follows:

[0136] (a) The preset switching direction of the conductive vias in the first repair unit _B is: D0 / 2 - D0 / 3 - D0 / 4 - D0 / 1 - D0 / 0 - D0 / 5 in the second signal region 22; (b) The preset switching direction of the conductive vias in the second repair unit _B is: D1 / 2 - D1 / 3 - D1 / 4 - D1 / 1 - D1 / 0 - D1 / 5 in the first signal region 21; (c) The preset switching direction of the conductive vias in the third repair unit _B is: D2 / 2 - D2 / 3 - D2 / 4 - D2 / 1 - D2 / 0 - D2 / 5 in the fourth signal region 24; (d) The preset switching direction of the conductive vias in the fourth repair unit _B is: D3 / 2 - D3 / 3 - D3 / 4 - D3 / 1 - D3 / 0 - D3 / 5 in the third signal region 23;

[0137] Please refer to Figure 8C , the description of the preset switching direction of the 3rd repair unit group _C is as follows:

[0138] (a) The preset switching direction of the conductive vias in the first repair unit _C is: D0 / 2 - D0 / 3 - D0 / 4 - D0 / 1 - D0 / 0 - D0 / 5 in the third signal region 23; (b) The preset switching direction of the conductive vias in the second repair unit _C is: D1 / 2 - D1 / 3 - D1 / 4 - D1 / 1 - D1 / 0 - D1 / 5 in the fourth signal region 24; (c) The preset switching direction of the conductive vias in the second repair unit _C is: D2 / 2 - D2 / 3 - D2 / 4 - D2 / 1 - D2 / 0 - D2 / 5 in the first signal region 21; (d) The preset switching direction of the conductive vias in the fourth repair unit _C is: D3 / 2 - D3 / 3 - D3 / 4 - D3 / 1 - D3 / 0 - D3 / 5 in the second signal region 22;

[0139] Please refer to Figure 8D , the description of the preset switching direction of the 4th repair unit group _C is as follows:

[0140] (a) The preset switching direction of the conductive vias in the first repair unit _D is: D0 / 2 - D0 / 3 - D0 / 4 - D0 / 1 - D0 / 0 - D0 / 5 in the fourth signal region 24; (b) The preset switching direction of the conductive vias in the second repair unit _D is: D1 / 2 - D1 / 3 - D1 / 4 - D1 / 1 - D1 / 0 - D1 / 5 in the third signal region 23; (c) The preset switching direction of the conductive vias in the second repair unit _D is: D2 / 2 - D2 / 3 - D2 / 4 - D2 / 1 - D2 / 0 - D2 / 5 in the second signal region 22; (d) The preset switching direction of the conductive vias in the fourth repair unit _D is: D3 / 2 - D3 / 3 - D3 / 4 - D3 / 1 - D3 / 0 - D3 / 5 in the first signal region 21;

[0141] The following provides a specific description of a signal switching related circuit with the normal conductive vias: the repair ratio of redundant conductive vias = 4:2 as an example. Taking the first repair unit _A (D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the first signal region 21) of the 1st repair unit group as an example, please refer to Figure 8A, D0 / 2, D0 / 3, D0 / 4 are connected to the first signal selection circuit 100, and the first signal selection circuit 100 connects D0 / 2 to the internal circuit of the logic circuit 10; D0 / 3, D0 / 4, D0 / 1 are connected to the second signal selection circuit 100, and the second signal selection circuit 100 connects D0 / 3 to the internal circuit of the logic circuit 10; D0 / 4, D0 / 1, D0 / 0 are connected to the third signal selection circuit 100, and the third signal selection circuit 100 connects D0 / 3 to the internal circuit of the logic circuit 10, D0 / 1, D0 / 0, D0 / 5 are connected to the fourth signal selection circuit 100, and the fourth signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10; then, if D0 / 2 is damaged, the first signal selection circuit 100 connects D0 / 3 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 2 will be transmitted by D0 / 3; at the same time, the second signal selection circuit 100 connects D0 / 4 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 3 will be transmitted by D0 / 4, the third signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 4 will be transmitted by D0 / 1, and at the same time, the fourth signal selection circuit 100 connects D0 / 0 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 4 will be transmitted by D0 / 0. Please refer to the understanding for the remaining repair units.

[0142] Similarly, Figures 8A to 8D is only an example of the preset switching direction; the preset switching direction also has a very flexible selection.

[0143] It should also be noted that in the foregoing example, in each signal region, the conductive via groups 0, 1, and 2 are aligned in the first direction; the conductive via groups 3, 4, and 5 are aligned in the first direction, the conductive via groups 2 and 3 are aligned in the second direction, the conductive via groups 1 and 4 are aligned in the second direction, and the conductive via groups 0 and 5 are aligned in the second direction, but this is only an example, and the via groups 1 to 5 can be respectively located at any position in the same signal region.

[0144] In this way, the conductive via positions and the preset switching directions of different repair units all maintain the above-mentioned symmetrical relationship, so that the subsequent formed chip stack structure can achieve the signal rotation transmission relationship through the direct connection configuration. Please refer to the subsequent description for details.

[0145] It should be noted that for the same logic chip, it can adopt a repair unit such as Figure 5 , or adopt a repair unit such as Figure 7 , or adopt both a repair unit such as Figure 5 and a repair unit such asFigure 7 two types of repair units, or include more types of repair units.

[0146] It should also be noted that the conductive vias mentioned above can be at least embodied as Through-Silicon Vias (TSVs), specifically a vertical interconnection structure that penetrates a silicon wafer / memory chip. For example, Figure 1 type 1 in Figure 1 ; of course, the conductive vias can also adopt

[0147] The conductive vias can be fabricated by one or more of the following processes: via-first process, mid-via process, via-last process, and backside via process. Among them, the via-first process refers to a via process method in which the via structure is fabricated before the fabrication of a device, such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET or simply MOS transistor) device structure. The mid-via process is a via structure formed during the manufacturing process of the process flow, often a via process fabricated after the formation of the device and before the fabrication of the stack. The via-last process is a manufacturing process in which the via is formed from the front side of the wafer after the completion of the Back End of Line (BEOL) process. The backside via process is a manufacturing process in which the via structure is formed from the back side of the wafer after the completion of the BEOL process. That is to say, the via-first process can mean fabricating the via first and then the circuit; the mid-via process can mean fabricating the circuit and some metal layers first, then the via, and finally the remaining vias; the via-last process and the backside via process can mean fabricating the circuit and metal layers first and finally the via.

[0148] In summary, the embodiments of the present disclosure provide a logic chip, in which the repair unit group, normal conductive vias, and preset switching direction in each channel signal region have special symmetry, and can be directly applied to a face-to-face stacking structure without two sets of masks or two sets of vias; the chip stacking structure formed by the logic chip and the memory chip (which also has this characteristic) can achieve the signal rotation transmission effect through the direct connection configuration of the conductive vias, and both the parasitic resistance and the parasitic capacitance are relatively small; at the same time, through the symmetrically arranged repair units, the redundant repair function of the above structure can be realized, improving the stability of the memory chip.

[0149] In another embodiment of the present disclosure, referring to Figure 9 , which shows a schematic structural diagram of a memory chip 30 provided by the embodiments of the present disclosure, and can be specifically understood as a cross-sectional view of the active surface. As Figure 9As shown, the memory chip 30 includes m channels ( Figure 3 taking m = 4 as an example for illustration), the m channels are arranged in sequence along the first direction, the memory chip 9 has a chip axis YY' extending along the second direction and passing through the center of the memory chip, and the m channels are symmetric about the chip axis YY'; each channel includes a first memory array region, a channel signal region, and a second memory array region distributed in sequence along the second direction, and the center of each channel signal region coincides with the center of the corresponding channel. Here, the area of the channel signal region in the logic chip 10 is the same as the area of the channel signal region in the memory chip 30. Specifically, the area of the active surface of the logic chip 10 may be the same as the area of the active surface of the memory chip 30, or the area of the active surface of the logic chip 10 may be larger than the area of the active surface of the memory chip 30.

[0150] It should be noted that during the chip manufacturing process, in order to distinguish different channels of the chip, a positioning structure can be made on the reference channel (for example: the first channel) of the memory chip 30, so that during subsequent packaging, the position of the reference channel can be identified through the positioning structure, and at the same time, other channels can be identified in combination with the orientation of the active surface of the chip.

[0151] Figure 9 Taking m = 4 as an example for illustration, the following also takes m = 4 as an example for description, but m can be any positive integer. Specifically, if m is an even number, then m / 2 channels are located on one side of the global signal region along the first direction, and the remaining m / 2 channels are located on the other side of the global signal region along the first direction; if m is an odd number, then the (m + 1) / 2-th channel needs to be divided into two parts and located on both sides of the global signal region along the first direction respectively, while the other (m - 1) / 2 channels are located on one side of the global signal region along the first direction, and the remaining (m - 1) / 2 channels are located on the other side of the global signal region along the first direction.

[0152] Figure 9 It can be regarded as a cross-sectional view of the active surface of the memory chip 30. As Figure 9 shown, the center and its adjacent area of the active surface of the memory chip 30 are defined as the global signal region. At this time, the first channel, the second channel, the global signal region, the third channel, and the fourth channel are distributed in sequence along the first direction. The signals transmitted by the global signal region are shared by the m channels of the memory chip; while the signals transmitted by each channel signal region are only used by the corresponding channel.

[0153] Please refer to Figure 10A , which specifically shows the schematic diagrams of the channel signal region 11 of the first channel, the channel signal region 12 of the second channel, the channel signal region 13 of the third channel, and the channel signal region 14 of the fourth channel. Figure 10A The global signal region is omitted.

[0154] As shown Figure 10A in the figure, each channel signal region has a first axis AA' and a second axis BB'. The first axis AA' extends along a first direction or a second direction, and the second axis BB' is perpendicular to and intersects the first axis AA' at the center of the corresponding channel signal region. Figure 4A Taking the first axis AA' extending along the first direction as an example for illustration, other cases should be understood adaptively.

[0155] Due to limited space, only one channel signal region is taken as an example in the subsequent figures to illustrate the composition and principle of the repair unit group. In fact, the structures of all channel signal regions are the same, that is, the channel signal region in the figure can be understood as any one of the channel signal regions 11, 12, 13, and 14.

[0156] Please refer to Figure 10A , each channel signal region includes a first axis AA' and a second axis BB'. The first axis AA' is parallel to the first side of the memory chip, and the first axis AA' and the second axis BB' are perpendicular to each other and intersect at the center point of the corresponding channel signal region. In Figure 11 it, the first axis AA' extends along the first direction, and the second axis BB' extends along the second direction, but this is only an example and does not constitute a specific limitation. As Figure 10A shown in the figure, each channel signal region is penetrated by a plurality of conductive vias along a third direction. The first direction and the second direction are parallel to the top surface of the memory chip 30, and the third direction is perpendicular to the top surface of the memory chip 30.

[0157] The memory chip 30 also has a structure similar to that of the repair unit in the aforementioned logic chip 10, and the specific description is as follows.

[0158] Please refer to Figure 10B , for each channel signal region, the plurality of conductive vias therein are divided into a plurality of repair unit groups; each repair unit group includes a first repair unit, a second repair unit, a third repair unit, and a fourth repair unit; the first repair unit and the second repair unit are symmetric about the first axis AA' of the corresponding channel signal region, the third repair unit and the fourth repair unit are symmetric about the first axis AA' of the corresponding channel signal region, and the first repair unit and the fourth repair unit are symmetric about the second axis BB' of the corresponding channel signal region.

[0159] Each repair unit includes at least one redundant conductive via and at least one normal conductive via. When any normal conductive via is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset signal switching direction; the normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit correspond one-to-one and are symmetrical along the first axis AA' of the channel signal area to which they belong, the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit correspond one-to-one and are symmetrical along the first axis AA' of the channel signal area to which they belong, and the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit correspond one-to-one and are symmetrical along the second axis BB' of the channel signal area to which they belong.

[0160] In particular, for the logic chip 10, the normal conductive vias in each repair unit are electrically connected to the internal circuit of the logic chip 10. In other words, please refer to Figures 6A to 6D , Figures 8A to 8D Each repair unit is connected to a corresponding signal selection circuit 100, and any conductive via therein is electrically connected to the inside of the logic chip when selected as a normal conductive via.

[0161] However, for the memory chip 30, only the conductive vias in the first repair unit are electrically connected to the internal circuit of the memory chip 30 when used to transmit valid signals, that is, only the normal conductive vias in the first repair unit are electrically connected to the internal circuit of the memory chip 30. For example, please refer to the subsequent Figures 12A to 12D , or 14A~ Figure 14D Only the first repair unit is connected to the corresponding signal selection circuit 100, so that the conductive via in the first repair unit is electrically connected to the interior of the logic chip when it is selected as a normal conductive via; all the conductive vias in the remaining second to fourth repair units are completely independent of the internal circuit of the memory chip 30, and will not be electrically connected to the interior of the memory chip 30 even if they are selected as normal conductive vias.

[0162] In the embodiment of the present disclosure, for each repair unit group, the preset switching direction of the conductive via in the first repair unit and the preset switching direction of the conductive via in the second repair unit are symmetrical along the first axis AA' of the channel signal area to which they belong; the preset switching direction of the conductive via in the third repair unit and the preset switching direction of the conductive via in the fourth repair unit are symmetrical along the first axis AA' of the channel signal area to which they belong; the preset switching direction of the conductive via in the first repair unit and the preset switching direction of the conductive via in the fourth repair unit are symmetrical along the second axis BB' of the channel signal area to which they belong; the preset switching direction of the conductive via in the second repair unit and the preset switching direction of the conductive via in the third repair unit are symmetrical along the second axis BB' of the channel signal area to which they belong.

[0163] In some embodiments, seeFigure 10A , each channel signal region is divided into 2×2 signal areas, the conductive vias in each signal area are divided into n conductive via groups with the same distribution positions, n is a positive integer, the conductive via groups in the first signal area 21 and the conductive via groups in the second signal area 22 correspond one by one and are symmetric along the first axis AA', the conductive via groups in the third signal area 23 and the conductive via groups in the fourth signal area 24 correspond one by one and are symmetric along the first axis AA', the conductive via groups in the first signal area 21 and the conductive via groups in the fourth signal area 24 group correspond one by one and are symmetric along the second axis BB'; each conductive via group includes a first conductive via, a second conductive via D1, a third conductive via D2, and a fourth conductive via D3 that are presented in a 2×2 array distribution.

[0164] The conductive vias in each signal area have the following characteristics:

[0165] (1) In the same channel signal region, the whole formed by the first conductive via in a conductive via group in the first signal area 21, the second conductive via D1 in the corresponding conductive via group in the second signal area 22, the third conductive via D2 in the corresponding conductive via group in the third signal area 23, and the fourth conductive via D3 in the corresponding conductive via group in the fourth signal area 24 is symmetric along the first axis AA' and symmetric along the second axis BB';

[0166] (2) In the same channel signal region, the whole formed by the second conductive via D1 in a conductive via group in the first signal area 21, the first conductive via in the corresponding conductive via group in the second signal area 22, the fourth conductive via D3 in the corresponding conductive via group in the third signal area 23, and the third conductive via D2 in the corresponding conductive via group in the fourth signal area 24 is symmetric along the first axis AA' and symmetric along the second axis BB';

[0167] (3) In the same channel signal region, the whole formed by the third conductive via D2 in a conductive via group in the first signal area 21, the fourth conductive via D3 in the corresponding conductive via group in the second signal area 22, the first conductive via in the corresponding conductive via group in the third signal area 23, and the second conductive via D1 in the corresponding conductive via group in the fourth signal area 24 is symmetric along the first axis AA' and symmetric along the second axis BB';

[0168] (4) In the same channel signal region, the whole formed by the fourth conductive via D3 in a conductive via group in the first signal area 21, the third conductive via D2 in the corresponding conductive via group in the second signal area 22, the second conductive via D1 in the corresponding conductive via group in the third signal area 23, and the first conductive via in the corresponding conductive via group in the fourth signal area 24 is symmetric along the first axis AA' and symmetric along the second axis BB'.

[0169] It should be understood that in Figure 10A , the 4 conductive vias in each conductive via group are arranged in a 2×2 array. However, in other embodiments, the 4 conductive vias in each conductive via group can be arbitrarily distributed as long as the above symmetry principle is followed.

[0170] For better understanding, the following drawings only take one channel signal region as an example to illustrate the composition and principle of the repair unit group. In particular, all channel signal regions have exactly the same structure, that is, the channel signal region in the drawings can be understood as any one of channel signal region 11, channel signal region 12, channel signal region 13, and channel signal region 14.

[0171] In some embodiments, the B conductive via groups in each signal region are called 1 conductive via combination. The whole formed by the conductive via groups b in the corresponding conductive via combinations in all signal regions is symmetric along the first axis AA' and symmetric along the second axis BB'. B is a positive integer less than or equal to n, and b is a natural number less than B.

[0172] In the same channel signal region, a total of 4 repair unit groups are formed by the corresponding 1 conductive via combination in each signal region:

[0173] (1) For the first repair unit group, the first repair unit therein includes: the first conductive vias D0 of all conductive via groups in the conductive via combination in the first signal region 21; the second repair unit therein includes: the second conductive vias D1 of all conductive via groups in the conductive via combination in the second signal region 22; the third repair unit therein includes: the third conductive vias D2 of all conductive via groups in the conductive via combination in the third signal region 23; the fourth repair unit therein includes: the fourth conductive vias D3 of all conductive via groups in the conductive via combination in the fourth signal region 24;

[0174] (2) For the second repair unit group, the first repair unit therein includes: the first conductive vias D0 of all conductive via groups in the conductive via combination in the second signal region 22; the second repair unit therein includes: the second conductive vias D1 of all conductive via groups in the conductive via combination in the first signal region 21; the third repair unit therein includes: the third conductive vias D2 of all conductive via groups in the conductive via combination in the fourth signal region 24; the fourth repair unit therein includes: the fourth conductive vias D3 of all conductive via groups in the conductive via combination in the third signal region 23;

[0175] (3) For the third repair unit group, the first repair unit therein includes: the first conductive vias D0 of each conductive via group in the conductive via combination in the third signal region 23; the second repair unit therein includes: the second conductive vias D1 of each conductive via group in the conductive via combination in the fourth signal region 24; the third repair unit therein includes: the third conductive vias D2 of each conductive via group in the conductive via combination in the first signal region 21; the fourth repair unit therein includes: the fourth conductive vias D3 of each conductive via group in the conductive via combination in the second signal region 22;

[0176] (4) For the fourth repair unit group, the first repair unit therein includes: the first conductive vias D0 of each conductive via group in the conductive via combination in the fourth signal region 24; the second repair unit therein includes: the second conductive vias D1 of each conductive via group in the conductive via combination in the third signal region 23; the third repair unit therein includes: the third conductive vias D2 of each conductive via group in the conductive via combination in the second signal region 22; the fourth repair unit therein includes: the fourth conductive vias D3 of each conductive via group in the conductive via combination in the first signal region 21.

[0177] It should be noted that for the same logic chip 10, B can have multiple values. For example, in the same logic chip 10, there are conductive via combinations composed of 4 conductive via groups, and there are also conductive via combinations composed of 6 conductive via groups, or there are more forms. However, no matter how many conductive via groups are included, each conductive via combination will surely form 4 repair unit groups.

[0178] In the first specific embodiment, please refer to Figure 11 , B = 3, and b takes 0, 1, or 2. At this time, the conductive via groups 0 to 2 in each signal region in the same channel signal region together constitute 4 repair unit groups:

[0179] Please refer to Figure 12A, for the first repair unit group _1: (1) The first repair unit _1 therein includes: the first conductive vias of the conductive via groups 0, 1, and 2 in the first signal region 21, that is, D0 / 0, D0 / 1, and D0 / 2 in the first signal region 21; (2) The second repair unit _1 therein includes: the second conductive vias of the conductive via groups 0, 1, and 2 in the second signal region 22, that is, D1 / 0, D1 / 1, and D1 / 2 in the second signal region 22; (3) The third repair unit _1 therein includes: the third conductive vias of the conductive via groups 0, 1, and 2 in the third signal region 23, that is, D2 / 0, D2 / 1, and D2 / 2 in the third signal region 23; (4) The fourth repair unit _1 therein includes: the fourth conductive vias of the conductive via groups 0, 1, and 2 in the fourth signal region 24, that is, D3 / 0, D3 / 1, and D3 / 2 in the fourth signal region 24.

[0180] Please refer to Figure 12B , for the second repair unit group _2, (1) The first repair unit _2 therein includes: the first conductive vias of the conductive via groups 0, 1, and 2 in the second signal region 22, that is, D0 / 0, D0 / 1, and D0 / 2 in the second signal region 22; (2) The second repair unit _2 therein includes: the second conductive vias of the conductive via groups 0, 1, and 2 in the first signal region 21, that is, D1 / 0, D1 / 1, and D1 / 2 in the first signal region 21; (3) The third repair unit _2 therein includes: the third conductive vias of the conductive via groups 0, 1, and 2 in the fourth signal region 24, that is, D2 / 0, D2 / 1, and D2 / 2 in the fourth signal region 24; (4) The fourth repair unit _2 therein includes: the fourth conductive vias of the conductive via groups 0, 1, and 2 in the third signal region 23, that is, D3 / 0, D3 / 1, and D3 / 2 in the third signal region 23.

[0181] Please refer to Figure 12C, for the 3rd repair unit group _3, (1) the first repair unit _3 therein includes: the first conductive vias of the conductive via groups 0, 1, and 2 in the third signal region 23, i.e., D0 / 0, D0 / 1, D0 / 2 in the third signal region 23; (2) the second repair unit _3 therein includes: the second conductive vias of the conductive via groups 0, 1, and 2 in the fourth signal region 24, i.e., D1 / 0, D1 / 1, D1 / 2 in the fourth signal region 24; (3) the third repair unit _3 therein includes: the third conductive vias of the conductive via groups 0, 1, and 2 in the first signal region 21, i.e., D2 / 0, D2 / 1, D2 / 2 in the first signal region 21; (4) the fourth repair unit _3 therein includes: the fourth conductive vias of the conductive via groups 0, 1, and 2 in the second signal region 22, i.e., D3 / 0, D3 / 1, D3 / 2 in the second signal region 22.

[0182] Please refer to Figure 12D , for the 4th repair unit group _4, (1) the first repair unit _4 therein includes: the first conductive vias of the conductive via groups 0, 1, and 2 in the fourth signal region 24, i.e., D0 / 0, D0 / 1, D0 / 2 in the fourth signal region 24; (2) the second repair unit _4 therein includes: the second conductive vias of the conductive via groups 0, 1, and 2 in the third signal region 23, i.e., D2 / 0, D2 / 1, D2 / 2 in the third signal region 23; (3) the third repair unit _4 therein includes: the third conductive vias of the conductive via groups 0, 1, and 2 in the second signal region 22, i.e., D2 / 0, D2 / 1, D2 / 2 in the second signal region 22; (4) the fourth repair unit _4 therein includes: the fourth conductive vias of the conductive via groups 0, 1, and 2 in the first signal region 21, i.e., D3 / 0, D3 / 1, D3 / 2 in the first signal region 21.

[0183] The following provides an example of a preset switching direction for better understanding of the foregoing description, but the following example is not the only solution.

[0184] In some embodiments, please refer to Figure 11 , the conductive vias in the conductive via group 0 are all normal conductive vias. As described above, only the normal conductive vias in the first repair unit will be connected to the inside of the storage chip. Therefore, the preset switching direction of the conductive vias in any first repair unit is: the first conductive via in the conductive via group 0 is allowed to be switched to the first conductive via in the conductive via group 1 in the same signal region, and the first conductive via in the conductive via group 1 is allowed to be switched to the first conductive via in the conductive via group 2 in the same signal region.

[0185] That is, please refer to Figure 12A , for the first repair unit group, the preset switching direction of the conductive vias in the first repair unit_1 is: D0 / 0 - D0 / 1 - D0 / 2 in the first signal region 21; please refer to Figure 12B , for the second repair unit group, the preset switching direction of the conductive vias in the first repair unit_2 is: D0 / 0 - D0 / 1 - D0 / 2 in the second signal region 22; please refer to Figure 12C , for the third repair unit group, the preset switching direction of the conductive vias in the first repair unit_3 is: D0 / 0 - D0 / 1 - D0 / 2 in the third signal region 23; please refer to Figure 12D , for the fourth repair unit group, the preset switching direction of the conductive vias in the first repair unit_4 is: D0 / 0 - D0 / 1 - D0 / 2 in the fourth signal region 24.

[0186] For the sake of easy understanding, a specific description of a signal switching related circuit is provided below by taking the case where the ratio of normal conductive vias to redundant conductive vias is 2:1 as an example.

[0187] To implement the above switching process, please refer to Figures 12A to 12D , the memory chip 30 further includes a plurality of signal selection circuits 100 for implementing the switching of the above-mentioned conductive vias. Taking the first repair unit_1 of the first repair unit group as an example, please refer to Figure 12A , D0 / 0 and D0 / 1 are connected to the first signal selection circuit 100, and the first signal selection circuit 100 connects D0 / 0 to the internal circuit of the logic circuit 10; D0 / 1 and D0 / 2 are connected to the second signal selection circuit 100, and the second signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10; then, if D0 / 0 is damaged, the first signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 0 will be transmitted by D0 / 1; at the same time, the second signal selection circuit 100 connects D0 / 2 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 1 will be transmitted by D0 / 2. However, for the second to fourth repair units, no signal selection circuit 100 is provided, and whether the conductive vias therein are normal conductive vias or redundant conductive vias, they are not connected to the memory chip 30. Therefore, the switching of the conductive vias for transmitting signals in the repair units of the memory chip only follows the switching of the conductive vias for transmitting signals in the logic chip 10, and the memory chip 30 is actually unaware of it. Therefore, only the preset switching direction of the first repair unit is emphasized in this embodiment.

[0188] Please refer to the other repair units for understanding.

[0189] It should be noted that Figures 12A to 12D This is only an example of the preset switching direction; in fact, the preset switching direction has very flexible options. Taking the first repair unit_1 as an example, it can currently switch sequentially along D0 / 0, D0 / 1, D0 / 2, or it can switch in the order of D0 / 2, D0 / 1, D0 / 0, or use D0 / 1 as the switching starting point, etc.

[0190] In this way, the positions of the conductive vias and the preset switching directions of different repair units all maintain the above-mentioned symmetrical relationship to ensure that the subsequent formed chip stacking structure can achieve the relationship of signal rotation transmission through a direct connection configuration. For specific details, please refer to the subsequent description.

[0191] In the second specific embodiment, please refer to Figure 13 , B = 6, and b takes 0, 1, 2, 3, 4, or 5. At this time, the conductive via groups 0 to 5 in each signal area in the same channel signal area together constitute 4 repair unit groups:

[0192] Please refer to Figure 14A , for the first repair unit group_A: (1) The first repair unit_A therein includes: the first conductive vias of the conductive via groups 0 to 5 in the first signal area 21, that is, D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the first signal area 21; (2) The second repair unit_A therein includes: the second conductive vias of the conductive via groups 0 to 5 in the second signal area 22, that is, D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the second signal area 22; (3) The third repair unit_A therein includes: the third conductive vias of the conductive via groups 0 to 5 in the third signal area 23, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the third signal area 23; (4) The fourth repair unit_A therein includes: the fourth conductive vias of the conductive via groups 0 to 5 in the fourth signal area 24, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the fourth signal area 24.

[0193] Please refer to Figure 14B, for the second repair unit group _B, (1) the first repair unit _B therein includes: the first conductive vias of each of the conductive via groups 0 to 5 in the second signal region 22, that is, D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the second signal region 22, that is, D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the second signal region 22; (2) the second repair unit _B therein includes: the second conductive vias of each of the conductive via groups 0 to 5 in the first signal region 21, that is, D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the first signal region 21; (3) the third repair unit _B therein includes: the third conductive vias of each of the conductive via groups 0 to 5 in the fourth signal region, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the fourth signal region 24; (4) the fourth repair unit _B therein includes: the fourth conductive vias of each of the conductive via groups 0 to 5 in the third signal region 23, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the third signal region 23.

[0194] Please refer to Figure 14C , for the third repair unit group _C, (1) the first repair unit _C therein includes: the first conductive vias of each of the conductive via groups 0 to 5 in the third signal region 23, that is, D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the third signal region 23; (2) the second repair unit _C therein includes: the second conductive vias of each of the conductive via groups 0 to 5 in the fourth signal region 24, that is, D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the fourth signal region 24; (3) the third repair unit _C therein includes: the third conductive vias of each of the conductive via groups 0 to 5 in the first signal region 21, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the first signal region 21; (4) the fourth repair unit _C therein includes: the fourth conductive vias of each of the conductive via groups 0 to 5 in the second signal region 22, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the second signal region 22.

[0195] Please refer to Figure 14D, for the 4th repair unit group _D, the first repair unit therein includes: the first conductive vias of each of the conductive via groups 0 to 5 in the fourth signal region 24, that is, D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the fourth signal region 24; (2) the second repair unit _D therein includes: the second conductive vias of each of the conductive via groups 0 to 5 in the third signal region 23, that is, D1 / 0, D1 / 1, D1 / 2, D1 / 3, D1 / 4, D1 / 5 in the third signal region 23; (3) the fourth repair unit _D therein includes: the third conductive vias of each of the conductive via groups 0 to 5 in the second signal region 22, that is, D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the second signal region 22; the fourth repair unit _D therein includes: the fourth conductive vias of each of the conductive via groups 0 to 5 in the first signal region 21, that is, D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the first signal region 21.

[0196] The following provides an example of a preset switching direction for better understanding of the foregoing description, but the following example is not the only solution.

[0197] Assume that the conductive vias in conductive via group 0 of all signal regions are normal conductive vias. Please refer to Figure 14A ~Please refer to Figure 14D , the preset switching direction of the conductive vias in the first repair unit is: the first conductive via in conductive via group 2 is allowed to be switched to the first conductive via in conductive via group 3 in the same signal region, the first conductive via in conductive via group 3 is allowed to be switched to the first conductive via in conductive via group 4 in the same signal region, the first conductive via in conductive via group 4 is allowed to be switched to the first conductive via in conductive via group 1 in the same signal region; the first conductive via in conductive via group 1 is allowed to be switched to the first conductive via in conductive via group 0 in the same signal region; the first conductive via in conductive via group 0 is allowed to be switched to the first conductive via in conductive via group 5 in the same signal region.

[0198] That is to say, please refer to Figure 14A , the preset switching direction of the conductive vias in the first repair unit _A is: D0 / 2 - D0 / 3 - D0 / 4 - D0 / 1 - D0 / 0 - D0 / 5 in the first signal region 21; please refer to Figure 14B , the preset switching direction of the conductive vias in the first repair unit _B is: D0 / 2 - D0 / 3 - D0 / 4 - D0 / 1 - D0 / 0 - D0 / 5 in the second signal region 22; please refer to Figure 14C, the preset switching direction of the conductive vias in the first repair unit _C is: D0 / 2 - D0 / 3 - D0 / 4 - D0 / 1 - D0 / 0 - D0 / 5 in the third signal region 23; please refer to Figure 14D , the preset switching direction of the conductive vias in the first repair unit _D is: D0 / 2 - D0 / 3 - D0 / 4 - D0 / 1 - D0 / 0 - D0 / 5 in the fourth signal region 24;.

[0199] The following provides a specific description of a signal switching related circuit with the repair ratio of normal conductive vias: redundant conductive vias = 4:2 as an example. Taking the first repair unit _A of the first repair unit group as an example, please refer to Figure 14A , D0 / 2, D0 / 3, and D0 / 4 are connected to the first signal selection circuit 100, and the first signal selection circuit 100 connects D0 / 2 to the internal circuit of the logic circuit 10; D0 / 3, D0 / 4, and D0 / 1 are connected to the second signal selection circuit 100, and the second signal selection circuit 100 connects D0 / 3 to the internal circuit of the logic circuit 10; D0 / 4, D0 / 1, and D0 / 0 are connected to the third signal selection circuit 100, and the third signal selection circuit 100 connects D0 / 3 to the internal circuit of the logic circuit 10, D0 / 1, D0 / 0, and D0 / 5 are connected to the fourth signal selection circuit 100, and the fourth signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10; then, if D0 / 2 is damaged, the first signal selection circuit 100 connects D0 / 3 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 2 will be transmitted by D0 / 3; at the same time, the second signal selection circuit 100 connects D0 / 4 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 3 will be transmitted by D0 / 4, the third signal selection circuit 100 connects D0 / 1 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 4 will be transmitted by D0 / 1, and at the same time, the fourth signal selection circuit 100 connects D0 / 0 to the internal circuit of the logic circuit 10, that is, the signal originally transmitted by D0 / 4 will be transmitted by D0 / 0. Please refer to the other repair units for understanding.

[0200] Similarly, for the memory chip 30, only the vias in the first repair unit (i.e., the vias filled with a pure white pattern) are connected to the corresponding signal selection circuit 100. Similarly, for the second to fourth repair units, whether the vias therein are normal vias or redundant vias, they are not connected to the memory chip 30. Therefore, the switching of the vias for transmitting signals in the repair units of the memory chip only follows the switching of the vias for transmitting signals in the logic chip 10, and the memory chip 30 is actually unaware of it. Therefore, this embodiment only emphasizes the preset switching direction of the first repair unit.

[0201] An embodiment of the present disclosure provides a memory chip 30, in which the vias in each channel signal region are symmetric about the first axis AA' and symmetric about the second axis BB'. At the same time, the switching direction of the repair unit further formed by the vias also follows the symmetry principle. The above memory chip not only has a small parasitic capacitance and parasitic resistance when forming a chip stack structure, but also realizes a face-to-face stacking method. At the same time, the embodiment of the present disclosure also provides a related mechanism for redundant repair under this structure.

[0202] In another embodiment of the present disclosure, refer to Figure 15 , which shows a schematic diagram of the composition structure of a chip stack structure 40 provided by an embodiment of the present disclosure. As Figure 15 shown, the chip stack structure 40 includes the aforementioned logic chip 10 and at least one stack unit, and the logic chip 10 and at least one stack unit are stacked in sequence along the third direction; each stack unit includes a first memory chip 31, a second memory chip 32, a third memory chip 33, and a fourth memory chip 34 stacked along the third direction; the logic chip 10, and the structures of the first memory chip 31, the second memory chip 32, the third memory chip 33, and the fourth memory chip 34 are all the aforementioned memory chip 30. The third direction is perpendicular to the top surface of each chip.

[0203] For each stack unit, the first memory chip 31 and the second memory chip 32 are stacked face to face, the second memory chip 32 and the third memory chip 33 are stacked back to back, and the third memory chip 33 and the fourth memory chip 34 are stacked face to face; the first memory chip 31 in the first stack unit and the logic chip 10 are stacked back to face, or the first memory chip 31 in the first stack unit and the logic chip 10 are stacked back to back.

[0204] In the embodiments of the present disclosure, face-to-face stacking means that the top surfaces of two chips are approximately aligned along the third direction, and the center points of the two chips, the first axis AA' and the second axis BB' of the top surface are all aligned along the third direction; back-to-back stacking means that the top surfaces of two chips are approximately aligned along the third direction; face-to-back stacking means that the top surface of one chip and the bottom surface of the other chip are approximately aligned along the third direction. When not specifying a logic chip or a storage chip, "chip" can refer to either a logic chip or a storage chip.

[0205] It should be noted that, in one possibility, for two chips connected face-to-face, the bonding surfaces of the two (the positions where the middle conductive vias are aligned along the third direction) are electrically connected through a hybrid bonding structure (Hyperbonding, also known as bonding pillars); for two chips connected back-to-back or for two chips connected back-to-face, the bonding surfaces of the two (the positions where the middle conductive vias are aligned along the third direction) are electrically connected through conductive bumps (UBump, also known as micro-bumps).

[0206] In another possibility, for two chips connected face-to-face or for two chips connected back-to-back or for two chips connected back-to-face, the bonding surfaces of the two (the positions where the middle conductive vias are aligned along the third direction) are all connected through a hybrid bonding structure.

[0207] In yet another possibility, for two chips connected face-to-face or for two chips connected back-to-back or for face-to-back connection, the bonding surfaces of the two (the positions where the middle conductive vias are aligned along the third direction) are all connected through conductive bumps.

[0208] Here, the above chips can refer to logic chip 10 or storage chip 30.

[0209] It should be noted that, compared with the conductive bump process, face-to-face connection using the hybrid bonding process can make the adjacent storage chips fit more closely with basically no gaps, thereby greatly reducing the height of the chip stacking structure, which is also one of the advantages of face-to-face stacking. Of course, two storage chips connected back-to-back can also be connected through a hybrid bonding structure, but their connection performance is weaker than that achieved through the conductive bump process. Thus, in the embodiments of the present disclosure, the chip stacking structure supports face-to-face stacking with better performance.

[0210] As described above, the logic chip 10 and each memory chip each have n repair unit groups, and the n repair unit groups in the logic chip 10, the n repair unit groups in each first memory chip 31, the n repair unit groups in each second memory chip 32, the n repair unit groups in each third memory chip 33, and the n repair unit groups in each fourth memory chip 34 correspond to each other one by one and are aligned along the third direction. Thus, when a certain conductive via is damaged, the logic chip 10 and each memory chip 0 will synchronously perform a signal switching operation.

[0211] In some embodiments, the logic chip 10 includes m channel signal regions arranged along the first direction, each memory chip has m channels arranged along the first direction, and each channel includes a first memory array region, a channel signal region, and a second memory array region sequentially distributed along the second direction; the first direction, the second direction, and the third direction are perpendicular to each other in pairs, and the first direction and the second direction are parallel to the top surface of each chip.

[0212] Specifically, Figure 15 Two second directions are shown in [figure], because for clear illustration, the perspective angles of two adjacent chips are different, thus corresponding to a second direction respectively.

[0213] It should be understood that the logic chip 10 or each memory chip can be divided into a high-bit transmission region and a low-bit transmission region, and the arrows in the subsequent drawings are uniformly located in the high-bit transmission region of the chip. Specifically, the high-bit transmission region and the low-bit transmission region in the embodiments of the present disclosure are only two regions for distinguishing the memory chip, and do not have any additional restrictions, and have nothing to do with the high-bit data and low-bit data commonly mentioned in the data transmission process.

[0214] In the first specific embodiment, please refer to Figure 17A , when the logic chip 10 and the first memory chip 31 are stacked back-to-back, and the first axes AA' of the logic chip 10 and each of the memory chips 30 extend along the first direction (that is, the second axis AA' divides the respective chip into a high-bit transmission region and a low-bit transmission region), the high-bit transmission region of the logic chip 10, the high-bit transmission region of the first memory chip 31, the low-bit transmission region of the second memory chip 32, the low-bit transmission region of the third memory chip 33, and the high-bit transmission region of the fourth memory chip 34 are aligned along the third direction; the low-bit transmission region of the logic chip 10, the low-bit transmission region of the first memory chip 31, the high-bit transmission region of the second memory chip 32, the high-bit transmission region of the third memory chip 33, and the low-bit transmission region of the fourth memory chip 34 are aligned along the third direction.

[0215] The channel signal regions of each chip have the following alignment relationships: the (m-i)-th channel signal region in the logic chip 10 is aligned with the channel signal region in the (i+1)-th channel of the first storage chip 31, the channel signal region in the (i+1)-th channel of the second storage chip 32, the channel signal region in the (m-i)-th channel of the third storage chip 33, and the channel signal region in the (m-i)-th channel of the fourth storage chip 34 along the third direction; where i is a natural number less than m.

[0216] Figure 17A Taking m = 4 as an example for illustration, at this time:

[0217] (1) The 4th channel signal region 14 in the logic chip 10 is aligned with the channel signal region 11 in the first channel of the first storage chip 31 along the third direction, the channel signal region 11 in the first channel of the second storage chip 32 along the third direction, the channel signal region 14 in the fourth channel of the third storage chip 33 along the third direction, and the channel signal region 14 in the fourth channel of the fourth storage chip 34 along the third direction;

[0218] (2) The 3rd channel signal region 13 in the logic chip 10 is aligned with the channel signal region 12 in the second channel of the first storage chip 31 along the third direction, the channel signal region 12 in the second channel of the second storage chip 32 along the third direction, the channel signal region 13 in the third channel of the third storage chip 33 along the third direction, and the channel signal region 13 in the third channel of the fourth storage chip 34 along the third direction;

[0219] (3) The 2nd channel signal region 12 in the logic chip 10 is aligned with the channel signal region 13 in the third channel of the first storage chip 31 along the third direction, the channel signal region 13 in the third channel of the second storage chip 32 along the third direction, the channel signal region 12 in the second channel of the third storage chip 33 along the third direction, and the channel signal region 12 in the second channel of the fourth storage chip 34 along the third direction;

[0220] (4) The 1st channel signal region 11 in the logic chip 10 is aligned with the channel signal region 14 in the fourth channel of the first storage chip 31 along the third direction, the channel signal region 14 in the fourth channel of the second storage chip 32 along the third direction, the channel signal region 11 in the first channel of the third storage chip 33 along the third direction, and the channel signal region 11 in the first channel of the fourth storage chip 34 along the third direction.

[0221] In the second specific embodiment, please refer to Figure 18A(Taking m = 4 as an example for illustration), when the logic chip 10 and the first memory chip 31 are stacked back-to-back, and the second axes BB' of the logic chip 10 and each memory chip extend along the first direction (i.e., the second axis BB' divides the corresponding chip into a high-order transmission area and a low-order transmission area), the low-order transmission area of the logic chip 10, the high-order transmission area of the first memory chip 31, the high-order transmission area of the second memory chip 32, the low-order transmission area of the third memory chip 33, and the low-order transmission area of the fourth memory chip 34 are aligned along the third direction; the high-order transmission area of the logic chip 10, the low-order transmission area of the first memory chip 31, the low-order transmission area of the second memory chip 32, the high-order transmission area of the third memory chip 33, and the high-order transmission area of the fourth memory chip 34 are aligned along the third direction.

[0222] Specifically, the channel signal regions of each chip have the following symmetry relationship: the (i + 1)-th channel signal region in the logic chip 10 is aligned with the channel signal region in the (i + 1)-th channel of the first memory chip 31, the channel signal region in the (m - i)-th channel of the second memory chip 32, the channel signal region in the (m - i)-th channel of the third memory chip 33, and the channel signal region in the (i + 1)-th channel of the fourth memory chip 34 along the third direction; where i is a natural number less than m.

[0223] Figure 18A Taking m = 4 as an example for illustration, at this time:

[0224] (1) The first channel signal region 11 in the logic chip 10, the channel signal region 11 in the first channel of the first memory chip 31, the channel signal region 14 in the fourth channel of the second memory chip 32, the channel signal region 14 in the fourth channel of the third memory chip 33, and the channel signal region 11 in the first channel of the fourth memory chip 34 are aligned along the third direction;

[0225] (2) The second channel signal region 12 in the logic chip 10, the channel signal region 12 in the second channel of the first memory chip 31, the channel signal region 13 in the third channel of the second memory chip 32, the channel signal region 13 in the third channel of the third memory chip 33, and the channel signal region 12 in the second channel of the fourth memory chip 34 are aligned along the third direction;

[0226] (3) The third channel signal region 13 in the logic chip 10, the channel signal region 13 in the third channel of the first memory chip 31, the channel signal region 12 in the second channel of the second memory chip 32, the channel signal region 12 in the second channel of the third memory chip 33, and the channel signal region 13 in the third channel of the fourth memory chip 34 are aligned along the third direction;

[0227] (4) The channel signal regions 14 in the fourth channel of the logic chip 10, the channel signal regions 14 in the fourth channel of the first memory chip 31, the channel signal regions 11 in the first channel of the second memory chip 32, the channel signal regions 11 in the first channel of the third memory chip 33, and the channel signal regions 14 in the fourth channel of the fourth memory chip 34 are aligned along the third direction.

[0228] Simply put, for Figures 17A to 18B , the logic chip 10 and the fourth memory chip 34 are arranged in the same way.

[0229] It should also be noted that the channel signal regions in each channel of the memory chips 30 and the logic chip 31 are each divided into 2×2 signal regions arranged in an array. Please refer to Figure 17B or Figure 18B , for multiple channel signal regions aligned along the third direction, they have the following characteristics:

[0230] (1) The fourth signal region 24 belonging to the logic chip 10, the first signal region 21 belonging to the first memory chip 31, the second signal region 22 belonging to the second memory chip 32, the third signal region 23 belonging to the third memory chip 33, and the fourth signal region 24 belonging to the fourth memory chip 34 are aligned along the third direction;

[0231] (2) The third signal region 23 belonging to the logic chip 10, the second signal region 22 belonging to the first memory chip 31, the first signal region 21 belonging to the second memory chip 32, the fourth signal region 24 belonging to the third memory chip 33, and the third signal region 23 belonging to the fourth memory chip 34 are aligned along the third direction;

[0232] (3) The second signal region 22 belonging to the logic chip 10, the third signal region 23 belonging to the first memory chip 31, the fourth signal region 24 belonging to the second memory chip 32, the first signal region 21 belonging to the third memory chip 33, and the second signal region 22 belonging to the fourth memory chip 34 are aligned along the third direction;

[0233] (4) The first signal region 21 belonging to the logic chip 10, the fourth signal region 24 belonging to the first memory chip 31, the third signal region 23 belonging to the second memory chip 32, the second signal region 22 belonging to the third memory chip 33, and the first signal region 21 belonging to the fourth memory chip 34 are aligned along the third direction.

[0234] In some embodiments, each signal region includes n conductive via groups with the same distribution positions. In each channel signal region, the conductive via regions of the first signal region and the conductive via groups of the second signal region correspond one-to-one and are symmetric about the first axis. The conductive via regions of the third signal region and the conductive via groups of the fourth signal region correspond one-to-one and are symmetric about the first axis. The conductive via regions of the first signal region and the conductive via groups of the fourth signal region correspond one-to-one and are symmetric about the second axis. Meanwhile, the conductive via groups in different channel signal regions correspond one-to-one and have the same distribution positions (relative to the center of the respective signal region); each conductive via group includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via.

[0235] Please refer to Figure 17B or Figure 18B , for multiple signal regions aligned along the third direction:

[0236] (1) The fourth conductive via D3 belonging to the logic chip 10, the first conductive via D0 belonging to the first memory chip 31, the second conductive via D1 belonging to the second memory chip 32, the third conductive via D2 belonging to the third memory chip 33, and the fourth conductive via D3 belonging to the fourth memory chip 34 are aligned along the third direction;

[0237] (2) The third conductive via D2 belonging to the logic chip 10, the second conductive via D1 belonging to the first memory chip 31, the first conductive via D0 belonging to the second memory chip 32, the fourth conductive via D3 belonging to the third memory chip 33, and the third conductive via D2 belonging to the fourth memory chip 34 are aligned along the third direction;

[0238] (3) The second conductive via D1 belonging to the logic chip 10, the third conductive via D2 belonging to the first memory chip 31, the fourth conductive via D3 belonging to the second memory chip 32, the first conductive via D0 belonging to the third memory chip 33, and the second conductive via D1 belonging to the fourth memory chip 34 are aligned along the third direction;

[0239] (4) The first conductive via D0 belonging to the logic chip 10, the fourth conductive via D3 belonging to the first memory chip 31, the third conductive via D2 belonging to the second memory chip 32, the second conductive via D1 belonging to the third memory chip 33, and the first conductive via D0 belonging to the fourth memory chip 34 are aligned along the third direction; wherein, the multiple conductive vias aligned along the third direction are coupled to form a signal transmission channel.

[0240] Please refer to Figure 16A , when stacking according to the first and second specific embodiments, the repair units of each chip have the following relationships:

[0241] (a) A fourth repair unit in the logic chip 10, a first repair unit in the first memory chip 31, a second repair unit in the second memory chip 32, a third repair unit in the third memory chip 33, and a fourth repair unit in the fourth memory chip 34 are aligned in the third direction and synchronously perform a conductive via switching operation;

[0242] (b) A third repair unit in the logic chip 10, a second repair unit in the first memory chip 31, a first repair unit in the second memory chip 32, a fourth repair unit in the third memory chip 33, and a third repair unit in the fourth memory chip 34 are aligned in the third direction and synchronously perform a conductive via switching operation;

[0243] (c) A second repair unit in the logic chip 10, a third repair unit in the first memory chip 31, a fourth repair unit in the second memory chip 32, a first repair unit in the third memory chip 33, and a second repair unit in the fourth memory chip 34 are aligned in the third direction and synchronously perform a conductive via switching operation;

[0244] (d) A first repair unit in the logic chip 10, a fourth repair unit in the first memory chip 31, a third repair unit in the second memory chip 32, a second repair unit in the third memory chip 33, and a first repair unit in the fourth memory chip 34 are aligned in the third direction and synchronously perform a conductive via switching operation.

[0245] It should be noted that for the logic chip 10, each repair unit therein is coupled to the internal circuit, that is, the normal conductive vias in each repair unit are electrically connected to the internal circuit of the logic chip 10; however, for the memory chips, only the first repair unit is coupled to the internal circuit, that is, only the normal conductive vias in the first repair unit are electrically connected to the internal circuit of the memory chip, and all the conductive vias in the second, third, and fourth repair units are isolated from the internal circuit of the logic chip 10.

[0246] Figure 17C Taking Figure 5 and Figure 11 the division form of the repair unit group and the stacking manner of the first specific embodiment as an example, a schematic diagram of a repair unit group of the logic chip 10 and the symmetry and switching directions of the first repair units in the corresponding memory chips is shown, and other repair units are omitted. That is to say, in Figure 17CIn the example, the first repair unit, the second repair unit, the third repair unit and the fourth repair unit indicated by the curved arrows in the logic chip 10 are all coupled to the internal circuit; however, for the memory chip, only the first repair unit indicated by the curved arrow is coupled to the internal circuit.

[0247] Figure 7 and Figure 13 The chip stacking structure formed by the repair unit group also has the above characteristics, please understand accordingly.

[0248] In this way, the repair units of the chip stacking structure 40 are aligned along the third direction and have symmetrical switching directions, thereby achieving the same switching function.

[0249] In the third specific embodiment, see Figure 19A (Taking m=4 as an example for illustration), when the logic chip 10 and the first memory chip 31 are stacked back to back, and the first axis AA' of the logic chip 10 and each memory chip extends along the first direction (that is, the first axis AA' divides the corresponding chip into a high-order transmission area and a low-order transmission area), the low-order transmission area of ​​the logic chip 10, the high-order transmission area of ​​the first memory chip 31, the low-order transmission area of ​​the second memory chip 32, the low-order transmission area of ​​the third memory chip 33, and the high-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction; the high-order transmission area of ​​the logic chip 10, the low-order transmission area of ​​the first memory chip 31, the high-order transmission area of ​​the second memory chip 32, the high-order transmission area of ​​the third memory chip 33, and the low-order transmission area of ​​the fourth memory chip 34 are aligned along the third direction.

[0250] Specifically, the channel signal areas of each chip have the following symmetrical relationship: the i+1th channel signal area in the logic chip 10 is aligned along the third direction with the channel signal area in the i+1th channel in the first storage chip 31, the channel signal area in the i+1th channel in the second storage chip 32, the channel signal area in the mi-th channel in the third storage chip 33, and the channel signal area in the mi-th channel in the fourth storage chip 34; wherein i is a natural number less than m.

[0251] Figure 19A Take m=4 as an example. At this time:

[0252] (1) the first channel signal region 11 in the logic chip 10, the channel signal region 11 in the first channel of the first memory chip 31, the channel signal region 11 in the first channel of the second memory chip 32, the channel signal region 14 in the fourth channel of the third memory chip 33, and the channel signal region 14 in the fourth channel of the fourth memory chip 34 are aligned along a third direction;

[0253] (2) The second channel signal region 12 in the logic chip 10, the channel signal region 12 in the second channel of the first memory chip 31, the channel signal region 12 in the second channel of the second memory chip 32, the channel signal region 13 in the third channel of the third memory chip 33, and the channel signal region 13 in the third channel of the fourth memory chip 34 are aligned along the third direction;

[0254] (3) The third channel signal region 13 in the logic chip 10, the channel signal region 13 in the third channel of the first memory chip 31, the channel signal region 13 in the third channel of the second memory chip 32, the channel signal region 12 in the second channel of the third memory chip 33, and the channel signal region 12 in the second channel of the fourth memory chip 34 are aligned along the third direction;

[0255] (4) The fourth channel signal region 14 in the logic chip 10, the channel signal region 14 in the fourth channel of the first memory chip 31, the channel signal region 14 in the fourth channel of the second memory chip 32, the channel signal region 11 in the first channel of the third memory chip 33, and the channel signal region 11 in the first channel of the fourth memory chip 34 are aligned along the third direction.

[0256] In the fourth specific embodiment, please refer to Figure 20A (illustrated with m = 4 as an example), when m = 4 and the logic chip 10 and the first memory chip 31 are stacked back-to-back, and the second axes BB' of the logic chip 10 and each memory chip extend along the first direction (that is, the second axis BB' divides the respective chip into a high-bit transmission region and a low-bit transmission region), the high-bit transmission regions of the logic chip 10, the first memory chip 31, the second memory chip 32, the low-bit transmission region of the third memory chip 33, and the low-bit transmission region of the fourth memory chip 34 are aligned along the third direction; the low-bit transmission regions of the logic chip 10, the first memory chip 31, the second memory chip 32, the high-bit transmission region of the third memory chip 33, and the high-bit transmission region of the fourth memory chip 34 are aligned along the third direction.

[0257] Specifically, the channel signal regions of each chip have the following symmetry relationship: the (m - i)-th channel signal region in the logic chip 10 is aligned along the third direction with the channel signal region in the (i + 1)-th channel of the first memory chip 31, the channel signal region in the (m - i)-th channel of the second memory chip 32, the channel signal region in the (m - i)-th channel of the third memory chip 33, and the channel signal region in the (i + 1)-th channel of the fourth memory chip 34; where i is a natural number less than m.

[0258] (1) The fourth channel signal region 14 in the logic chip 10, the channel signal region 11 in the first channel of the first memory chip 31, the channel signal region 14 in the fourth channel of the second memory chip 32, the channel signal region 14 in the fourth channel of the third memory chip 33, and the channel signal region 11 in the first channel of the fourth memory chip 34 are aligned along the third direction;

[0259] (2) The third channel signal region 13 in the logic chip 10, the channel signal region 12 in the second channel of the first memory chip 31, the channel signal region 13 in the third channel of the second memory chip 32, the channel signal region 13 in the third channel of the third memory chip 33, and the channel signal region 12 in the second channel of the fourth memory chip 34 are aligned along the third direction;

[0260] (3) The second channel signal region 12 in the logic chip 10, the channel signal region 13 in the third channel of the first memory chip 31, the channel signal region 12 in the second channel of the second memory chip 32, the channel signal region 12 in the second channel of the third memory chip 33, and the channel signal region 13 in the third channel of the fourth memory chip 34 are aligned along the third direction;

[0261] (4) The first channel signal region 11 in the logic chip 10, the channel signal region 14 in the fourth channel of the first memory chip 31, the channel signal region 11 in the first channel of the second memory chip 32, the channel signal region 11 in the first channel of the third memory chip 33, and the channel signal region 14 in the fourth channel of the fourth memory chip 34 are aligned along the third direction.

[0262] Simply put, for Figures 19A to 20B , the logic chip 10 and the second memory chip 32 are arranged in the same way.

[0263] In some embodiments, please refer to Figure 19B and Figure 20B , the channel signal regions in each channel of the memory chip and the logic chip 10 are each divided into 2×2 signal regions arranged in an array. Please refer to Figure 19B and Figure 19B , for multiple channel signal regions aligned along the third direction:

[0264] (1) The second signal region 22 belonging to the logic chip 10, the first signal region 21 belonging to the first memory chip 31, the second signal region 22 belonging to the second memory chip 32, the third signal region 23 belonging to the third memory chip 33, and the fourth signal region 24 belonging to the fourth memory chip 34 are aligned along the third direction;

[0265] (2) The first signal region 21 belonging to the logic chip 10, the second signal region 22 belonging to the first memory chip 31, the first signal region 21 belonging to the second memory chip 32, the fourth signal region 24 belonging to the third memory chip 33, and the third signal region 23 belonging to the fourth memory chip 34 are aligned along the third direction;

[0266] (3) The fourth signal region 24 belonging to the logic chip 10, the third signal region 23 belonging to the first memory chip 31, the fourth signal region 24 belonging to the second memory chip 32, the first signal region 21 belonging to the third memory chip 33, and the second signal region 22 belonging to the fourth memory chip 34 are aligned along the third direction;

[0267] (4) The third signal region 23 belonging to the logic chip 10, the fourth signal region 24 belonging to the first memory chip 31, the third signal region 23 belonging to the second memory chip 32, the second signal region 22 belonging to the third memory chip 33, and the first signal region 21 belonging to the fourth memory chip 34 are aligned along the third direction.

[0268] Please refer to Figure 19B or Figure 19B , each signal region of the memory chip and the logic chip 10 includes n conductive via groups with the same distribution positions, and each conductive via group includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via.

[0269] For multiple signal regions aligned along the third direction:

[0270] (1) The second conductive via D1 belonging to the logic chip 10, the first conductive via D0 belonging to the first memory chip 31, the second conductive via D1 belonging to the second memory chip 32, the third conductive via D2 belonging to the third memory chip 33, and the fourth conductive via D3 belonging to the fourth memory chip 34 are aligned along the third direction;

[0271] (2) The first conductive via D0 belonging to the logic chip 10, the second conductive via D1 belonging to the first memory chip 31, the first conductive via D0 belonging to the second memory chip 32, the fourth conductive via D3 belonging to the third memory chip 33, and the third conductive via D2 belonging to the fourth memory chip 34 are aligned along the third direction;

[0272] (3) The fourth conductive via D3 belonging to the logic chip 10, the third conductive via D2 belonging to the first memory chip 31, the fourth conductive via D3 belonging to the second memory chip 32, the first conductive via D0 belonging to the third memory chip 33, and the second conductive via D1 belonging to the fourth memory chip 34 are aligned along the third direction;

[0273] (4) The third conductive vias D2 belonging to the logic chip 10, the fourth conductive vias D3 belonging to the first memory chip 31, the third conductive vias D2 belonging to the second memory chip 32, the second conductive vias D1 belonging to the third memory chip 33, and the first conductive vias D0 belonging to the fourth memory chip 34 are aligned along the third direction;

[0274] Among them, multiple conductive vias aligned along the third direction are coupled to form a signal transmission channel.

[0275] Please refer to Figure 16B , for the 3rd and 4th specific embodiments, the repair units of each chip have the following relationships:

[0276] (a) A second repair unit in the logic chip 10, a first repair unit in the first memory chip 31, a second repair unit in the second memory chip 32, a third repair unit in the third memory chip 33, and a fourth repair unit in the fourth memory chip 34 are aligned along the third direction and synchronously perform conductive via switching operations;

[0277] (b) A first repair unit in the logic chip 10, a second repair unit in the first memory chip 31, a first repair unit in the second memory chip 32, a fourth repair unit in the third memory chip 33, and a third repair unit in the fourth memory chip 34 are aligned along the third direction and synchronously perform conductive via switching operations;

[0278] (c) A fourth repair unit in the logic chip 10, a third repair unit in the first memory chip 31, a fourth repair unit in the second memory chip 32, a first repair unit in the third memory chip 33, and a second repair unit in the fourth memory chip 34 are aligned along the third direction and synchronously perform conductive via switching operations;

[0279] (d) A third repair unit in the logic chip 10, a fourth repair unit in the first memory chip 31, a third repair unit in the second memory chip 32, a second repair unit in the third memory chip 33, and a first repair unit in the fourth memory chip 34 are aligned along the third direction and synchronously perform conductive via switching operations.

[0280] Similarly, the repair units of the chip stack structure 40 are aligned along the third direction and have symmetric switching directions, so as to achieve the same switching function.

[0281] For a more convenient understanding of the signal switching process of the chip stack structure 40, the signal switching is described below for a specific working scenario: Using Figure 5 the logic chip 10 provided, and Figure 11The provided memory chip 30 passes through Figure 17A The chip stack structure 40 formed in a stacked form, assuming that each repair unit is a 2:1 repair. Please refer to Figure 21 , which provides a signal transmission schematic diagram of the chip stack structure 40.

[0282] Figure 21 It shows one repair unit group in each chip. For their respective repair unit groups, there are only 2 signal selection circuits 100 in each memory chip, so that only two conductive vias in the first repair unit in the repair unit group are connected to the internal circuit of the memory chip, that is, only the signal channel composed of 2 conductive vias is connected to the internal circuit of the memory chip. There are 8 signal selection circuits in the logic chip 10, so that 2 conductive vias in each repair unit in the repair unit group are connected to the internal circuit of the logic chip, that is, a total of 8 conductive vias in 4 repair units form a signal channel connected to the internal circuit of the logic chip. Furthermore, the logic chip 10 can be respectively connected to the corresponding memory chip through 2 signal conductions for signal interaction.

[0283] Please refer to Figures 21 to 22B , and the following exemplary working scenarios are provided:

[0284] Taking the fourth repair unit composed of D3 / 0, D3 / 1, D3 / 2 in the fourth signal area of the logic chip 10, the first repair unit composed of D0 / 0, D0 / 1, D0 / 2 in the first signal area of the first memory chip 31, the second repair unit composed of D1 / 0, D1 / 1, D1 / 2 in the second signal area of the second memory chip 32, the third repair unit composed of D2 / 0, D2 / 1, D2 / 2 in the third signal area of the third memory chip 33, and the fourth repair unit composed of D3 / 0, D3 / 1, D3 / 2 in the fourth signal area of the fourth memory chip 34 as an example, the specific process of signal switching is described.

[0285] As Figure 21As shown, D3 / 0 in the fourth signal area of the logic chip 10, D0 / 0 in the first signal area of the first memory chip 31, D1 / 0 in the second signal area of the second memory chip 32, D2 / 0 in the third signal area of the third memory chip 33, and D3 / 0 in the fourth signal area of the fourth memory chip 34 are connected to form a signal channel (the first normal signal channel); at the same time, D3 / 1 in the fourth signal area of the logic chip 10, D0 / 1 in the first signal area of the first memory chip 31, D1 / 1 in the second signal area of the second memory chip 32, D2 / 1 in the third signal area of the third memory chip 33, and D3 / 1 in the fourth signal area of the fourth memory chip 34 are connected to form a signal channel (the second normal signal channel), and all of the above are normal conductive vias; at the same time, D3 / 2 in the fourth signal area of the logic chip 10, D0 / 2 in the first signal area of the first memory chip 31, D1 / 2 in the second signal area of the second memory chip 32, D2 / 2 in the third signal area of the third memory chip 33, and D3 / 2 in the fourth signal area of the fourth memory chip 34 are connected to form a signal channel (the first redundant signal channel);

[0286] When all the conductive vias are normal, please refer to Figure 22A , the signal selection circuit 100a in the logic chip 10 connects D3 / 0 to the internal circuit, and the signal selection circuit 100c in the first memory chip 31 connects D0 / 0 to the internal circuit, so that the first normal signal channel is used to transmit the valid signal (denoted as signal1), and the logic chip 10 can send / receive the valid signal signal1 from D3 / 0 through the signal selection circuit 100a, and the first memory chip 31 can receive / send the valid signal signal1 from D0 / 0 through the signal selection circuit 100c;

[0287] Similarly, the signal selection circuit 100b in the logic chip 10 connects D3 / 1 to the internal circuit, and the second normal signal channel sends / receives another valid signal (denoted as signal2), and the signal selection circuit 100d in the first memory chip 31 connects D0 / 1 to the internal circuit, so as to receive / send the valid signal signal2;

[0288] Please refer to Figure 22B, assume that any one of the conductive vias in the first normal signal channel is damaged, that is, the corresponding first normal signal channel cannot be used. At this time, the redundant signal channel needs to be used for repair. Then, for the logic chip 10, the signal selection circuit 100a connects D0 / 1 to the internal circuit to replace the original D0 / 0 to send / receive the valid signal signal1; the signal selection circuit 100b connects D0 / 2 to the internal circuit to replace the original D0 / 1 to send / receive the valid signal signal2; at the same time, for the first storage chip 31, the signal selection circuit 100c connects D0 / 1 to the internal circuit to replace the original D0 / 0 to receive / send the valid signal signal1; the signal selection circuit 100d connects D0 / 2 to the internal circuit to replace the original D0 / 1 to receive / send the valid signal signal12; thus, the switching work of the first normal signal channel to the second normal signal channel and the second normal signal channel to the first redundant signal channel is completed.

[0289] The following specifically describes the signal switching for the following specific working scenarios: Using Figure 7 the provided logic chip 10 and Figure 13 the provided storage chip 30 through Figure 17A the stacked form of Figure 23 which provides a signal transmission schematic diagram of the chip stack structure 40.

[0290] Please refer to Figures 23 to 24B which provides the following exemplary working scenarios:

[0291] Taking the fourth repair unit composed of D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the fourth signal area of the logic chip 10, the first repair unit composed of D0 / 0, D0 / 1, D0 / 2, D0 / 3, D0 / 4, D0 / 5 in the first signal area of the first storage chip 31, the second repair unit composed of D1 / 0, D1 / 1, D1 / 2, D1 / 3, D0 / 4, D1 / 5 in the second signal area of the second storage chip 32, the third repair unit composed of D2 / 0, D2 / 1, D2 / 2, D2 / 3, D2 / 4, D2 / 5 in the third signal area of the third storage chip 33, and the fourth repair unit composed of D3 / 0, D3 / 1, D3 / 2, D3 / 3, D3 / 4, D3 / 5 in the fourth signal area of the fourth storage chip 34 as an example, the specific process of signal switching is described.

[0292] As Figure 23As shown, D3 / 2 in the fourth signal area of the logic chip 10, D0 / 2 in the first signal area of the first memory chip 31, D1 / 2 in the second signal area of the second memory chip 32, D2 / 2 in the third signal area of the third memory chip 33, and D3 / 2 in the fourth signal area of the fourth memory chip 34 are connected to form a signal channel (the first normal signal channel); D3 / 3 in the fourth signal area of the logic chip 10, D0 / 3 in the first signal area of the first memory chip 31, D1 / 3 in the second signal area of the second memory chip 32, D2 / 3 in the third signal area of the third memory chip 33, and D3 / 3 in the fourth signal area of the fourth memory chip 34 are connected to form a signal channel (the second normal signal channel); D3 / 4 in the fourth signal area of the logic chip 10, D0 / 4 in the first signal area of the first memory chip 31, D1 / 4 in the second signal area of the second memory chip 32, D2 / 4 in the third signal area of the third memory chip 33, and D3 / 4 in the fourth signal area of the fourth memory chip 34 are connected to form a signal channel (the third normal signal channel); D3 / 1 in the fourth signal area of the logic chip 10, D0 / 1 in the first signal area of the first memory chip 31, D1 / 1 in the second signal area of the second memory chip 32, D2 / 1 in the third signal area of the third memory chip 33, and D3 / 0 in the fourth signal area of the fourth memory chip 34 are connected to form a signal channel (the fourth normal signal channel); and all of the above are normal conductive vias;

[0293] Meanwhile, D3 / 0 in the fourth signal area of the logic chip 10, D0 / 0 in the first signal area of the first memory chip 31, D1 / 0 in the second signal area of the second memory chip 32, D2 / 0 in the third signal area of the third memory chip 33, and D3 / 0 in the fourth signal area of the fourth memory chip 34 are connected to form a signal channel (the first redundant signal channel); D3 / 5 in the fourth signal area of the logic chip 10, D0 / 5 in the first signal area of the first memory chip 31, D1 / 5 in the second signal area of the second memory chip 32, D2 / 5 in the third signal area of the third memory chip 33, and D3 / 5 in the fourth signal area of the fourth memory chip 34 are connected to form a signal channel (the second redundant signal channel);

[0294] When all the conductive vias are normal, please refer to Figure 24A, the signal selection circuit 100A in the logic chip 10 connects D3 / 2 to the internal circuit, and the signal selection circuit 100E in the first memory chip 31 connects D0 / 2 to the internal circuit. Thus, the first normal signal channel is used to transmit the valid signal (denoted as signal1). Specifically, the logic chip 10 can send / receive the valid signal signal1 from D2 / 6 through the signal selection circuit 100A, and the first memory chip 31 can receive / send the valid signal signal1 from D1 / 1 through the signal selection circuit 100E;

[0295] Similarly, the signal selection circuit 100B in the logic chip 10 connects D3 / 3 to the internal circuit, and the second normal signal channel sends / receives another valid signal (denoted as signal2). The signal selection circuit 100F in the first memory chip 31 connects D0 / 3 to the internal circuit to receive / send the valid signal signal2; the signal selection circuit 100C in the logic chip 10 connects D3 / 4 to the internal circuit, and the second normal signal channel sends / receives another valid signal (denoted as signal3). The signal selection circuit 100G in the first memory chip 31 connects D0 / 4 to the internal circuit to receive / send the valid signal signal3; the signal selection circuit 100D in the logic chip 10 connects D3 / 4 to the internal circuit, and the second normal signal channel sends / receives another valid signal (denoted as signal4). The signal selection circuit 100H in the first memory chip 31 connects D0 / 4 to the internal circuit to receive / send the valid signal signal4.

[0296] Please refer to Figure 24B , assuming that the first normal signal channel cannot be used and the redundant signal channel needs to be utilized for repair at this time. Then, for the logic chip 10, the signal selection circuit 100A connects D3 / 3 to the internal circuit to send / receive the valid signal signal1 instead of the original D3 / 2; the signal selection circuit 100B connects D3 / 4 to the internal circuit to send / receive the valid signal signal2 instead of the original D3 / 3; the signal selection circuit 100C connects D3 / 1 to the internal circuit to send / receive the valid signal signal3 instead of the original D3 / 4; the signal selection circuit 100D connects D3 / 0 to the internal circuit to send / receive the valid signal signal4 instead of the original D3 / 1;

[0297] Meanwhile, for the first memory chip 31, the signal selection circuit 100E connects D0 / 3 to the internal circuit to receive / transmit the valid signal signal1 instead of the original D1 / 2; the signal selection circuit 100F connects D0 / 4 to the internal circuit to receive / transmit the valid signal signal12 instead of the original D0 / 3; the signal selection circuit 100G connects D0 / 1 to the internal circuit to receive / transmit the valid signal signal13 instead of the original D0 / 4; the signal selection circuit 100H connects D0 / 0 to the internal circuit to receive / transmit the valid signal signal15 instead of the original D0 / 1.

[0298] Thus, the switching work of the first normal signal channel to the second normal signal channel, the second normal signal channel to the third normal signal channel, the third normal signal channel to the fourth normal signal channel, and the fourth normal signal channel to the first redundant signal channel is completed.

[0299] Meanwhile, from Figure 17B 、 Figure 18B 、 Figure 19B 、 Figure 20B 、 Figures 21 to 24B It can be seen that for the chip stack structure 40, the signal transmission path from bottom to top will be similar to the following form: Please refer to Figure 17B 、 Figure 18B , the fourth conductive via D3 in the logic chip 10 (or the fourth conductive via D1 in the logic chip 10, please refer to Figure 19B 、 Figure 20B ) - the first conductive via D0 in the first memory chip 31 - the second conductive via D1 in the second memory chip 32 - the third conductive via D2 in the third memory chip 33 - the fourth conductive via D3 in the fourth memory chip 34... for transmission. That is to say, for the chip stack structure 40, from a physical perspective, the conductive vias therein are still in a direct connection configuration, but from the absolute position of the conductive vias on the active surface, the conductive vias therein can be regarded as a functional rotation configuration, that is, a signal transmission effect similar to Figure 2B (i.e., the rotation transmission effect of conductive via D0 - conductive via D1 - conductive via D2 - conductive via D3...) is achieved through the physical direct connection configuration. Simply put, Figure 2B the chip stack structure 40 in

[0300] In another embodiment of the present disclosure, refer to Figure 25, which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. As Figure 25 shown, the memory 70 includes the chip stacking structure 40 of the foregoing embodiment.

[0301] In some embodiments, the chip stacking structure 40 can be applied to the memory 70. Among them, the memory 70 can be, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc., and specific limitations are not made here.

[0302] In the embodiment of the present disclosure, for the memory 70, the chip area can be reduced and the chip manufacturing cost can be reduced.

[0303] For the details not disclosed in the embodiments of the present disclosure, reference may be made to the description of the foregoing embodiments for understanding.

[0304] The above are only the preferred embodiments of the present disclosure, and are not used to limit the protection scope of the present disclosure.

[0305] It should be noted that in the present disclosure, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, the element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0306] The serial numbers of the above embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0307] The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0308] The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0309] The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0310] As mentioned above, the above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A logic chip, characterized in that, the logic chip includes m channel signal regions arranged in sequence along a first direction, the logic chip has a chip axis extending along a second direction and passing through the center of the logic chip, and the m channel signal regions are symmetric about the chip axis; m is a positive integer; each of the channel signal regions has a first axis and a second axis, the first axis extends along the first direction or the second direction, and the second axis is perpendicular to and intersects the first axis at the center of the corresponding channel signal region; each of the channel signal regions is penetrated by a plurality of conductive vias along a third direction, the first direction, the second direction, and the third direction are perpendicular to each other in pairs, the first direction and the second direction are parallel to the top surface of the logic chip, and the third direction is perpendicular to the top surface of the logic chip; for each of the channel signal regions, the plurality of conductive vias therein are divided into a plurality of repair unit groups; each of the repair unit groups includes a first repair unit, a second repair unit, a third repair unit, and a fourth repair unit; the first repair unit and the second repair unit are symmetric about the first axis of the corresponding channel signal region, the third repair unit and the fourth repair unit are symmetric about the first axis of the corresponding channel signal region, and the first repair unit and the fourth repair unit are symmetric about the second axis of the corresponding channel signal region; each of the repair units includes at least one redundant conductive via and at least one normal conductive via, and when any one of the normal conductive vias is damaged, the effective signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset signal switching direction; any one of the conductive vias in any one of the repair units is electrically connected to the internal circuit of the logic chip when used for transmitting an effective signal; the normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit are in one-to-one correspondence and symmetric about the first axis of the corresponding channel signal region, the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit are in one-to-one correspondence and symmetric about the first axis of the corresponding channel signal region, and the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit are in one-to-one correspondence and symmetric about the second axis of the corresponding channel signal region.

2. The logic chip according to claim 1, characterized in that, For each of the repair unit groups, the preset switching direction of the conductive vias in the first repair unit and the preset switching direction of the conductive vias in the second repair unit are symmetric about the first axis of the channel signal region to which they belong; the preset switching direction of the conductive vias in the third repair unit and the preset switching direction of the conductive vias in the fourth repair unit are symmetric about the first axis of the channel signal region to which they belong; the preset switching direction of the conductive vias in the first repair unit and the preset switching direction of the conductive vias in the fourth repair unit are symmetric about the second axis of the channel signal region to which they belong; the preset switching direction of the conductive vias in the second repair unit and the preset switching direction of the conductive vias in the third repair unit are symmetric about the second axis of the channel signal region to which they belong.

3. The logic chip according to claim 2, wherein, each of the channel signal regions is divided into 2×2 signal regions, and the conductive vias in each signal region are divided into n conductive via groups with the same distribution positions, where n is a positive integer; in the same channel signal region, the conductive via groups in the first signal region and the conductive via groups in the second signal region correspond one by one and are symmetric about the first axis of the channel signal region to which they belong, the conductive via groups in the third signal region and the conductive via groups in the fourth signal region correspond one by one and are symmetric about the first axis of the channel signal region to which they belong, and the conductive via groups in the first signal region and the conductive via groups in the fourth signal region correspond one by one and are symmetric about the second axis of the channel signal region to which they belong; each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via; in the same channel signal region, the whole formed by the first conductive via in a conductive via group in the first signal region, the second conductive via in the corresponding conductive via group in the second signal region, the third conductive via in the corresponding conductive via group in the third signal region, and the fourth conductive via in the corresponding conductive via group in the fourth signal region is symmetric about the first axis and symmetric about the second axis; in the same channel signal region, the whole formed by the second conductive via in a conductive via group in the first signal region, the first conductive via in the corresponding conductive via group in the second signal region, the fourth conductive via in the corresponding conductive via group in the third signal region, and the third conductive via in the corresponding conductive via group in the fourth signal region is symmetric about the first axis and symmetric about the second axis; in the same channel signal region, the whole formed by the third conductive via in a conductive via group in the first signal region, the fourth conductive via in the corresponding conductive via group in the second signal region, the first conductive via in the corresponding conductive via group in the third signal region, and the second conductive via in the corresponding conductive via group in the fourth signal region is symmetric about the first axis and symmetric about the second axis; In the same channel signal region, the whole formed by the fourth conductive vias in a conductive via group in the first signal region, the third conductive vias in the corresponding conductive via group in the second signal region, the second conductive vias in the corresponding conductive via group in the third signal region, and the first conductive vias in the corresponding conductive via group in the fourth signal region is symmetric along the first axis and symmetric along the second axis.

4. The logic chip according to claim 3, wherein, each B conductive via groups in each signal region are referred to as 1 conductive via combination, and the whole formed by the conductive via groups b in the corresponding conductive via combinations in all signal regions is symmetric along the first axis and symmetric along the second axis, B is a positive integer less than or equal to n, and b is a natural number less than B; each corresponding 1 conductive via combination in each signal region in the same channel signal region together form 4 repair unit groups: For the 1st repair unit group, the first repair unit therein includes: the first conductive vias of all the conductive via groups in the conductive via combination in the first signal region; the second repair unit therein includes: the second conductive vias of all the conductive via groups in the conductive via combination in the second signal region; the third repair unit therein includes: the third conductive vias of all the conductive via groups in the conductive via combination in the third signal region; the fourth repair unit therein includes: the fourth conductive vias of all the conductive via groups in the conductive via combination in the fourth signal region; For the 2nd repair unit group, the first repair unit therein includes: the first conductive vias of all the conductive via groups in the conductive via combination in the second signal region; the second repair unit therein includes: the second conductive vias of all the conductive via groups in the conductive via combination in the first signal region; the third repair unit therein includes: the third conductive vias of all the conductive via groups in the conductive via combination in the fourth signal region; the fourth repair unit therein includes: the fourth conductive vias of all the conductive via groups in the conductive via combination in the third signal region; For the 3rd repair unit group, the first repair unit therein includes: the first conductive vias of all the conductive via groups in the conductive via combination in the third signal region; the second repair unit therein includes: the second conductive vias of all the conductive via groups in the conductive via combination in the fourth signal region; the third repair unit therein includes: the third conductive vias of all the conductive via groups in the conductive via combination in the first signal region; the fourth repair unit therein includes: the fourth conductive vias of all the conductive via groups in the conductive via combination in the second signal region; For the fourth repair unit group, the first repair unit therein includes: the first conductive vias of each of the conductive via groups in the conductive via combination in the fourth signal region; the second repair unit therein includes: the second conductive vias of each of the conductive via groups in the conductive via combination in the third signal region; the fourth repair unit therein includes: the third conductive vias of each of the conductive via groups in the conductive via combination in the second signal region; the fourth repair unit therein includes: the fourth conductive vias of each of the conductive via groups in the conductive via combination in the first signal region.

5. The logic chip according to claim 4, wherein, when B = 3, the value of b is 0, 1 or 2; all the conductive vias in the conductive via group 0 are normal conductive vias; The preset switching direction of the conductive vias in the Xth repair unit is: the Xth conductive via in the conductive via group 0 therein is allowed to be switched to the Xth conductive via in the conductive via group 1 in the same signal region, and the Xth conductive via in the conductive via group 1 is allowed to be switched to the Xth conductive via in the conductive via group 2 in the same signal region; X takes one, two, three or four.

6. The logic chip according to claim 4, wherein, when B = 6, the value of b is 0, 1, 2, 3, 4 or 5; all the conductive vias in the conductive via group 2 in all signal regions are normal conductive vias; The preset switching direction of the conductive vias in the Xth repair unit is: the Xth conductive via in the conductive via group 2 is allowed to be switched to the Xth conductive via in the conductive via group 3 in the same signal region, the Xth conductive via in the conductive via group 3 is allowed to be switched to the Xth conductive via in the conductive via group 4 in the same signal region, the Xth conductive via in the conductive via group 4 is allowed to be switched to the Xth conductive via in the conductive via group 1 in the same signal region; the Xth conductive via in the conductive via group 1 is allowed to be switched to the Xth conductive via in the conductive via group 0 in the same signal region; the Xth conductive via in the conductive via group 0 is allowed to be switched to the Xth conductive via in the conductive via group 5 in the same signal region.

7. The logic chip according to claim 6, wherein, in each signal region, the conductive via group 0, the conductive via group 1, and the conductive via group 2 are aligned along the first direction; the conductive via group 3, the conductive via group 4, and the conductive via group 5 are aligned along the first direction; the conductive via group 0 and the conductive via group 5 are aligned along the second direction, the conductive via group 1 and the conductive via group 4 are aligned along the second direction, and the conductive via group 2 and the conductive via group 3 are aligned along the second direction.

8. The logic chip according to any one of claims 1-7, wherein, The conductive vias are prepared by any one or more of the via-first process, via-middle process, via-last process, and back side via-last process; different conductive vias in the same logic chip are electrically isolated.

9. A memory chip, characterized in that the memory chip includes m channels, the m channels are arranged in sequence along a first direction, the memory chip has a chip axis extending along a second direction and passing through the center of the memory chip, and the m channels are symmetric about the chip axis; each of the channels includes a first memory array region, a channel signal region, and a second memory array region that are sequentially distributed along the second direction, and the center of each channel signal region coincides with the center of the corresponding channel, where m is a positive integer; each of the channel signal regions has a first axis and a second axis, the first axis extends along the first direction or the second direction, and the second axis is perpendicular to the first axis and intersects at the center of the corresponding channel signal region; each of the channel signal regions is penetrated by a plurality of conductive vias along a third direction, the first direction, the second direction, and the third direction are perpendicular to each other in pairs, the first direction and the second direction are parallel to the top surface of the memory chip, and the third direction is perpendicular to the top surface of the memory chip; for each of the channel signal regions, the plurality of conductive vias therein are divided into a plurality of repair unit groups; each repair unit group includes a first repair unit, a second repair unit, a third repair unit, and a fourth repair unit; the first repair unit and the second repair unit are symmetric about the first axis of the corresponding channel signal region, the third repair unit and the fourth repair unit are symmetric about the first axis of the corresponding channel signal region, and the first repair unit and the fourth repair unit are symmetric about the second axis of the corresponding channel signal region; each repair unit includes at least one redundant conductive via and at least one normal conductive via, and when any one of the normal conductive vias is damaged, the valid signal transmitted by the normal conductive via is switched to the next conductive via in the same repair unit along a preset signal switching direction; any conductive via in the first repair unit is electrically connected to the internal circuit of the memory chip when used to transmit a valid signal; the normal conductive vias in the first repair unit and the normal conductive vias in the second repair unit are in one-to-one correspondence and symmetric about the first axis of the corresponding channel signal region, the normal conductive vias in the third repair unit and the normal conductive vias in the fourth repair unit are in one-to-one correspondence and symmetric about the first axis of the corresponding channel signal region, and the normal conductive vias in the first repair unit and the normal conductive vias in the fourth repair unit are in one-to-one correspondence and symmetric about the second axis of the corresponding channel signal region.

10. The memory chip according to claim 9, characterized in that For each of the repair unit groups, the preset switching direction of the conductive vias in the first repair unit and the preset switching direction of the conductive vias in the second repair unit are symmetric about the first axis of the channel signal region to which they belong; the preset switching direction of the conductive vias in the third repair unit and the preset switching direction of the conductive vias in the fourth repair unit are symmetric about the first axis of the channel signal region to which they belong; the preset switching direction of the conductive vias in the first repair unit and the preset switching direction of the conductive vias in the fourth repair unit are symmetric about the second axis of the channel signal region to which they belong; the preset switching direction of the conductive vias in the second repair unit and the preset switching direction of the conductive vias in the third repair unit are symmetric about the second axis of the channel signal region to which they belong.

11. The memory chip according to claim 10, wherein, each of the channel signal regions is divided into 2×2 signal regions, and the conductive vias in each signal region are divided into n conductive via groups with the same distribution positions, where n is a positive integer; in the same channel signal region, the conductive via groups in the first signal region and the conductive via groups in the second signal region correspond one by one and are symmetric about the first axis, the conductive via groups in the third signal region and the conductive via groups in the fourth signal region correspond one by one and are symmetric about the first axis, and the conductive via groups in the first signal region and the conductive via groups in the fourth signal region correspond one by one and are symmetric about the second axis; each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via; For the same channel signal region, the whole formed by the first conductive via in a conductive via group in the first signal region, the second conductive via in the corresponding conductive via group in the second signal region, the third conductive via in the corresponding conductive via group in the third signal region, and the fourth conductive via in the corresponding conductive via group in the fourth signal region is symmetric about the first axis and symmetric about the second axis; In the same channel signal region, the whole formed by the second conductive via in a conductive via group in the first signal region, the first conductive via in the corresponding conductive via group in the second signal region, the fourth conductive via in the corresponding conductive via group in the third signal region, and the third conductive via in the corresponding conductive via group in the fourth signal region is symmetric about the first axis and symmetric about the second axis; In the same channel signal region, the whole formed by the third conductive via in a conductive via group in the first signal region, the fourth conductive via in the corresponding conductive via group in the second signal region, the first conductive via in the corresponding conductive via group in the third signal region, and the second conductive via in the corresponding conductive via group in the fourth signal region is symmetric about the first axis and symmetric about the second axis; In the same channel signal region, the overall structure formed by the fourth conductive vias in a conductive via group in the first signal region, the third conductive vias in the corresponding conductive via group in the second signal region, the second conductive vias in the corresponding conductive via group in the third signal region, and the first conductive vias in the corresponding conductive via group in the fourth signal region is symmetric about the first axis and symmetric about the second axis.

12. The memory chip according to claim 11, wherein, each B conductive via groups in each signal region are referred to as 1 conductive via combination, and the overall structure formed by the conductive via groups b in the corresponding conductive via combinations in all signal regions is symmetric about the first axis and symmetric about the second axis, where B is a positive integer less than or equal to n, and b is a natural number less than B; each of the corresponding 1 conductive via combinations in each signal region in the same channel signal region together form 4 repair unit groups: For the 1st repair unit group, the first repair unit therein includes: the first conductive vias of all the conductive via groups in the conductive via combination in the first signal region; the second repair unit therein includes: the second conductive vias of all the conductive via groups in the conductive via combination in the second signal region; the third repair unit therein includes: the third conductive vias of all the conductive via groups in the conductive via combination in the third signal region; the fourth repair unit therein includes: the fourth conductive vias of all the conductive via groups in the conductive via combination in the fourth signal region; For the 2nd repair unit group, the first repair unit therein includes: the first conductive vias of all the conductive via groups in the conductive via combination in the second signal region; the second repair unit therein includes: the second conductive vias of all the conductive via groups in the conductive via combination in the first signal region; the third repair unit therein includes: the third conductive vias of all the conductive via groups in the conductive via combination in the fourth signal region; the fourth repair unit therein includes: the fourth conductive vias of all the conductive via groups in the conductive via combination in the third signal region; For the 3rd repair unit group, the first repair unit therein includes: the first conductive vias of all the conductive via groups in the conductive via combination in the third signal region; the second repair unit therein includes: the second conductive vias of all the conductive via groups in the conductive via combination in the fourth signal region; the third repair unit therein includes: the third conductive vias of all the conductive via groups in the conductive via combination in the first signal region; the fourth repair unit therein includes: the fourth conductive vias of all the conductive via groups in the conductive via combination in the second signal region; For the fourth repair unit group, the first repair unit therein includes: the first conductive vias of each of the conductive via groups in the conductive via combination in the fourth signal region; the second repair unit therein includes: the second conductive vias of each of the conductive via groups in the conductive via combination in the third signal region; the fourth repair unit therein includes: the third conductive vias of each of the conductive via groups in the conductive via combination in the second signal region; the fourth repair unit therein includes: the fourth conductive vias of each of the conductive via groups in the conductive via combination in the first signal region.

13. The memory chip according to claim 12, wherein, when B = 3, the value of b is 0, 1 or 2; the conductive vias in the conductive via group 0 are all normal conductive vias; The preset switching direction of the conductive vias in any one of the first repair units is: the first conductive via in the conductive via group 0 is allowed to be switched to the first conductive via in the conductive via group 1 in the same signal region, and the first conductive via in the conductive via group 1 is allowed to be switched to the first conductive via in the conductive via group 2 in the same signal region.

14. The memory chip according to claim 13, wherein, when B = 6, the value of b is 0, 1, 2, 3, 4 or 5; the conductive vias in the conductive via group 0 of all signal regions are all normal conductive vias; The preset switching direction of the conductive vias in the first repair unit is: the first conductive via in the conductive via group 2 is allowed to be switched to the first conductive via in the conductive via group 3 in the same signal region, the first conductive via in the conductive via group 3 is allowed to be switched to the first conductive via in the conductive via group 4 in the same signal region, the first conductive via in the conductive via group 4 is allowed to be switched to the first conductive via in the conductive via group 1 in the same signal region; the first conductive via in the conductive via group 1 is allowed to be switched to the first conductive via in the conductive via group 0 in the same signal region; the first conductive via in the conductive via group 0 is allowed to be switched to the first conductive via in the conductive via group 5 in the same signal region.

15. A chip stack structure, wherein, the chip stack structure includes the logic chip according to any one of claims 1-8 and at least one stack unit, and the logic chip and at least one stack unit are stacked in sequence along the third direction; each stack unit includes a first memory chip, a second memory chip, a third memory chip and a fourth memory chip stacked in sequence along the third direction, and the third direction is perpendicular to the top surface of each chip; the first memory chip, the second memory chip, the third memory chip and the fourth memory chip are all memory chips according to any one of claims 9-14; The first memory chip and the second memory chip are stacked face to face, the second memory chip and the third memory chip are stacked back to back, and the third memory chip and the fourth memory chip are stacked face to face; The logic chip and the first memory chip are stacked back to back; Alternatively, the logic chip and the first memory chip are stacked back to face.

16. The chip stacking structure according to claim 15, wherein, the logic chip includes m channel signal regions arranged along a first direction, each memory chip has m channels arranged along the first direction, and each channel includes a first memory array region, a channel signal region, and a second memory array region sequentially distributed along a second direction; The first direction, the second direction, and the third direction are perpendicular to each other in pairs, and the first direction and the second direction are parallel to the top surface of each chip; When the logic chip and the first memory chip are stacked back to back, and the first axes of the logic chip and each memory chip extend along the first direction, the (m - i)-th channel signal region in the logic chip is aligned with the channel signal region in the (i + 1)-th channel of the first memory chip, the channel signal region in the (i + 1)-th channel of the second memory chip, the channel signal region in the (m - i)-th channel of the third memory chip, and the channel signal region in the (m - i)-th channel of the fourth memory chip along the third direction; where i is a natural number less than m.

17. The chip stacking structure according to claim 16, wherein, the logic chip includes m channel signal regions arranged along a first direction, each memory chip has m channels arranged along the first direction, and each channel includes a first memory array region, a channel signal region, and a second memory array region sequentially distributed along a second direction; When the logic chip and the first memory chip are stacked back to back, and the second axes of the logic chip and each memory chip extend along the first direction, the (i + 1)-th channel signal region in the logic chip is aligned with the channel signal region in the (i + 1)-th channel of the first memory chip, the channel signal region in the (m - i)-th channel of the second memory chip, the channel signal region in the (m - i)-th channel of the third memory chip, and the channel signal region in the (i + 1)-th channel of the fourth memory chip along the third direction; where i is a natural number less than m.

18. The chip stacking structure according to claim 16 or 17, wherein, the channel signal region in each channel is divided into 2×2 signal regions distributed in an array; Only for multiple channel signal regions aligned along the third direction: The fourth signal region belonging to the logic chip, the first signal region in the first memory chip, the second signal region in the second memory chip, the third signal region in the third memory chip, and the fourth signal region in the fourth memory chip are aligned along the third direction; The third signal region belonging to the logic chip, the second signal region in the first memory chip, the first signal region in the second memory chip, the fourth signal region in the third memory chip, and the third signal region in the fourth memory chip are aligned along the third direction; The second signal region belonging to the logic chip, the third signal region in the first memory chip, the fourth signal region in the second memory chip, the first signal region in the third memory chip, and the second signal region in the fourth memory chip are aligned along the third direction; The first signal region belonging to the logic chip, the fourth signal region in the first memory chip, the third signal region in the second memory chip, the second signal region in the third memory chip, and the first signal region in the fourth memory chip are aligned along the third direction.

19. The chip stack structure according to claim 18, wherein, each of the signal regions includes n conductive via groups with the same distribution positions, and each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via; only for the multiple signal regions aligned along the third direction: the fourth conductive via belonging to the logic chip, the first conductive via belonging to the first memory chip, the second conductive via belonging to the second memory chip, the third conductive via belonging to the third memory chip, and the fourth conductive via belonging to the fourth memory chip are aligned along the third direction; the third conductive via belonging to the logic chip, the second conductive via belonging to the first memory chip, the first conductive via belonging to the second memory chip, the fourth conductive via belonging to the third memory chip, and the third conductive via belonging to the fourth memory chip are aligned along the third direction; the second conductive via belonging to the logic chip, the third conductive via belonging to the first memory chip, the fourth conductive via belonging to the second memory chip, the first conductive via belonging to the third memory chip, and the second conductive via belonging to the fourth memory chip are aligned along the third direction; the first conductive via belonging to the logic chip, the fourth conductive via belonging to the first memory chip, the third conductive via belonging to the second memory chip, the second conductive via belonging to the third memory chip, and the first conductive via belonging to the fourth memory chip are aligned along the third direction; wherein, the multiple conductive vias aligned along the third direction are coupled to form a signal transmission channel.

20. The chip stack structure according to claim 19, wherein, One of the fourth repair units in the logic chip, one of the first repair units in the first memory chip, one of the second repair units in the second memory chip, one of the third repair units in the third memory chip, and one of the fourth repair units in the fourth memory chip are aligned in the third direction and synchronously perform a conductive via switching operation; One of the third repair units in the logic chip, one of the second repair units in the first memory chip, one of the first repair units in the second memory chip, one of the fourth repair units in the third memory chip, and one of the third repair units in the fourth memory chip are aligned in the third direction and synchronously perform a conductive via switching operation; One of the second repair units in the logic chip, one of the third repair units in the first memory chip, one of the fourth repair units in the second memory chip, one of the first repair units in the third memory chip, and one of the second repair units in the fourth memory chip are aligned in the third direction and synchronously perform a conductive via switching operation; One of the first repair units in the logic chip, one of the fourth repair units in the first memory chip, one of the third repair units in the second memory chip, one of the second repair units in the third memory chip, and one of the first repair units in the fourth memory chip are aligned in the third direction and synchronously perform a conductive via switching operation.

21. The chip stack structure according to claim 15, wherein, the logic chip includes m channel signal regions arranged in the first direction, each memory chip has m channels arranged in the first direction, and each channel includes a first memory array region, a channel signal region, and a second memory array region sequentially distributed in the second direction; when the logic chip and the first memory chip are stacked back-to-back and the first axes of the logic chip and each memory chip extend in the first direction, the (i + 1)-th channel signal region in the logic chip is aligned with the channel signal region in the (i + 1)-th channel in the first memory chip, the channel signal region in the (i + 1)-th channel in the second memory chip, the channel signal region in the (m - i)-th channel in the third memory chip, and the channel signal region in the (m - i)-th channel in the fourth memory chip in the third direction; where i is a natural number less than m.

22. The chip stack structure according to claim 15, wherein, the logic chip includes m channel signal regions arranged in the first direction, each memory chip has m channels arranged in the first direction, and each channel includes a first memory array region, a channel signal region, and a second memory array region sequentially distributed in the second direction; When the logic chip and the first memory chip are stacked back-to-back, and the second axes of the logic chip and each memory chip extend in the first direction, the (m - i)-th channel signal region in the logic chip is aligned with the channel signal region in the (i + 1)-th channel of the first memory chip, the channel signal region in the (m - i)-th channel of the second memory chip, the channel signal region in the (m - i)-th channel of the third memory chip, and the channel signal region in the (i + 1)-th channel of the fourth memory chip in the third direction; where i is a natural number less than m.

23. The chip stacking structure according to claim 21 or 22, characterized in that, the channel signal region in each channel is divided into 2×2 signal regions distributed in an array; only for a plurality of the channel signal regions aligned in the third direction: the second signal region belonging to the logic chip, the first signal region in the first memory chip, the second signal region in the second memory chip, the third signal region in the third memory chip, and the fourth signal region in the fourth memory chip are aligned in the third direction; the first signal region belonging to the logic chip, the second signal region in the first memory chip, the first signal region in the second memory chip, the fourth signal region in the third memory chip, and the third signal region in the fourth memory chip are aligned in the third direction; the fourth signal region belonging to the logic chip, the third signal region in the first memory chip, the fourth signal region in the second memory chip, the first signal region in the third memory chip, and the second signal region in the fourth memory chip are aligned in the third direction; the third signal region belonging to the logic chip, the fourth signal region in the first memory chip, the third signal region in the second memory chip, the second signal region in the third memory chip, and the first signal region in the fourth memory chip are aligned in the third direction.

24. The chip stacking structure according to claim 23, characterized in that, each signal region includes n conductive via groups with the same distribution positions, and each conductive via group includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via; for a plurality of the signal regions aligned in the third direction: the second conductive via belonging to the logic chip, the first conductive via in the first memory chip, the second conductive via in the second memory chip, the third conductive via in the third memory chip, and the fourth conductive via in the fourth memory chip are aligned in the third direction; The first conductive vias belonging to the logic chip, the second conductive vias belonging to the first memory chip, the first conductive vias belonging to the second memory chip, the fourth conductive vias belonging to the third memory chip, and the third conductive vias belonging to the fourth memory chip are aligned along a third direction; The fourth conductive vias belonging to the logic chip, the third conductive vias belonging to the first memory chip, the fourth conductive vias belonging to the second memory chip, the first conductive vias belonging to the third memory chip, and the second conductive vias belonging to the fourth memory chip are aligned along a third direction; The third conductive vias belonging to the logic chip, the fourth conductive vias belonging to the first memory chip, the third conductive vias belonging to the second memory chip, the second conductive vias belonging to the third memory chip, and the first conductive vias belonging to the fourth memory chip are aligned along a third direction; Among them, a plurality of conductive vias aligned along the third direction are coupled to form a signal transmission channel.

25. The chip stack structure according to claim 24, wherein, One of the second repair units in the logic chip, one of the first repair units in the first memory chip, one of the second repair units in the second memory chip, one of the third repair units in the third memory chip, and one of the fourth repair units in the fourth memory chip are aligned along the third direction and synchronously perform a conductive via switching operation; One of the first repair units in the logic chip, one of the second repair units in the first memory chip, one of the first repair units in the second memory chip, one of the fourth repair units in the third memory chip, and one of the third repair units in the fourth memory chip are aligned along the third direction and synchronously perform a conductive via switching operation; One of the fourth repair units in the logic chip, one of the third repair units in the first memory chip, one of the fourth repair units in the second memory chip, one of the first repair units in the third memory chip, and one of the second repair units in the fourth memory chip are aligned along the third direction and synchronously perform a conductive via switching operation; One of the third repair units in the logic chip, one of the fourth repair units in the first memory chip, one of the third repair units in the second memory chip, one of the second repair units in the third memory chip, and one of the first repair units in the fourth memory chip are aligned along the third direction and synchronously perform a conductive via switching operation.

26. The chip stack structure according to any one of claims 15-25, wherein, For two chips connected face to face, the positions where the conductive vias in the two chips are aligned in the third direction are electrically connected through a hybrid bonding process; for two chips connected back to back or for two chips connected back to face, the positions where the conductive vias in the two chips are aligned in the third direction are electrically connected through a conductive bump bonding process; or, For two chips connected face to face or for two chips connected back to back or for two chips connected back to face, the positions where the conductive vias in the two chips are aligned in the third direction are all electrically connected through a hybrid bonding process; or, For two chips connected face to face or for two chips connected back to back or for two chips connected back to face, the positions where the conductive vias in the two chips are aligned in the third direction are all electrically connected through a conductive bump bonding process.

27. A memory, characterized in that, it includes a chip stack structure according to any one of claims 15-26.

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