Semiconductor device and manufacturing method thereof, wafer structure and electronic equipment

Abstract

The invention provides a semiconductor device, a manufacturing method thereof, a wafer structure and electronic equipment, and relates to the technical field of semiconductors. The semiconductor device includes: a first logic circuit; the interface circuit is coupled with the first logic circuit and is used for providing an external connection interface of the semiconductor device; and the interconnection circuit is coupled with the first logic circuit and is used for providing an internal expansion interface of the semiconductor device. Through the technical scheme, the development cost can be reduced while various application scenes are coped with.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and a manufacturing method thereof, a wafer structure and an electronic device. Background Art

[0002] With the explosion of information technology in human society, chips as information processing carriers have been widely used. However, the increasing variety of application scenarios has also posed challenges to chip design. How to cope with the increasing variety of application scenarios at a lower development cost has become a technical problem that needs to be solved urgently. Summary of the invention

[0003] The present application provides a semiconductor device and a manufacturing method thereof, a wafer structure and an electronic device, which can cope with a variety of application scenarios while reducing development costs.

[0004] In a first aspect, a semiconductor device is provided, comprising: a first logic circuit; an interface circuit coupled to the first logic circuit and used to provide an external connection interface for the semiconductor device; and an interconnection circuit coupled to the first logic circuit and used to provide an internal expansion interface for the semiconductor device.

[0005] Through the design of the above semiconductor device, interconnection design can be performed before wafer production according to the computing power or specification requirements of different application scenarios. For example, when the computing power or specification requirements are small, the internal expansion of the semiconductor device can be omitted to obtain a chip structure including one logic circuit. For another example, when the computing power or specification requirements are large, the internal expansion of the semiconductor device can be performed to obtain a chip structure including multiple logic circuits. In this way, a chip can be reused from architecture design to wafer production, and even its verification process can be reused, which is suitable for the development of chips with multiple specifications or computing power, thereby meeting the needs of different application scenarios or businesses at a lower chip development cost. For example, in the engineering change instruction stage after the chip development tape-out, the interconnection scheme can be determined, the mask design can be performed, and the design of some metal layers can be adjusted to obtain a chip structure including one or more logic circuits, and when multiple logic circuits are included, the interconnection circuit is used to realize the connection between different logic circuits, so as to achieve the effect of producing chips with different computing power or specifications in one tape-out, so that a chip architecture design can meet the needs of multiple scenarios at the same time. Compared with the traditional method of developing independent chips for each scenario, the technical solution of the embodiments of the present application can reduce the number of architecture designs and even the number of verifications and tape-outs, thereby saving time, manpower, materials or design costs in the chip development process, reducing R&D risks and shortening the development cycle.

[0006] In certain implementations of the first aspect, the state of the interconnect circuit includes a connected state or a disconnected state.

[0007] With this technical solution, the interconnection circuit can support connection or non - connection with other logic circuits. In the non - connection state, the semiconductor device can include a single logic circuit to implement corresponding functions, while in the connection state, the semiconductor device can include multiple logic circuits to implement corresponding functions. The interconnection circuit can form semiconductor devices with different specifications in different states, so as to be applied to different scenarios and meet the requirements of different scenarios.

[0008] In some implementations of the first aspect, the interconnection circuit is asynchronous with the clock of the first logic circuit, which can prevent the influence of the interconnection circuit on the logic circuit.

[0009] In some implementations of the first aspect, the semiconductor device includes multiple interconnection circuits, and the multiple interconnection circuits include a first interconnection circuit and a second interconnection circuit.

[0010] With this technical solution, multiple interconnection circuits in the semiconductor device can provide more internal expansion interfaces for the semiconductor device, which is beneficial to more flexible expansion of the number of logic circuits in the semiconductor device. Thus, it is beneficial to make the architecture design in the chip development process applicable to more specifications or computing power scenarios, so that the semiconductor devices obtained from one design can be applicable to more application scenarios. In addition, the multiple interconnection circuits can be located at different physical positions in the semiconductor device. When the interconnection circuit is set at the edge position, it is beneficial to the connection wiring inside the circuit unit, reduces the wiring complexity, and reduces signal interference.

[0011] In some implementations of the first aspect, the first interconnection circuit and the second interconnection circuit are in a non - connection state.

[0012] In some implementations of the first aspect, the first interconnection circuit is used to provide internal expansion in the first direction of the semiconductor device; the second interconnection circuit is used to provide internal expansion in the second direction of the semiconductor device.

[0013] With this technical solution, multiple interconnection circuits in the semiconductor device can provide expansion interfaces in different directions, so as to facilitate the interconnection of logic circuits in the semiconductor device with other logic circuits in different directions, can more flexibly expand the number of logic circuits in the semiconductor device, and is beneficial to making the semiconductor device applicable to more application scenarios.

[0014] In some implementations of the first aspect, the first interconnection circuit is in a non - connection state, the second interconnection circuit is in a connection state, and the semiconductor device further includes a second logic circuit. The multiple interconnection circuits further include a third interconnection circuit, the third interconnection circuit is coupled to the second logic circuit and is in a connection state; the first logic circuit is connected to the second logic circuit through the second interconnection circuit and the third interconnection circuit.

[0015] With this technical solution, a semiconductor device can include multiple logic circuits. The arrangement of the multiple logic circuits can improve the specifications or computing power of the semiconductor device, meeting the requirements of scenarios with higher specifications and computing power.

[0016] In some implementations of the first aspect, the multiple interconnect circuits further include a fourth interconnect circuit, which is coupled to the first logic circuit.

[0017] In some implementations of the first aspect, the fourth interconnect circuit is in a non-connected state; or, the fourth interconnect circuit is in a connected state, and the semiconductor device further includes a third logic circuit. The multiple interconnect circuits further include a fifth interconnect circuit, which is coupled to the third logic circuit and is in a connected state; the first logic circuit is connected to the third logic circuit through the fourth interconnect circuit and the fifth interconnect circuit.

[0018] With this technical solution, a semiconductor device can include a relatively large number of logic circuits. The arrangement of the multiple logic circuits can further improve the specifications or computing power of the semiconductor device to meet the requirements of scenarios with higher specifications and computing power.

[0019] In some implementations of the first aspect, the semiconductor device further includes: a substrate, on which the first logic circuit, the interface circuit, and the interconnect circuit are disposed, and the interface circuit and the interconnect circuit are located at at least one edge of the substrate.

[0020] In this technical solution, disposing the interface circuit and the interconnect circuit at the edge of the substrate is beneficial to the wiring connection between the interface circuit and the interconnect circuit and the logic circuit, reducing the wiring complexity and signal interference, improving the performance of the semiconductor structure and the semiconductor device, and enhancing the reliability of the semiconductor device.

[0021] In some implementations of the first aspect, the substrate includes a first edge, a second edge, a third edge, and a fourth edge. The third edge is opposite to the first edge, the fourth edge is opposite to the second edge, and an interface circuit is disposed at the first edge, and at least one of the first edge, the second edge, the third edge, and the fourth edge is provided with an interconnect circuit.

[0022] In a second aspect, a wafer structure is provided, including: a wafer substrate; a semiconductor structure formed on the wafer substrate, the semiconductor structure including a logic circuit, an interface circuit, and an interconnect circuit. The interface circuit is coupled to the logic circuit and is used to provide an external connection interface for the semiconductor structure; the interconnect circuit is coupled to the logic circuit and is used to provide an internal expansion interface for the semiconductor structure.

[0023] For the description of the beneficial effects of the second aspect, reference can be made to the description of the beneficial effects of the first aspect, which will not be elaborated here.

[0024] In certain implementations of the second aspect, the wafer structure includes a plurality of semiconductor structures, the plurality of semiconductor structures including a first semiconductor structure and a second semiconductor structure; the first semiconductor structure includes a first edge, a second edge, a third edge, and a fourth edge, the first edge being opposite to the third edge, the second edge and the fourth edge being opposite to each other, the first edge and the third edge intersecting with the second edge and intersecting with the fourth edge; the second semiconductor structure includes a fifth edge, a sixth edge, a seventh edge, and an eighth edge, the fifth edge being opposite to the seventh edge, the sixth edge and the eighth edge being opposite to each other, the fifth edge and the seventh edge intersecting with the sixth edge and intersecting with the eighth edge; an interface circuit is formed at the first edge and the fifth edge; the third edge and the seventh edge are adjacent, and an interconnect circuit is formed at the third edge and the seventh edge.

[0025] In certain implementations of the second aspect, an interconnect circuit is formed at the second edge and the fourth edge; and / or, an interconnect circuit is formed at the sixth edge and the eighth edge.

[0026] In a third aspect, a method for manufacturing a semiconductor device is provided, including: forming the wafer structure in the second aspect or any implementation of the second aspect; determining a partitioning manner of the wafer structure; and cutting the wafer structure according to the partitioning manner to obtain a semiconductor device, the semiconductor device including one or more logic circuits.

[0027] In certain implementations of the third aspect, when the semiconductor device includes a plurality of logic circuits, the method further includes: forming a connection structure for connecting the interconnect circuits of the plurality of logic circuits.

[0028] In a fourth aspect, an electronic device is provided, including: the semiconductor device in the first aspect or any possible implementation of the first aspect. Description of the Drawings

[0029] Figure 1 A schematic diagram of a wafer structure according to an exemplary embodiment of the present application is shown.

[0030] Figure 2 A schematic diagram of a semiconductor device according to an exemplary embodiment of the present application is shown.

[0031] Figure 3 A schematic diagram of another semiconductor device according to an exemplary embodiment of the present application is shown.

[0032] Figure 4 A schematic diagram of a semiconductor structure according to an exemplary embodiment of the present application is shown.

[0033] Figure 5 A schematic diagram of another semiconductor structure according to an exemplary embodiment of the present application is shown.

[0034] Figure 6 The figure shows a schematic diagram of another semiconductor device according to an exemplary embodiment of the present application.

[0035] Figure 7 The figure shows a schematic diagram of another semiconductor device according to an exemplary embodiment of the present application.

[0036] Figure 8 The figure shows a schematic diagram of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application.

[0037] Figure 9 The figure shows a schematic diagram of a chip development process according to an exemplary embodiment of the present application.

[0038] Figure 10 The figure shows a schematic diagram of another chip development process according to an exemplary embodiment of the present application.

[0039] Figure 11 The figure shows a schematic diagram of the division of a wafer structure according to an exemplary embodiment of the present application.

[0040] Figure 12 The figure shows a schematic diagram of the division of another wafer structure according to an exemplary embodiment of the present application.

[0041] Figure 13 The figure shows a schematic diagram of the division of another wafer structure according to an exemplary embodiment of the present application.

[0042] Figure 14 The figure shows a schematic diagram of the division of another wafer structure according to an exemplary embodiment of the present application.

[0043] Figure 15 The figure shows a schematic diagram of an electronic device according to an exemplary embodiment of the present application. Detailed implementation manners

[0044] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings.

[0045] To make the drawings concise, only the parts related to the corresponding embodiments are schematically shown in the drawings of the embodiments of the present application, and they do not represent the actual structure of the product. In addition, to make the drawings concise and easy to understand, in some drawings, only some structures or components are schematically shown, and there may actually be more or fewer identical or similar structures or components.

[0046] The business scenarios described in the embodiments of the present application are used to exemplarily illustrate the technical solutions in the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those of ordinary skill in the art know that with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0047] In this application, unless otherwise clearly specified or limited, "connection" includes direct connection or indirect connection between objects: the objects to be connected can be directly connected through a medium (such as a wire, a trace, etc.), or can be indirectly connected through other components, or can be internally connected. "Coupling" includes signal connection between objects, which can be achieved directly through a medium (such as a wire, a trace, etc.), or can be achieved through other components. "Grounding" includes direct grounding or indirect grounding. Indirect grounding includes, for example, grounding through other components.

[0048] In this application, unless otherwise clearly specified or limited, ordinal numbers, such as "first", "second", etc., are only used to distinguish the described objects, and cannot be understood as indicating or implying the relative importance or order between the described objects. In addition, ordinal numbers do not represent the quantity of the described objects. "Multiple" includes two or more, and other quantifiers are similar. "Or", "and / or" are used to describe the relationship between objects, which means non-exclusive inclusion. For example, "A and / or B", "A or B" can include: "A alone", "B alone", or "A and B". Again, "A, B and / or C", "A, B or C" can include: "A alone", "B alone", "C alone", "A and B", "A and C", "B and C", or "A, B and C". In addition, " / " in this application is used to represent the "or" relationship between the front and back objects. The meaning of "one or more of A and B" or "at least one of A and B" in this application is the same as the meaning of the above "A and / or B", "A or B". The meaning of "one or more of A, B and C" or "at least one of A, B and C" is the same as the meaning of the above "A, B and / or C", "A, B or C".

[0049] In semiconductor technology, one or more semiconductor components (such as transistors, resistors, capacitors, or inductors, etc.) can be integrated on one or more semiconductor wafers or dielectric substrates by using semiconductor manufacturing processes to form a semiconductor device including an integrated circuit (IC). This semiconductor device can be called a chip. A chip is the core of an electronic device and is widely used in various fields such as computers, communications, consumer electronics, automobiles, industries, or medical fields.

[0050] In different application scenarios, the specifications or computing power requirements of a chip vary greatly. In the traditional chip development process, chips are developed independently for different application scenarios, and the complete chip development process is used to adapt to the requirements of various application scenarios. However, the chip development process is a complex process, involving multiple stages from requirement confirmation to final mass production. Developing chips independently for different application scenarios will result in a relatively high chip development cost, such as high time cost, labor cost, material cost, or design cost, etc.

[0051] In view of this, an embodiment of the present application provides a semiconductor device, which can solve the problem of relatively high chip development cost described above. The following is a description with reference to the accompanying drawings.

[0052] Figure 1 FIG. shows a schematic diagram of a wafer structure according to an exemplary embodiment of the present application. As Figure 1 shown, the wafer structure 100 may include a wafer substrate 110 and a semiconductor structure 120, and the semiconductor structure 120 is formed on the wafer substrate 110. As Figure 1 shown, the semiconductor structure 120 includes: a logic circuit 121, an interface circuit 122, and an interconnect circuit 123. Among them, the interface circuit 122 is coupled to the logic circuit 121 and is used to provide an external connection interface for the semiconductor structure 120, and the interconnect circuit 123 is coupled to the logic circuit 121 and is used to provide an internal expansion interface for the semiconductor structure 120.

[0053] The semiconductor structure 120 can also be referred to as a circuit unit (or logic unit). The logic circuit 121 included in the circuit unit (cell) can implement one or more logic operations through signal processing. The signal can include a digital signal, an analog signal, or a combination of a digital signal and an analog signal. The embodiments of the present application do not limit the type or quantity of the logic operations of the logic circuit. Different logic circuit designs can be adopted in different application scenarios, and the logic circuit can include a digital circuit, an analog circuit, or a hybrid circuit of a digital circuit and an analog circuit. In addition, the logic circuits of different circuit units can be the same or different, which is not limited in the present application and different designs can be adopted in different application scenarios. The interface circuit 122 is used to provide an external connection interface for the circuit unit. After the wafer is produced, the above wafer structure 100 can be obtained. By dicing the wafer, a bare die can be obtained. The bare die can be packaged, and the interface circuit 122 can be connected to the pins of the packaged chip to provide an external connection interface for the chip, enabling the chip to be connected to other chips or a circuit board. The interconnection circuit 123 can provide an internal expansion interface for the circuit unit. Thus, during the chip development process, before the wafer is produced, according to the computing power or specification requirements, by adjusting the interconnection scheme, a chip structure scheme including one or more circuit units can be obtained, so that one architecture design scheme can be applied to the chip development with different specification or computing power requirements. After the wafer is produced, the wafer can be diced to obtain bare dies that meet the requirements of different application scenarios.

[0054] Through the design of the above semiconductor structure, before wafer production, interconnection design can be carried out according to the computing power or specification requirements of different application scenarios, etc. For example, in the case of relatively small computing power or specification requirements, the internal expansion of the semiconductor structure can be not carried out, and a chip structure including a single circuit unit can be obtained. For another example, in the case of relatively large computing power or specification requirements, the internal expansion of the semiconductor structure can be carried out to obtain a chip structure including multiple circuit units. In this way, from the architecture design to wafer production, and even the verification process of the chip can be reused, which is applicable to the development of chips with various specifications or computing powers, so as to meet the requirements of different application scenarios or services at a relatively low chip development cost. For example, in the engineering change order (ECO) stage after tapeout in chip development, the interconnection scheme can be determined, mask design can be carried out, and the design of some metal layers can be adjusted, so as to obtain a chip structure including one or more circuit units. When including multiple circuit units, the connection between different circuit units is realized by using the interconnection circuit, achieving the effect that different computing power or specification chips can be produced in one tapeout, so that one chip architecture design can meet the requirements of multiple scenarios at the same time. Compared with the traditional independent chip development for each scenario, the technical solution of the embodiment of the present application can reduce the number of architecture designs, and even reduce the number of verifications and tapeouts, thus saving costs such as time, manpower, materials or design in the chip development process, reducing the R & D risk and shortening the development cycle.

[0055] In the above semiconductor structure 120, one interconnection circuit can be included to achieve interconnection expansion in one direction, or multiple interconnection circuits can be included to achieve interconnection expansion in multiple directions. The number of interconnection circuits included in different semiconductor structures 120 can be the same or different, and the expansion directions can be the same or different. The embodiment of the present application also provides a semiconductor device, which can be obtained by dicing the above wafer structure. Optionally, the semiconductor device can include a chip, and the chip can include a packaged or unpackaged chip, such as a die or a die after packaging. The semiconductor device can include one semiconductor structure or can include multiple semiconductor structures. The following is described with reference to the drawings.

[0056] Figure 2 FIG. shows a schematic diagram of a semiconductor device according to an exemplary embodiment of the present application. As Figure 2 shown, the semiconductor device 200 includes a logic circuit 210, an interface circuit 220, and n interconnection circuits 230, where n is a positive integer greater than or equal to 1.

[0057] The descriptions of the logic circuit 210, the interface circuit 220, and the interconnection circuit 230 are the same as those in the above embodiments.

[0058] The present application does not limit the functions of the semiconductor device, which may have different functions according to different application scenarios or business requirements. The structure of the semiconductor device provided by the present application is also independent of the functions of the semiconductor device and may be related to the computing power or specifications of the semiconductor device. By way of example and not limitation, it is assumed that the first semiconductor device and the second semiconductor device can be obtained using the above wafer structure. The first semiconductor device is used for consumer electronics and is used to implement the inference function. The second semiconductor device is used for the server side and is used to implement the training function or to implement the inference and training functions. The second semiconductor device has a greater demand for computing power than the first semiconductor device, or the second semiconductor device has higher specifications than the first semiconductor device. The second semiconductor device may include more semiconductor structures (or circuit units) relative to the first semiconductor device. For example, the structural design of different semiconductor devices can be achieved using the ECO stage. The embodiments of the present application do not limit the implementation of the logic circuit, which can be implemented using digital circuits, can be implemented using analog circuits, or can be implemented using analog and digital circuits. The logic circuit can be implemented using the von Neumann architecture or can be implemented using the in-memory computing architecture.

[0059] The interface circuit 122 / 220 can provide an external connection interface for the semiconductor device 200, so as to realize the coupling between the semiconductor device 200 and other semiconductor devices. As an example, the interface circuit 220 can be connected to other semiconductor devices through package bonding or electrical connectors, where the electrical connectors include but are not limited to circuit board connectors such as printed circuit boards (PCBs). The present application does not limit the interface protocol type of the interface circuit 220, which can include a serial communication interface or a parallel communication interface, and can include existing interface types for data transmission or interface types for data transmission obtained with the evolution of technology. By way of example, the interface type can include but is not limited to Peripheral Component Interconnect Express (PCIe), Universal Chiplet Interconnect Express (UCIe), Mobile Industry Processor Interface (MIPI), Universal Serial Bus (USB), General-Purpose Input / Output (GPIO), Universal Asynchronous Receiver / Transmitter (UART), Inter-Integrated Circuit (I2C), Serial Peripheral Interface (SPI), or Controller Area Network (CAN), etc.

[0060] In some embodiments, the interface circuit 122 / 220 can include a connected state or a disconnected state. The semiconductor device 200 can include one or more circuit units, and one or more interface circuits 220 can be included in the circuit units; where the interface circuits can all be in the disconnected state, or some can be in the connected state, or all can be in the connected state. For example, for the case where the semiconductor device 200 includes one circuit unit, the interface circuit of this circuit unit is in the connected state. For the case where the semiconductor device 200 includes multiple circuit units, the interface circuit of one of the circuit units can be used for the external connection of the semiconductor device, and the interface circuits of other circuit units can be in the disconnected state, thus simplifying the design of the docking interface and preventing interference between more interface circuits. Alternatively, the interface circuits of some or all of the circuit units can be used for the external connection of the semiconductor device to provide flexibility in external connection.

[0061] The interconnect circuit 230, which can also be referred to as an interconnect cell, provides an internal expansion interface for the semiconductor device 200, enabling the coupling between logic circuits in the semiconductor device 200 and facilitating the expansion of the number of logic circuits within the semiconductor device 200. The structure of the interconnect circuit 123 / 230 is not limited in this application and can have the same or different structures in different application scenarios or service scenarios, as long as the structure does not affect the functional implementation of the logic circuits and can provide the coupling ability between different logic circuits. For example, the interconnect circuit 123 / 230 can include one or more functions such as buffering, conversion, or control, for buffering the data transmitted between logic circuits, or for converting the signals transmitted between logic circuits, or for controlling the collaborative work between logic circuits, etc., to achieve the efficient collaborative work between different logic circuits. As an example, the interconnect circuit 123 / 230 can include one or more semiconductor components such as transistors, resistors, capacitors, or inductors.

[0062] In some embodiments, the interconnect circuit 123 / 230 can be connected to a metal interconnect layer. The interconnect circuit 230 can provide an interface for connecting to the metal interconnect layer, and the metal interconnect layer can be fabricated through mask design.

[0063] In some embodiments, the interconnect circuit 123 / 230 is asynchronous with the clock of the logic circuit 121 / 210, that is, within the same semiconductor device or the same semiconductor structure, the logic circuit and the interconnect circuit use different clock signals. For example, the logic circuit and the interconnect circuit include sequential logic circuits, and by using different clock signals, the impact of the interconnect circuit on the logic circuit can be prevented.

[0064] In some embodiments, the interconnect circuit 123 / 230 can be in a connected state or a non-connected state. When the interconnect circuit 123 / 230 is used to couple with other logic circuits, the interconnect circuit 123 / 230 can be in a connected state; when the interconnect circuit 123 / 230 is not used to couple with other logic circuits, the interconnect circuit 123 / 230 can be in a non-connected state.

[0065] The semiconductor device 200 may include one or more circuit units, and the circuit units may include one or more interconnect circuits 230; among them, all the interconnect circuits may be in a non-connected state, or some may be in a connected state, or all may be in a connected state. For example, the semiconductor device 200 includes one circuit unit. Regardless of the number of interconnect circuits included in this circuit unit, the interconnect circuits within this circuit unit are all in a non-connected state. Another example is that the semiconductor device 200 includes multiple circuit units, and among them, the circuit unit includes at least one interconnect circuit in a connected state. Optionally, the circuit unit may also include at least one interconnect circuit in a non-connected state.

[0066] The interconnect circuit being in a connected state may mean that when the semiconductor device is powered on, the interconnect circuit can achieve one or more of the above coupling capabilities, and the semiconductor elements in the circuit can be turned on. The interconnect circuit being in a non-connected state may mean that when the semiconductor device is powered on, its above coupling capabilities are turned off, so as not to affect the operation of other circuits. For example, some semiconductor elements of the interconnect circuit are connected to a specific pin through a metal layer design. When the semiconductor device is powered on, this pin is coupled to a target voltage or current or grounded, etc., so that the semiconductor elements therein are in an off state.

[0067] Multiple interconnect circuits within the circuit unit can provide more internal expansion interfaces for the semiconductor device, which is beneficial to more flexibly expanding the number of logic circuits within the semiconductor device. Thus, it is beneficial to enable the architecture design in the chip development process to be applicable to more specifications or computing power scenarios, so that the semiconductor devices obtained from one design can be applicable to more application scenarios.

[0068] For the sake of easy understanding, Figure 3 is taken as an example for description. Figure 3 shows a schematic diagram of another semiconductor device according to an exemplary embodiment of the present application. In this semiconductor device, two interconnect circuits are shown in one circuit unit. The present application is not limited thereto and may include more interconnect circuits.

[0069] Such as Figure 3As shown, the semiconductor device 300 may include: logic circuits 311, logic circuits 312, interface circuits 321, interface circuits 322, and interconnect circuits 331 to interconnect circuits 334. Interface circuit 321, interconnect circuit 331, and interconnect circuit 332 are coupled to logic circuit 311. Interface circuit 322, interconnect circuit 333, and interconnect circuit 334 are coupled to logic circuit 312. Interconnect circuit 332 and interconnect circuit 333 are in a connected state, and logic circuit 311 is connected to logic circuit 312 through interconnect circuit 332 and interconnect circuit 333. Optionally, interconnect circuit 332 may be in a connected state to couple to the interconnect circuits of other logic circuits, or interconnect circuit 332 may be in a non-connected state. Interconnect circuit 334 may be in a connected state to couple to the interconnect circuits of other logic circuits, or interconnect circuit 334 may be in a non-connected state. One of interface circuit 321 or interface circuit 322 may be in a connected state, or both interface circuit 321 and interface circuit 322 may be in a connected state. When the semiconductor device 300 further includes other circuit units, the interface circuits of the other circuit units may be in a connected state, and both interface circuit 321 and interface circuit 322 may be in a non-connected state.

[0070] In some embodiments, multiple interconnect circuits may be located at different physical positions in a semiconductor structure or a semiconductor device. When the interconnect circuits are disposed at edge positions, it is beneficial for the internal connection wiring of circuit units, reduces the wiring complexity, and reduces signal interference, and also facilitates establishing connections between the interconnect circuits.

[0071] For example, Figure 4 shows a schematic diagram of a semiconductor structure according to an exemplary embodiment of the present application. The semiconductor device may include this semiconductor structure. As Figure 4 shown, the semiconductor structure 400 may include a logic circuit 411, an interface circuit 421, an interconnect circuit 431, and an interconnect circuit 432. Interface circuit 421, interconnect circuit 431, and interconnect circuit 432 are coupled to logic circuit 411. Interconnect circuit 431 is used to provide internal expansion in the first direction of the semiconductor structure 400, and interconnect circuit 432 is used to provide internal expansion in the second direction of the semiconductor structure 400, and the first direction and the second direction are different.

[0072] As an example, the semiconductor structure 400 may further include a substrate 401. The logic circuit 411, the interface circuit 421, the interconnect circuit 431, and the interconnect circuit 432 may be formed on the substrate 401. Among them, the interconnect circuit 431 may be located in a first direction of the logic circuit 411, and the interconnect circuit 432 may be located in a second direction of the logic circuit 411. In some examples, there is a certain angle between the first direction and the second direction, and the angle may include an acute angle, a right angle, an obtuse angle, or a flat angle. For example, the first direction and the second direction may be perpendicular to each other; for another example, the first direction and the second direction may be opposite, etc.

[0073] Through the technical solution of the embodiments of the present application, multiple interconnect circuits in a semiconductor device can provide expansion interfaces in different directions, so as to facilitate the interconnection of logic circuits in different directions in the semiconductor device with other logic circuits, and can more flexibly expand the number of logic circuits in the semiconductor device, which is beneficial to enabling the semiconductor device to be applicable to more application scenarios.

[0074] Figure 5 FIG. shows a schematic diagram of another semiconductor structure according to an exemplary embodiment of the present application.

[0075] As Figure 5 shown, the semiconductor structure 500 may include: a logic circuit 511, an interface circuit 521, and multiple interconnect circuits (for example, Figure 5 interconnect circuits 531, 532, and 533 are schematically shown in ), the interface circuit 521 and the multiple interconnect circuits are coupled to the logic circuit 511. The semiconductor structure 500 may further include a substrate 501, and the logic circuit 511, the interface circuit 521, and the interconnect circuits may be formed on the substrate 501. Optionally, the interface circuit 521 and the interconnect circuits may be located at at least one edge of the substrate 501. For example, one interconnect circuit may be provided on one edge, or more than one interconnect circuit may be provided on one edge, so that there are more expansion possibilities in the direction where the edge is located. The edge where the interface circuit 521 is located may not be provided with interconnect circuits to reduce the routing complexity.

[0076] The interconnect circuit 531 is used to provide inboard expansion in the first direction of the semiconductor structure 500, the interconnect circuit 532 is used to provide inboard expansion in the second direction of the semiconductor structure 500, and the interconnect circuit 533 is used to provide inboard expansion in the third direction of the semiconductor structure 500, and the first direction, the second direction, and the third direction are different. The description of the different directions may refer to the above description of the different first direction and second direction.

[0077] As an example, Figure 5The substrate 501 shown in the figure may include four edges. Among them, the first edge and the third edge are opposite, the second edge and the fourth edge are opposite. An interface circuit 521 is provided at the first edge, and an interconnection circuit is provided at each of the second edge, the third edge, and the fourth edge. As another example, in addition to the interface circuit 521, an interconnection circuit may further be provided at the first edge. Optionally, an interconnection circuit is provided at at least one of the first edge, the second edge, the third edge, and the fourth edge. Separating the interconnection circuit and the interface circuit and arranging them on different edges is beneficial to reducing the size of the circuit unit.

[0078] Optionally, in addition to being located at the edge of the substrate 501, the interface circuit 521 and the interconnection circuit may also be located in other regions of the substrate 501, which may also be referred to as non-edge regions, for example, the middle region. For example, at least one of the interface circuit 521 and the interconnection circuit is located in the middle region of the substrate 501. For another example, both the interface circuit 521 and the interconnection circuit are located in the non-edge region of the substrate 501.

[0079] In the embodiments of the present application, arranging the interface circuit and the interconnection circuit at the edge of the substrate is beneficial to the wiring connection between the interface circuit and the interconnection circuit and the logic circuit, reducing the wiring complexity and signal interference, improving the performance of the semiconductor structure and the semiconductor device, and enhancing the reliability of the semiconductor device. In addition, arranging the interconnection circuit at the edge of the substrate facilitates the establishment of connections between the interconnection circuits.

[0080] The number of interconnection circuits in the semiconductor structure in the schematic diagrams of the above embodiments is only an example. In some alternative embodiments, the semiconductor structure may further include more or fewer interconnection circuits, and the embodiments of the present application do not make specific limitations on its number. In addition, in the above embodiments, only one interface circuit is schematically shown. In some alternative embodiments, the semiconductor structure may further include two or more interface circuits, and the embodiments of the present application do not make specific limitations on its number either.

[0081] In addition, the embodiments of the present application do not limit the number of semiconductor structures (circuit units) included in the semiconductor device. The semiconductor device may include one semiconductor structure, or the semiconductor device may include multiple semiconductor structures. For example, Figure 6 shows a schematic diagram of another semiconductor device according to an exemplary embodiment of the present application.

[0082] As Figure 6As shown, the semiconductor device 600 may include: a logic circuit 611, a logic circuit 612, an interface circuit 621, an interconnection circuit 631, and an interconnection circuit 632. Among them, the logic circuit 611 is coupled to the interface circuit 621 and the interconnection circuit 631, and the logic circuit 612 is coupled to the interconnection circuit 632. For the convenience of distinction, the logic circuit 611 and the logic circuit 612 may be referred to as the first logic circuit and the second logic circuit, and the interconnection circuit 631 and the interconnection circuit 632 may be referred to as the first interconnection circuit and the second interconnection circuit.

[0083] In the semiconductor device 600, the interconnection circuit 631 and the interconnection circuit 632 may be in a connected state, and the two interconnection circuits are connected to each other. The logic circuit 611 can be connected to the logic circuit 612 through the two interconnection circuits. Through the technical solution of this embodiment, the semiconductor device 600 can include multiple logic circuits, and the setting of the multiple logic circuits can improve the specifications or computing power of the semiconductor device 600, meeting the requirements of scenarios with higher specifications and computing power.

[0084] Optionally, as shown in Figure 6 In the circuit unit 601 where the logic circuit 611 is located, in addition to including the interconnection circuit 631, other interconnection circuits may also be included, such as the interconnection circuits 633 and 634 shown in the figure. The other interconnection circuits in the circuit unit 601 except the interconnection circuit 631 may be in a non-connected state. In addition, in the circuit unit 602 where the logic circuit 612 is located, in addition to including the interconnection circuit 632, other interconnection circuits may also be included, such as the interconnection circuits 635 and 636 shown in the figure. The other interconnection circuits in the circuit unit 602 except the interconnection circuit 632 may be in a non-connected state.

[0085] Optionally, as shown in Figure 6 The semiconductor device 600 may further include an interface circuit 622, and the interface circuit 622 is coupled to the logic circuit 612. At least one of the interface circuit 622 and the interface circuit 621 can be used to implement the external connection of the semiconductor device 600. In some embodiments, one of the interface circuit 622 and the interface circuit 621 is used to implement the external connection of the semiconductor device 600, and the other is in a non-connected state.

[0086] During the manufacturing process of the semiconductor device 600, the circuit unit 601 and the circuit unit 602 may be arranged adjacent to each other on the wafer, so as to conveniently connect the interconnection circuits of the two circuit units through interconnection traces. Or, in other alternative embodiments, the circuit unit 601 and the circuit unit 602 in the semiconductor device 600 may be arranged non-adjacent to each other.

[0087] The functions or circuit structures of the logic circuits in circuit unit 601 and circuit unit 602 may be the same or different. The physical locations of the interface circuits in circuit unit 601 and circuit unit 602 may be the same or different. The circuit structures of the interface circuits in circuit unit 601 and circuit unit 602 may be the same or different. The number and / or physical locations of the interconnection circuits in circuit unit 601 and circuit unit 602 may be the same or different. The structures of the interconnection circuits in circuit unit 601 and circuit unit 602 may be the same or different. The embodiments of the present application do not specifically limit the number and physical locations of the interconnection circuits and interface circuits in semiconductor device 600.

[0088] Figure 7 FIG. shows a schematic diagram of another semiconductor device according to an exemplary embodiment of the present application.

[0089] As Figure 7 shown, semiconductor device 700 may include: logic circuit 711, logic circuit 712, and logic circuit 713. Logic circuit 711 is coupled to interconnection circuit 731 and interconnection circuit 732, logic circuit 712 is coupled to interconnection circuit 734, and logic circuit 713 is coupled to interconnection circuit 738. Circuit unit 701 includes logic circuit 711 and the interconnection circuit coupled thereto; circuit unit 702 includes logic circuit 712 and the interconnection circuit coupled thereto; circuit unit 703 includes logic circuit 713 and the interconnection circuit coupled thereto.

[0090] In the embodiments of the present application, interconnection circuit 731 coupled to logic circuit 711 and interconnection circuit 734 coupled to logic circuit 712 may be in a connected state, and the interconnection circuit 731 and interconnection circuit 734 are connected to each other to achieve the connection between logic circuit 711 and logic circuit 712. Additionally, interconnection circuit 732 coupled to logic circuit 711 and interconnection circuit 738 coupled to logic circuit 713 may also be in a connected state, and the interconnection circuit 732 and interconnection circuit 738 are connected to each other to achieve the connection between logic circuit 711 and logic circuit 713.

[0091] Through the technical solution of this embodiment, flexibility for logic circuit expansion can be provided in more than one direction, such that more logic circuits can be included in semiconductor device 700. The setting of the logic circuits in more directions can further enhance the flexibility of the specifications or computing power of the semiconductor device to meet the requirements of scenarios with more demanding specifications and computing power.

[0092] Optionally, in circuit unit 701 where logic circuit 711 is located, interconnect circuit 731 is located at the edge of circuit unit 701 close to circuit unit 702 where logic circuit 712 is located. Similarly, in circuit unit 702, interconnect circuit 734 is located at the edge of circuit unit 702 close to circuit unit 701. Additionally, in circuit unit 701, interconnect circuit 732 is located at the edge of circuit unit 701 close to circuit unit 703 where logic circuit 713 is located. In circuit unit 703, interconnect circuit 738 is located at the edge of circuit unit 703 close to circuit unit 701.

[0093] Optionally, continuing to refer to Figure 7 As shown, logic circuit 712 can be further coupled to interconnect circuit 735, and logic circuit 713 can be further coupled to interconnect circuit 737. Through interconnect circuit 735 and interconnect circuit 737, it is beneficial to realize the further connection of logic circuit 712 and logic circuit 713 to other logic circuits. For example, logic circuit 712 and logic circuit 713 can be connected to logic circuit 714. Among them, logic circuit 714 is coupled to interconnect circuit 7310 and interconnect circuit 7311, and these two interconnect circuits are respectively connected to interconnect circuit 735 and interconnect circuit 737. In this embodiment, semiconductor device 700 can include multiple logic circuits, and the logic circuits can be coupled to multiple interconnect circuits, thereby realizing a more flexible extended connection method between the logic circuits.

[0094] Optionally, in Figure 7 In semiconductor device 700 shown, the logic circuits can also be further coupled to interface circuits. For example, logic circuits 711 to 714 shown in the figure are respectively coupled to interface circuits 721 to 724. In some examples, interface circuits 721 to 724 can be located at at least one edge of semiconductor device 700, so as to facilitate the external connection of semiconductor device 700.

[0095] Additionally, in some embodiments, in addition to the interconnect circuits in the connected state described above that are coupled to the logic circuits, the interconnect circuits can further include interconnect circuits in a non-connected state. For example, in Figure 7 In the example shown, logic circuit 711 is also coupled to interconnect circuit 733, logic circuit 712 is also coupled to interconnect circuit 736, logic circuit 713 is also coupled to interconnect circuit 739, and logic circuit 714 is also coupled to interconnect circuit 7312. Interconnect circuits 733, 736, 739, and 7312 are in a non-connected state. Optionally, these multiple interconnect circuits in the non-connected state can also be located at at least one edge of semiconductor device 700.

[0096] Optionally, based on Figure 7In the illustrated embodiment, for any one or more of the multiple interconnected circuits in the non-connected state described above, one or more of these interconnected circuits can also be in the connected state. In this case, the one or more interconnected circuits can be further connected to a logic circuit, thereby further expanding the number of logic circuits in the semiconductor device.

[0097] As described above in conjunction with Figures 1 to 7 the related embodiments of the semiconductor structure and the semiconductor device provided in the present application have been described. Below, in conjunction with Figures 8 to 10 this, embodiments of the manufacturing method and design process of the semiconductor device provided in the present application will be described. In the following method embodiments, the related descriptions of the semiconductor structure and the semiconductor device can be referred to the above description. For the sake of brevity, they will not be elaborated too much below.

[0098] Figure 8 FIG. shows a schematic diagram of a manufacturing method of a semiconductor device according to an exemplary embodiment of the present application.

[0099] As Figure 8 shown, the manufacturing method 800 of the semiconductor device may include the following steps.

[0100] S810: Form a wafer structure.

[0101] S820: Determine the partitioning method of the semiconductor device within the wafer structure. The partitioned semiconductor device includes one or more logic circuits.

[0102] S830: Cut the wafer structure according to the partitioning method to obtain the semiconductor device.

[0103] In the embodiment of the present application, the wafer structure can refer to Figure 1 the related solution of the wafer structure 100 shown. The wafer structure includes a wafer substrate and a plurality of semiconductor structures formed on the wafer substrate. The semiconductor structures may include logic circuits, interconnected circuits, and interface circuits.

[0104] According to the application requirements of the semiconductor device to be manufactured, the number of logic circuits in the semiconductor device can be determined. In the case where the semiconductor device includes multiple logic circuits, the interconnection method between the multiple logic circuits can be further determined. Based on this interconnection method, a connection structure can be further formed on the wafer structure. The connection structure is used to connect the interconnected circuits of the multiple logic circuits. Optionally, the connection structure may include at least one metal interconnection layer formed on the wafer substrate. The at least one metal interconnection layer can be formed on the wafer substrate through semiconductor manufacturing processes. The metal interconnection layer may include metal structures connecting the interconnected circuits. The metal interconnection layer may also include metal structures with other connection functions.

[0105] Based on the interconnection method between multiple logic circuits in a semiconductor device, the division method of the wafer structure can be determined, and according to this division method, the wafer structure is cut and divided to obtain a semiconductor device, which may include one or more semiconductor structures (circuit units).

[0106] Through the technical solution of the embodiments of the present application, during the manufacturing process of a semiconductor device, interconnection design can be performed according to the computing power or specification requirements of different application scenarios, etc., before cutting the wafer structure. For example, during the engineering change order (ECO) stage after tapeout in chip development, the interconnection scheme can be determined, mask design can be carried out, and the design of some metal layers can be adjusted, so as to obtain a chip structure including one or more circuit units. When including multiple circuit units, the interconnection circuit is used to realize the connection between different circuit units, achieving the effect that different chips with different computing powers or specifications can be produced in one tapeout, so that one chip architecture design can meet the requirements of multiple scenarios at the same time. Compared with the traditional independent chip development for each scenario, the technical solution of the embodiments of the present application can reduce the number of architecture designs, and even reduce the number of verifications and tapeouts, thereby saving costs such as time, manpower, materials or design in the chip development process, reducing the R & D risk and shortening the development cycle.

[0107] Figure 9 shows a schematic diagram of a chip development process according to an exemplary embodiment of the present application. As Figure 9 shown, in this chip development process, for different application scenarios of the chip (such as application scenario 1 and application scenario 2 shown in the figure), based on different application scenario requirements, a variable specification chip architecture can be designed in the architecture design stage. In subsequent stages, that is, in the chip development, tapeout, ECO, wafer production, and dicing and packaging stages, different chip development designs can be carried out for different application scenarios. In this embodiment, different chip versions can be derived from one chip architecture and designed and manufactured respectively, and used for different product lines. This method will save a certain amount of chip design manpower and simplify software development and maintenance.

[0108] Figure 10 shows a schematic diagram of another chip development process according to an exemplary embodiment of the present application. As Figure 10As shown, in this chip development process, first, the functions of the chip can be determined according to the requirements of different application scenarios. In the architecture design stage, the chip architecture can be designed based on the functions of the chip. For example, it can include the structural design of the logic circuit, the interconnect circuit, and the interface circuit in the chip. However, in this architecture design stage, the connection forms of the interconnect circuits in the logic circuit of the chip are not determined. Then, the development of the chip is executed to develop and verify the functions of the logic circuit, the interconnect circuit, and the interface circuit. In the chip tapeout stage, the design data of the chip is obtained. This design data is used to configure production equipment, set masks, etc., so that the produced chip meets the design requirements. At this time, the design data in this stage includes the data of the masks that can fabricate other layers except for several metal interconnect layers. Further, the different interconnect methods of the logic circuits in the chip can be determined according to the requirements of different application scenarios, and implemented by adjusting several metal interconnect layers in the chip ECO stage. For example, the masks of several metal interconnect layers can be fabricated according to the determined interconnect method in the ECO stage. In the wafer production stage, wafers with different interconnect forms can be produced according to the masks of other layers except for several metal interconnect layers determined by tapeout and the masks of metal interconnect layers determined by ECO. Then, according to the interconnect methods corresponding to different application scenarios, the wafer structure can be diced and packaged in different ways, thereby producing different types of chips.

[0109] In the above design process, the masks of several metal interconnect layers can be determined and fabricated in the ECO stage. The masks of several metal interconnect layers can be flexibly adjusted according to different application scenarios, thereby producing wafers with different interconnect forms and chips. This method can reduce at least one design or verification process from architecture design to tapeout, so as to obtain a chip design applicable to multiple scenarios at a reduced chip development cost, meet the requirements of chip manufacturing in different scenarios, and can greatly reduce the manufacturing cost and R & D cycle of the chip.

[0110] In other embodiments, in the chip tapeout stage, the design data of the chip is obtained. This design data is used to configure production equipment, set masks, etc., so that the produced chip meets the design requirements. At this time, the design data in this stage includes the data of some or all masks. For example, it includes the data of the masks that can fabricate several metal interconnect layers. During or after the chip tapeout stage, if the requirements of the application scenario change, the design data can be adjusted through the chip ECO stage. For example, the different interconnect methods of the logic circuits in the chip can be modified according to the requirements of the new application scenario, and implemented by adjusting several metal interconnect layers in the chip ECO stage. For example, the masks of several metal interconnect layers can be fabricated according to the modified interconnect method in the ECO stage. In this way, only the masks of the fabricated several metal interconnect layers need to be modified, reducing the cost brought by the change of requirements.

[0111] In the above method embodiments, the magnitudes of the serial numbers of the respective processes do not imply the order of execution. The order of execution of the respective processes should be determined according to their functions and internal logic, and should not impose any limitation on the implementation process of the embodiments of the present application.

[0112] Next, in conjunction with Figures 11 to 14 , several partitioning methods of the wafer structure provided by the present application and the structures of the corresponding semiconductor devices will be described.

[0113] Figure 11 FIG. shows a schematic diagram of a partitioning of a wafer structure according to an exemplary embodiment of the present application.

[0114] As Figure 11 shown, the wafer structure 1100 may include a wafer substrate 1110, a semiconductor structure 1120, and a semiconductor structure 1130. Among them, the semiconductor structure 1120 includes a first edge, a second edge, a third edge, and a fourth edge. The first edge is opposite to the third edge, the second edge and the fourth edge are opposite to each other, and the first edge and the third edge intersect with the second edge and also intersect with the fourth edge. The semiconductor structure 1130 includes a fifth edge, a sixth edge, a seventh edge, and an eighth edge. The fifth edge is opposite to the seventh edge, the sixth edge and the eighth edge are opposite to each other, and the fifth edge and the seventh edge intersect with the sixth edge and also intersect with the eighth edge. Optionally, as Figure 11 shown, the semiconductor structure 1120 and the semiconductor structure 1130 include, but are not limited to, a rectangular structure, and may also be a square structure, a parallelogram structure, or other polygon structures.

[0115] Optionally, interconnection circuits may be formed on two adjacent edges of the semiconductor structure 1120 and the semiconductor structure 1130. As an example, the third edge in the semiconductor structure 1120 is adjacent to the seventh edge in the semiconductor structure 1130, and an interconnection circuit may be provided on the third edge and the seventh edge. In some examples, the third edge and the seventh edge may be adjacent in a certain direction, and this direction may be perpendicular to the third edge and / or the seventh edge in the semiconductor structure 1120.

[0116] Optionally, interface circuits may be formed on two edges of the semiconductor structure 1120 and the semiconductor structure 1130 that are far from each other. As an example, the first edge opposite to the third edge in the semiconductor structure 1120 and the fifth edge opposite to the seventh edge in the semiconductor structure 1130 are far from each other, and an interface circuit may be provided on the first edge and the fifth edge.

[0117] In some embodiments, in addition to interface circuits and interconnection circuits being provided at opposite third and first edges, the semiconductor structure 1120 may further have circuits provided at opposite second and fourth edges. For example, interconnection circuits may be provided at both the second and fourth edges. In addition to interface circuits and interconnection circuits being provided at opposite seventh and fifth edges, the semiconductor structure 1130 may further have interconnection circuits provided at opposite sixth and eighth edges.

[0118] Through the technical solution of this embodiment, interface circuits or interconnection circuits can be provided at multiple edges of the semiconductor structure to achieve expansion of the semiconductor structure in multiple directions, thereby enabling a wafer structure and a semiconductor device with various different interconnection methods to be implemented more flexibly.

[0119] Optionally, the semiconductor structure 1120 and the semiconductor structure 1130 may have one or more circuits provided at the same edge. For example, the semiconductor structure 1120 may have both an interface circuit and an interconnection circuit provided at the first edge simultaneously. As another example, the semiconductor structure 1120 may have multiple interconnection circuits provided at the third edge.

[0120] In some embodiments, the above semiconductor structure 1120 and semiconductor structure 1130 may be arranged in a mirror image. Based on this embodiment, it is convenient for the manufacture of the semiconductor structure 1120 and the semiconductor structure 1130 on the wafer substrate, and it is also convenient for the same type of circuits in the semiconductor structure 1120 and the semiconductor structure 1130 to be adjacent to each other, such as adjacent interconnection circuits, thereby facilitating the wiring design between the interconnection circuits of the two semiconductor structures.

[0121] In some examples, as Figure 11 shown, multiple semiconductor structures 1120 and multiple semiconductor structures 1130 may be arranged in an array form on the wafer substrate 1110. Optionally, the multiple semiconductor structures 1120 and the multiple semiconductor structures 1130 may be spaced apart in the row direction, and the multiple semiconductor structures 1120 are arranged in the column direction, and the multiple semiconductor structures 1130 are also arranged in the column direction. Alternatively, the multiple semiconductor structures 1120 and the multiple semiconductor structures 1130 may be spaced apart in the column direction, and the multiple semiconductor structures 1120 are arranged in the row direction, and the multiple semiconductor structures 1130 are also arranged in the row direction. Optionally, the multiple semiconductor structures 1120 and the multiple semiconductor structures 1130 may be spaced apart in the row direction and spaced apart in the column direction.

[0122] In Figure 11In the example shown, the plurality of semiconductor structures in the wafer structure 1100 may be cut and divided to obtain a semiconductor device 1121 including a semiconductor structure 1120 and a semiconductor device 1131 including a semiconductor structure 1130. In the semiconductor device 1121 and the semiconductor device 1131, the interface circuit may be in a connected state, and the interconnection circuit may be in a non-connected state. Figure 11 In the semiconductor device 1121 and the semiconductor device 1131 shown, the positions and numbers of the interface circuits and the interconnection circuits are for illustration only. The circuit structures in the two semiconductor devices can refer to any of the above embodiments and will not be elaborated herein.

[0123] Figure 12 A schematic diagram of dividing another wafer structure according to an exemplary embodiment of the present application is shown.

[0124] like Figure 12 As shown, the wafer structure 1200 may include a wafer substrate 1210, a semiconductor structure 1220 and a semiconductor structure 1230. Figure 11 The related description of the wafer structure 1100 shown can be applied to the wafer structure 1200 in the embodiment of the present application.

[0125] In the embodiment of the present application, the wafer structure 1200 is cut and divided to form a semiconductor device 1221 and a semiconductor device 1231, wherein the semiconductor device 1221 may include a plurality of adjacent semiconductor structures 1220, and the semiconductor device 1231 may include a plurality of adjacent semiconductor structures 1230. As an example, Figure 12 The semiconductor device 1221 shown may include two semiconductor structures 1220, and the semiconductor device 1231 may include two semiconductor structures 1230. In other examples, the semiconductor device 1221 and the semiconductor device 1231 may also include three or more semiconductor structures.

[0126] In a semiconductor device, logic circuits of multiple semiconductor structures may be interconnected via interconnect circuits. A semiconductor structure may include one or more interconnect circuits. When the semiconductor structure includes multiple interconnect circuits, one of the interconnect circuits may be in a connected state, and the other interconnect circuits may be in a non-connected state. In addition, the semiconductor structure may also include one or more interface circuits. One interface circuit in the semiconductor device may be in a connected state, and the other interface circuits may be in a non-connected state.

[0127] Figure 13 A schematic diagram of dividing another wafer structure according to an exemplary embodiment of the present application is shown.

[0128] like Figure 13As shown, the wafer structure 1300 may include a wafer substrate 1310, a semiconductor structure 1320, and a semiconductor structure 1330. The relevant descriptions of the wafer structure 1100 described above Figure 11 can be applied to the wafer structure 1300 in the embodiments of the present application.

[0129] In the embodiments of the present application, by cutting and dividing the wafer structure 1300, a semiconductor device 1301 can be formed. Among them, the semiconductor device 1301 may include adjacent semiconductor structures 1320 and 1330. Inside the semiconductor device 1301, the logic circuits in the semiconductor structures 1320 and 1330 can be interconnected through an interconnect circuit. Optionally, the semiconductor structure 1320 may include one or more interconnect circuits, and the semiconductor structure 1330 may include one or more interconnect circuits. In the semiconductor structure, one of the interconnect circuits may be in a connected state, and the other interconnect circuits may be in a non-connected state. Additionally, the semiconductor structure may also include one or more interface circuits. One interface circuit in the semiconductor device may be in a connected state, and the other interface circuits may be in a non-connected state.

[0130] For Figure 12 and Figure 13 the semiconductor device shown, it may include two or more semiconductor structures. Compared with Figure 11 the semiconductor device shown, it can achieve an improvement in computing power or specifications, such as doubling the computing power or specifications.

[0131] Figure 14 shows a schematic diagram of the division of another wafer structure according to an exemplary embodiment of the present application.

[0132] As Figure 14 shown, the wafer structure 1400 may include a wafer substrate 1410, a semiconductor structure 1420, and a semiconductor structure 1430. The relevant descriptions of the wafer structure 1100 described above Figure 11 can be applied to the wafer structure 1400 in the embodiments of the present application.

[0133] In the embodiments of the present application, by cutting and dividing the wafer structure 1400, a semiconductor device 1401 can be formed. Among them, the semiconductor device 1401 may include adjacent multiple semiconductor structures 1420 and multiple semiconductor structures 1430. As an example, Figure 14 the semiconductor device 1401 shown may include two semiconductor structures 1420 and two semiconductor structures 1430. In other examples, the semiconductor device 1401 may also include more or fewer semiconductor structures 1420, and more or fewer semiconductor structures 1430.

[0134] In some other embodiments, within the wafer structure or semiconductor device, expansion can also be carried out in a direction perpendicular to the substrate or base. For example, an interconnect circuit layer can be provided in a certain direction, and one or more interconnect circuits can be provided in the interconnect circuit layer within the semiconductor structure for internal expansion of the semiconductor device in the vertical direction, that is, expansion of the logic circuits within the semiconductor device.

[0135] The position of the interconnect circuits within the semiconductor structure can also have other settings. For example, it can include interconnect circuits located in the central region. Optionally, it can also include interconnect circuits located at the edges. The interconnect circuits located in the central region can achieve expansion of the logic circuits in at least one direction. The position of the interface circuits within the semiconductor structure can also have other settings. For example, it can include interface circuits located in the central region. For Figure 14 the semiconductor device shown, it can include four or more semiconductor structures. Compared with Figure 12 and Figure 13 the semiconductor devices shown, it can achieve further improvement in computing power and specifications.

[0136] This application also provides an electronic device, which can be referred to Figure 15 . Figure 15 shows a schematic diagram of an electronic device according to an exemplary embodiment of the present application.

[0137] As Figure 15 shown, the electronic device 1500 can include a semiconductor device 1510. The semiconductor device 1510 can include the semiconductor device in any of the above embodiments. In some embodiments, the semiconductor device 1510 can include, for example, a storage device or a memory - computing device.

[0138] This application does not limit the type of the electronic device. For example, according to some embodiments, the electronic device can include a wearable device. Wearable devices include, for example, but are not limited to: head - mounted devices (such as helmets or hats, etc.), devices that can be worn on the ears (such as headphones), devices that can be worn on the wrists (such as watches), devices that can be worn on other parts (such as electronic necklaces, medical monitoring devices, or glasses, etc.). According to some embodiments, the electronic device can include a portable terminal. For example, the electronic device can include, but is not limited to, mobile phones, general computing devices (such as laptop computers or tablet computers, etc.), personal digital assistants, and so on. According to some embodiments, the electronic device can include other types of end - side devices, such as personal computers, in - vehicle computers or in - vehicle computing platforms, or smart home electronic products. According to some embodiments, the electronic device can also include devices such as servers.

[0139] In the above embodiments, the descriptions of different embodiments have their own focuses. For parts that are not described or recorded in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments. And the above different embodiments can be freely combined as needed. Moreover, with the evolution of technology, the elements described in this application can be replaced by equivalent elements that appear after this application.

Claims

1. A semiconductor device, characterized in that: include: a first logic circuit; an interface circuit, coupled to the first logic circuit, for providing an external connection interface for the semiconductor device; The interconnection circuit is coupled to the first logic circuit and is used to provide an internal expansion interface for the semiconductor device.

2. The semiconductor device according to claim 1, wherein: The state of the interconnection circuit includes a connection state or a disconnection state.

3. The semiconductor device according to claim 1 or 2, characterized in that: The interconnect circuit is asynchronous with a clock of the first logic circuit.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that The semiconductor device includes a plurality of interconnection circuits including a first interconnection circuit and a second interconnection circuit.

5. The semiconductor device according to claim 4, wherein: The first interconnection circuit and the second interconnection circuit are in a disconnected state.

6. The semiconductor device according to claim 4 or 5, characterized in that The first interconnection circuit is used to provide an inward expansion of the semiconductor device in a first direction; and the second interconnection circuit is used to provide an inward expansion of the semiconductor device in a second direction.

7. The semiconductor device according to claim 4 or 6, characterized in that: The first interconnection circuit is in a non-connected state, the second interconnection circuit is in a connected state, and the semiconductor device further includes a second logic circuit, and the plurality of interconnection circuits further include a third interconnection circuit, the third interconnection circuit is coupled to the second logic circuit and is in a connected state; The first logic circuit is connected to the second logic circuit through the second interconnection circuit and the third interconnection circuit.

8. The semiconductor device according to any one of claims 4 to 7, characterized in that The plurality of interconnection circuits further include a fourth interconnection circuit coupled to the first logic circuit.

9. The semiconductor device according to claim 8, wherein: The fourth interconnection circuit is in a disconnected state; or, The fourth interconnection circuit is in a connected state, and the semiconductor device further includes a third logic circuit, and the plurality of interconnection circuits further include a fifth interconnection circuit, the fifth interconnection circuit is coupled to the third logic circuit and is in a connected state; The first logic circuit is connected to the third logic circuit through the fourth interconnection circuit and the fifth interconnection circuit.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that Also includes: A substrate, wherein the first logic circuit, the interface circuit and the interconnection circuit are arranged on the substrate, and the interface circuit and the interconnection circuit are located at at least one edge of the substrate.

11. The semiconductor device according to claim 10, wherein: The substrate includes a first edge, a second edge, a third edge and a fourth edge, the third edge is opposite to the first edge, the fourth edge is opposite to the second edge, and the interface circuit is arranged at the first edge, and at least one of the first edge, the second edge, the third edge and the fourth edge is arranged with an interconnection circuit.

12. A wafer structure, characterized in that: include: Wafer substrate; A semiconductor structure formed on the wafer substrate, the semiconductor structure comprising a logic circuit, an interface circuit and an interconnection circuit, the interface circuit being coupled to the logic circuit and used to provide an external connection interface for the semiconductor structure; The interconnection circuit is coupled to the logic circuit and is used to provide an internal expansion interface for the semiconductor structure.

13. The wafer structure according to claim 12, characterized in that: The wafer structure includes a plurality of semiconductor structures, wherein the plurality of semiconductor structures include a first semiconductor structure and a second semiconductor structure; The first semiconductor structure includes a first edge, a second edge, a third edge and a fourth edge, the first edge is opposite to the third edge, the second edge is opposite to the fourth edge, the first edge and the third edge intersect with the second edge and intersect with the fourth edge; The second semiconductor structure includes a fifth edge, a sixth edge, a seventh edge and an eighth edge, the fifth edge is opposite to the seventh edge, the sixth edge is opposite to the eighth edge, the fifth edge and the seventh edge intersect with the sixth edge and intersect with the eighth edge; An interface circuit is formed at the first edge and the fifth edge; The third edge is adjacent to the seventh edge, and an interconnection circuit is formed at the third edge and the seventh edge.

14. The wafer structure according to claim 13, characterized in that: An interconnection circuit is formed at the second edge and the fourth edge; and / or an interconnection circuit is formed at the sixth edge and the eighth edge.

15. A method for manufacturing a semiconductor device, characterized in that: include: Forming a wafer structure as claimed in any one of claims 12 to 14; Determining a division method of the wafer structure; According to the division method, the wafer structure is cut to obtain the semiconductor device, which includes one or more logic circuits.

16. The manufacturing method according to claim 15, characterized in that: When the semiconductor device includes a plurality of logic circuits, the method further includes: A connection structure is formed, the connection structure being used to connect the interconnection circuits of the plurality of logic circuits.

17. An electronic device, characterized in that: include: The semiconductor device according to any one of claims 1 to 11.

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