Driver device and corresponding method

Abstract

The invention relates to a driver device and a corresponding method. Disclosed is an apparatus comprising: a plurality of channels that drive one or more electrical loads; and a control module that generates a control signal to operate at least one of the plurality of channels; an electronic fuse that monitors one or more operating parameters in a respective channel and detects an abnormal condition in the channel based on the monitored parameters; and a parallel mode block defining one or more groups of channels including two or more channels configured to drive the same load. The control module receives a parallel mode management control signal from the parallel mode block and operates a channel of the set of channels based on the parallel mode management control signal received by the parallel mode block. The electronic fuse causes the channels in the group to be non-conductive in response to detecting an abnormal condition even only in one channel in the group.

Description

Technical Field

[0001] This specification relates to electronic circuits.

[0002] One or more embodiments can be applied to electronic circuits (such as, for example, high-side driver (HSD) circuits). Background Art

[0003] High-side drivers are widely used in automotive applications to couple a load to a voltage supply.

[0004] Typically, such a high-side driver can integrate a digital or analog control circuit with a vertical power transistor to obtain a VIPower HSD (“Vertical Intelligent Power High-Side Driver”).

[0005] Thus, such a VIPower HSD is a monolithic silicon chip that combines control and protection circuitry with one or more standard power MOSFETs, having a power-stage current that flows vertically therein.

[0006] Figure 1 A block diagram of a high-side driver 10 (e.g., VIPower HSD) is illustrated, which includes a logic component 100 (regulated voltage V generated by a voltage regulator 106) REG power supply) and a component including a gate driver and MOSFET 102 (powered by supply voltage V) CC power supply).

[0007] For example, the logic component 100 can include a watchdog unit 1002, an ADC (“Analog-to-Digital Converter”) 1004, a priority manager 1006, a PWM (“Pulse-Width Modulation”) engine 1008, an OTP (“One-Time Programmable Memory”) 1010, a block 1012 containing flags, and a reverse battery block 1014.

[0008] The watchdog unit 1002 can be configured to receive a serial signal from an SPI (“Serial Peripheral Interface”) block 104 and implement one or more watchdog timers, i.e., one or more timers for detecting and recovering from faults.

[0009] The ADC 1004 can be configured to receive a serial signal from the SPI block 104, convert an internal analog signal (such as an internal analog current proportional to the output) into a digital vector, and provide such internal analog current and such digital vector to the priority manager block 1006 (e.g., if there are multiple output channels (collectively referred to as CH)) or the PWM engine 1008 (e.g., if there is a single output channel CH).

[0010] Depending on the number of output channels (e.g., if there are multiple output channels (collectively referred to as CH)), the priority manager block 1006 or the PWM engine 1008 can be configured to multiplex the received internal analog current and store the digital conversion data (i.e., such received digital vectors) into a given register.

[0011] In this way, an external finishing unit (such as a microcontroller, etc.) can read data from such a given register.

[0012] In fact, the high-side driver 10 can include:

[0013] A single output channel CH, which includes a single integrated power MOSFET, or multiple output channels, e.g., up to four output channels CH 1 、CH 2 、CH 3 and CH 4 (collectively referred to as CH), with corresponding integrated power MOSFETs, such that different loads can be driven by the same high-side driver 10 (e.g., a single load can be driven by each channel CH, i.e., by each of the corresponding integrated power MOSFETs).

[0014] The priority manager 1006 can be configured to receive such analog signals and manage channel transition arbitration and synchronization if multiple channels are to be operated.

[0015] If the high-side driver 10 includes a single output channel CH, the priority manager 1006 can be configured to address the same single output channel CH.

[0016] Such a priority manager 1006 can further be configured to provide a priority control signal to the ADC block 1004, such a priority control signal containing information about channel transition arbitration and synchronization.

[0017] The PWM engine 1008 can be configured to receive an external PWM clock signal PWM CLK and digital signals from the SPI block 104, and generate one or more channel control signals (i.e., one or more PWM signals) based on the received signals for operating a single channel CH or a group of channels (a single channel among such multiple channels, all channels among such multiple channels, or a subset including any number of channels among such multiple channels) of the multiple channels CH through corresponding output terminals.

[0018] The channel control signal, i.e., the PWM signal generated by the PWM engine 1008, can be used to operate such a single channel CH or such a group of channels in multiple channels CH. Therefore, since each of the channels CH can be implemented using a corresponding power MOSFET, such a channel control signal can be used to drive, through the corresponding gate terminals, a number of power MOSFETs equal to the number of channels in such a single channel CH or such a group of channels in multiple channels CH.

[0019] Therefore, such one or more power MOSFETs included within a corresponding one or more channels CH (e.g., in the component including the gate driver and MOSFET 102) are configured to have:

[0020] Its gate terminal coupled to the corresponding output terminal of the PWM engine 1008,

[0021] Its drain terminal coupled to the supply voltage V CC and

[0022] Its source terminal coupled to a corresponding capacitor (e.g., Figure 1 C 1 , C 2 , C 3 and C 4 (collectively referred to as C)) and a corresponding load (coupled to the corresponding channel and not shown in Figure 1 ).

[0023] The OTP 1010 and the block 1012 containing the flag may contain information used by other blocks to perform their functions, or may contain, for example, information for extending monitoring options or configuration information for implementing methods (such as auto-restart or latching functions).

[0024] (Optional) The reverse battery block 1014 may be configured to perform a protection function, for example, by providing a self-conduction function to one or more power MOSFETs included in one or more channels CH.

[0025] For each channel CH, the component including the gate driver and MOSFET 102 advantageously includes a current sensing block 1020, which is coupled to the source terminal of the power MOSFET included in each channel and is configured to sense the value of the current flowing therein and provide such a sensed current value as feedback to the ADC 1004.

[0026] If there are multiple channels CH, the component including the gate driver and MOSFET 102 may further include a current sensing block 1020 and a current sensing multiplexer. Such a current sensing block 1020 is configured to sense the current value flowing in each of the channels among the multiple channels CH (e.g., by coupling to the source terminal of the corresponding power MOSFET included in the considered channel) and send each of such sensed current values to the corresponding input terminal of the current sensing multiplexer.

[0027] Thus, such a current sensing multiplexer is configured to select a given sensed current value from the multiple sensed current values received at its input terminals and provide such a selected given sensed current value as feedback to the ADC1004.

[0028] Typically, a vehicle includes one or more silicon devices, each of which integrates multiple high-side drivers 10 having different current capabilities for driving loads with different current requirements.

[0029] Such a technical solution for managing loads with different current requirements may result in a large footprint because multiple high-side drivers 10 are to be integrated within the same silicon device.

[0030] Therefore, a technical solution that promotes reducing the number of high-side drivers integrated within a single silicon device without degrading robustness and compatibility with loads having different current requirements would be beneficial in order to reduce the footprint and the number of circuit devices used while still providing compatibility with different types of loads. Summary of the Invention

[0031] An object of one or more embodiments is to contribute to providing such a technical solution.

[0032] According to one or more embodiments, this object is achieved via a circuit (driver device, such as a high-side driver (e.g., HSD circuit)) having the features set forth in the appended claims.

[0033] One or more embodiments relate to methods of related operations.

[0034] The claims are an essential part of the technical teachings provided for the embodiments.

[0035] The technical solution as described herein includes a driver device (such as a high-side driver device), including:

[0036] a plurality of channels configured to drive one or more loads, and

[0037] a control module configured to generate one or more channel control signals to operate one or more of such channels.

[0038] The technical solutions described herein may further include:

[0039] An electronic fuse (“E-Fuse”) configured to monitor one or more parameters in a respective channel of a plurality of channels and use such one or more monitored parameters to detect an abnormal condition on the respective channel, and

[0040] A parallel mode block configured to define one or more groups of channels (where each group of channels includes at least two channels), and the channels in the same group of channels are configured to drive the same load.

[0041] In addition, the control module of the technical solutions described herein may further be configured to receive an administrative control signal from the parallel mode block and operate the channels in one or more groups of channels based on the received administrative control signal.

[0042] The electronic fuse of the technical solutions described herein may further be configured to render the channels in such same group of channels non-conductive in response to detecting an abnormal condition in one or more channels in the same group of channels.

[0043] In an embodiment, the high-side driver device described herein may include an additional module configured to provide compatibility with a load that includes one or more capacitive components to be pre-charged (i.e., candidates for pre-charging).

[0044] In an embodiment, the high-side driver device described herein may include one or more built-in self-test (BIST) circuitry configured to check whether the functional safety requirements including the analog-to-digital converter and / or the implemented harness protection are met.

[0045] In an embodiment, the high-side driver device described herein may include an enhanced digital power supply that includes a capacitor configured to be charged to supply power to a dedicated pin in the event of a global supply voltage drop.

[0046] The technical solutions described herein facilitate reducing the number of high-side drivers integrated within a single silicon device without reducing robustness and compatibility with loads having different current requirements, in order to reduce the footprint and the number of circuit devices used, while still providing compatibility with different types of loads. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] One or more embodiments will now be described by way of example only with reference to the drawings, in which:

[0048] Figure 1 is a block diagram of a high-side driver;

[0049] Figure 2is a block diagram of a high-side driver according to an embodiment of the present specification;

[0050] Figure 3 is a diagram including steps and components involved in the operation of a high-side driver according to an embodiment of the present specification in the presence of a capacitive load;

[0051] Figure 4 is according to an embodiment of the present specification, when according to Figure 3 a timing diagram of the behavior of signals related to the high-side driver when operating according to the diagram of;

[0052] Figure 5 is a part of BIST ("Built-In Self-Test") used in a high-side driver according to an embodiment of the present specification; and

[0053] Figure 6 is an enhanced digital power supply used in a high-side driver according to an embodiment of the present specification.

[0054] Unless otherwise indicated, corresponding numbers and symbols in different figures generally refer to corresponding parts.

[0055] The diagrams are drawn to clearly illustrate relevant aspects of the embodiments, and the diagrams are not necessarily drawn to scale.

[0056] The edges of the features drawn in these diagrams do not necessarily indicate the termination of the scope of the features. Detailed Description

[0057] One or more specific details are shown in the following description, aiming to provide an in-depth understanding of examples of embodiments of the present specification. Embodiments can be obtained without one or more specific details, or by using other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail, so that certain aspects of the embodiments are not obscured.

[0058] References to "an embodiment" or "one embodiment" in the framework of the present specification are intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is included in at least one embodiment. Thus, phrases (such as "in an embodiment" or "in one embodiment") that may exist at one or more points in the present specification do not necessarily refer to the same embodiment.

[0059] Furthermore, a particular configuration, structure, or characteristic can be combined in one or more embodiments in any suitable manner.

[0060] The headings / references used herein are provided for convenience only and thus do not limit the scope or extent of protection of the embodiments.

[0061] For simplicity and ease of explanation, throughout the specification, and unless the context otherwise indicates, like reference numerals are used in the various figures to indicate like parts or elements, and the corresponding descriptions will not be repeated for each figure.

[0062] Possible application scenarios of the technical solutions described herein can be automotive scenarios. For example, the technical solutions described herein can be used in automotive power distribution applications characterized by different current loads.

[0063] The power distribution domain including a high-side driver is an example of a possible application of the embodiments, where the high-side driver needs to be compatible with loads having different current requirements in order to enhance compatibility with different types of loads.

[0064] It should be noted that even though the following description mainly focuses on automotive applications, the technical solutions described herein can also be used in different applications and scenarios including drivers (such as high-side drivers), for example, for which compatibility with loads having different current requirements is a desired feature.

[0065] As previously described, the technical solutions described herein aim to facilitate reducing the number of high-side drivers integrated within a single silicon device without degrading robustness and compatibility with loads having different current requirements, thereby reducing the footprint and the number of circuit devices used, while still providing compatibility with different types of loads.

[0066] Thus, in response to the current requirement of a given load being higher than the current that can be provided by a single channel (i.e., by a single power MOSFET included in such a single channel), the technical solutions described herein can be configured to parallelize the channels in a group of channels included in multiple channels CH, so as to use more than one channel (i.e., use each of the channels included in such a group of channels) to drive such the same given load by actuating the channels included in such a group of channels on the given load.

[0067] Otherwise, in response to the current requirement of a given load being lower than or equal to the current that can be provided by a single channel (i.e., by a single power MOSFET included in such a single channel), the technical solutions described herein can be configured to use such a single channel to drive such the given load by actuating the single channel on such the given load.

[0068] Note that if there are multiple loads with current requirements higher than the current that can be provided by a single channel, the technical solution described herein can be configured to parallelize the channels included in more than one group of channels (e.g., the number of groups of channels equal to the number of such multiple loads), where each of the channels included in the same group of channels is configured to drive the same load among such multiple loads.

[0069] Thus, each of the channels included in the same group of channels is actuated on the same corresponding load among such multiple loads, while the channels included in different groups of channels are actuated on different corresponding loads among such multiple loads.

[0070] It should be noted that the number of channels that drive the same given load and are included in the same group of channels can depend on the current requirement of such given load. For example, based on the current requirement of the load, a single channel, a subset of multiple channels CH, or all of the multiple channels CH can be used to drive such load.

[0071] For example, the parallelized channels, i.e., the channels included in the same group of channels among multiple channels CH and actuated on the same load, can include corresponding power MOSFETs with the same or different current capabilities. Thus, the number of channels that drive the same given load and are included in the same group of channels can also depend on the current capabilities of the corresponding power MOSFETs included therein.

[0072] Therefore, in order to select different current capabilities of the high-side driver 20 to drive a load with a current requirement higher than the current that a single channel can provide, a higher number of channels (i.e., more than one single channel) are used to drive such load, such channels are included in the same group of channels, and such channels are selected considering the current requirement of such load and the current capabilities of the corresponding power MOSFETs included therein.

[0073] It should be noted that the higher the number of channels selected to drive a single load, the higher the current requirement of such single load (i.e., the current required to drive such single load).

[0074] As already described, it should be noted that if a single channel can provide the current capability requested by a given load, such parallelization can be disabled.

[0075] In addition, it should be noted that such parallelization can be selectively enabled for a subset of the channels among multiple channels CH. Thus, such subset of channels can operate in a parallelization mode (i.e., the channels included in such subset of channels can be configured to drive the same load).

[0076] In this case, channels that are not included in such a subset of channels can operate in a standard mode, that is, so as to drive the corresponding load individually (i.e., each of such channels that is not included in such a subset of channels can be used to drive the corresponding load).

[0077] It should also be noted that such parallelization can be selectively enabled for multiple sets of channels, where each set of such channels includes channels that can be configured to drive the same load, and channels included in different sets of channels can be configured to drive different loads. For example, a first set of channels can include a pair of channels configured to drive the same first load, and a second set of channels can include three channels configured to drive the same second load.

[0078] In some applications, using multiple channels to drive a single load can cause faults (such as thermal shutdown, EMI ("electromagnetic interference" - for example, using unbalanced equivalent power MOSFETs to maintain residual demagnetization energy), switching losses, and the risk of damaging one or more of the channels).

[0079] For example, if the balance of the current flowing within parallelized channels (i.e., channels included in the same set of channels and actuating on the same coupled load) depends on:

[0080] external synchronization of the channel control signals (thus, the protection mechanisms are not synchronized for channels driving the same coupled load), and

[0081] the balance of the external tracks / traces coupling the high-side drivers to such a coupled load.

[0082] In the case of a thermal event on at least one of the parallelized channels (such that no current is flowing), the current flowing within the other channels in the parallelized channels increases in order to provide the amount of current required to drive such a coupled load to the coupled load, thereby causing an overload of such other channels in the parallelized channels and leading to possible destruction of one or more of them.

[0083] Therefore, a technical solution capable of managing parallelized channels (i.e., channels included in the same set of channels and actuating on the same load) can advantageously reduce the probability of having the above-mentioned faults, for example, by facilitating the balance of the current flowing within such parallelized channels.

[0084] Therefore, in the technical solution described herein, the activation of the channels can be managed internally, and channel internal protection and diagnosis can be performed on the parallelized channels as a group, rather than individually on each of such parallelized channels (even though such internal protection and diagnosis can be individually activated for each of the parallelized channels).

[0085] The average value of the current flowing in the parallelized channels can be used as the trip current to keep the harness protection separate.

[0086] Figure 2 It is a block diagram of the high-side driver 20 according to an embodiment of the present specification.

[0087] Hereinafter, the blocks, elements, and / or components already referred to Figure 1 are denoted by the same reference numerals, and thus, the description of such previously described elements will not be repeated herein so as not to make the present specification overly verbose.

[0088] Figure 2 shows the high-side driver 20, which, in addition to Figure 1 the elements already described in Figure 1 also includes an E-Fuse (“electronic fuse”) 200 and a parallel mode block 202, both of which are included in the logic component 100′ (corresponding to Figure 2 the logic component 100 but also including

[0089] The E-Fuse 200, such as an I2t (optionally CCM, i.e., implementing a capacitive charging mode) E-Fuse, can be configured to:

[0090] continuously monitor at least one parameter of each of the plurality of channels CH, such as the harness current and / or other parameters for detecting abnormal conditions,

[0091] check for abnormal conditions in such corresponding channels using each of at least one monitored parameter associated with the corresponding channels of the plurality of channels CH;

[0092] perform protection operations (such as internal channel protection and diagnostics) based on the detected abnormal conditions, for example, independently, i.e., without interference from an external microcontroller (or any other equivalent external unit, such as a microprocessor, a logic unit, etc.), and

[0093] be compatible with (even large) capacitive loads, for example, by enabling specific functions (such as a capacity charging mode, CCM feature) (optionally).

[0094] I2t (current squared times time) is an electrical quantity commonly used to determine the energy of a protection device (such as a circuit breaker or a fuse).

[0095] On the parallelized channels as a group, rather than individually on each of such parallelized channels, perform the protection operations as contemplated herein (even if such protection operations may be individually activated for each of the parallelized channels driving the same load). Thus, for example, in the case of a thermal event (or any other fault / anomaly condition) on at least one of the parallelized channels, each of the parallelized channels is decoupled from the load or turned off, i.e., becomes non-conductive, and thus interrupts the current flowing within each of the parallelized channels driving the same load.

[0096] In fact, the protection and diagnosis performed on each of the channels can be active and separate from the protection and diagnosis of other channels, but triggering at least one protection associated with a channel in a group of parallelized channels driving the same given load can also trigger the protection of other channels in such a group of parallelized channels.

[0097] The protection operations can include one or more of the following operations: power limiting, thermal shutdown, current limiting, and I2t trip time scaling (i.e., scaling of harness protection, where the I2t trip time describes the quadratic law by which a wire harness can sustain a current for a certain time without melting).

[0098] In addition, the protection operations can also include harness protection that uses the average value of the current flowing within the parallelized channels as the trip current, thus adapting such harness protection to the parallel mode (i.e., the operation of the high-side drivers with parallelized channels), for example, using additional logic.

[0099] It should be noted that the OTP 1010 can retain information about the configuration of each of the channels and other useful information (such as information about testing and fine-tuning).

[0100] If the parallel mode block 202 is enabled, it is configured to define at least one group of channels including at least two channels among the plurality of channels CH, and each of such channels included in such at least one group of channels is configured to drive the same corresponding load. Thus, such a parallel mode block 202 is configured to define the channels to be parallelized.

[0101] The parallel mode block 202 can also be configured to configure and activate such channels to be parallelized (i.e., the channels included in the same group of channels and driving the same load) and manage such parallelized channels synchronously, for example, by providing activation and synchronization control signals to the PWM engine 1008.

[0102] Thus, such a PWM engine 1008 can also be configured to use the information of such activation and synchronization control signals to correctly manage the parallelized channels, for example, by generating one or more channel control signals based on such received activation and synchronization control signals.

[0103] For example, the parallel mode block 202 can be enabled by setting a digital enable, for example, by setting the bits of the enable register of the SPI block 104 to a high logic level (or a low logic level), by setting the bits of one or more registers within the parallel mode block 202 in real time, or by any other enable signal or any other register setting.

[0104] The parallel mode block 202 can include at least one channel control register for each channel CH, such at least one channel control register being configured to be linked to the corresponding channel and storing the configuration parameters of such corresponding channel therein. Thus, such a driver device 20 can include a channel control register configured to store the configuration parameters of the corresponding channel among a plurality of channels CH therein.

[0105] In fact, if a channel is enabled and configured to be parallelized with other channels, i.e., configured to supply power to the same load as such other channels, at least one channel control register corresponding to such a channel is configured to store the configuration parameters for such a channel. For example, such configuration parameters can be used by the parallel mode block 202 to provide activation and synchronization control signals to the PWM engine 1008, so as to facilitate the activation and synchronization management of such a channel and other channels to be parallelized with such a channel.

[0106] It should be noted that the configuration parameters associated with the parallelized channels (driving the same load) stored in the corresponding channel control registers can advantageously be equal. Thus, the channel control registers of the channels in the same group of channels (i.e., the group of channels including the channels configured to be parallelized to drive the same load) can be configured to store the same configuration parameters of the corresponding channels in such same group of channels, and the control module (e.g., the PWM engine 1008) can be configured to receive parallel mode management control signals (i.e., activation and synchronization control signals) from the parallel mode block 202 based on such same configuration parameters.

[0107] In this way, each of the control commands addressed to one of the parallelized channels can be equal to the control commands addressed to the other parallelized channels, thus facilitating the synchronous management of such parallelized channels.

[0108] In fact, the parallel mode block 202 can also be configured such that if the control commands addressed to other channels in the parallelized channels are different from the control commands addressed to one of the parallelized channels (i.e., the updated control register selected from such channel control registers) (e.g., the first channel receiving the control command or the specific channel specifying the received control command), such control commands are ignored to avoid their desynchronization.

[0109] Therefore, the channel control registers of the channels in the same group of channels can be configured to:

[0110] Receive an update request for the same configuration parameter at an updated control register outside the channel control register of the channels in the same group of channels,

[0111] In response to receiving the update request at the updated control register, update the same configuration parameter in the channel control registers of the channels in the at least one group of channels, and

[0112] Ignore other update requests received at the channel control registers of the channels in the at least one group of channels that are different from the same configuration parameter of the updated control register.

[0113] It should be noted that such added blocks, namely the E-Fuse 200 and the parallel mode block 202, may not affect other blocks in the logic component 100 (e.g., the ADC 1004, and / or the current sensing block 1020 included in the component including the gate driver and the MOSFET 102).

[0114] Therefore, the technical solution described herein promotes reducing the number of high-side drivers integrated in a single silicon device without reducing the compatibility with loads having different current requirements, because a smaller number of high-side drivers 20 configured to parallelize the output channels to drive loads with higher current requirements can be utilized instead of a larger number of high-side drivers with different current capabilities.

[0115] In addition, such an advantage can be provided without reducing the robustness of the high-side driver, because protection operations can be performed on the parallelized channels as a group, and the control commands addressed to each of the parallelized channels can be kept synchronized.

[0116] Therefore, the technical solution described herein can promote obtaining higher performance, robustness, and greater versatility in the management terminal. Applications (such as the high-side driver described herein) can drive loads with different configurations, for example, in a current range from about 1.5 A to about 30 A, and even reduce the occupied area.

[0117] It should be noted that such a current range may be even wider if a hybrid driver rather than a monolithic high-side driver is considered, i.e., the control stage of the high-side driver is located in one die and the power stage is located in another die, and the two dies are assembled in one package.

[0118] In summary, a driver device 20 (such as a high-side driver device) as described herein may include:

[0119] A plurality of channels CH, configured to drive one or more electrical loads, for example, using corresponding power MOSFETs coupled to such electrical loads;

[0120] A control module (such as a PWM engine 1008), configured to generate one or more channel control signals (such as one or more PWM signals) to operate at least one of the plurality of channels CH;

[0121] An electronic fuse 200, configured to monitor one or more parameters (such as harness current, etc.) in a corresponding channel of the plurality of channels CH, and detect an abnormal condition in the corresponding channel based on the one or more monitored parameters; and

[0122] A parallel mode block 202, configured to define one or more groups of channels including two or more channels of the plurality of channels CH, and channels in the same group of channels are configured to drive the same load, i.e., such channels included in the same group of channels are configured to be paralleled.

[0123] The control module 1008 may be configured to receive parallel mode management control signals (such as such activation and synchronization control signals) from the parallel mode block 202, and operate the channels in the one or more groups of channels based on the parallel mode management control signals received by the parallel mode block 202, and the electronic fuse 200 may be configured to render the channels in the same group of channels non-conductive in response to an abnormal condition detected in at least one channel in the at least one group of channels.

[0124] Using a technical solution such as an E-Fuse 200 that is not provided with compatibility with a capacitive load (or a load including capacitive components) may not provide management of such types of loads. Figure 2 of may not provide management of such types of loads.

[0125] Managing capacitive loads may be useful in different applications (such as in automotive applications).

[0126] In fact, each time the vehicle is powered on, a controlled pre-charge is performed on the capacitors included in the ECU ("electronic control unit") and / or different capacitive loads included in the power distribution domain.

[0127] It should be noted that a discharged capacitor (or a discharged capacitive load) can be modeled as a short circuit. Therefore, pre-charging a (even large) capacitor or a generally capacitive load using the high-side driver 20 can cause a (high) surge current to flow within the high-side driver assembly.

[0128] Such a surge current can cause thermal shutdown of the corresponding high-side driver 20, thus interrupting the charging of the capacitive load.

[0129] For example, a first method that can avoid such thermal shutdown includes using a dedicated unit to perform pre-charging of the capacitive load. The dedicated unit is configured to manage a sequence of current pulse spikes regardless of the thermal behavior of the power MOSFET included in the channel of the corresponding high-side driver.

[0130] Therefore, using such a method may not provide the possibility of optimizing the charging time and the thermal capacity of the power MOSFET included in the channel because the thermal behavior of such a power MOSFET is not considered.

[0131] In fact, the current pulse used in such a first method can only depend on the programmed frequency and there is no feedback from thermal protection (i.e., it is an open-loop solution).

[0132] In addition, problems related to the management of (very) high current spikes can occur. For example, the size of the ground connection may be important.

[0133] Therefore, a different solution is described herein. Such a solution includes the implementation of an additional module (i.e., the CCM module) on the high-side driver 20, for example, implemented within the E-Fuse 200 and coupled to the PWM engine 1008.

[0134] Such a CCM module is configured to provide compatibility with the capacitive load, so that at least one power MOSFET that can be included in the corresponding channel of the high-side driver 20 operates in the CCM ("capacitive charging mode") mode. Such at least one power MOSFET is coupled to a load including a capacitive component.

[0135] Enabling the CCM mode can involve limitations:

[0136] The current flowing within such at least one power MOSFET, and

[0137] The thermal increase of at least one power MOSFET with respect to the chip temperature, considering such additional thermal increase with respect to the thermal increase that affects such at least one power MOSFET during "normal" operation, i.e., enabling such CCM mode to charge a capacitive load within a certain (desired) time range when the capacitive load has been pre-charged, and thus performing such pre-charge based on the actual MOSFET temperature rather than the current pulse spike sequence.

[0138] It should be noted that the CCM module can be integrated within the E-Fuse 200 and coupled to the PWM engine 1008, and thus, no additional components need to be added to the high-side driver 20.

[0139] It should be noted that such a CCM mode, i.e., the mode that manages the operating conditions of at least one power MOSFET included in the channel of the high-side driver 20 when such a power MOSFET is coupled to a load including a capacitive component to be pre-charged (i.e., a candidate for pre-charge), can be used for both fail-safe (i.e., in the presence of a fault, the device responds in a way that causes minimal or no harm to other devices, the environment, or personnel) and normal mode devices (i.e., non-fail-safe devices).

[0140] The technical solutions described herein facilitate the resolution of previous problems, and thus, provide even wider load compatibility (even compatible with capacitive loads and loads including capacitive components to be pre-charged), and further reduce the number of components, because another high-side driver dedicated to the pre-charge of such capacitive loads can be dispensed with. For example, the use of a dedicated unit configured to manage the previously described current pulse spike sequence can be avoided.

[0141] Therefore, the technical solutions described herein can include:

[0142] Performing smooth charging of the capacitive load to be pre-charged using (low or medium) RMS ("root mean square") current, and

[0143] Disabling the harness protection of the E-Fuse 200 during such pre-charge of the capacitive load (i.e., during the CCM mode).

[0144] It should be noted that the technical solutions described below can be advantageously used even under high ambient temperature conditions, and it can be used to drive capacitive loads on both parallelized channels and individual channels depending on the corresponding configuration parameters (stored in the parallel mode block 202).

[0145] Figure 3FIG. 30 according to an embodiment of the present specification, including steps (e.g., partially implemented in the CCM module) and components, where the steps and components relate to the operation of at least one power MOSFET (represented by block 308 in FIG. 30) included in the channel of the high-side driver 20 in the presence of a capacitive load.

[0146] According to Figure 3 FIG. 30, such operation of at least one power MOSFET 308 included in the channel of the high-side driver 20 can advantageously facilitate the charging of the capacitive load during a certain time period without turning off the power MOSFET (i.e., making it non-conductive) in response to thermal shutdown.

[0147] The first block of FIG. 30 is the check block 300, which includes steps performed, for example, by the CCM module, such steps including:

[0148] Receiving a start signal CCM indicating whether to operate at least one power MOSFET 308 included in the channel of the high-side driver 20 using the CCM mode ON / OFF ,

[0149] Using the information of such a start signal CCM ON / OFF to check whether to operate such at least one power MOSFET 308 of the high-side driver 20 using such a CCM mode,

[0150] If the check step determines to use the CCM mode, generate a first output check signal Y (indicated by the first output check branch Y in FIG. 30) and continue to the first setting block 302 including the first setting step, and

[0151] If the check step determines not to use the CCM mode, generate a second output check signal N (represented by the second output check branch N in FIG. 30) and continue to the second setting block 304 including the second setting step.

[0152] The first setting block 302 includes a first setting step (e.g., implemented using the CCM module), including selecting a first set of limit values LV in response to the reception of the first output check signal Y 1 , the first set of limit values LV 1 including a limit value of the current flowing within such at least one power MOSFET 308 (i.e., the output current limit threshold) and a thermal increase of at least one power MOSFET 308 with respect to the chip temperature, considering such a thermal increase with respect to the thermal conditions of such at least one power MOSFET 308 during normal operation.

[0153] For example, exemplary values of such limit values may be (it should be noted that such values are provided herein only by way of example and are not limiting for the scope of protection of this document):

[0154] The limit value I of the current flowing in such at least one power MOSFET 308 limL may be equal to forty percent (i.e., 40%) of the maximum current I limH which can flow in such at least one power MOSFET 308 before possible damage or before triggering thermal shutdown; and limH The limit value ΔT of the thermal increase of at least one power MOSFET with respect to the chip temperature

[0155] may be equal to 35 °C. PL The first setting step may further include providing such a first set of limit values LV

[0156] to the controller block 306 (e.g., implemented within the PWM engine 1008), such that the limit values included in such a first set of limit values LV 1 can be used during the operation of at least one power MOSFET 308 in the CCM mode. 1 The second setting block 304 includes a second setting step (e.g., implemented using the CCM module or by default when not using such a CCM module), including selecting a second set of limit values LV

[0157] in response to the reception of the second output check signal N, the second set of limit values LV 2 including the limit value of the current flowing in such at least one power MOSFET 308, i.e., the output current limit threshold, and the thermal increase of at least one power MOSFET 308 with respect to the chip temperature, considering such thermal increase with respect to the thermal conditions of such at least one power MOSFET 308 during normal operation. 2 It should be noted that the limit values included in the second set of limit values LV

[0158] may be higher than the corresponding limit values included in the first set of limit values LV 2 1 For example, exemplary values of the limit values included in the second set of limit values LV 2

[0159] may be (it should be noted that such values are provided herein only by way of example and are not limiting for the scope of protection of this document): 2 For example, exemplary values of such limit values may be (it should be noted that such values are provided herein only by way of example and are not limiting for the scope of protection of this document):

[0160] The limit value I of the current flowing in such at least one power MOSFET 308 limHi.e., the maximum current I that can flow within such at least one power MOSFET 308 before possible damage or before triggering thermal shutdown limH ; and

[0161] a limiting value ΔT that can affect the thermal increase of such at least one power MOSFET 308 PL , which can be equal to 80 °C.

[0162] The second setting step may further include providing such a second set of limiting values LV to the controller block 306 2 such that the limiting values included in such a second set of limiting values LV can be used during operation of at least one power MOSFET 308 in an operating mode different from the CCM mode 2 .

[0163] The controller block 306 may include steps performed, for example, within the PWM engine 1008, such steps including enabling or disabling one or more high-side driver functions based on the reception of a function enable / disable signal S ON / OFF wherein such a function enable / disable signal S ON / OFF indicates enabling or disabling such a function (or a subset of such functions) within the duration of the CCM mode (i.e., when the start signal CCM ON / OFF indicates that the CCM mode is to be used to operate at least one power MOSFET 308 of the high-side driver 20).

[0164] For example, if the steps included in the controller block 306 are performed within the PWM engine 1008, such a PWM engine 1008 may further be configured to send a set of control signals to the E-Fuse 200 in response to receiving such a function enable / disable signal S ON / OFF (e.g., indicating disabling of harness protection and / or enabling of automatic restart of TSD (“thermal shutdown”) (without delay) within the duration of the CCM mode).

[0165] Otherwise, if the steps included in the controller block 306 are performed within the E-Fuse 200, an enable / disable signal S indicating enabling or disabling of a protection function may be received by such an E-Fuse 200 ON / OFF , and such an E-Fuse 200 may, for example, further be configured to disable harness protection and / or enable automatic restart of TSD (“thermal shutdown”) (without delay) within the duration of the CCM mode in response to receiving such an enable / disable signal S ON / OFF .

[0166] The steps included in the controller block 306 may further include:

[0167] Receive a first set of limit values LV from a first setting step included in the first setting block 302 1 or receive a second set of limit values LV from a second setting step included in the second setting block 304 2 ,

[0168] Receive a feedback signal FS from at least one power MOSFET represented by block 308 (i.e., from at least one channel including such at least one power MOSFET 308), such a feedback signal FS indicating the actual value of the current flowing therein and its actual thermal increase, and

[0169] Based on the received signal / values (i.e., the function enable / disable signal S ON / OFF , the first set of limit values LV 1 or the second set of limit values LV 2 and the feedback signal FS) drive at least one power MOSFET 308.

[0170] It should be noted that Figure 3 the technical solution of

[0171] also consider the actual conditions of at least one power MOSFET 308 (i.e., the actual conditions of the corresponding channel including such at least one power MOSFET 308) in order to drive such a power MOSFET 308 (i.e., such a corresponding channel), and

[0172] modulate the charging performance of the capacitive components of the load to obtain a desired charging time, for example, select different limit values for such a first set of limit values LV 1 to obtain such a desired charging time.

[0173] Such a closed-loop implementation can promote the optimization of the pre-charging of such capacitive components of the load, because the thermal behavior of the power MOSFET 308 is provided as feedback to the steps included in the controller block 306, and thus such steps can use such information to optimize the driving of such corresponding power MOSFETs.

[0174] In this way, the power MOSFET can transition from a conductive state to a non-conductive state only when there is a risk of thermal shutdown, and thus the time required to pre-charge such capacitive components of the load can be minimized.

[0175] Furthermore, by selecting desired values for the limit values in the first set of limit values LV 1 it may be possible to charge the capacitive components of the load within a certain (desired) time range (e.g., 100 milliseconds).

[0176] Therefore, a technical solution using the CCM mode (e.g., according to Figure 3 the illustration 30 described in

[0177] Figure 4 can be advantageously more comprehensive in a management terminal application (i.e., in managing different types of loads), because even loads including capacitive components (even large ones) to be precharged can be considered. Figure 3 FIG. 40 is a timing diagram of signal behavior related to the high-side driver 20 when operating according to the illustration of

[0178] In response to the input signal IN commuting (e.g., from a low logic level to a high logic level (e.g., corresponding to vehicle power-on)), the precharging of the capacitive load (or the capacitive component of the load) coupled to the power MOSFET 308 to be operated in the CCM mode starts at the start charging time SC.

[0179] In response to the input signal IN commuting, the CCM mode is enabled to operate at least one power MOSFET 308 coupled to a load including a capacitive component to be precharged. Such a CCM mode is enabled by the start signal CCM ON / OFF so that the first set of limit values LV 1 is selected, and the function enable / disable signal S ON / OFF (e.g., indicating disabling harness protection and enabling TSD auto-restart (without delay)).

[0180] Furthermore, as previously described, the driving step can be performed, for example, using the PWM engine 1008 to drive at least one power MOSFET 308 to conduct, where the driving step is included in the controller block 306. At least one power MOSFET is coupled to such a load including a capacitive component to be precharged. Therefore, an output current I limL having a limit value equal to the selected current limit value I 1 (included in the first set of limit values LV OUT ) starts to flow within such at least one power MOSFET 308, and a corresponding output voltage V O equal to V OUT is applied to it.

[0181] It should be noted that Figure 4 the exemplary inrush current I Inrush (dotted line) shown in InrushHas a high value that can cause thermal shutdown of at least one power MOSFET 308.

[0182] In response to the output current I OUT Flowing within at least one power MOSFET 308, the temperature of such at least one power MOSFET 308 (i.e., its junction temperature) can increase to the operating temperature T O (i.e., the (junction) temperature of at least one power MOSFET 308 when coupled to a capacitively loaded that has been pre-charged) above.

[0183] Higher than the operating value I of the current flowing in such at least one power MOSFET 308 when the capacitive load has been pre-charged O Of the output current I flowing within at least one power MOSFET 308 OUT Value (i.e., the limit value I limL ) can cause a temperature increase.

[0184] It should be noted that in Figure 4 The temperature behavior measured using two different temperature sensors is shown: the temperature behavior measured using the high temperature sensor HS and the temperature behavior measured using the low temperature sensor CS.

[0185] Such temperature behavior can be used to detect two different thermal protections: thermal shutdown protection and power limit protection.

[0186] When the junction temperature T of the power MOSFET measured by the high temperature sensor j (Called HS in Figure 4 ) reaches the absolute threshold T j_SD (For example, equal to 180 °C), thermal shutdown protection can be triggered.

[0187] In this case, the power MOSFET 308 is turned off until the junction temperature T j (HS) cools to the first thermal shutdown reset threshold T j_SD_R , where such first thermal shutdown reset threshold T j_SD_R Is equal to the absolute threshold T j_SD Minus 7 °C, i.e., T j_SD_R = T j_SD – 7 °C.

[0188] When the junction temperature T of the power MOSFET 308 j (HS) reaches the first thermal shutdown reset threshold T j_SD_R , such power MOSFET 308 can be turned on again.

[0189] When thermal protection is activated, i.e., when the power MOSFET 308 is turned off, a thermal shutdown diagnostic flag can be triggered, and when the temperature T j (HS) of the junction of the power MOSFET 308 reaches a second thermal shutdown reset threshold T j_SD_RS , the thermal shutdown diagnostic flag can be reset, where such a second thermal shutdown reset threshold T j_SD_RS is equal to the absolute threshold T j_SD minus 15 °C, i.e., T j_SD_RS = T j_SD - 15 °C.

[0190] It should be noted that when the thermal shutdown diagnostic flag is triggered, the current flowing in at least one such power MOSFET 308 is limited by the current limit value I limL rather than the current limit value I limH .

[0191] When the temperature T j (HS) of the junction of the power MOSFET measured by the high-temperature sensor reaches a relative threshold ΔT j_PL of approximately 80 °C considering the temperature of the chip, i.e., ΔT j_PL = T j – T chip = 80 °C, power limit protection can be triggered.

[0192] The temperature of the chip T chip can be measured using a low-temperature sensor, and thus it is referred to as CS in Figure 4 .

[0193] In such a case, the power MOSFET 308 is turned off until the relative temperature ΔT j measured between the power MOSFET 308 and the chip, i.e., ΔT j = T j – T chip , cools by 7 °C, and thus reaches the first power limit reset threshold ΔT j_PL_R = ΔT j_PL – 7 °C.

[0194] When the relative temperature ΔT j reaches the above value, such a power MOSFET 308 can be turned on again.

[0195] When thermal protection is activated (i.e., when the power MOSFET 308 is turned off), a power limit diagnostic flag can be triggered, and when the relative temperature ΔT j reaches a value equal to the second power limit reset threshold ΔT j_PL_RS = ΔT j_PL – 15 °C, the power limit diagnostic flag can be reset.

[0196] If the CCM mode is active, the relative threshold ΔT j_PL can be reduced to 35 °C (instead of 80 °C), and the current flowing in at least one such power MOSFET 308 is limited by the current limit value I limL (for example, equal to forty percent (40%) of the current limit value I limH ).

[0197] The relative temperature ΔT in the above situation j remains unchanged, i.e., equal to ΔT j_PL_R = ΔT j_PL – 7 °C to turn on the power MOSFET 308 again, and equal to ΔT j_PL_RS = ΔT j_PL – 15 °C to reset the power limit diagnostic flag.

[0198] It should be noted that if the CCM mode is active, the first thermal shutdown reset threshold T j_SD_R and the second thermal shutdown reset threshold T j_SD_RS also remain unchanged.

[0199] If the temperature of the junction of at least one such power MOSFET 308 increases to an operating temperature T O above by an amount higher than the selected thermal increase limit value ΔT PL (included in the first set of limit values LV 1 ), reaching the relative threshold ΔT j_PL , then the driving step (for example, performed using the PWM engine 1008) included in the controller block 306 can drive at least one power MOSFET 308 to be non-conductive. Thus, the output current I OUT and the output voltage V OUT reach values that are substantially zero (considering the given tolerances).

[0200] When at least one power MOSFET 308 is in the non-conductive state, its (junction) temperature begins to decrease.

[0201] When the amount of such temperature decrease is equal to / higher than a given temperature amount (for example, 7 °C), i.e., reaching the first power limit reset threshold ΔT j_PL_R , causing the actual temperature of at least one such power MOSFET 308 to be less than the operating temperature T O by the selected thermal increase limit value ΔT PLWhen the number of the sums is equal to such a given number of temperatures, at least one such power MOSFET 308 can be restarted by, for example, a PWM engine 1008 configured to be included again in the driving step in the execution controller block 306 so as to turn at least one such power MOSFET 308 into a conductive state again, causing a corresponding output current I OUT and an output voltage V OUT , where I OUT has a value equal to a selected current limit value I limL flowing therein, and the output voltage V OUT has a value equal to V O applied thereto.

[0202] It should be noted that within the time required to complete the pre-charging of the capacitive load, i.e., until the end charging time EC (e.g., about 100 milliseconds after the start charging time SC), the CCM mode can be active.

[0203] After such an end charging time EC, the CCM mode can be disabled, and at least one power MOSFET 308 can be configured to drive a corresponding load in a "normal" mode (i.e., the mode used when the capacitive load has been pre-charged), so that a current with an operating value I O flows therein and a voltage with an operating value V O is applied thereto.

[0204] Therefore, the technical solution described herein can provide compatibility with a capacitive load (or a load having a (even large) capacitive component to be pre-charged) by enabling the operation of at least one power MOSFET 308 included in the channel of the high-side driver 20 in the CCM mode, thus providing a wider load compatibility and further reducing the number of components used.

[0205] In addition, by performing the pre-charging of the capacitive component of the load coupled to one or more power MOSFETs through the current flowing in such a power MOSFET, such a current is limited to a predetermined value (i.e., the value included in the first set of limit values LV 1 ), and by limiting a predetermined value that can affect the thermal increase of such a power MOSFET (i.e., again the value included in the first set of limit values LV 1 ), thus facilitating the charging of a (even large) capacitive load in certain time ranges, reducing the critical reference to ground, and enabling such a CCM mode without the intervention of an external finishing unit (such as a microcontroller, a microprocessor, a logic unit, etc.).

[0206] In addition, limited by the thermal increase that can affect the power MOSFET and the value of the current flowing in such a power MOSFET, even under high ambient temperature conditions, such a CCM mode can be used for capacitive loads with relatively large capacitive components.

[0207] In addition, by changing the limiting values that can affect the thermal increase of the power MOSFET and the current flowing in such a power MOSFET, it may be possible to complete the pre-charging of the capacitive components of the load within a given (desired) time.

[0208] In summary, the driver device 20 as described herein may include additional modules (e.g., implemented in an additional CCM module (e.g., included in the E-Fuse 200)), configured to:

[0209] For example, receive, in the check block 300, a start signal CCM indicating whether one or more of the plurality of channels CH are coupled to a load (one or more loads) including a capacitive component candidate for pre-charging ON / OFF ;

[0210] For example, in response to the start signal CCM ON / OFF indicating that one or more of the plurality of channels CH are coupled to a load (one or more loads) including a capacitive component candidate for pre-charging, select, in the first setting block 302, a first set of limiting values LV of the driver operation parameters 1 ; and

[0211] For example, in response to the start signal CCM ON / OFF indicating that no channel among the plurality of channels CH is coupled to a load including a capacitive component candidate for pre-charging, select, in the second setting block 304, a second set of limiting values LV for the driver operation parameters 2 , the second set of limiting values LV 2 including limiting values that are higher than or equal to the limiting values in the first set of limiting values LV 1 .

[0212] The control module 1008, the control module 306 may be configured to:

[0213] Based on the start signal CCM ON / OFF receive, from the additional module CCM, the first set of limiting values LV 1 or the second set of limiting values LV 2 ;

[0214] Receive a feedback signal FS, where the feedback signal FS provides an actual value for drive operation parameters other than the drive operation parameters, and the actual value is associated with one or more channels among a plurality of channels CH coupled to a (one or more) load including a capacitive component candidate for pre-charging; and

[0215] Based on the feedback signal FS and based on the first set of limit values LV 1 or the second set of limit values LV 2 Drive one or more channels among the plurality of channels CH coupled to a (one or more) load including a capacitive component candidate for pre-charging according to the limit values therein.

[0216] The drive operation parameters may include:

[0217] The current flowing within one or more channels among the plurality of channels CH coupled to a (one or more) load including a capacitive component candidate for pre-charging; and

[0218] The heat increase affecting one or more channels among the plurality of channels CH coupled to a (one or more) load including a capacitive component candidate for pre-charging, where the heat increase is an excess that affects the temperature of one or more channels among the plurality of channels CH coupled to a (one or more) load including a capacitive component in response to the capacitive component being pre-charged.

[0219] In addition, the electronic fuse 200 may be configured to perform a protection operation selected from the following:

[0220] Harness protection, where the electronic fuse 200 may be configured to disable the harness protection based on a function enable / disable signal S generated in response to the start signal CCM ON / OFF ; and / or ON / OFF Non-delayed thermal shutdown auto-restart, where the electronic fuse 200 may be configured to enable the non-delayed thermal shutdown auto-restart based on the function enable / disable signal S

[0221] ON / OFF Enable the non-delayed thermal shutdown auto-restart.

[0222] The E-Fuse 200 included in the high-side driver 20 as described herein may advantageously be configured to implement additional protection functions, for example, including one or more BISTs ("built-in self-tests") for checking whether the ADC 1004 or the harness protection is working properly (e.g., performing such a check each time the device under monitoring exits the standby state).

[0223] ​Such additional protection features can be useful, for example, in an automobile because more and more applications and / or devices need to be safety-related or compliant with ISO ("International Organization for Standardization"), and thus, more software and hardware countermeasures may help to achieve the ASIL ("Automotive Safety Integrity Level") level.

[0224] To comply with ISO 26262 (which defines the functional safety of automotive equipment throughout the entire life cycle of automotive electronic and electrical safety-related systems), safety mechanisms (such as replication / lockstep, DCLS, and logical triple, TMR, etc.) can be used, but such mechanisms may have a significant impact on silicon area, power, and cost.

[0225] Therefore, technical solutions that are often considered include using circuit devices that can be used for both functional safety and manufacturing testing, including structures such as BIST.

[0226] Built-in self-test (BIST) is a structural test method that can be used as a safety mechanism for functional safety and adds logic to an integrated circuit (IC) to periodically test its own operation to check whether the functional safety requirements are met.

[0227] However, known BIST structures may suffer from potential fault detection on the ADC and may not be able to evaluate the FIT ("Failure in Time") rate / coverage, and thus do not meet the ASIL level B.

[0228] The technical solutions described herein can facilitate solving such problems of potential fault detection on the analog-to-digital converter (e.g., using ADC BIST), and can facilitate improving the FIT ("Failure in Time") rate and reliability of the wire harness protection analog comparator (e.g., using I2t BIST). Therefore, the technical solutions described herein can achieve the ASIL level B.

[0229] The technical solutions described herein can include:

[0230] A first BIST circuit device B 1 , for checking whether the functional safety requirements of an ADC (e.g., ADC 1004 included in the high-side driver 20) are met, and

[0231] A second BIST circuit device B 2 , for checking whether the functional safety requirements of the wire harness protection analog comparator (e.g., the wire harness protection analog comparator of the E-Fuse 200) are met.

[0232] Therefore, the BIST circuit devices (collectively referred to as B) of the technical solutions described herein can provide an automatic check of the health of the ADC conversion and the wire harness protection analog comparator over the operating life of the corresponding device.

[0233] For example, such a BIST circuit device B can be configured to perform such an inspection operation each time a POR ("power-on reset") signal is generated, i.e., each time the corresponding device exits the standby mode.

[0234] It should be noted that the first BIST circuit B 1 and the second BIST circuit B 2 can be considered independently, so the high-side driver 20 can include only one of the two BISTs or both of them.

[0235] The first BIST circuit device B 1 is configured to suppress, during the duration of the operation performed by such a first BIST circuit device B 1 the feedback information received by the ADC 1004 from the current sensing block 1020 regarding the sensed current flowing in each of the channels.

[0236] The first BIST circuit device B 1 is configured to generate, for example, three different current signals indicating different current levels, i.e., a low reference current LC, a medium reference current MC, and a high reference current HC, from the same reference current signal, and supply such three current signals to the corresponding input terminals of a first multiplexer included in, for example, such a first BIST B 1 circuit device.

[0237] Therefore, the ADC 1004 can be further configured to sequentially receive the low reference current LC, the medium reference current MC, and the high reference current HC from the output terminal of the first multiplexer, and for each received reference current, it can be configured to convert the received reference current into a corresponding current digital value.

[0238] The current digital value obtained from such a conversion can be sent to the first BIST circuit device B 1 (e.g., sent to the first BIST digital component of such a first BIST circuit device B 1 ) and stored in the corresponding ADC BIST register included in such a first BIST digital component, so that:

[0239] The first ADC BIST register included in such a first BIST digital component of the first BIST circuit device B 1 can be configured to store the current digital value corresponding to the low reference current LC converted by the ADC 1004, and such a current digital value is a low-level digital current value for self-testing,

[0240] The second ADC BIST register included in such a first BIST digital component may be configured to store a current digital value corresponding to a mid-reference current MC converted by the ADC 1004, such a current digital value being a mid-level digital current value for self-testing, and

[0241] The third ADC BIST register included in such a first BIST digital component may be configured to store a current digital value corresponding to a high-reference current HC converted by the ADC 1004, such a current digital value being a high-level digital current value for self-testing.

[0242] Thus, a first BIST finishing unit (e.g., included inside or outside the first BIST circuit B 1 such as a logic unit, microcontroller, microprocessor, etc.) may be configured to read the digital current values for self-testing stored in such corresponding ADC BIST registers and compare such digital current values with a current acceptance mask.

[0243] For example, such a current acceptance mask may contain the current digital values expected from the ADC conversion.

[0244] Thus, if the digital current value stored in such a corresponding ADC BIST register is equal to the value of the current acceptance mask, the BIST operation performed by the first BIST circuit device B 1 may be regarded as successful, and the functional safety requirements of the analog-to-digital converter 1004 may be regarded as being met.

[0245] Otherwise, if the digital current value stored in such a corresponding ADC BIST register is different from the value of the current acceptance mask, the BIST operation performed by the first BIST circuit device B 1 may be regarded as a failure, and there may be an abnormal condition, and thus, the functional safety requirements of the analog-to-digital converter 1004 may be regarded as not being met.

[0246] For example, an R&C (i.e., "Read and Clear") command may be sent by such a first BIST finishing unit to the corresponding ADC BIST register containing the digital current value in order to detect any stuck bits.

[0247] Such a sending of the R&C command may allow an external finishing unit (such as an external microcontroller, etc.) to read the register value and at the same time reset the content of such a register to a default content, for example, reset to a content all containing zeros.

[0248] Thus, in any case of logical stuck (low or high), the R&C command may allow detection of register hardware faults.

[0249] At the end of such an inspection operation (and thus, at the end of the first BIST B 1 operation), the first BIST circuit device B 1 is further configured to suppress the low reference current LC, the medium reference current MC, and the high reference current HC, and to restore the feedback information regarding the sensed current flowing in each of the channels received by the ADC1004 from the current sensing block 1020. Thus, the ADC is again configured to operate as described Figure 2 for the operation.

[0250] It should be noted that such a configuration can be maintained until the next power-on reset POR of the ADC 1004 when a further BIST operation is performed by the first BIST circuit device B 1

[0251] In summary, the driver device 20 as described herein may include:

[0252] a current sensing block 1020 configured to sense the current flowing in the channels of a plurality of channels CH; and

[0253] an analog-to-digital converter ADC 1004 configured to receive the channel current sensed for the channels of a plurality of channels CH and to convert the sensed channel current into a digital channel current signal.

[0254] The control module 1008 may be configured to generate one or more channel control signals based on the digital channel current signals corresponding to the one or more channels to operate one or more channels of the plurality of channels CH, and wherein the electronic fuse 200 includes an ADC built-in self-test BIST circuit device (i.e., such a first BIST circuit device B 1 ) configured to perform a self-test for meeting the functional safety requirements in the analog-to-digital converter 1004.

[0255] The ADC BIST circuit device (i.e., such a first BIST circuit device B 1 ) may be configured to:

[0256] generate a plurality of reference current signals indicating different reference current levels (e.g., a low reference current LC, a medium reference current MC, and a high reference current HC), and

[0257] provide the plurality of reference current signals (e.g., such low LC, medium MC, and high HC reference currents) to the analog-to-digital converter 1004.

[0258] ​The analog-to-digital converter 1004 can be configured to receive multiple reference current signals and convert them into digital reference current signals, and the ADC BIST circuitry (i.e., such a first BIST circuitry B 1 ), can be configured to perform the self-test regarding meeting the functional safety requirements in the analog-to-digital converter 1004 by:

[0259] Receiving the digital reference current signal and comparing it with a current acceptance mask,

[0260] In response to the digital reference current signal matching the current acceptance mask, considering the functional safety requirements in the analog-to-digital converter 1004 as being met, and in response to the digital reference current signal failing to match the current acceptance mask, considering the functional safety requirements in the analog-to-digital converter 1004 as not being met.

[0261] It should be noted that the ADC BIST circuitry can be configured to disable the current sensing performed by the current sensing block 1020 during the self-test regarding meeting the functional safety requirements in the analog-to-digital converter 1004.

[0262] The second BIST circuitry B 2 is configured to disable the harness protection of the E-Fuse 200 during the duration of the operation performed by such a second BIST circuitry B 2 .

[0263] The second BIST circuitry B 2 is configured to generate, for example, three different voltage levels from the same reference voltage level, namely a first (low) reference voltage level LV, a second (medium) reference voltage level MV, and a third (high) reference voltage level HV, and apply such three different voltage levels to the corresponding input terminals of the second multiplexer 500.

[0264] For example, Figure 5 shows a second BIST (“built-in self-test”) circuitry B for checking the functional safety of the harness protection analog comparator in the high-side driver 20 according to an embodiment of the present specification 2 portion.

[0265] In fact, Figure 5 shows a coupling 50 between such a second multiplexer 500 and the ADC 1004, where such a second multiplexer is configured to receive the low reference voltage level LV, the medium reference voltage level MV, and the high reference voltage level HV.

[0266] It should be noted that such an ADC 1004 can be of any known type, for example (by way of example only and without limiting the scope of protection of this document) it can include:

[0267] The analog part includes multiple comparators (504 0 , ..., 504 N-1 ,504 N , collectively referred to as 504), a plurality of comparators are configured to convert a voltage input signal V to be converted into a digital value MPX and multiple voltage reference signals (V REF0 , ..., V REFN-1 、V REFN , collectively referred to as V REF ) for comparison, and

[0268] The logic part 502 includes a plurality of XOR operators (506 0 , ..., 506 N-2 ,506 N-1 , collectively referred to as 506), the plurality of XOR operators are configured to receive the outputs of such a plurality of comparators 504 and perform XOR operations on such outputs to obtain a plurality of comparison values ​​(COMP 0 、...、COMP N-2 、COMP N-1 , collectively referred to as COMP), and the last converter 504 by inverting 508 N The logic level of the output is obtained by comparing the value COMP N , such a comparison value is further processed (for example, using an encoder) to obtain such a voltage input signal V MPX digital representation.

[0269] It should be noted that such a structure can be easily adapted to obtain the first BIST circuit device B 1 An equivalent diagram of, for example, by converting a voltage signal into a current signal, or converting a current level into a voltage level and then using the same structure.

[0270] Therefore, the ADC 1004 can also be configured to sequentially receive the low reference voltage level LV, the middle reference voltage level MV and the high reference voltage level HV from the output terminal of the second multiplexer 500 (for example, where such a sequence is obtained using a multiplexer control signal including two bits r0 and r1), and for each received reference voltage V MPX , which can be configured to receive a reference voltage V MPX Convert to the corresponding voltage digital value.

[0271] Therefore, after a conversion delay, the voltage digital value obtained from such a conversion can be sent to the second BIST circuit device B 2, for example, sent to such a second BIST circuit device B 2 of the second BIST digital component and stored in the corresponding wire harness BIST register included in such a second BIST digital section, thus:

[0272] The first wire harness BIST register included in such a second BIST digital component of the second BIST circuit device B 2 can be configured to store the voltage digital value corresponding to the low reference voltage level LV converted by the ADC 1004,

[0273] The second wire harness BIST register included in such a second BIST digital component can be configured to store the voltage digital value corresponding to the medium reference voltage level MV converted by the ADC 1004, and

[0274] The third wire harness BIST register included in such a second BIST digital component can be configured to store the voltage digital value corresponding to the high reference voltage level HV converted by the ADC 1004.

[0275] Therefore, the second BIST finishing unit (for example, included inside or outside the second BIST circuit B 2 such as a logic unit, a microcontroller, a microprocessor, etc.) can be configured to read the voltage digital values stored in such corresponding wire harness BIST registers and compare such voltage digital values with a voltage acceptance mask.

[0276] It should be noted that if both BIST circuit devices are present in the same high-side driver 20, such a second BIST finishing unit can be a shared finishing unit between such a second BIST circuit device B 2 and the first BIST circuit device B 1 thus saving additional components.

[0277] For example, such a voltage acceptance mask can contain the voltage digital values expected from the ADC conversion.

[0278] Therefore, if the voltage digital value stored in such a corresponding wire harness BIST register is equal to the value of the voltage acceptance mask, the BIST operation performed by the second BIST circuit device B 2 can be regarded as successful, and at least one corresponding bit can be set to a high logic level to indicate such a successful condition, thus regarding the functional safety requirements of the wire harness protection as being met.

[0279] Otherwise, if the digital value of the voltage stored in such a corresponding wire harness BIST register is different from the value of the voltage acceptance mask, the BIST operation performed by the second BIST circuit device B 2 can be regarded as a failure, and there can be an abnormal condition. Therefore, at least one corresponding bit can be set to a low logic level to indicate such an abnormal condition, and thus the functional safety requirement of the wire harness protection is regarded as not being met.

[0280] It should be noted that during the BIST operation performed by the second BIST circuit device B 2 multiple channels of the corresponding high-side driver 20 can be kept disabled until the end of such a BIST operation.

[0281] At the end of such an inspection operation (therefore, at the end of the second BIST B 2 operation), the second BIST circuit device B 2 is also configured to inhibit the multiplexer 500 by setting the multiplexer 500 to a high impedance, and the wire harness protection of the E-Fuse 200 is restored. Therefore, such an E-Fuse 200 is again configured to operate as described for Figure 2 the operation.

[0282] It should be noted that such a configuration can be maintained until the next power-on reset POR of the E-Fuse 200 when a further BIST operation is performed by the second BIST circuit device B 2 In summary, the electronic fuse 200 can be configured to provide wire harness protection. Therefore, such a driver device 20 as described herein can include a wire harness protection built-in self-test BIST circuit device (i.e., the second BIST circuit B

[0283] 2 ) which is configured to perform a self-test on whether the wire harness protection meets the functional safety requirements.

[0284] Figure 2 Therefore, the driver device 20 can include an analog-to-digital (ADC) converter, for example, Figure 2 the same ADC 1004 or a different ADC 1004, which is configured to receive one or more input signals and convert the one or more received input signals into a digital output signal, and the wire harness protection BIST circuit device (i.e., the second BIST circuit B 2 ) can be configured to:

[0285] generate multiple reference voltage signals indicating different voltage levels (e.g., a low reference voltage level LV, a medium reference voltage level MV, and a high reference voltage level HV), and

[0286] Provide the plurality of reference voltage signals to an analog-to-digital converter 1004, where the analog-to-digital converter 1004 may be configured to receive the plurality of reference voltage signals and convert them into digital reference voltage signals.

[0287] The harness protection BIST circuit device may be configured to perform the self-test by: the self-test regarding meeting the functional safety requirements through the harness protection.

[0288] Receive the digital reference voltage signal and compare it with a voltage acceptance mask, and

[0289] In response to the digital reference voltage signal matching the voltage acceptance mask, consider the functional safety requirements in the harness protection to be met, and in response to the digital reference voltage signal failing to match the voltage acceptance mask, consider the functional safety requirements in the harness protection to be unmet.

[0290] In addition, the harness protection BIST circuit device B2 may be configured to disable the harness protection provided by the electronic fuse 200 during the self-test regarding meeting the functional safety requirements in the harness protection.

[0291] It should be noted that the self-test regarding the functional safety requirements may be performed in response to a power-on reset (POR) signal (e.g., in response to the ADC 1004 or the harness protection exiting the standby mode).

[0292] Such a BIST circuit device included in the logic component 100 of such a high-side driver 20 is to be powered with a certain power (e.g., powered by a power supply architecture).

[0293] Such a power supply architecture may also be used to provide a continuous and stable voltage supply to other digital components of the high-side driver 20.

[0294] For example, in automotive applications, a battery failure or a short power supply interruption that interrupts the operation of such a BIST circuit device may occur, thus increasing the time required to perform the functional safety check and / or increasing the probability of a missed detection or a false detection.

[0295] In fact, in automotive applications, the power supply may come from the battery of the considered vehicle, and thus, the battery voltage level may be affected by failures, fluctuations, short interruptions, cranking, and oscillations in response to the types and numbers of electronic devices included and used in such a considered vehicle.

[0296] The digital components that regulate the operability and protection of such a high-side driver 20 (e.g., such a BIST circuit B as described herein 1 、B 2 ) are stable and reliable in order to meet automotive standards.

[0297] In fact, for example, in response to an unreliable and unstable power supply architecture, there is an unreliable and unstable BIST circuit device B 1 、B 2 , which may lead to missed detections or delayed anomaly detections. For example, anomalies in the ADC 1004 or the analog comparator protected by the wire harness may be missed or detected late, resulting in possible critical situations.

[0298] Furthermore, if such a battery failure or short power supply interruption occurs when the ADC BIST register in the first BIST digital component of the first BIST circuit device B 1 or the wire harness BIST register in the second BIST digital component of the second BIST circuit device B 2 stores the corresponding current or voltage digital value, such a register may lose its content, thus resulting in a functional safety check failure during execution.

[0299] The first technical solution may be a digital component power supply structure using the power supply rail from the microcontroller, etc. However, such a technical solution can still suffer from fluctuations and instabilities in the supply voltage of such a microcontroller. Therefore, in the case of an unstable supply voltage, both the microcontroller and the corresponding digital components powered by it (such as the BIST circuit device B 1 and B 2 ) can be reset. For example, the ADC BIST register or the wire harness BIST register may lose its content.

[0300] Such a reset may not be a problem for the microcontroller (etc.) or for some of the digital components, but it can impair the correct operation of such BIST circuit devices B 1 and B 2 . For example, since the information in the wire harness BIST register included in the second BIST circuit device B 2 may be lost, it may lead to wire harness overheating and unpredictable failures.

[0301] For this purpose, according to an embodiment of the present specification, an enhanced digital power supply structure 60 is shown in Figure 6 .

[0302] It should be noted that advantageously, such an enhanced digital power supply structure 60 can also be used to power other digital components 620 included in the high-side driver (such as the high-side driver 20 described herein), so as to even obtain the advantages described for them.

[0303] Battery failures or short power supply interruptions are regulated by the LV124 specification (i.e., the specification that defines the test procedures for electronic and electrical vehicle components, including electrical tests, mechanical tests, weather tests, and duration tests), and as Figure 6 shown in

[0304] the enhanced digital power supply structure 60 can facilitate compliance with this specification.

[0305] Such a digital power supply structure 60 is based on the use of an external capacitor C coupled to the corresponding high-side driver 20 through a dedicated pin. Such an external capacitor C is also configured to supply power to the digital components of such a high-side driver 20 and to protect such digital components in the event of a battery failure or short power supply interruption, in order to increase the level of protection of the high-side driver 20 itself and the loads coupled thereto.

[0306] As previously described, such a protection function can also help to retain the information stored in the volatile registers during such battery failures or short power supply interruptions.

[0307] It should be noted that the architecture described below is configured to prevent the external capacitor C from discharging into the battery line when the condition V pre_reg >V bat is valid. In fact, the charge stored in the external capacitor C can only be used to supply power to the internal circuitry (i.e., the digital components 620) and is not wasted into the faulty battery line.

[0308] The vehicle battery can be configured to provide a global supply voltage V bat (e.g., a global supply voltage of about 13V), for example, in order to supply power to the components included in such a vehicle through the battery pin 614.

[0309] The device power supply unit (e.g., the power supply rail corresponding to a microcontroller, etc.) can be configured to receive the global supply voltage V bat , and generate a scaled supply voltage V DD , for example, a scaled supply voltage of about 5V.

[0310] Such a scaled supply voltage V DD can be provided to the scaled voltage pin 616. Such a scaled supply voltage V DD is the same voltage as the voltage for powering an external finishing unit (e.g., a microcontroller, etc.).

[0311] Thus, the digital power supply structure 60 includes a reference for such a scaled supply voltage V DD (i.e., the scaled voltage pin 616) in order to align with an external finishing unit and correctly receive communication from the SPI block 104, e.g., via digital pins (such as SDI, CNS, SCK, SDO, PWM CLK), which are internally powered by the voltage of the scaled voltage pin 616.

[0312] The digital power supply structure 60 described herein may receive from such a voltage supply (i.e., from a vehicle battery and a device power supply unit):

[0313] a scaled supply voltage V via the scaled voltage pin 616 DD ; and

[0314] a global supply voltage V via the battery pin 614 bat .

[0315] The digital power supply structure 60 may be configured to:

[0316] generate a pre-regulated voltage (i.e., the digital supply voltage V pre_reg ) from the battery pin 614 to the dedicated pin 608 via a voltage pre-regulator 600 and a switching circuit arrangement configured to implement internal active diodes 610 - 612; and

[0317] supply the digital supply voltage V pre_reg to an external capacitor C, such an external capacitor C being coupled, for example, between the dedicated pin 608 and the ground terminal 606 via a resistor R, thus increasing the amount of charge stored therein (i.e., charging it until it is substantially equal (taking into account a given tolerance) to the voltage level of such a digital supply voltage V pre_reg ).

[0318] The digital power supply structure 60 may be configured to forward the digital supply voltage V DD on such a dedicated pin 608 based on such a received scaled supply voltage V pre_reg . It should be noted that the coupling between the scaled voltage pin 616 and the dedicated pin 608 via the external diode 618 is optional.

[0319] The digital power supply structure 60 may further be configured (regardless of the operating conditions of the high-side driver 20) to supply the digital supply voltage V pre_reg to a voltage regulator unit 602 in order to facilitate the digital components 620 included in such a high-side driver 20 (e.g., including such BIST circuit arrangements B 1 and B 2)Power supply.

[0320] Thus, such a dedicated pin is a pin to which the output terminal of the voltage pre-regulator 600, the external capacitor C, and the input terminal of the voltage regulator unit 602 can all be coupled.

[0321] Thus, such a voltage regulator unit 602 can be configured to receive a voltage at its input terminal, which voltage is the voltage applied to such a dedicated pin, and thus:

[0322] If there are no malfunctions, fluctuations, short interruptions, cranks, and / or oscillations in the external power supply, the dedicated pin is set to be equal to the digital supply voltage V pre_reg supplied by the voltage pre-regulator 600; and

[0323] If there are malfunctions, fluctuations, short interruptions, cranks, and / or oscillations in the external power supply, such a voltage pre-regulator 600 cannot provide such a digital supply voltage V pre_reg , so the dedicated pin is powered by the capacitor voltage V C (i.e., the voltage applied to a network including the external capacitor C and resistor R and (optionally) from the external diode 618).

[0324] It should be noted that such a digital supply voltage V pre_reg and such a capacitor voltage V C (i.e., the voltage applied to the external capacitor C) can be equal under steady-state conditions.

[0325] In fact, such a voltage pre-regulator 600 and such an external capacitor C (through the resistor R) are coupled between the same nodes, i.e., between such a dedicated pin and the ground terminal 606, and thus under steady-state conditions, the digital supply voltage V pre_reg and the capacitor voltage V C have the same value.

[0326] In this way, the voltage applied to such a dedicated pin received by the voltage regulator unit 602 (through its input terminal) can be a substantially constant voltage (considering a given tolerance), because the digital supply voltage V pre_reg (if there are no abnormalities in the external power supply) and the capacitor voltage V C (if there are abnormalities in the external power supply) have the same value, thus facilitating the provision of a stable supply voltage to such a digital component 620.

[0327] In fact, the voltage regulator unit 602 is further configured to be based on the voltage applied to such a dedicated pin (i.e., the digital supply voltage V pre_reg and / or the capacitor voltage VC )Generate the circuit supply voltage V CC (e.g., a circuit supply voltage of about 3V), and supply such a circuit supply voltage V CC to the digital component 620 (e.g., including such a BIST circuit device B 1 and B 2 ), and to the LVD unit 604.

[0328] It should be noted that the optional external active diode 618 can facilitate synchronization between the dedicated pin 608 and the scaled voltage pin 616 (e.g., coupled to the supply rail of the corresponding finishing unit (e.g., a microcontroller, etc.)).

[0329] The internal active switch 610 (e.g., MOSFET ("Metal Oxide Semiconductor Field Effect Transistor"), BJT ("Bipolar Junction Transistor"), etc.) can be configured to have its current drain terminal coupled to the pre-regulator unit 600, its current source terminal coupled to the dedicated pin 608 and to the voltage regulator unit 602, and its control terminal coupled to the output terminal of the amplifier 612, which receives at its input terminals the voltage value provided by the pre-regulator unit 600 and the voltage value visible on the dedicated pin 608.

[0330] Such an internal active switch 610 and such an amplifier 612 can be configured to implement an internal active diode 610-612, which is configured to limit the discharge of the external capacitor C if the global supply voltage V bat supplied by the battery pin 614 drops in response to malfunction, fluctuations, short interruptions, cranking, and oscillations.

[0331] The pre-regulator unit 600 can be configured to receive the global supply voltage V from the battery pin 614 bat , and based on such a global supply voltage V bat operate the internal active diode 610-612. For example, if such a global supply voltage V bat drops, the pre-regulator unit 600 can be configured to turn off the internal active switch 610 so as to render the internal active diode 610-612 non-conductive, thereby limiting the discharge of the external capacitor C.

[0332] The LVD ("Low Voltage Detector") unit 604 is a protection module, which can be configured to disconnect the digital component 620 from the voltage regulator unit 602 to save battery power when the circuit supply voltage V of the voltage regulator 602 CC drops below the minimum supply voltage threshold of the digital component 620, and to facilitate the further startup of such a digital component 620 in response to sufficient power remaining in such a battery pin 614.

[0333] It should be noted that even in the presence of failures, fluctuations, short interruptions, cranks and / or oscillations of the external power supply, such a circuit supply voltage V provided by the voltage regulator unit 602 CC can be kept stable.

[0334] In fact, if the digital supply voltage V pre_reg is substantially equal (considering a given tolerance) to the capacitor voltage V C , then the voltage received as input by such a voltage regulator unit 602 (i.e., the voltage applied to such a dedicated pin) (therefore, such a digital supply voltage V pre_reg or such a capacitor voltage V C ) can be constant and not affected by such failures, fluctuations, short interruptions, cranks and / or oscillations of the external power supply.

[0335] In fact, even when the global supply voltage V bat drops, the pre - regulator unit 600 can, for example, disconnect the internal active switch 610 so as to make the internal active diode 610 - 612 non - conductive, in order to limit the discharge of the external capacitor C, and thus attempt to maintain the voltage applied to such a dedicated pin (i.e., the capacitor voltage V C ) stable.

[0336] Therefore, in response to the drop of the global supply voltage V powered by the battery pin 614 bat , the voltage regulator unit 602 can be configured to generate the circuit supply voltage V based on a substantially constant (considering a given tolerance) voltage applied to such a dedicated pin CC , thus providing a more stable (and uninterrupted) voltage supply to such digital components 620.

[0337] Therefore, the technical solution described herein can advantageously provide:

[0338] Preserving the content of volatile registers (such as the ADC BIST register included in the first BIST digital component of the first BIST circuit B 1 and / or the harness BIST register included in such a second BIST digital component of the second BIST circuit B 2 ), because the voltage supplying such digital components 620 (i.e., the circuit supply voltage V CC ) can be more stable and not affected by changes in the global supply voltage V powered by the battery pin 614 bat ;

[0339] Improved protection reliability, for example, such as improving the BIST circuit device B 1 and B2 reliability, as without loss of supply voltage, e.g., BIST circuit B as described herein 1 device and B 2 can prevent missed or late anomaly detections; and / or

[0340] The independence of the voltage regulator unit 602 (i.e., the independence of the unit configured to supply power to such digital component 620) is not affected by the external power supply, because in the case of failure, fluctuation, short interruption, crank, and / or oscillation of the external power supply, the voltage regulator unit 602 can still be configured to supply a substantially stable (considering a given tolerance) circuit supply voltage V to such digital component 620 within a given time (such time depends on the time required for the discharge of the external capacitor C). CC , because the capacitor voltage V applied to the external capacitor C C can compensate for the changes in the voltage provided by the external power supply.

[0341] It should be noted that the slower the discharge of the external capacitor C, the longer the time during which the voltage regulator unit 602 can still be able to supply a substantially stable circuit supply voltage V CC to such digital component 620.

[0342] In summary, the technical solution described herein may include:

[0343] A voltage pre-regulator 600, configured to generate a pre-regulated supply voltage (e.g., digital supply voltage V pre_reg ) for device 20;

[0344] A capacitor, such as external capacitor C, coupled to a dedicated pin 608, and capacitor C can be configured to be charged to a capacitor charging voltage equal to the pre-regulated supply voltage V pre_reg (i.e., capacitor voltage V C ); and

[0345] A switching circuit device, such as active diodes 610 - 612, which is coupled to the voltage pre-regulator 600 through the switching circuit device 610 - 612 and is configured to detect the voltage drop in the pre-regulated supply voltage V pre_reg , and in response to detecting the voltage drop in the pre-regulated supply voltage V pre_reg , resist the discharge of capacitor C relative to the charging voltage V equal to the pre-regulated supply voltage V pre_reg . C

[0346] In addition, a power supply unit (e.g., scaled voltage pin 616) can be configured to:

[0347] ​Based on the battery supply voltage (e.g., the global supply voltage V bat ), receive a scaled supply voltage V DD ; and

[0348] in the driver device 20, apply the scaled supply voltage V DD to a dedicated pin 608, for example, via an external diode 618, to generate the pre-regulated supply voltage V DD from the scaled supply voltage V pre_reg .

[0349] The technical solutions described herein facilitate the implementation of a driver device (e.g., a high-side driver device) that includes: a plurality of channels configured to drive one or more loads (e.g., electrical loads); and a control module configured to generate one or more channel control signals to operate one or more corresponding channels.

[0350] Such a device may further include: an electronic fuse (“E-Fuse”) configured to monitor one or more parameters of such channels and use such one or more monitored parameters to detect abnormal channel conditions; and a parallel mode block configured to define one or more groups of channels (including at least two channels).

[0351] It should be noted that the channels in the same group of channels defined by such a parallel mode block are configured to drive the same load.

[0352] In addition, the control module of the technical solutions described herein may further be configured to receive management control signals from the parallel mode block and operate the channels in one or more groups of channels based on the received management control signals, and the electronic fuse of the technical solutions described herein may further be configured to render the channels in the same group of channels non-conductive in response to detecting abnormal conditions in one or more channels included in the same group of channels.

[0353] In an embodiment, the high-side driver device described herein may include an additional module configured to provide compatibility with a load including one or more capacitive components to be pre-charged.

[0354] In an embodiment, the high-side driver device described herein may include one or more BIST circuit devices configured to check whether the functional safety requirements of the analog-to-digital converters and / or implemented harness protection included therein are met.

[0355] In an embodiment, the high-side driver device described herein may include an enhanced digital power supply including a capacitor configured to be charged to supply power to a dedicated pin in the event of a drop in the global supply voltage.

[0356] Thus, the techniques described herein facilitate reducing the number of high-side drivers integrated within a single silicon device without degrading robustness and compatibility with loads having different current requirements, in order to reduce the footprint and the number of circuit devices used, while still providing compatibility with different types of loads.

[0357] Moreover, embodiments of the techniques described herein can facilitate providing additional compatibility with loads that include one or more capacitive components (even during their pre-charge phase).

[0358] Embodiments of the techniques described herein can facilitate implementing additional protection in the high-side driver device as described herein.

[0359] Embodiments of the techniques described herein can also facilitate providing a continuous and stable voltage supply for digital components of the high-side driver device as described herein (e.g., including such implemented additional protection).

[0360] Without affecting the basic principles, and without departing from the scope of the embodiments, details and embodiments can vary, even significantly, from what is described by way of example only.

[0361] The scope of protection is determined by the appended claims.

[0362] A device (20) can be generally summarized as including: a plurality of channels (CH) configured to drive at least one electrical load; and a control module (1008) configured to generate at least one channel control signal to operate at least one of the plurality of channels (CH), wherein the device (20) includes: an electronic fuse (200) configured to monitor at least one parameter in a respective one of the plurality of channels (CH) and detect an abnormal condition in the respective channel based on at least one monitored parameter; and a parallel mode block (202) configured to define at least one set of channels including at least two of the plurality of channels (CH), the channels in the at least one set of channels being configured to drive the same load, wherein: the control module (1008) is configured to receive a parallel mode management control signal from the parallel mode block (202) and operate the channels in the at least one set of channels based on the parallel mode management control signal received by the parallel mode block (202); and the electronic fuse (200) is configured to render the channels in the at least one set of channels non-conductive in response to detecting an abnormal condition in at least one of the channels in the at least one set of channels.

[0363] The device (20) can include a channel control register configured to store therein configuration parameters for a respective one of the plurality of channels (CH).

[0364] The channel control registers of the channels in at least one set of channels can be configured to store therein the same configuration parameters for the corresponding channels in the at least one set of channels, and the control module (1008) can be configured to receive a parallel mode management control signal from the parallel mode block (202) based on the same configuration parameters.

[0365] The channel control registers of the channels in at least one set of channels can be configured to: receive an update request for the same configuration parameters at an update control register outside the channel control registers of the channels in the at least one set of channels; update the same configuration parameters in the channel control registers of the channels in the at least one set of channels in response to receiving the update request at the update control register; and ignore other update requests for the same configuration parameters received at the channel control registers of the channels in the at least one set of channels that are different from the update control register.

[0366] The apparatus (20) may include an additional module (CCM) configured to: receive (300) a start signal (CCM ON / OFF ) indicating whether at least one of a plurality of channels (CH) can be coupled to a load including a capacitive component candidate for precharging; select (302) a first set of limit values (LV ON / OFF ) of driver operation parameters in response to the start signal (CCM 1 ) indicating that at least one of the plurality of channels (CH) can be coupled to a load including a capacitive component candidate for precharging; and select (304) a second set of limit values (LV ON / OFF ) of driver operation parameters in response to the start signal (CCM 2 ) indicating that none of the plurality of channels (CH) can be coupled to a load including a capacitive component candidate for precharging, the second set of limit values (LV 2 ) including limit values that are higher than or equal to the limit values in the first set of limit values (LV 1 ), and wherein the control module (1008; 306) can be configured to: receive from the additional module (CCM) the first set of limit values (LV ON / OFF ) or the second set of limit values (LV 1 ) based on the start signal (CCM 2 ); receive a feedback signal (FS) providing an actual value of a driver operation parameter other than the driver operation parameter, the actual value being related to at least one of the plurality of channels (CH) coupled to a load including a capacitive component candidate for precharging; and drive at least one of the plurality of channels (CH) coupled to a load including a capacitive component candidate for precharging based on the feedback signal (FS) and based on the limit values in the first set of limit values (LV 1 ) or the second set of limit values (LV 2 ).

[0367] The drive operation parameters may include: a current flowing in at least one of a plurality of channels (CH), at least one channel being coupled to a load including a capacitive component candidate for pre - charging; and a thermal increase affecting at least one of the plurality of channels (CH), at least one channel being coupled to a load including a capacitive component candidate for pre - charging, the thermal increase being an excess that affects the temperature of at least one of the plurality of channels (CH) in response to the capacitive component being pre - charged, at least one channel being coupled to a load including a capacitive component.

[0368] The electronic fuse (200) may be configured to perform a protection operation selected from: harness protection, wherein the electronic fuse (200) may be configured to disable harness protection based on a function enable / disable signal (S ON / OFF ) generated in response to a start signal (CCM ON / OFF ); and / or non - delayed thermal shutdown auto - restart, wherein the electronic fuse (200) may be configured to enable non - delayed thermal shutdown auto - restart based on the function enable / disable signal (S ON / OFF ).

[0369] The device (20) may include: a current sensing block (1020) configured to sense a current flowing in a channel among a plurality of channels (CH); and an analog - to - digital converter ADC (1004) configured to receive the sensed channel current for the channels among the plurality of channels (CH) and convert the sensed channel current into a digital channel current signal, wherein a control module (1008) may be configured to generate at least one channel control signal based on the digital channel current signal corresponding to at least one channel to operate at least one of the plurality of channels (CH), and wherein the electronic fuse (200) may include an ADC built - in self - test BIST circuit device (B 1 ) configured to perform a self - test regarding meeting the functional safety requirements in the analog - to - digital converter (1004).

[0370] The ADC BIST circuit device (B1) may be configured to: generate a plurality of reference current signals (LC; MC; HC) indicating different reference current levels; and provide the plurality of reference current signals (LC; MC; HC) to the analog - to - digital converter (1004), wherein the analog - to - digital converter (1004) may be configured to receive the plurality of reference current signals (LC; MC; HC) and convert them into digital reference current signals, and wherein the ADC BIST circuit device (B 1) can be configured to perform a self - test regarding the functional safety requirements met in the analog - to - digital converter (1004) by: receiving a digital reference current signal and comparing it with a current acceptance mask; and in response to the digital reference current signal matching the current acceptance mask, considering the functional safety requirements in the analog - to - digital converter (1004) as met, and in response to the digital reference current signal failing to match the current acceptance mask, considering the functional safety requirements in the analog - to - digital converter (1004) as not met.

[0371] The ADC BIST circuit device (B1) can be configured to disable the current sensing performed by the current sensing block (1020) during a self - test regarding the satisfaction of functional safety requirements in the analog - to - digital converter (1004).

[0372] The electronic fuse (200) can be configured to provide harness protection and includes a built - in self - test BIST circuit device (B2) for harness protection, which is configured to perform a self - test regarding the satisfaction of functional safety requirements for harness protection.

[0373] The device (20) can include an analog - to - digital ADC converter (1004), which is configured to receive at least one input signal and convert the received at least one input signal into a digital output signal, and wherein the harness protection BIST circuit device (B 2 ) can be configured to: generate a plurality of reference voltage signals (LV; MV; HV) indicating different voltage levels; and provide the plurality of reference voltage signals (LV; MV; HV) to the analog - to - digital converter (1004), wherein the analog - to - digital converter (1004) is configured to receive the plurality of reference voltage signals (LV; MV; HV) and convert them into a digital reference voltage signal, and wherein the harness protection BIST circuit device (B 2 ) can be configured to perform a self - test regarding the satisfaction of functional safety requirements for harness protection by: receiving the digital reference voltage signal and comparing it with a voltage acceptance mask; and in response to the digital reference voltage signal matching the voltage acceptance mask, considering the functional safety requirements in the harness protection as met, and in response to the digital reference voltage signal failing to match the voltage acceptance mask, considering the functional safety requirements in the harness protection as not met.

[0374] The harness protection BIST circuit device (B2) can be configured to disable the harness protection provided by the electronic fuse (200) during a self - test regarding the satisfaction of functional safety requirements in the harness protection.

[0375] A self - test regarding functional safety requirements can be performed in response to a power - on reset signal.

[0376] The device (20) may include: a voltage pre-regulator (600) configured to generate a pre-regulated supply voltage (V pre_reg ) for the device (20); a capacitor (C) coupled to a dedicated pin (608), the capacitor (C) being configured to be charged to a capacitor charging voltage (V pre_reg ) equal to the pre-regulated supply voltage (V C ); and switching circuitry (610 - 612) coupled to the voltage pre-regulator (600), the switching circuitry (610 - 612) being configured to detect a voltage drop in the pre-regulated supply voltage (V pre_reg ) and, in response to detecting the voltage drop in the pre-regulated supply voltage (V pre_reg ), resist discharge of the capacitor relative to the charging voltage (V pre_reg ) equal to the pre-regulated supply voltage (V C ), wherein the switching circuitry (610 - 612) is further configured to detect a voltage drop on a battery line (V bat ) coupled to the voltage pre-regulator (600) and, in response to the detection, avoid discharge of the capacitor (C).

[0377] The device (20) may include a supply pin (616) configured to: receive a battery supply voltage through a battery pin (614); receive a scaled supply voltage (V bat ) based on the battery supply voltage (V DD ); and apply the scaled supply voltage (V DD ) to a dedicated pin (608) in the device (20) to generate a pre-regulated supply voltage (V DD ) from the scaled supply voltage (V pre_reg ) through a diode (618).

[0378] A method of operating a device (20) having at least one electrical load coupled to a plurality of channels (CH) to be driven, wherein the method may generally include: an electronic fuse (200) monitoring at least one parameter in a respective one of the plurality of channels (CH) and detecting an abnormal condition in the respective channel based on the at least one monitored parameter; a parallel mode block (202) defining at least one set of channels including at least two of the plurality of channels (CH); a control module (1008) receiving a parallel mode management control signal from the parallel mode block (202) and operating the channels in the at least one set of channels based on the parallel mode management control signal received by the parallel mode block (202); and the electronic fuse (200) rendering non-conductive the channels in the at least one set of channels in response to detecting an abnormal condition in at least one of the channels in the at least one set of channels.

[0379] The various embodiments described above can be combined to provide further embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in this specification and / or listed in the Application Data Sheet are hereby incorporated by reference in their entirety. Aspects of the embodiments may be modified as necessary to adopt the concepts of various patents, applications, and publications to provide yet further additional embodiments.

[0380] These and other changes may be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed so as to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to such claims being granted. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A device comprising: a plurality of channels configured to drive at least one electrical load; a control module configured to generate at least one channel control signal to operate at least one channel of the plurality of channels; an electronic fuse configured to monitor at least one parameter in a corresponding channel of the plurality of channels and detect an abnormal condition in the corresponding channel based on the at least one parameter; as well as a parallel mode block configured to define at least one group of channels including at least two channels of the plurality of channels, the channels of the at least one group of channels being configured to drive a same load, in: The control module is configured to receive a parallel mode management control signal from the parallel mode block and operate the channels of the at least one group of channels based on the parallel mode management control signal received by the parallel mode block, and The electronic fuse is configured to render a channel in the at least one group of channels non-conductive in response to an abnormal condition detected in at least one channel in the at least one group of channels.

2. The device according to claim 1, comprising: The channel control register is configured to store configuration parameters for corresponding channels among the plurality of channels in the channel control register.

3. The apparatus of claim 2 , wherein the channel control registers of the channels in the at least one group of channels are configured to store the same configuration parameters for the corresponding channels in the at least one group of channels in the channel control registers, and the control module is configured to receive a parallel mode management control signal from the parallel mode block based on the same configuration parameters.

4. The apparatus of claim 3, wherein the channel control registers of the channels in the at least one group of channels are configured as: receiving an update request for the same configuration parameter at an update control register outside the channel control register of the channel in the at least one group of channels; in response to receiving the update request at the update control register, updating the same configuration parameter in the channel control register of the channel in the at least one group of channels; as well as Other update requests for the same configuration parameter received at a channel control register of the channel in the at least one group of channels other than the update control register are ignored.

5. The device according to claim 1, comprising: Additional modules are configured to: receiving a start signal indicating whether at least one of the plurality of channels is coupled to a load including a capacitive component candidate for precharging; selecting a first set of limit values ​​for driver operating parameters in response to the start signal indicating that the at least one of the plurality of channels is coupled to the load including the capacitive component candidate for precharging; and In response to the start signal indicating that none of the plurality of channels is coupled to the load that includes the capacitive component candidate for precharging, selecting a second set of limit values ​​for the driver operating parameters, the second set of limit values ​​including limit values ​​that are higher than or equal to the limit values ​​in the first set of limit values, and The control module is configured as follows: receiving the first set of limit values ​​or the second set of limit values ​​from the additional module based on the start signal; receiving a feedback signal providing an actual value of a driver operating parameter other than the driver operating parameter, the actual value associated with the at least one channel of the plurality of channels coupled to the load including the capacitive component candidate for precharging; and The at least one channel of the plurality of channels is driven based on the feedback signal and based on the limit value in the first set of limit values ​​or the second set of limit values, the at least one channel being coupled to the load including the capacitive component candidate for precharging.

6. The apparatus of claim 5, wherein the driver operating parameters include: a current flowing in the at least one channel of the plurality of channels, the at least one channel coupled to the load including the capacitive component candidate for precharging; as well as A thermal increase affecting at least one of the plurality of channels, the at least one channel being coupled to the load including the capacitive component candidate for precharging, the thermal increase being an excess affecting a temperature of the at least one of the plurality of channels coupled to the load including the capacitive component candidate in response to the capacitive component candidate being precharged.

7. The apparatus of claim 5, wherein the electronic fuse is configured to perform a protection operation selected from: a wiring harness protection, wherein the electronic fuse is configured to disable the wiring harness protection based on a function enable / disable signal generated in response to the start signal; or A non-delayed thermal shutdown auto-restart is provided, wherein the electronic fuse is configured to enable the non-delayed thermal shutdown auto-restart based on the functional enable / disable signal.

8. The device according to claim 1, comprising: a current sensing block configured to sense a current flowing in the channel among the plurality of channels; as well as an analog-to-digital converter ADC configured to receive a channel current sensed for the channel among the plurality of channels and convert the sensed channel current into a digital channel current signal, wherein the control module is configured to generate at least one channel control signal based on the digital channel current signal corresponding to the at least one channel to operate at least one channel of the plurality of channels, and The electronic fuse comprises an ADC built-in self-test (BIST) circuit arrangement configured to perform a self-test on meeting functional safety requirements in the analog-to-digital converter.

9. The apparatus of claim 8, wherein the ADC BIST circuit arrangement is configured to: generating a plurality of reference current signals indicative of different reference current levels; and providing the plurality of reference current signals to the analog-to-digital converter, wherein the analog-to-digital converter is configured to receive the plurality of reference current signals and convert the plurality of reference current signals into digital reference current signals, and wherein the ADC BIST circuit arrangement is configured to perform the self-test regarding fulfillment of functional safety requirements in the analog-to-digital converter by: receiving the digital reference current signal and comparing the digital reference current to a current acceptance mask; and In response to the digital reference current signal matching the current acceptance mask, a functional safety requirement in the analog-to-digital converter is deemed satisfied, and in response to the digital reference current signal failing to match the current acceptance mask, a functional safety requirement in the analog-to-digital converter is deemed unsatisfied. 10 . The apparatus of claim 9 , wherein the ADC BIST circuitry is configured to disable current sensing by the current sensing block during the self-test regarding functional safety requirements being met in the analog-to-digital converter.

11. The apparatus of claim 1, wherein the electronic fuse is configured to provide harness protection and comprises a harness protection built-in self-test (BIST) circuit device configured to perform a self-test on functional safety requirements satisfied by the harness protection.

12. The apparatus according to claim 11, wherein the apparatus comprises an analog-to-digital converter (ADC) configured to receive at least one input signal and convert the at least one input signal into a digital output signal, and The wiring harness protection BIST circuit device is configured as follows: generating a plurality of reference voltage signals indicative of different voltage levels; and providing the plurality of reference voltage signals to the analog-to-digital converter, wherein the analog-to-digital converter is configured to receive the plurality of reference voltage signals and convert the plurality of reference voltage signals into digital reference voltage signals, and wherein the wiring harness protection BIST circuit arrangement is configured to perform the self-test on the functional safety requirements satisfied by the wiring harness protection by: receiving the digital reference voltage signal and comparing the digital reference voltage signal to a voltage acceptance mask; and In response to the digital reference voltage signal matching the voltage acceptance mask, a functional safety requirement in the harness protection is deemed satisfied, and in response to the digital reference voltage signal failing to match the voltage acceptance mask, a functional safety requirement in the harness protection is deemed unsatisfied.

13. The apparatus of claim 12, wherein the harness protection BIST circuitry is configured to disable harness protection provided by the electronic fuse during the self-test regarding functional safety requirements being met in the harness protection. 14 . The apparatus of claim 8 , wherein the self-test regarding functional safety requirements is performed in response to a power-on reset signal.

15. The apparatus according to claim 1, comprising: a voltage pre-regulator configured to generate a pre-regulated supply voltage for the device; a capacitor coupled to the dedicated pin, the capacitor being configured to be charged to a capacitor charging voltage equal to the pre-regulated supply voltage; as well as a switching circuit arrangement coupled to the voltage pre-regulator, the switching circuit arrangement being configured to detect a voltage drop in the pre-regulated supply voltage and, in response to detecting the voltage drop in the pre-regulated supply voltage, resist discharge of the capacitor relative to the charging voltage equal to the pre-regulated supply voltage, wherein the switching circuit arrangement is further configured to detect a voltage drop on a battery line coupled to the voltage pre-regulator and, in response to the detection, prevent discharge of the capacitor.

16. The apparatus of claim 15, comprising a power supply pin, the power supply pin being configured to: Receive battery supply voltage through the battery pin; receiving a scaled supply voltage based on the battery supply voltage; and The scaled supply voltage is applied to the dedicated pin in the device to generate the preregulated supply voltage from the scaled supply voltage through a diode.

17. A method of operating a device, the device comprising: A plurality of channels configured to drive at least one electrical load; a control module configured to generate at least one channel control signal to operate at least one channel of the plurality of channels; an electronic fuse configured to monitor at least one parameter in a corresponding channel of the plurality of channels and detect an abnormal condition in the corresponding channel based on the at least one parameter; and a parallel mode block configured to define at least one group of channels including at least two channels of the plurality of channels, the channels of the at least one group of channels being configured to drive a same load, wherein the control module is configured to receive a parallel mode management control signal from the parallel mode block and operate the channels of the at least one group of channels based on the parallel mode management control signal received by the parallel mode block, and wherein the electronic fuse is configured to render the channels of the at least one group of channels non-conductive in response to detecting an abnormal condition in at least one channel of the at least one group of channels, and wherein at least one electrical load coupled to the plurality of channels is driven, wherein the method comprises: The electronic fuse monitors at least one parameter in a corresponding channel of the plurality of channels and detects an abnormal condition in the corresponding channel based on the at least one parameter; The parallel mode block defines the at least one group of channels including at least two channels of the plurality of channels; The control module receives a parallel mode management control signal from the parallel mode block and operates the channels of the at least one group of channels based on the parallel mode management control signal received by the parallel mode block; and The electronic fuse renders a channel in the at least one group of channels non-conductive in response to detecting an abnormal condition in at least one channel in the at least one group of channels.

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