Power supply control circuit and electronic equipment

Abstract

The invention discloses a power supply control circuit and electronic equipment, and belongs to the technical field of electronics. The power supply control circuit is used for controlling a power supply to be in a low power consumption mode LPM or a normal power consumption mode NPM. The power supply control circuit comprises an LPM power supply protection module, a register unit and an adjustment module, the LPM power supply protection module is used for judging whether a power supply abnormal event is triggered or not according to an output signal of the power supply under the condition that the power supply is in the LPM; a first bit in the register unit comprises a first identifier or a second identifier, and the first identifier is used for controlling a power supply to be in an LPM; the second identifier is used for controlling the power supply to be in NPM; the adjusting module is used for adjusting the first bit in the register unit to be a second identifier before a possibly triggered power supply abnormal event according to the target signal, or adjusting the first bit in the register unit to be the second identifier under the condition that the power supply abnormal event is frequently triggered; the target signal comprises at least one of the following: an output signal of the power supply and a signal in the LPM power supply protection module.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, and particularly relates to a power control circuit and an electronic device. Background Art

[0002] The power supply itself has static power consumption, that is, the power consumption to maintain its own working state. According to the magnitude of the static power consumption, the working mode of the power supply can be divided into a low power mode (Low Power Mode, LPM) and a normal mode (Normal Power Mode, NPM).

[0003] In the LPM, a series of state changes are required to match in order to reduce the static power consumption. For example: turning off some functions, such as overvoltage protection, undervoltage protection, etc.; reducing the working frequency of the internal clock, such as reducing from 26 MHZ to 32 KHZ; reducing the driving circuit ability and reducing the driving circuit loss; turning off the bias circuit function, etc. And the output current magnitude of the power supply is completely determined by the load. Thus, in the LPM, due to the significant decrease in the load current capacity and the load dynamic current response ability of the power supply, when the load's load drawing exceeds the power supply response ability of the power device, it indicates that an overcurrent (Over Current, OC) event or a "Power Good" (PG) abnormal event has occurred, and it will trigger the overcurrent protection (Over Current Protection, OCP) or PG abnormal protection of the power device, increasing the probability of the power supply system being shut down and the entire machine system being shut down and restarted. Summary of the Invention

[0004] The purpose of the embodiments of this application is to provide a power control circuit and an electronic device, which can reduce the probability of the power supply system being shut down and the entire machine system being shut down and restarted due to the protection mechanism triggered by power abnormal events in the LPM mode.

[0005] In a first aspect, the embodiments of this application provide a power control circuit for controlling a power supply to be in LPM or NPM. The power control circuit includes:

[0006] An LPM power protection module, which is used to be electrically connected to the output end of the power supply, and in the case where the power supply is in the LPM, determine whether a power abnormal event is triggered according to the output signal of the power supply;

[0007] A register unit, which is used to be connected to the power supply. The first bit in the register unit includes a first identifier or a second identifier, where the first identifier is used to control the power supply to be in the LPM; the second identifier is used to control the power supply to be in the NPM;

[0008] Adjustment module, a first end of the adjustment module is configured to be electrically connected to at least one of an output end of the power supply and the LPM power protection module, and a second end of the adjustment module is connected to the storage unit; when the adjustment module determines, according to a target signal, that a power supply anomaly event may be triggered, before triggering the power supply anomaly event, the adjustment module adjusts the first bit in the storage unit to the second identifier, or, when the adjustment module determines, according to the target signal, that the power supply anomaly event is frequently triggered, the adjustment module adjusts the first bit in the storage unit to the second identifier;

[0009] Wherein, the target signal includes at least one of the following: an output signal of the power supply and a signal in the LPM power protection module.

[0010] In a second aspect, an embodiment of the present application provides an electronic device, which includes: a power supply and the power control circuit as described in the first aspect.

[0011] In the embodiment of the present application, when the power supply is in the LPM state, the adjustment module determines whether the power supply may trigger a power supply anomaly event, such as an OC event and / or a PG anomaly event, or whether the power supply anomaly event is frequently triggered, and accordingly actively adjusts the identifier in the first bit of the storage unit, so as to switch the power supply to the NPM before triggering the power supply anomaly event, or, in the case of frequently triggering the power supply anomaly event, limit the power supply to be in the NPM. In this way, the probability that the power supply triggers a power supply anomaly event or frequently triggers a power supply anomaly event in the LPM mode can be reduced, and further the probability that the power supply system is shut down and the entire machine system is shut down and restarted due to the protection mechanism for triggering the power supply anomaly event in the LPM mode can be reduced. Description of the Drawings

[0012] Figure 1 is the OC protection logic block diagram of the power supply in the related art;

[0013] Figure 2 is one of the logic block diagrams of the power control circuit in the embodiment of the present application;

[0014] Figure 3 is another logic block diagram of the power control circuit in the embodiment of the present application;

[0015] Figure 4 is yet another logic block diagram of the power control circuit in the embodiment of the present application;

[0016] Figure 5 is still another logic block diagram of the power control circuit in the embodiment of the present application;

[0017] Figure 6 is the fifth logic block diagram of the power control circuit in the embodiment of the present application. Detailed Embodiments

[0018] The following will clearly describe the technical solutions in the embodiments of the present application in combination with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0019] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type, and the number of objects is not limited. For example, the first object can be one or multiple. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally indicates an "or" relationship between the associated objects before and after.

[0020] To facilitate the understanding of the power control circuit provided in the embodiments of the present application, the related technologies, nouns, and terms of the present application will be explained first.

[0021] 1. LPM refers to a working mode in which the power supply reduces the static power consumption of the battery itself by at least one of the measures such as turning off a part of the functions, reducing the operating frequency of the internal clock, reducing the driving circuit ability, and turning off the bias circuit function.

[0022] 2. NPM refers to a working mode in which, relative to LPM, the static power consumption of the battery itself is not reduced.

[0023] 3. The LPM power protection module refers to a functional module that performs OC event trigger judgment and executes OC protection during the period when the power supply is in LPM, and / or a functional module that performs PG abnormal event trigger judgment and executes PG abnormal protection.

[0024] 4. The NPM power protection module refers to a functional module that performs OC event trigger judgment and executes OCP during the period when the power supply is in NPM, and / or a functional module that performs PG abnormal event trigger judgment and executes PG abnormal protection.

[0025] 5. The OC event refers to an event in which the current of the power supply or the load is too large.

[0026] 6. The PG abnormal event refers to an event in which the output voltage of the power supply is unstable.

[0027] 7. A direct current to direct current (DC / DC) power supply, also known as a switching power supply, realizes step-down or step-up by controlling the charging and discharging of inductors and capacitors through a switching waveform.

[0028] 8. A low dropout regulator (LDO) power supply, based on a negative feedback system, realizes voltage regulation by detecting the output voltage and adjusting the output voltage.

[0029] 9. The OC debounce duration means that when the overcurrent protection module detects that the output current of the power supply exceeds the OC threshold voltage and lasts for a certain duration, then after this duration, an OC event is triggered and OCP is executed. Among them, the duration during which the output current of the power supply exceeds the OC threshold voltage is the OC debounce duration. The purpose of setting this OC debounce duration is to avoid frequent false triggering of OC events caused by short-term jitter of the output current of the power supply.

[0030] For the sake of convenience in description, in the embodiments of the present application, it is usually taken as an example that the LPM power protection module is the LPM overcurrent protection module, the NPM power protection module is the NPM overcurrent protection module, and the LPM overcurrent protection module and the NPM overcurrent protection module are respectively used to judge the triggering of OC events and execute OCP when the power supply is in the LPM and NPM states. This does not constitute a specific limitation here.

[0031] Of course, the LPM power protection module may also be an LPM overvoltage protection module, the NPM power protection module may be an NPM overvoltage protection module. The LPM overvoltage protection module and the NPM overvoltage protection module are respectively used to judge the triggering of PG abnormal events and execute the PG abnormal event protection function when the power supply is in the LPM and NPM states. The main difference between the two is that the LPM overvoltage protection module and the NPM overvoltage protection module are used to detect the output voltage of the power supply to judge whether to trigger a PG abnormal event, while the LPM overcurrent protection module and the NPM overcurrent protection module are used to detect the output current of the power supply or a voltage signal that can reflect the magnitude of the output current of the power supply to judge whether to trigger an OC event. The working principles of the LPM overvoltage protection module and the NPM overvoltage protection module can refer to the explanations of the LPM overcurrent protection module and the NPM overcurrent protection module in the embodiments of the present application.

[0032] Such as Figure 1As shown, in the related art, the OC protection of the power supply under LPM and NPM is independent of each other. Taking the OC protection of the DC / DC power supply under LPM as an example, the LPM overcurrent protection module includes a voltage detection unit 101, a reference voltage providing unit 102, a comparator 103, a time delay unit 104, a combinational logic unit 105, an LPM mode OC flag register unit 106, and an OC response unit 107.

[0033] The working principle of the LPM overcurrent protection module to trigger OCP is as follows: The voltage detection unit 101 detects the voltage difference across the MOS tube at the output end of the DC / DC power supply, and compares this voltage difference with the OC threshold voltage under LPM, that is, the reference voltage provided by the reference voltage providing unit 102. Based on the fact that the output current of the DC / DC power supply is proportional to the voltage difference across the MOS tube, if the voltage difference across the MOS tube is greater than the OC threshold voltage under LPM, it indicates that the output current of the DC / DC power supply may trigger OC protection. At this time, the output state of the comparator 103 flips, that is, the digital logic signal output by the comparator 103 flips from "0" to "1". This digital logic signal "1" is delayed by a certain time through the time delay unit 104. If the state of this digital logic signal is still "1" after the delay, the LPM mode OC flag in the LPM mode OC flag register unit 106 is adjusted to "1", indicating that an OC event is triggered. Once an OC event is triggered, the OC response unit 107 will turn off this power supply path or even the entire power supply system.

[0034] It should be noted that in the related art, the LPM overcurrent protection module and the NPM overcurrent protection module work independently of each other. That is, when the power supply is in the LPM state, Figure 1 the upper LPM overcurrent protection module works. When the power supply is in the NPM state, Figure 1 the lower NPM overcurrent protection module works.

[0035] Among them, the difference between the LPM overcurrent protection module and the NPM overcurrent protection module is that the OC threshold voltage under LPM in the LPM overcurrent protection module is lower than the OC threshold voltage under NPM in the NPM overcurrent protection module, and the OC debounce duration of the LPM overcurrent protection module, that is, the delay duration of the time delay unit 104, is less than the OC debounce duration of the NPM overcurrent protection module.

[0036] It should be noted that in the related art, the power supply can be controlled to switch from LPM to NPM in a software-controlled manner. However, when the power supply is in the LPM state and a load draw occurs, if the load draw is too large, since the load current capacity and the load dynamic current response capacity of the power supply significantly decrease, and it takes a certain amount of time to control the power supply to switch from LPM to NPM through software control, there is a risk of triggering OCP before controlling the power supply to switch from LPM to NPM through software control, resulting in the shutdown of the power supply system and the reboot of the entire machine system.

[0037] Specifically, in the related art, although the power supply can be controlled to switch from LPM to NPM in a software-controlled manner to improve the load current capacity and the load dynamic current response capacity of the power supply and reduce the probability of triggering OCP. However, during the process of the power supply switching from LPM to NPM, a significant low voltage drop will occur due to the load draw, triggering OCP and causing the power supply system to be shut down and the entire machine system to reboot. At this time, the switching scheme of the power supply from LPM to NPM fails.

[0038] For example: Taking the power supply as a Low-dropout regulator (LDO) body, the load can be directly electrically connected to the LDO body or connected to the LDO body through an input DC / DC converter. Among them, for the load on the DC / DC converter, the way for the DC / DC converter to switch from LPM to NPM through software is as follows: When it is detected in the software that the subsequent LDO load of a DC / DC power supply is to be turned on, first calculate the load size of the subsequent LDO load through software superposition, and adjust the working mode of the DC / DC converter to NPM before starting the load, that is, actively improve the power supply capacity of the DC / DC converter, which can reduce the problem of triggering OCP under LPM and causing the power supply system to be shut down and the entire machine system to reboot. However, for the LDO body, the power supply capacity of the LDO power supply is increased after OC is triggered, and its response speed is slow. When the load draw is large, causing a significant voltage drop, OCP is triggered before the power supply capacity of the LDO power supply is increased, resulting in the shutdown of the power supply system and the reboot of the entire machine system.

[0039] Therefore, in the related art, the LDO power supply and the DC / DC power supply have the problem of triggering OCP due to the slow response speed of the power supply capacity and causing the power supply system to be shut down and the entire machine system to reboot.

[0040] In addition, the power supply in the embodiments of the present application can be a DC / DC power supply or an LDO power supply. For the convenience of description, in the embodiments of the present application, the LDO power supply is usually taken as an example for illustration, which does not constitute a specific limitation here.

[0041] In the embodiments of the present application, when the power supply is in the LPM state, the adjustment module determines whether the power supply may trigger a power supply abnormal event, such as an OC event and / or a PG abnormal event, or whether it frequently triggers a power supply abnormal event, and accordingly actively adjusts the identifier in the first bit of the register unit, so as to switch the power supply to the NPM before triggering the power supply abnormal event, or, in the case of frequently triggering the power supply abnormal event, limit the power supply to be in the NPM. In this way, the probability that the power supply triggers a power supply abnormal event or frequently triggers a power supply abnormal event in the LPM mode can be reduced, and further the probability that the power supply system is shut down and the entire machine system is shut down and restarted due to the protection mechanism triggered by the power supply abnormal event in the LPM mode can be reduced.

[0042] The following will combine the accompanying drawings to detail the power control circuit and the electronic device provided by the embodiments of the present application through specific embodiments and their application scenarios.

[0043] The power control circuit provided by the embodiments of the present application is used to control the power supply 10 to be in the LPM or NPM. Refer to Figure 2 , the power control circuit includes:

[0044] The LPM power protection module 20 is used to be electrically connected to the output end of the power supply 10, and when the power supply 10 is in the LPM state, it determines whether to trigger a power supply abnormal event according to the output signal of the power supply 10;

[0045] The register unit 30 is used to be connected to the power supply 10. The first bit in the register unit 30 includes a first identifier or a second identifier. Among them, the first identifier is used to control the power supply 10 to be in the LPM; the second identifier is used to control the power supply 10 to be in the NPM;

[0046] The adjustment module 40, the first end of the adjustment module 40 is used to be electrically connected to at least one of the output end of the power supply 10 and the LPM power protection module 20, and the second end of the adjustment module 40 is connected to the register unit 30; the adjustment module 40 adjusts the first bit in the register unit 30 to the second identifier before triggering the power supply abnormal event according to the target signal to determine that a power supply abnormal event may be triggered, or, when the adjustment module 40 determines that the power supply abnormal event is frequently triggered according to the target signal, it adjusts the first bit in the register unit 30 to the second identifier; among them, the target signal includes at least one of the following: the output signal of the power supply 10 and the signal in the LPM power protection module 20.

[0047] In some embodiments, the power supply abnormal event includes at least one of an overcurrent (OC) event and a voltage instability event. Among them, the voltage instability event can also be referred to as a "Power Good (PG)" abnormal event, that is, the output voltage of the power supply 10 is unstable.

[0048] It is worth noting that the OC event usually occurs when there is a load drawdown, causing the output current of the power supply 10 to increase, thereby triggering the overcurrent protection mechanism to turn off the power supply or shut down the machine. The PG signal is a signal used to detect the stability of the power supply output voltage. When the output voltage of the power supply 10 is stable, the PG signal changes from a low level to a high level, thereby telling the motherboard that the power supply is in a normal working state. If the power supply output voltage is unstable or too low, it may cause hardware damage, and the PG signal can detect such problems in a timely manner. By triggering the PG abnormal event to turn off the power supply or shut down the machine, the safe operation of the hardware is protected. The two have similarities. Under LPM, since both the power supply ability of the power supply 10 and the load dynamic current response ability are reduced, the triggering probabilities of the OC event and the PG abnormal event triggered by the LPM power protection module 20 under LPM increase.

[0049] For ease of explanation, in the following embodiments of the present application, the power supply abnormal event is taken as an OC event, and the LPM power protection module 20 is taken as an LPM overcurrent protection module as an example for illustration, which does not constitute a specific limitation here.

[0050] In some embodiments, the register unit 30 is connected to the power supply 10, and may be connected to the register unit 30 through an additional logic judgment unit. For example, the processor system is connected to the register unit 30 through a System Power Management Interface (SPMI) interface to read the identifier in the first bit of the register unit 30 and control the working mode of the power supply 10 according to the read identifier. At this time, when the processor system reads the first identifier from the first bit of the register unit 30 through the SPMI interface, it controls the power supply 10 to be in the LPM; when the processor system reads the second identifier from the first bit of the register unit 30 through the SPMI interface, it controls the power supply 10 to be in the NPM.

[0051] In some embodiments, after the adjustment module 40 adjusts the first bit in the register unit 30 to the second identifier, a logic judgment unit connected to the register unit 30, such as a control unit like a Power Management IC (PMIC) or a System on Chip (SoC), will control the power supply 10 to switch to NPM in the next clock cycle. Since both the power supply capacity and the load dynamic current response ability of the power supply 10 under NPM are improved, the probability of triggering an OC event based on a load drawdown is greatly reduced when a load drawdown occurs.

[0052] In some embodiments, the LPM power protection module 20 includes: a first detection unit 21, a first comparator 22, a second delay unit 23, a third logic unit 24, an LPM OC flag register unit 25, and a first OC response unit 26;

[0053] The first detection unit 21 is electrically connected to the output terminal of the power supply 10 and the first terminal of the first comparator 22 respectively. The second terminal of the first comparator 22 is used to receive a first reference electrical signal, that is, the LPM OC-REF voltage. The third terminal of the first comparator 22 is electrically connected to the first terminal of the third logic unit 24 and the first terminal of the second delay unit 23 respectively. The second terminal of the second delay unit 23 is electrically connected to the second terminal of the third logic unit 24. The third terminal of the third logic unit 24 is electrically connected to the first terminal of the LPM OC flag register unit 25. The first OC response unit 26 is electrically connected to the second terminal of the LPM OC flag register unit 25.

[0054] The working principle of the LPM power protection module is the same as that of the LPM power protection module in the related art. For example: The first detection unit 21 is used to detect the magnitude of the output signal of the power supply 10, such as the output voltage or output current, and the first comparator 22 is used to compare the magnitude of this output signal with the first reference electrical signal. If the output signal is greater than the first reference electrical signal, the first comparator 22 can output a high-level signal. The second delay unit 23 is used to delay for a certain period of time. If it is determined that the first comparator 22 still outputs a high-level signal, it transmits a high-level signal to the second terminal of the third logic unit 24. The third logic unit 24 is used to transmit a high-level signal to the LPM OC flag register unit 25 when both its first terminal and second terminal receive high-level signals, so as to set the LPM OC flag in the LPM OC flag register unit 25 to "1", that is, an OC event occurs. The first OC response unit 26 is used to execute an OC response according to the set "1" LPM OC flag, such as turning off the power supply or shutting down the machine.

[0055] As can be seen from the above, the delay duration for the LPM power protection module 20 to trigger the power protection mechanism is the same as the delay duration of the second delay unit 23, and the judgment threshold of the LPM power protection module 20 is the same as the value of the first reference electrical signal.

[0056] It should be noted that in the above embodiments, when the output signal of the power supply 10 is greater than the first reference electrical signal, the first comparator 22 outputs a high level; otherwise, the first comparator 22 outputs a low level. Taking this as an example, at this time, the third logic unit 24 can be an "AND" gate logic unit. Of course, in some other possible implementation manners, when the output signal of the power supply 10 is greater than the first reference electrical signal, the output signal of the first comparator 22 can be a low level. At this time, the judgment logic of the third logic unit 24 can also change accordingly, which is not specifically limited herein.

[0057] In addition, for the convenience of description, in the embodiments of the present application, when the output signal of the power supply 10 is greater than the first reference electrical signal, the first comparator 22 outputs a high level; otherwise, the first comparator 22 outputs a low level. Taking this as an example, this does not constitute a specific limitation.

[0058] In addition, in the embodiments of the present application, taking the detection unit, such as the first detection unit 21 and the subsequent second detection unit 44, etc., which are all used to detect the voltage difference across the MOS tube corresponding to the output current of the power supply 10 as an example, at this time, the OC threshold, that is, the reference electrical signal, is a voltage threshold. Of course, in some other possible implementation manners, the first detection unit 21 and the subsequent second detection unit 44, etc. may also be used to directly detect the output current of the power supply 10. At this time, the OC threshold, that is, the reference electrical signal, can be a current threshold, which is not specifically limited herein.

[0059] In some embodiments, as Figure 3 shown, the power control circuit further includes:

[0060] The NPM power protection module 50, which is used to be electrically connected to the output end of the power supply 10 and is used to judge whether to trigger an OC event according to the output signal of the power supply 10 when the power supply 10 is in the NPM state.

[0061] Among them, when the power supply 10 switches to NPM, the NPM power protection module 50 is enabled, and the LPM power protection module 20 is disabled; when the power supply 10 is in the LPM state, the LPM power protection module 20 is enabled, and the NPM power protection module 50 is disabled.

[0062] It should be noted that since both the power supply capacity of the power supply 10 and the load dynamic current response capacity under NPM are improved, at this time, the OC debounce delay time of the NPM power protection module 50 is longer than that of the LPM power protection module 20; the reference electrical signal for the NPM power protection module 50 to judge the trigger of the OC event is greater than the reference electrical signal for the LPM power protection module 50 to judge the trigger of the OC event.

[0063] In this way, the judgment threshold for the NPM power protection module 50 to trigger the OC event is higher than that of the LPM power protection module 20, so that the probability of the power supply 10 triggering the OC event under NPM is lower than the probability of the power supply 10 triggering the OC event under LPM, thereby reducing the probability of the power supply 10 being powered off or shut down due to OCP under NPM.

[0064] Among them, the NPM power protection module 50 has the same structure and working principle as the NPM power protection module in the prior art. For example: as Figures 2 to 6 shown, the NPM power protection module 50 includes:

[0065] a third detection unit 51, a third comparator 52, a third delay unit 53, a fourth logic unit 54, an NPM OC flag bit storage unit 55, and a second OC response unit 56;

[0066] The third detection unit 51 is used to be electrically connected to the output end of the power supply 10 and the first end of the third comparator 52 respectively. The second end of the third comparator 52 is used to receive a third reference electrical signal, that is, the NPM OC-REF voltage. The third end of the third comparator 52 is electrically connected to the first end of the fourth logic unit 54 and the first end of the third delay unit 53 respectively. The second end of the third delay unit 53 is electrically connected to the second end of the fourth logic unit 54. The third end of the fourth logic unit 54 is electrically connected to the first end of the NPM OC flag bit storage unit 55. The second OC response unit 56 is electrically connected to the second end of the NPM OC flag bit storage unit 55.

[0067] The working principle of the NPM power protection module is the same as that of the NPM power protection module in the related art. For example, the third detection unit 51 is used to detect the magnitude of the output signal of the power supply 10, such as the output voltage or output current, and the third comparator 52 is used to compare the magnitude of the output signal with the first reference electrical signal. If the output signal is greater than the first reference electrical signal, the third comparator 52 can output a high-level signal. The third time delay unit 53 is used to delay for a certain period of time. If it is determined that the third comparator 52 still outputs a high-level signal, a high-level signal is transmitted to the second terminal of the fourth logic unit 54. The fourth logic unit 54 is used to transmit a high-level signal to the NPM OC flag register unit 55 when high-level signals are received at both its first terminal and second terminal, so as to set the NPM OC flag in the NPM OC flag register unit 55 to "1", that is, an OC event occurs. The second OC response unit 56 is used to execute an OC response according to the set NPM OC flag, such as turning off the power supply or shutting down the machine.

[0068] As can be seen from the above, the delay duration for the NPM power protection module 50 to trigger the power protection mechanism is the same as the delay duration of the third time delay unit 53, and the judgment threshold of the NPM power protection module 50 is the same as the value of the third reference electrical signal.

[0069] It should be noted that the third reference voltage is greater than the first reference voltage, that is, the OC judgment threshold of NPM is higher than that of LPM. In addition, the delay duration of the third time delay unit 53 can be longer than the delay duration of the second time delay unit 23, so that the OC debounce duration under NPM is longer.

[0070] In some embodiments, the adjustment module 40 can be hardware-connected to the register unit 30. In this way, the adjustment module 40 can rewrite the identifier of the first bit in the register unit 30 by transmitting a hardware signal to the register unit 30.

[0071] For example: as Figure 2 、 Figure 3 、 Figure 4 or Figure 5 shown, the adjustment module 40 is used to transmit a first signal or a second signal to the register unit 30 according to the target signal;

[0072] Among them, when the adjustment module 40 transmits the first signal to the register unit 30, the identifier of the first bit in the register unit 30 remains unchanged; when the adjustment module 40 transmits the second signal to the register unit 30, the register unit 30 adjusts the first bit to the second identifier in response to the first signal.

[0073] For example: The first signal is a low-level signal and the second signal is a high-level signal. At this time, when the storage unit 30 obtains a low-level signal from the adjustment module 40, the first bit remains unchanged, and at this time, the operating state of the power supply 10 remains unchanged; or, when the storage unit 30 obtains a high-level signal from the adjustment module 40, the first bit is adjusted to the second identifier, and at this time, the operating state of the power supply 10 is switched to NPM.

[0074] In this embodiment, by interconnecting the hardware signals between the adjustment module 40 and the storage unit 30, the identifier of the first bit in the storage unit 30 can be quickly adjusted following the logic state of the adjustment module 40.

[0075] Of course, in some other embodiments, the adjustment module 40 can be software-connected to the storage unit 30, such as setting up an intermediate signal processing module for obtaining the output signal of the adjustment module 40 and, according to the output signal of the adjustment module 40, performing corresponding rewriting on the identifier of the first bit in the storage unit 30.

[0076] In some embodiments, if the adjustment module 40 determines that an OC event may be triggered, before the LPM power protection module 20 triggers the OC event to execute OCP, the adjustment module 40 adjusts the first bit in the storage unit 30 to the second identifier, so as to switch the power supply 10 to NPM in advance before the LPM power protection module 20 actually triggers the OC event, thereby enhancing the power supply capacity of the power supply 10 and the load dynamic current response ability, and reducing the probability of triggering the OC event.

[0077] To determine whether an OC event may be triggered, the adjustment module 40 can adopt at least one of the following methods:

[0078] Method 1: The first end of the adjustment module 40 is used to be electrically connected to the output end of the power supply 10. In this way, the adjustment module 40 can detect the output signal of the power supply 10, such as the output voltage or output current, and when the power supply is in LPM, compare the magnitude or change rate of the output signal of the power supply 10 with the OC threshold value under LPM to determine whether an OC event may be triggered according to the comparison result. For example: Assume that the OC threshold voltage under LPM is the LPM OC threshold voltage. If the voltage value corresponding to the output current of the power supply 10 is greater than this LPM OC threshold voltage, it is determined that an OC event may be triggered.

[0079] As an optional embodiment, as Figure 4 shown, the adjustment module 40 includes: a first logic unit 41, a first delay unit 42, a second logic unit 43, a second detection unit 44, and a second comparator 45;

[0080] The second detection unit 44 is used to be electrically connected to the output terminal of the power supply 10 and the first terminal of the second comparator 45 respectively. The second terminal of the second comparator 45 is used to receive a second reference electrical signal, that is, the LPM PRE-OC REF voltage. The third terminal of the second comparator 45 is electrically connected to the first terminal of the first logic unit 41;

[0081] The second terminal of the first logic unit 41 is electrically connected to the first terminal of the first time-delay unit 42 and the first terminal of the second logic unit 43 respectively. The second terminal of the first time-delay unit 42 is electrically connected to the second terminal of the second logic unit 43. The third terminal of the second logic unit 43 is electrically connected to the register unit 30;

[0082] Wherein, when the output signal of the power supply 10 is greater than the second reference electrical signal, the third terminal of the second comparator 45 outputs a third signal; when the output signal of the power supply 10 is less than or equal to the second reference electrical signal, the third terminal of the second comparator 45 outputs a fourth signal;

[0083] When the first logic unit 41 receives the third signal, the first logic unit 41 transmits a first intermediate signal to the first time-delay unit 42 and the second logic unit 43. The first time-delay unit 42 outputs a second intermediate signal after receiving the first intermediate signal and delaying for a first duration. The second logic unit 43 outputs the second signal based on receiving the first intermediate signal and the second intermediate signal;

[0084] When the first logic unit 41 receives the fourth signal, the first logic unit 41 transmits a third intermediate signal to the first time-delay unit 42 and the second logic unit 43. The first time-delay unit 42 outputs a fourth intermediate signal after receiving the third intermediate signal and delaying for a first duration. The second logic unit 43 outputs the first signal based on receiving the third intermediate signal and the fourth intermediate signal;

[0085] Wherein, the first duration is shorter than the delay duration for the LPM power protection module 20 to trigger the power protection mechanism, and / or, the preset threshold value is less than the judgment threshold of the LPM power protection module 20.

[0086] Wherein, the judgment threshold of the LPM power protection module 20 has the same value as the value of the first reference electrical signal. The delay duration for the LPM power protection module to trigger the power protection mechanism can be equal to the delay duration of the second time-delay unit 23.

[0087] In some embodiments, the first logic unit 41 may be set to an initial state, so as to make the initial state of the identification of the first bit in the register unit 30 controllable by setting the initial state of the first logic unit 41. For example, the user may adjust the default working state of the power supply after each power-on through software setting. The initial state of the first logic unit 41 may be to output a low-level signal, that is, the first logic unit 41 outputs a low-level signal at each power-on, so that the first delay unit 42 and the second logic unit 43 output a low-level signal accordingly, that is, the first signal, to the register unit 30. At this time, the register unit 30 does not change the identification of the first bit. In this way, the initial state of the identification of the first bit in the register unit 30 is not affected by the adjustment module 40.

[0088] In some embodiments, the second reference electrical signal may be less than the first reference signal. At this time, the adjustment module 40 independently determines whether an OC event may be triggered without depending on the LPM power protection module 20, and the threshold for the adjustment module 40 to determine that an OC event may be triggered is lower than the threshold for the LPM power protection module 20 to determine that an OC event is triggered. In this way, the adjustment module 40 can switch to the NPM in advance before the LPM power protection module 20 actually triggers an OC event.

[0089] In other embodiments, the second reference electrical signal may be equal to the first reference signal, and the first duration is shorter than the OC debounce duration of the LPM power protection module 20. For example, the OC debounce duration of the LPM power protection module 20 is 32 μs, and the first duration is 2 μs, so that there is an order-of-magnitude time difference between the first duration and the OC debounce duration of the LPM power protection module 20. In this way, the adjustment module 40 independently determines whether an OC event may be triggered without depending on the LPM power protection module 20. Although the threshold for the adjustment module 40 to determine that an OC event may be triggered is the same as the threshold for the LPM power protection module 20 to determine that an OC event is triggered, the delay for the adjustment module 40 to determine whether an OC event may be triggered is shorter. Therefore, the adjustment module 40 can switch to the NPM in advance before the LPM power protection module 20 actually triggers an OC event.

[0090] In still other embodiments, the second reference electrical signal may be less than the first reference signal, and the first duration is shorter than the OC debounce duration of the LPM power protection module 20. At this time, the threshold for the adjustment module 40 to determine that an OC event may be triggered is lower than the threshold for the LPM power protection module 20 to determine that an OC event is triggered, and the delay for the adjustment module 40 to determine whether an OC event may be triggered is shorter. In this way, the adjustment module 40 can switch to the NPM more reliably in advance before the LPM power protection module 20 actually triggers an OC event.

[0091] Method 2: The LPM power protection module 20 has a logic unit for determining whether an OC event is triggered. To prevent false triggering or frequent triggering of the OC event, after detecting that an OC event may be triggered, the LPM power protection module 20 will wait for a period of time, that is, after the OC debounce duration, before actually triggering OCP. Based on this principle, the first end of the adjustment module 40 can be connected to the logic unit in the LPM power protection module 20 that determines whether an OC event is triggered, so as to reuse the logic unit in the LPM power protection module 20 that determines whether an OC event is triggered to determine whether an OC event may occur. If the determination result is that an OC event may occur, the adjustment module 40 will adjust the first bit in the register unit 30 to the second identifier before the OC debounce duration of the LPM power protection module 20, so as to adjust the power supply 10 to NPM before the LPM power protection module 20 actually triggers OCP.

[0092] As an alternative implementation, as Figure 2 or Figure 3 shown, the adjustment module 40 includes: a first logic unit 41, a first delay unit 42, and a second logic unit 43;

[0093] The first end of the first logic unit 41 is used to receive a third signal or a fourth signal. The second end of the first logic unit 41 is electrically connected to the first end of the first delay unit 42 and the first end of the second logic unit 43 respectively. The second end of the first delay unit 42 is electrically connected to the second end of the second logic unit 43. The third end of the second logic unit 43 is electrically connected to the register unit 30;

[0094] Wherein, the third signal and the fourth signal are related to the output signal of the power supply 10, and the third signal is used to indicate that the output signal of the power supply 10 is greater than a preset threshold value, and the fourth signal is used to indicate that the output signal of the power supply 10 is less than or equal to the preset threshold value;

[0095] When the first logic unit 41 receives the third signal, the first logic unit 41 transmits a first intermediate signal to the first delay unit 42 and the second logic unit 43. The first delay unit 42 outputs a second intermediate signal after receiving the first intermediate signal and delaying for a first duration. The second logic unit 43 outputs the second signal based on receiving the first intermediate signal and the second intermediate signal;

[0096] When the first logic unit 41 receives the fourth signal, the first logic unit 41 transmits a third intermediate signal to the first delay unit 42 and the second logic unit 43. The first delay unit 42 outputs a fourth intermediate signal after receiving the third intermediate signal and delaying for a first duration. The second logic unit 43 outputs the first signal based on receiving the third intermediate signal and the fourth intermediate signal;

[0097] Among them, the first duration is shorter than the OC debounce duration of the LPM power protection module 20.

[0098] In some embodiments, the third signal and the fourth signal may come from the LPM power protection module 20. For example, when the LPM power protection module 20 determines that the output signal of the power supply 10 is greater than or equal to the first reference electrical signal, before waiting for the OC debounce duration, the third signal is input to the first end of the first logic unit 41; when the LPM power protection module 20 determines that the output signal of the power supply 10 is less than the first reference electrical signal, the fourth signal is input to the first end of the first logic unit 41.

[0099] As an alternative embodiment, the preset threshold value has the same value as the first reference electrical signal; the first end of the first logic unit 41 is electrically connected to the third end of the first comparator 22;

[0100] Among them, when the output signal of the power supply 10 is greater than the first reference electrical signal, the third signal is output from the third end of the first comparator 22; when the output signal of the power supply 10 is less than or equal to the first reference electrical signal, the fourth signal is output from the third end of the first comparator 22.

[0101] In this embodiment, the logic unit in the LPM power protection module 20 for determining whether an OC event is triggered can be reused to determine whether an OC event may occur, and the first duration of the first delay unit 42 is shorter than the OC debounce duration of the LPM power protection module 20. In this way, when the determination result is that an OC event may occur, the adjustment module 40 can adjust the first bit in the register unit 30 to the second identifier before the OC debounce duration of the LPM power protection module 20, so as to adjust the power supply 10 to NPM before the LPM power protection module 20 actually triggers OCP.

[0102] It should be noted that the third signal in the embodiments of the present application may be a high-level signal, the fourth signal may be a low-level signal, the first logic unit 41 receiving the third signal may be the first logic unit 41 receiving a high-level signal, and the first logic unit 41 receiving the fourth signal may be the first logic unit 41 receiving a low-level signal or not receiving a high-level signal. For example, if no level signal is obtained, that is, the obtained level signal is 0.

[0103] Such as Figure 2 、 Figure 3 and Figure 4In the illustrated embodiment, the adjustment module 40 adjusts the identifier of the first bit in the storage unit 30 based on whether the output signal of the power supply 10 triggers an OC event of the LPM power protection module 20. That is, when the output signal of the power supply 10 triggers an OC event of the LPM power protection module 20, the identifier of the first bit in the storage unit 30 is adjusted to the second identifier in advance, so as to switch the power supply to NPM before the LPM power protection module 20 triggers an OC event.

[0104] In some other embodiments, the adjustment module 40 can also adjust the identifier of the first bit in the storage unit 30 based on information such as the number of times and / or probability that the LPM power protection module 20 triggers an OC event. For example, the adjustment module 40 can adjust the identifier of the first bit in the storage unit 30 to the second identifier when the number of times the LPM power protection module 20 triggers an OC event reaches a preset number or the number of times the LPM power protection module 20 newly triggers an OC event within a specified duration reaches a preset number, limit the power supply 10 to operate under NPM, and improve the power supply capacity and load dynamic current response ability of the power supply 10 to reduce the probability of subsequent triggering of an OC event.

[0105] As an alternative embodiment, as Figure 5 shown, the adjustment module 40 includes:

[0106] A first OC trigger counting unit 46, a first end of the first OC trigger counting unit 46 is electrically connected to the LPM power protection module 20, and a second end of the first OC trigger counting unit 46 is electrically connected to the storage unit 30;

[0107] The first OC trigger counting unit 46 is used to count the number of times the LPM power protection module 20 triggers an OC event. Among them, when the count value of the first OC trigger counting unit 46 is greater than or equal to a first preset value, the first OC trigger counting unit 46 transmits the second signal to the storage unit 30; when the count value of the first OC trigger counting unit 46 is less than the first preset value, the first OC trigger counting unit 46 transmits the first signal to the storage unit 30.

[0108] In some embodiments, the second end of the first OC trigger counting unit 46 can be directly or indirectly connected to the storage unit 30.

[0109] Among them, when the second end of the first OC trigger counting unit 46 can be directly electrically connected to the storage unit 30, the first OC trigger counting unit 46 can rewrite the identifier of the first bit in the storage unit 30 by transmitting a hardware signal to the storage unit 30.

[0110] Of course, the second terminal of the first OC trigger counting unit 46 can be directly or indirectly connected to the storage unit 30. For example, the second terminal of the first OC trigger counting unit 46 and the storage unit 30 can be connected through other logic units or processors, so that the count value of the first OC trigger counting unit 46 can be used as the basis for other logic units or processors to rewrite the identifier of the first bit in the storage unit 30.

[0111] In some embodiments, the first signal can be a low-level signal or a non-overflow signal output by the first OC trigger counting unit 46. Alternatively, the first signal can be a "0" signal, that is, the first OC trigger counting unit 46 has no output signal. At this time, the identifier of the first bit in the storage unit 30 remains unchanged.

[0112] In some embodiments, the first preset value can be the counting upper limit of the first OC trigger counting unit 46. That is, when the count of the first OC trigger counting unit 46 reaches the counting upper limit, an overflow signal is sent to the storage unit 30, so that the storage unit 30 adjusts the identifier of the first bit in the storage unit 30 to the second identifier based on the received overflow signal. At this time, the second signal is the overflow signal when the first OC trigger counting unit 46 reaches the counting upper limit.

[0113] In this embodiment, the first OC trigger counting unit 46 counts the number of times the LPM power protection module 20 triggers an OC event, and based on the hardware signal when the count result is greater than the first preset value, the identifier of the first bit in the storage unit 30 is rewritten as the second identifier.

[0114] As an alternative embodiment, as Figure 6 shown, the adjustment module 40 includes:

[0115] A second OC trigger counting unit 47. The first terminal of the second OC trigger counting unit 47 is electrically connected to the LPM power protection module 20. The second OC trigger counting unit 47 is used to count the number of times the LPM power protection module 20 triggers an OC event;

[0116] The power control circuit further includes: a processor 60;

[0117] The processor 60 is configured to read the count value of the second OC trigger counting unit 47, and when the count value of the second OC trigger counting unit 47 is greater than or equal to the second preset value, the processor 60 controls the first bit in the storage unit 30 to be the second identifier; when the count value of the second OC trigger counting unit 47 is less than the second preset value, the identifier of the first bit in the storage unit 30 remains unchanged.

[0118] In some embodiments, the processor 60 may be respectively connected to the second OC trigger counting unit 47 and the register unit 30 through the SPMI interface, so as to read the count value of the second OC trigger counting unit 47 through the SPMI interface connected to the second OC trigger counting unit 47, and compare the count value with a second preset value. If it is determined that the count value is greater than or equal to the second preset value, the first bit in the register unit 30 is rewritten as a second identifier through the SPMI interface connected to the register unit 30; otherwise, the identifier of the first bit in the register unit 30 is not rewritten.

[0119] In some embodiments, the second preset value is pre-stored in the processor 60. For example, it can be pre-stored in the processor 60 in the form of factory pre-configuration or user dynamic setting.

[0120] It should be noted that the second OC trigger counting unit 47 is used to count the number of times the LPM power protection module 20 triggers an OC event. That is, whenever the LPM power protection module 20 triggers an OC event, the count value of the second OC trigger counting unit 47 is incremented by 1 until the counting upper limit of the second OC trigger counting unit 47 is reached.

[0121] In some embodiments, after the second OC trigger counting unit 47 reaches the counting upper limit, the count of the second OC trigger counting unit 47 can be cleared to start counting again.

[0122] In other embodiments, after the count value of the second OC trigger counting unit 47 reaches the second preset value, the processor 60 may, according to the fact that the count value read from the second OC trigger counting unit 47 reaches the second preset value, while rewriting the first bit in the register unit 30 as the second identifier, also clear the count value of the second OC trigger counting unit 47 to enable the second OC trigger counting unit 47 to start counting again.

[0123] It should be noted that in some embodiments, the processor 60 may also perform more complex logical processing on the count value read by the second OC trigger counting unit 47, and in addition to rewriting the identifier of the first bit in the register unit 30, the processor 60 may also adjust the parameters in the LPM power protection module 20 and the adjustment module 40.

[0124] For example, three thresholds from small to large are set in the processor 60, namely the first threshold, the second threshold, and the third threshold. When the count value of the second OC trigger counting unit 47 is greater than or equal to the first threshold and less than the second threshold, the judgment threshold of the LPM power protection module 20 is increased, that is, the first reference electrical signal; when the count value of the second OC trigger counting unit 47 is greater than or equal to the second threshold and less than the third threshold, the debounce duration of the LPM power protection module 20 is increased, that is, the delay duration of the second delay unit 23; when the count value of the second OC trigger counting unit 47 is greater than or equal to the third threshold, the judgment threshold and the debounce duration of the LPM power protection module 20 are restored to the initial state, and the first bit in the register unit 30 is adjusted to the second identifier.

[0125] In this embodiment, the processor 60 software-controls the identifier of the first bit in the register unit 30 according to the output signal of the adjustment module 40, and its response speed is slower than the method in the previous embodiment of making the identifier of the first bit in the register unit 30 follow the logic state of the adjustment module 40 for adjustment.

[0126] It is worth noting that when the LPM power protection module 20 triggers an OC event, the third logic unit 24 will transmit a high-level signal to the LPM OC flag bit register unit 25 to set the LPM OC flag bit in the LPM OC flag bit register unit 25 to "1". Based on this principle, the OC trigger counting unit in the embodiments of the present application, that is, the first OC trigger counting unit 46 or the second OC trigger counting unit 47, can be electrically connected to the third logic unit 24 so that when the third logic unit 24 outputs a high level, the count of the first OC trigger counting unit 46 or the second OC trigger counting unit 47 is incremented by 1.

[0127] In some other embodiments, when the LPM power protection module 20 triggers an OC event, the OC flag bit in the LPM OC flag bit register unit 25 is "1". Based on this principle, the OC trigger counting unit in the embodiments of the present application, that is, the first OC trigger counting unit 46 or the second OC trigger counting unit 47, can be electrically connected to the LPM OC flag bit register unit 25 so that when the OC flag bit in the LPM OC flag bit register unit 25 is converted from "0" to "1" each time, the count of the first OC trigger counting unit 46 or the second OC trigger counting unit 47 is incremented by 1.

[0128] In some other embodiments, when the LPM power protection module 20 triggers an OC event, the first OC response unit 26 will turn off the power supply or directly shut down the machine. Based on this principle, the OC trigger counting unit in the embodiments of the present application, that is, the first OC trigger counting unit 46 or the second OC trigger counting unit 47, can also be electrically connected to the first OC response unit 26, or used to be electrically connected to the output terminal of the power supply 10, so that each time the first OC response unit 26 turns off the power supply or shuts down the machine, the count of the first OC trigger counting unit 46 or the second OC trigger counting unit 47 is incremented by 1.

[0129] It is worth noting that in the related art, whenever the power supply triggers an OC or "Power Good" (PG) abnormal protection mechanism, the power supply and the PMIC will be turned off, and only the current OC event / PG abnormal event can be recorded once, and the OC event / PG abnormal event of the power supply cannot be recorded multiple times, that is, the event will be cleared after being triggered once. The reason for being cleared is that the default code preset state will be executed when the system restarts, that is, the configuration parameters of all hardware will be reset to the default code state, so that the historical anomalies of the local machine cannot be recognized. In the embodiments of the present application, by adding the first OC trigger counting unit 46 or the second OC trigger counting unit 47, the trigger times of the current OC and the historical OC can be recorded.

[0130] It should be noted that for the cases of reporting OC in actual applications, they are usually sporadic and non-reproducible, and are abnormal situations that need to be triggered in combination with various conditions in a specific user scenario; in this embodiment, the power supply 10 can be restricted to work in NPM after the trigger times of the OC event accumulate to a certain number. Compared with the previous embodiment, each time it is predicted that the power supply 10 will trigger an OC event in LPM, and the power supply 10 is switched to NPM in advance, the power consumption waste caused by the power supply 10 continuously working in NPM can be reduced.

[0131] In the embodiments of the present application, when the power supply is in the LPM state, the adjustment module determines whether the power supply may trigger a power supply abnormal event, such as an OC event and / or a PG abnormal event, or whether it frequently triggers an OC event and / or a PG abnormal event, and accordingly actively adjusts the identifier in the first bit of the register unit, so as to switch the power supply to NPM before triggering an OC event and / or a PG abnormal event, or restrict the power supply to be in NPM in the case of frequently triggering an OC event and / or a PG abnormal event. In this way, the probability of the power supply triggering an OC event and / or a PG abnormal event or frequently triggering an OC event and / or a PG abnormal event in the LPM mode can be reduced, and further the probability of the power supply system being shut down and the whole machine system being shut down and restarted due to triggering OCP and / or PG abnormal protection in the LPM mode can be reduced.

[0132] The embodiment of the present application also provides an electronic device, which includes a power supply 10 and the present application as shown in FIG. Figures 2 to 6 A power control circuit provided by any one of the embodiments.

[0133] In some embodiments, the electronic device may be a terminal or other device other than a terminal. For example, the electronic device may be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a personal digital assistant (PDA), etc. It may also be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiments of the present application.

[0134] The electronic device provided in the embodiment of the present application utilizes Figures 2 to 6 The power control circuit provided in any one of the embodiments controls the power supply 10 to be in LPM or NPM, which can reduce the probability of the power supply system being shut down and the whole system being shut down and restarted due to the protection mechanism of the power abnormality event triggered in the LPM mode. Figures 2 to 6 The power control circuit provided by any of the embodiments has the same beneficial effects, which will not be described again here to avoid repetition.

[0135] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0136] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative rather than restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them fall within the protection scope of the present application.

Claims

1. A power control circuit, characterized in that: Used to control the power supply to be in a low power consumption mode LPM or a normal power consumption mode NPM, the power supply control circuit includes: An LPM power protection module, the LPM power protection module is used to be electrically connected to the output end of the power supply, and when the power supply is in the LPM, determine whether to trigger a power abnormality event according to the output signal of the power supply; A register unit, the register unit is used to connect to the power supply, the first bit in the register unit includes a first identifier or a second identifier, wherein the first identifier is used to control the power supply to be in the LPM; the second identifier is used to control the power supply to be in the NPM; an adjustment module, wherein a first end of the adjustment module is used to be electrically connected to at least one of the output end of the power supply and the LPM power protection module, and a second end of the adjustment module is connected to the register unit; when the adjustment module determines that a power abnormality event may be triggered according to a target signal, before triggering the power abnormality event, the first bit in the register unit is adjusted to the second identifier, or when the adjustment module determines that a power abnormality event is frequently triggered according to a target signal, the first bit in the register unit is adjusted to the second identifier; The target signal includes at least one of the following: an output signal of the power supply and a signal in the LPM power protection module.

2. The power control circuit according to claim 1, characterized in that: The adjustment module is used to transmit the first signal or the second signal to the register unit according to the target signal; When the adjustment module transmits the first signal to the register unit, the identifier of the first bit in the register unit remains unchanged; when the adjustment module transmits the second signal to the register unit, the register unit adjusts the first bit to the second identifier in response to the second signal.

3. The power control circuit according to claim 2, characterized in that: The adjustment module includes: a first logic unit, a first delay unit and a second logic unit; The first end of the first logic unit is used to receive the third signal or the fourth signal, the second end of the first logic unit is electrically connected to the first end of the first delay unit and the first end of the second logic unit respectively, the second end of the first delay unit is electrically connected to the second end of the second logic unit, and the third end of the second logic unit is electrically connected to the register unit; The third signal and the fourth signal are related to the output signal of the power supply, and the third signal is used to indicate that the output signal of the power supply is greater than a preset threshold value, and the fourth signal is used to indicate that the output signal of the power supply is less than or equal to the preset threshold value; In the case where the first logic unit receives the third signal, the first logic unit transmits a first intermediate signal to the first delay unit and the second logic unit, the first delay unit outputs a second intermediate signal after receiving the first intermediate signal and delaying for a first time, and the second logic unit outputs the second signal based on receiving the first intermediate signal and the second intermediate signal; In the case where the first logic unit receives the fourth signal, the first logic unit transmits a third intermediate signal to the first delay unit and the second logic unit, the first delay unit outputs a fourth intermediate signal after receiving the third intermediate signal and delaying for a first time period, and the second logic unit outputs the first signal based on receiving the third intermediate signal and the fourth intermediate signal; The first duration is shorter than the delay duration for the LPM power protection module to trigger the power protection mechanism, and / or the preset threshold value is smaller than the judgment threshold of the LPM power protection module.

4. The power control circuit according to claim 3, characterized in that: The LPM power protection module includes: a first detection unit, a first comparator, a second delay unit, a third logic unit, an LPM OC flag register unit and a first OC response unit; The first detection unit is used to be electrically connected to the output end of the power supply and the first end of the first comparator respectively, the second end of the first comparator is used to receive a first reference electrical signal, the third end of the first comparator is electrically connected to the first end of the third logic unit and the first end of the second delay unit respectively, the second end of the second delay unit is electrically connected to the second end of the third logic unit, the third end of the third logic unit is electrically connected to the first end of the LPM OC flag register unit, and the first OC response unit is electrically connected to the second end of the LPM OC flag register unit; Among them, the delay duration of the LPM overcurrent protection module triggering the power protection mechanism is the same as the delay duration of the second delay unit, and the judgment threshold of the LPM overcurrent protection module is the same as the value of the first reference electrical signal.

5. The power control circuit according to claim 4, characterized in that: The preset threshold value is the same as the value of the first reference electrical signal; the first end of the first logic unit is electrically connected to the third end of the first comparator; When the output signal of the power supply is greater than the first reference electrical signal, the third end of the first comparator outputs the third signal; when the output signal of the power supply is less than or equal to the first reference electrical signal, the third end of the first comparator outputs the fourth signal.

6. The power control circuit according to claim 4, characterized in that: The adjustment module further includes: a second detection unit and a second comparator; The second detection unit is used to be electrically connected to the output end of the power supply and the first end of the second comparator respectively, the second end of the second comparator is used to receive a second reference electrical signal, and the third end of the second comparator is electrically connected to the first end of the first logic unit; Among them, the preset threshold value is the second reference electrical signal. When the output signal of the power supply is greater than the second reference electrical signal, the third end of the second comparator outputs the third signal; when the output signal of the power supply is less than or equal to the second reference electrical signal, the third end of the second comparator outputs the fourth signal.

7. The power control circuit according to claim 6, characterized in that: The second reference electrical signal is less than or equal to the first reference electrical signal.

8. The power control circuit according to claim 2, characterized in that: The adjustment module comprises: a first OC trigger counting unit, wherein a first end of the first OC trigger counting unit is electrically connected to the LPM power supply protection module, and a second end of the first OC trigger counting unit is electrically connected to the register unit; The first OC trigger counting unit is used to count the number of times the LPM overcurrent protection module triggers an OC event, wherein when the count value of the first OC trigger counting unit is greater than or equal to a first preset value, the first OC trigger counting unit transmits the second signal to the register unit; when the count value of the first OC trigger counting unit is less than the first preset value, the first OC trigger counting unit transmits the first signal to the register unit.

9. The power control circuit according to claim 1, characterized in that: The adjustment module comprises: a second OC trigger counting unit, wherein a first end of the second OC trigger counting unit is electrically connected to the LPM power protection module, and the second OC trigger counting unit is used to count the number of times the LPM overcurrent protection module triggers an OC event; The power control circuit further includes: a processor; The processor is used to read the count value of the second OC trigger counting unit, and when the count value of the second OC trigger counting unit is greater than or equal to the second preset value, the processor controls the first bit in the register unit to be the second identifier; when the count value of the second OC trigger counting unit is less than the second preset value, the identifier of the first bit in the register unit remains unchanged.

10. The power supply control circuit according to claim 8 or 9, characterized in that: The LPM overcurrent protection module includes: a first detection unit, a first comparator, a second delay unit, a third logic unit, an LPM OC flag register unit and a first OC response unit; The first detection unit is electrically connected to the output end of the power supply and the first end of the first comparator respectively, the second end of the first comparator is used to receive a first reference electrical signal, the third end of the first comparator is electrically connected to the first end of the third logic unit and the first end of the second delay unit respectively, the second end of the second delay unit is electrically connected to the second end of the third logic unit, the third end of the third logic unit is electrically connected to the first end of the LPM OC flag register unit, and the first OC response unit is electrically connected to the second end of the LPM OC flag register unit; The first OC trigger counting unit or the second OC trigger counting unit is electrically connected to the third end of the third logic unit.

11. An electronic device, characterized in that: include: A power supply and a power supply control circuit as claimed in any one of claims 1 to 10.

Images