Semiconductor device, charging method thereof, and electronic apparatus

Abstract

Provided are a novel semiconductor device or a semiconductor device capable of preventing overcharge, a charging method therefor, and an electronic apparatus. The power receiving unit has a function of generating a signal that cancels the wireless signal transmitted by the power supply unit when the battery charging is completed. Specifically, when the remaining power of the battery of the power receiving unit is 100% or more than a predetermined reference value, the power receiving unit has a function of generating an electromagnetic wave that cancels the electromagnetic wave transmitted by the power supply unit. As a result, a magnetic field that cancels out the magnetic field formed by the electromagnetic waves transmitted by the power supply unit is formed, and overcurrent in the power receiving unit can be suppressed.

Description

This divisional application of the invention application is a divisional application of the invention patent application with international application number PCT / IB2018 / 052795, international filing date April 23, 2018, entering the Chinese national phase with application number 201880028564.2, and title "Semiconductor Device, Its Charging Method, and Electronic Device". Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. As the technical field of one embodiment of the present invention disclosed in this specification, etc., semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, power storage systems, electronic devices, lighting devices, input devices, input / output devices, their driving methods, and their manufacturing methods can be cited.

[0003] In this specification, etc., a semiconductor device generally refers to a device that can operate by utilizing semiconductor characteristics. Transistors, semiconductor circuits, arithmetic devices, storage devices, etc. are all embodiments of semiconductor devices. In addition, display devices, imaging devices, electro-optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices sometimes each include a semiconductor device. Background Art

[0004] In recent years, various electronic devices such as portable information terminals represented by smartphones, power tools, and electric vehicles are equipped with batteries. Secondary batteries such as lithium-ion batteries that can store electrical energy by charging and can be reused are widely used. The battery can be charged by connecting the electronic device equipped with the battery to a power supply device.

[0005] In addition, by wirelessly supplying power from a power supply device to an electronic device equipped with a battery, the battery can be charged even if the electronic device is not physically connected to the power supply device. For example, Patent Document 1 discloses a power supply method using electromagnetic induction and magnetic field resonance methods. [References] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-125115 Summary of the Invention

[0007] One of the objects of an embodiment of the present invention is to provide a novel semiconductor device. Another object of an embodiment of the present invention is to provide a semiconductor device capable of preventing overcharging. Another object of an embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of an embodiment of the present invention is to provide a semiconductor device capable of increasing the charging speed. Another object of an embodiment of the present invention is to provide a semiconductor device with high versatility. Another object of an embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of an embodiment of the present invention is to provide a semiconductor device with a small area.

[0008] Note that an embodiment of the present invention does not need to achieve all of the above objects, and it is sufficient to achieve at least one object. The description of the above objects does not preclude the existence of other objects. Other objects than the above can be obviously seen and extracted from the descriptions in the specification, claims, drawings, etc.

[0009] The semiconductor device according to an embodiment of the present invention includes a transceiver circuit and a battery. The transceiver circuit is configured to receive a first electromagnetic wave transmitted by a power supply unit to supply power to the battery and generate a second electromagnetic wave using the power of the battery. The second electromagnetic wave is generated using the power of the battery when the battery charging is completed. The second electromagnetic wave is configured to cancel the first electromagnetic wave.

[0010] In the semiconductor device according to an embodiment of the present invention, the transceiver circuit includes an antenna circuit and a control circuit. The antenna circuit is configured to receive the first electromagnetic wave and transmit the second electromagnetic wave. The control circuit can be configured to: judge whether to generate the second electromagnetic wave according to the information about overcharging; when it is determined to generate the second electromagnetic wave, supply an AC signal for generating the second electromagnetic wave to the antenna circuit.

[0011] In the semiconductor device according to an embodiment of the present invention, the transceiver circuit includes an antenna circuit and a control circuit. The control circuit includes a determination circuit and a signal generation circuit. The antenna circuit is configured to receive the first electromagnetic wave and transmit the second electromagnetic wave. The determination circuit is configured to judge whether to generate the second electromagnetic wave according to the information about overcharging. The signal generation circuit can be configured to supply a second AC signal for generating the second electromagnetic wave to the antenna circuit using a first AC signal generated according to the first electromagnetic wave and the power supplied by the battery.

[0012] In the semiconductor device according to an embodiment of the present invention, the information about overcharging may further include temperature information measured by a sensor or reception time information of the first electromagnetic wave.

[0013] In a semiconductor device according to an embodiment of the present invention, the transceiver circuit includes a neural network. Data corresponding to information regarding overcharging can be input to the input layer of the neural network. Data corresponding to a determination result as to whether to generate a second electromagnetic wave can be output from the output layer of the neural network.

[0014] The semiconductor device according to any one of the embodiments of the present invention may also be configured to transmit a third electromagnetic wave that enhances the first electromagnetic wave when the battery charging is completed.

[0015] An electronic device according to an embodiment of the present invention is an electronic device including the above-described semiconductor device.

[0016] According to an embodiment of the present invention, a novel semiconductor device can be provided. According to an embodiment of the present invention, a semiconductor device capable of preventing overcharging can be provided. According to an embodiment of the present invention, a semiconductor device with high reliability can be provided. According to an embodiment of the present invention, a semiconductor device capable of increasing the charging speed can be provided. According to an embodiment of the present invention, a semiconductor device with high versatility can be provided. According to an embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to an embodiment of the present invention, a semiconductor device with a small area can be provided.

[0017] Note that the description of these effects does not preclude the existence of other effects. An embodiment of the present invention does not necessarily have all of the above effects. Effects other than the above can be obviously seen and extracted from the description of the specification, claims, drawings, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1A 、 Figure 1B1 、 Figure 1B2 and Figure 1C show a structural example of a power supply system. Figure 2 show a structural example of a power receiving unit. Figure 3 show a structural example of an antenna circuit. Figure 4A1 、 Figure 4A2 、 Figure 4B1 and Figure 4B2 show structural examples of a rectifier circuit and a charging circuit. Figure 5A 、 Figure 5B and Figure 5C show a structural example of a control circuit. Figure 6 is a flowchart. Figure 7A and Figure 7B are flowcharts. Figure 8Aand Figure 8B shows a structural example of a power supply system. Figure 9 shows a structural example of a power receiving unit. Figure 10A and Figure 10B shows a structural example of a delay circuit and an antenna circuit. Figure 11 shows a structural example of a control circuit. Figure 12A 、 Figure 12B and Figure 12C each shows a structural example of a neural network. Figure 13 shows a structural example of a semiconductor device. Figure 14 shows a structural example of a storage circuit. Figure 15 shows a structural example of a storage cell. Figure 16 shows a structural example of a circuit. Figure 17 is a timing diagram. Figure 18A 、 Figure 18B and Figure 18C shows a structural example of a transistor. Figure 19 is an energy band diagram. Figure 20 shows a structural example of a semiconductor device. Figure 21A 、 Figure 21B 、 Figure 21C 、 Figure 21D 、 Figure 21E and Figure 21F shows a structural example of an electronic device. Figure 22A and Figure 22B shows a structural example of an electronic device. Figure 23 shows a structural example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0019] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and it is easily understandable for those of ordinary skill in the art that the methods and details can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the contents described in the embodiments shown below.

[0020] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (Oxide Semiconductor, also simply referred to as OS), etc. For example, when a metal oxide is used in the channel formation region of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide has at least one of an amplification function, a rectification function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor, simply referred to as OS. In the following description, a transistor including a metal oxide in the channel formation region is also referred to as an OS transistor.

[0021] In this specification and the like, a metal oxide containing nitrogen is sometimes also referred to as a metal oxide. In addition, a metal oxide containing nitrogen can also be referred to as a metal oxynitride. The details of the metal oxide will be described later.

[0022] In this specification and the like, when it is clearly described as "X is connected to Y", it means the following situations: the situation where X is electrically connected to Y; the situation where X is functionally connected to Y; and the situation where X is directly connected to Y. Therefore, it is not limited to the connection relationships specified in the drawings or the text, and connection relationships other than those shown in the drawings or the text are also included in the drawings or the text. Here, X and Y are each an object (for example, a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film or layer, etc.).

[0023] As an example of the situation where X is directly connected to Y, the following can be cited: the situation where an element capable of electrically connecting X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, or a load, etc.) does not connect between X and Y; and the situation where X and Y are connected without passing through an element capable of electrically connecting X and Y.

[0024] As an example of the situation where X is electrically connected to Y, one or more elements capable of electrically connecting X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, or a load, etc.) can be connected between X and Y. Note that the switch is controlled to be turned on or off. In other words, whether to allow current to flow is controlled by making the switch in the on state or the off state. Or, the switch has a function of selecting and switching current paths. Note that the situation where X is electrically connected to Y includes the situation where X is directly connected to Y.

[0025] As an example of a case where X and Y are functionally connected, one or more circuits capable of functionally connecting X and Y can be connected between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (DA conversion circuits, AD conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boost circuits, buck circuits, etc.), level shift circuits that change the potential level of a signal, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits capable of increasing the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, storage circuits, control circuits, etc.). For example, even if there are other circuits between X and Y, when the signal output from X is transmitted to Y, X and Y are functionally connected. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

[0026] Note that when it is explicitly stated that "X and Y are electrically connected", in this specification, etc., it means the following cases: the case where X and Y are electrically connected (in other words, the case where X and Y are connected with other elements or other circuits interposed therebetween); the case where X and Y are functionally connected (in other words, the case where X and Y are functionally connected with other circuits interposed therebetween); and the case where X and Y are directly connected (in other words, the case where X and Y are connected without other elements or other circuits interposed therebetween). In other words, in this specification, etc., when it is explicitly stated that "X and Y are electrically connected", it has the same meaning as when it is only explicitly stated that "X and Y are connected".

[0027] Even if independent components in the drawings are electrically connected to each other, there are cases where one component has the functions of multiple components. For example, when a part of the wiring is also used as an electrode, one conductive film has the functions of wiring and an electrode. Therefore, the category of "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0028] (Embodiment 1) In this embodiment, a semiconductor device and a power supply system according to an embodiment of the present invention will be described.

[0029] <Structural example of the power supply system> Figure 1A A structural example of the power supply system 10 is shown. The power supply system 10 includes a power supply unit 11 and a power receiving unit 12. The power supply system 10 has a function of charging the power receiving unit 12 using a wireless signal transmitted by the power supply unit 11. Hereinafter, power supply using a wireless signal is also referred to as wireless power supply or radio frequency (RF) power supply.

[0030] Note that each of the power supply unit 11 and the power receiving unit 12 can be constituted by a semiconductor device. Therefore, each of the power supply unit 11 and the power receiving unit 12 can also be referred to as a semiconductor device.

[0031] The power supply unit 11 has a function of supplying power to the power receiving unit 12 using a wireless signal. Specifically, the power supply unit 11 has a function of generating an electromagnetic wave Wf for charging the power receiving unit 12. As the power supply unit 11, for example, a power supply device that wirelessly supplies power to the power receiving unit 12 in a non-contact manner or a power supply device that wirelessly supplies power to the power receiving unit 12 placed on a power supply board can be used.

[0032] The power receiving unit 12 has a function of being charged using the wireless signal transmitted by the power supply unit 11. Specifically, the power receiving unit 12 includes a battery, which has a function of charging the battery by supplying power generated from the electromagnetic wave Wf received from the power supply unit 11. As the power receiving unit 12, for example, electronic devices such as portable information terminals (mobile phones, smartphones, tablet information terminals, laptop computers, e-books, etc.), digital cameras, portable game consoles, portable music players, power tools, home appliances, medical devices, etc., vehicles, etc. can be used.

[0033] The transmission method of the electromagnetic wave Wf between the power supply unit 11 and the power receiving unit 12 can be appropriately set according to specifications and the like. For example, as the transmission method, an electromagnetic coupling method, an electromagnetic induction method, a microwave method, etc. can be used. There is no particular limitation on the frequency of the electromagnetic wave Wf generated by the power supply unit 11. For example, the following frequencies can be used: sub-millimeter waves of 300 GHz or more and less than 3 THz, millimeter waves of 30 GHz or more and less than 300 GHz, microwaves of 3 GHz or more and less than 30 GHz, ultra-short waves of 300 MHz or more and less than 3 GHz, extremely ultra-short waves of 30 MHz or more and less than 300 MHz, short waves of 3 MHz or more and less than 30 MHz, medium waves of 300 kHz or more and less than 3 MHz, long waves of 30 kHz or more and less than 300 kHz, or extremely long waves of 3 kHz or more and less than 30 kHz.

[0034] As Figure 1A shown, the power supply unit 11 can send an electromagnetic force Wf to a plurality of power receiving units 12. Thereby, a plurality of power receiving units 12 can be charged simultaneously.

[0035] However, the charging end times of the plurality of power receiving units 12 are not necessarily the same. Therefore, as Figure 1B1As shown, the charged power receiving unit 12 (the shaded power receiving unit 12 in the drawing) and the uncharged power receiving unit 12 may be mixed together. As long as there is an uncharged power receiving unit 12, the power supply unit 11 continuously transmits the electromagnetic wave Wf. Therefore, the charged power receiving unit 12 is also continuously exposed to the electromagnetic wave Wf and becomes overcharged, resulting in an overcurrent in the power receiving unit 12. This causes the metal part in the power receiving unit 12 to heat up, which may deteriorate or cause a fire in the components (elements or batteries, etc.) in the power receiving unit 12. Generally, when the remaining battery power is 100%, the deterioration due to temperature rise is particularly obvious. Therefore, if the power receiving unit 12 continues to receive the electromagnetic wave Wf after being charged, it is more likely to cause battery deterioration due to heating.

[0036] Here, the power receiving unit 12 according to an embodiment of the present invention has a function of generating a signal that cancels the wireless signal transmitted by the power supply unit 11 when the battery charging ends. Specifically, when the remaining battery power of the power receiving unit 12 is 100% or above a specified reference value, as Figure 1B2 shown, the power receiving unit 12 has a function of generating an electromagnetic wave Wc that cancels the electromagnetic wave Wf transmitted by the power supply unit 11. Thus, as Figure 1C shown, a magnetic field Hc that cancels the magnetic field Hf formed by the electromagnetic wave Wf transmitted by the power supply unit 11 is formed, thereby suppressing the overcurrent in the power receiving unit 12. Thereby, deterioration and ignition of the power receiving unit 12 can be prevented, and the reliability of the power receiving unit 12 can be improved.

[0037] Note that the electromagnetic wave Wc can be any electromagnetic wave as long as it can cancel the electromagnetic wave Wf. For example, as the electromagnetic wave Wc, an electromagnetic wave transmitted to the power supply unit 11 and having the same frequency as the electromagnetic wave Wf can be used. Specifically, the frequency of the electromagnetic wave Wc is set to an integer multiple of the frequency of the electromagnetic wave Wf.

[0038] Furthermore, the power receiving unit 12 according to an embodiment of the present invention has a function of generating the electromagnetic wave Wc using the power stored in the fully charged battery. Thereby, the remaining battery power can be maintained at a state less than 100% (for example, about 95%), and deterioration of the battery due to temperature change can be suppressed.

[0039] Note that in this specification, etc., "canceling the electromagnetic wave Wf" includes not only a method of completely canceling the electromagnetic wave Wf received by the power receiving unit 12 but also a method of weakening the electromagnetic wave Wf received by the power receiving unit 12. That is, an embodiment of the present invention includes not only a method of preventing the power receiving unit 12 from receiving the electromagnetic wave Wc using the electromagnetic wave Wf but also a method of weakening the electromagnetic wave Wf received by the power receiving unit 12 using the electromagnetic wave Wc.

[0040] <Structural example of the power receiving unit> Figure 2Shows a specific structural example of the power receiving unit 12 having the above functions. Figure 2 The power receiving unit 12 shown includes a transceiver circuit 20, a battery 30, a sensor 40, and a timer 50.

[0041] The transceiver circuit 20 has the function of receiving the electromagnetic wave Wf to supply power to the battery 30 and the function of generating the electromagnetic wave Wc using the power of the battery 30. The transceiver circuit 20 includes an antenna circuit 21, a rectifier circuit 22, a charging circuit 23, and a control circuit 24.

[0042] The antenna circuit 21 has the function of receiving the electromagnetic wave Wf generated by the power supply unit 11, converting it into an AC signal, and supplying the AC signal to the rectifier circuit 22 and the control circuit 24. In addition, the antenna circuit 21 also has the function of converting the AC signal supplied by the control circuit 24 into the electromagnetic wave Wc and transmitting the electromagnetic wave Wc to the outside of the power receiving unit 12.

[0043] The antenna can be used for receiving the electromagnetic wave Wf and transmitting the electromagnetic wave Wc. The shape of the antenna can be determined according to the transmission method. For example, when the electromagnetic coupling method or the electromagnetic induction method (e.g., 13.56 MHz band) is adopted as the transmission method, the electromagnetic induction according to the change of the electric field density is utilized. Therefore, as the antenna, a ring-shaped conductive film (e.g., loop antenna) or a spiral-shaped conductive film (e.g., spiral antenna) is preferably used. In the case of using the microwave method (e.g., UHF band (860 to 960 MHz band), 2.45 GHz band), the length or shape of the conductive film used as the antenna can be appropriately set considering the wavelength of the electromagnetic wave. For example, as the antenna, a linear conductive film (e.g., dipole antenna) or a flat-shaped conductive film (e.g., patch antenna) can be used. Note that the shape of the conductive film used as the antenna is not limited to this. For example, considering the wavelength of the electromagnetic wave, a curved shape and / or a meandering shape can be adopted. In addition, an antenna compatible with electromagnetic waves of multiple bands combining multiple shapes can also be used.

[0044] Figure 3 Shows a structural example of the antenna circuit 21. The antenna circuit 21 includes a receiving circuit 101 and a transmitting circuit 102. The receiving circuit 101 has the function of converting the electromagnetic wave Wf into an AC signal and supplying the AC signal to the rectifier circuit 22 and the control circuit 24. The transmitting circuit 102 has the function of converting the AC signal supplied by the control circuit 24 into the electromagnetic wave Wc and transmitting the electromagnetic wave Wc to the outside.

[0045] The receiving circuit 101 includes an antenna coil 111 and a capacitor 112. The capacitor 112 functions as a resonant capacitor. By using a variable capacitor as the capacitor 112 and controlling the capacitance value, the frequency of the received electromagnetic wave can be controlled. The transmitting circuit 102 includes an antenna coil 113 and a capacitor 114. The capacitor 114 functions as a resonant capacitor. The frequency of the electromagnetic wave Wc generated by the transmitting circuit 102 can be controlled by using the frequency of the AC signal input from the control circuit 24. Note that as each of the receiving circuit 101 and the transmitting circuit 102, a resonant circuit is preferably used.

[0046] Although Figure 3 the receiving circuit 101 and the transmitting circuit 102 are separately provided in Figure 3 , a circuit shared by each other may also be provided. For example, the transmitting circuit 102 in

[0047] can be omitted, and the receiving circuit 101 can also have the function of the transmitting circuit 102. Figure 4A1 The rectifying circuit 22 has a function of rectifying the AC signal supplied by the antenna circuit 21 and converting it into a DC signal.

[0048] Note that each of the diode 121 and the diode 123 may be a diode-connected transistor. Figure 4A2 The structural example when transistors are used as the diode 121 and the diode 123 is shown.

[0049] In order to prevent the reverse flow of current, it is preferable that the off-state current of the transistors used as the diode 121 and the diode 123 is extremely low. Therefore, an OS transistor is suitable as such a transistor. The off-state current of the OS transistor normalized by the channel width in a state where the source-drain voltage is 10 V and at room temperature (around 25 °C) can be 10×10 -21 A / μm (10 zA / μm) or less. Thus, the OS transistor can effectively prevent the reverse flow of current. The OS transistor will be described in detail in Embodiment 5.

[0050] The charging circuit 23 has a function of controlling the voltage level of the DC signal supplied by the rectifying circuit 22 and supplying it to the battery 30. Thus, a predetermined voltage is applied to the battery 30 and it can be charged.

[0051] Figure 4B1Shows a structural example of the charging circuit 23. The charging circuit 23 includes a regulator 131 and a switch 132. The regulator 131 has a function of controlling the voltage input from the rectifier circuit 22. The voltage converted by the regulator 131 is supplied to the battery 30 through the switch 132.

[0052] The switch 132 has a function of controlling whether to supply power to the battery 30. During the charging of the battery 30, the switch 132 is in the on state, and during the period when the battery 30 is not being charged, the switch 132 is in the off state.

[0053] Note that, as Figure 4B2 shown, a transistor can also be used as the switch 132. In this case, the on state of the switch 132 can be controlled by controlling the gate voltage of the transistor. The transistor used as the switch 132 can have a back gate.

[0054] In order to prevent power leakage of the battery 30, it is preferable that the off-state current of the transistor used as the switch 132 is small. Therefore, an OS transistor is preferably used as the switch 132.

[0055] The battery 30 has a function of supplying power to other circuits in the power receiving unit 12. Note that there is no particular limitation on the type of the battery 30. As the battery 30, for example, secondary batteries such as lithium-ion batteries, lead-acid batteries, lithium-ion polymer secondary batteries, nickel-metal hydride storage batteries, nickel-cadmium storage batteries, nickel-iron storage batteries, nickel-zinc storage batteries, silver-zinc oxide storage batteries, etc.; liquid circulation type secondary batteries such as redox flow batteries, zinc-chlorine batteries, zinc-bromine batteries, etc., mechanically rechargeable secondary batteries such as aluminum-air batteries, air-zinc batteries, air-iron batteries, etc.; and high-temperature operating secondary batteries such as sodium-sulfur batteries, lithium iron sulfide batteries, etc. can be used.

[0056] The control circuit 24 has a function of controlling the generation of the electromagnetic wave Wc. Specifically, the control circuit 24 has a function of judging whether to generate the electromagnetic wave Wc based on the information about overcharging (hereinafter, also referred to as overcharging information) input from the outside. When it is judged that the electromagnetic wave Wc needs to be generated, the control circuit 24 supplies an AC signal to the antenna circuit 21. Figure 2 As an example, a structural example is shown in which overcharging information is input from the sensor 40 and the timer 50 to the control circuit 24.

[0057] The sensor 40 has a function of measuring the temperature of the power receiving unit 12. Note that there is no particular limitation on the measurement location. For example, when the power receiving unit 12 is an electronic device, the sensor 40 can measure the temperature of the housing of the electronic device or any place inside the electronic device. The sensor 40 can also measure the surface temperature of the battery 30. The temperature measured by the sensor 40 is converted into a signal and input to the control circuit 24.

[0058] The timer 50 has a function of measuring the time of wireless power supply. For example, the timer 50 can measure the following times: the total time during which the power receiving unit 12 continuously receives the electromagnetic wave Wf; the time during which the power receiving unit 12 continuously receives the electromagnetic wave Wf after the battery 30 is fully charged; and so on. The time measured by the timer 50 is converted into a signal and input to the control circuit 24.

[0059] The temperature information obtained by the sensor 40 and the time information of wireless power supply obtained by the timer 50 are supplied to the control circuit 24 as overcharge information. The control circuit 24 has a function of selecting whether to generate the electromagnetic wave Wc based on this overcharge information. For example, when the temperature of the power receiving unit 12 is equal to or higher than a specified value or the total time during which the power receiving unit 12 continuously receives the electromagnetic wave Wf is equal to or higher than a specified value, the control circuit 24 can generate the electromagnetic wave Wc to stop the wireless power supply.

[0060] Note that either the sensor 40 or the timer 50 shown in the structural example can be omitted. In addition, a circuit for measuring other overcharge information (the distance between the power supply unit 11 and the power receiving unit 12, the magnetic induction intensity, the remaining battery power, etc.) can be provided to replace one or both of the sensor 40 and the timer 50.

[0061] Figure 5A A structural example of the control circuit 24 is shown. The control circuit 24 includes a determination circuit 141, a signal generation circuit 142, and a switch circuit 143. The overcharge information output from the sensor 40, the timer 50, etc. is input to the determination circuit 141.

[0062] The determination circuit 141 has a function of determining whether to generate the electromagnetic wave Wc based on the overcharge information. For example, when the temperature of the power receiving unit 12 is equal to or higher than a reference value or the total time during which the power receiving unit 12 continuously receives the electromagnetic wave Wf is equal to or higher than a reference value, the determination circuit 141 can determine to generate the electromagnetic wave Wc. When it is determined that the electromagnetic wave Wc needs to be generated, the determination circuit 141 has a function of providing a signal indicating the generation of the electromagnetic wave Wc to the signal generation circuit 142.

[0063] In addition, the determination circuit 141 has a function of outputting a control signal corresponding to the determination result to the switch circuit 143. Specifically, when the determination circuit 141 determines that the electromagnetic wave Wc needs to be generated, the determination circuit 141 has a function of controlling the conduction state of the switch circuit 143 so that the battery 30 supplies power to the signal generation circuit 142. Thereby, the signal generation circuit 142 can generate the electromagnetic wave Wc using the power of the battery 30.

[0064] The signal generation circuit 142 has a function of generating a signal for generating the electromagnetic wave Wc according to the determination result of the determination circuit 141. Specifically, when the determination circuit 141 determines that the electromagnetic wave Wc needs to be generated, the signal generation circuit 142 has a function of generating an alternating current signal by using the alternating current signal supplied by the antenna circuit 21 and the electric power supplied by the battery 30. When the determination circuit 141 determines that the electromagnetic wave Wc does not need to be generated, the battery 30 does not supply power to the signal generation circuit 142, and the signal generation circuit 142 does not generate an alternating current signal.

[0065] Figure 5B Fig. shows a structural example of the signal generation circuit 142. The signal generation circuit 142 includes a buffer circuit 150. The buffer circuit 150 has a function of controlling the output of the alternating current signal input from the antenna circuit 21 according to the signal input from the determination circuit 141. Specifically, the alternating current signal generated according to the electromagnetic wave Wf received by the antenna circuit 21 from the power supply unit 11 is input to the buffer circuit 150. The determination circuit 141 inputs a signal corresponding to whether the electromagnetic wave Wc needs to be generated to the buffer circuit 150. And when the determination circuit 141 determines that the electromagnetic wave Wc needs to be generated, the buffer circuit 150 outputs an alternating current signal to the antenna circuit 21. Thus, an alternating current signal synchronized with the frequency of the electromagnetic wave Wf is supplied to the antenna circuit 21. And the antenna circuit 21 converts the alternating current signal supplied by the signal generation circuit 142 into the electromagnetic wave Wc and transmits it to the outside.

[0066] Figure 5C Fig. shows a specific structural example of the buffer circuit 150. The buffer circuit 150 includes transistors 151 to 156 and an inverter 157. Transistors 151 to 154 constitute a first inverter. Transistors 155 and 156 constitute a second inverter. Note that the first inverter can control its operating state according to the signals input to transistors 153 and 154.

[0067] The gates of transistors 151 and 152 are each input with the alternating current signal output from the antenna circuit 21. Each of the source and drain of transistors 151 and 152 is connected to the gates of transistors 155 and 156. Each of the source and drain of transistors 155 and 156 is connected to the antenna circuit 21.

[0068] The determination circuit 141 inputs a signal corresponding to whether the electromagnetic wave Wc needs to be generated to the gate of the transistor 153. The signal input from the determination circuit 141 is inverted by the inverter 157, and this signal is input to the gate of the transistor 154. The transistors 153 and 155 are supplied with the high power supply potential VDD. The transistors 154 and 156 are supplied with the low power supply potential VSS. Note that the high power supply potential VDD and the low power supply potential VSS can be supplied from the battery 30 to the buffer circuit 150 through the switch circuit 143.

[0069] When the electromagnetic wave Wc is generated, the transistors 153 and 154 become conductive according to the signal supplied from the determination circuit 141. As a result, an AC signal synchronized with the frequency of the electromagnetic wave Wf is supplied from each of the source and drain of the transistors 155 and 156 to the antenna circuit 21. When the electromagnetic wave Wc is not generated, the transistors 153 and 154 become non-conductive according to the signal supplied from the determination circuit 141. As a result, the buffer circuit 150 stops generating the AC signal.

[0070] As described above, the power receiving unit 12 according to an embodiment of the present invention can control the power supply to the power receiving unit 12 by generating the electromagnetic wave Wc according to the charging state. Note that, as Figure 2 shown, the power supply unit 11 can have a signal Sr that outputs the following information to the power receiving unit 12: information on whether the charging of the battery 30 is completed; remaining battery level information of the battery 30; charging time information; and so on. When the power supply unit 11 outputs the signal Sr, the power receiving unit 12 outputs a signal Sq corresponding to the required information to the power supply unit 11. As a result, the power supply unit 11 can monitor the charging state of the power receiving unit 12 and select whether to transmit the electromagnetic wave Wf.

[0071] <Operating example of the power supply system> Next, an operating example of the power supply system 10 will be described with reference to Figure 6 the flowchart showing the operating example of the power supply system 10. Note that here, an example of charging a plurality of power receiving units 12 using the electromagnetic wave Wf transmitted by the power supply unit 11 will be described. Here, the temperature of the power receiving unit 12 is used as overcharge information, and it is determined whether to generate the electromagnetic wave Wc based on the temperature of the power receiving unit 12. Figure 6

[0072] First, when the power receiving unit 12 is arranged at a position where wireless charging can be performed, the power supply unit 11 transmits the electromagnetic wave Wf to the power receiving unit 12 (step S1). Then, the electromagnetic wave Wf is supplied to the battery 30 through the antenna circuit 21, the rectifying circuit 22, and the charging circuit 23 to charge the battery 30 (step S2).

[0073] When the battery 30 is fully charged (YES in step S3), it is confirmed whether all other power receiving units 12 are also fully charged (step S4). Step S4 can be performed by the following method: The power supply unit 11 sends a signal Sr to all the power receiving units 12 and receives a signal Sq from each power receiving unit 12 (refer to Figure 2 ). When all the power receiving units 12 are fully charged (YES in step S4), the power supply unit 11 stops transmitting the electromagnetic wave Wf (step S5).

[0074] Note that the criterion for determining that the battery 30 is fully charged can be freely set. For example, it can be based on whether the remaining battery power reaches a predetermined value (e.g., 100%). In addition, the charging status of the power receiving unit 12 can be monitored by causing the power supply unit 11 to send a signal Sr at a predetermined frequency.

[0075] On the other hand, when any of the power receiving units 12 is not fully charged (NO in step S4), the electromagnetic wave Wf is continuously transmitted. The temperature of the fully charged power receiving unit 12 is measured using the sensor 40. When the temperature of the power receiving unit 12 is above the reference value (YES in step S6), power is supplied to the control circuit 24 using the discharge of the battery 30 (step S7) to generate an electromagnetic wave Wc (step S8). Thereby, the electromagnetic wave Wf is canceled and the charging of the power receiving unit 12 is stopped, thereby preventing overcharging. Since the battery 30 discharges and the remaining power is less than 100%, the deterioration of the battery 30 can be suppressed.

[0076] Then, when the remaining power of the battery 30 remains above the reference value (NO in step S9), the operations of steps S6 to S8 are repeated. Note that when the temperature of the power receiving unit 12 is below the reference value, the power receiving unit 12 can determine that the influence of heat is small and does not need to generate the electromagnetic wave Wc (NO in step S6).

[0077] When the remaining power of the battery 30 becomes lower than the reference value due to the generation of the electromagnetic wave Wc (YES in step S9), the charging of the battery 30 is restarted (step S2). And the operations after step S3 are continuously performed until all the power receiving units 12 are fully charged.

[0078] Through the above operations, all the power receiving units 12 can be charged while suppressing overcharging. Note that the reference value of the temperature in step S6 and the reference value of the remaining power of the battery 30 in step S9 can be freely set according to the characteristics of the battery 30, etc. For example, when the maximum allowable temperature of the battery 30 is T °C, the reference value of the temperature can be set to above (T - 20) °C and below T °C, above (T - 15) °C and below T °C, above (T - 10) °C and below T °C, or above (T - 5) °C and below T °C, etc. As the reference value of the remaining power of the battery 30, the remaining power of 95%, 90%, 85%, 80%, etc. can be set.

[0079] [Additional operation 1] The operation of the power supply system 10 is not limited to Figure 6 the operation shown, and other operations can be appropriately added. For example, in Figure 6 , only the power receiving unit 12 that has been fully charged is subjected to temperature measurement (step S6), but in order to suppress heat generation, even if the power receiving unit 12 is being charged, as long as its temperature becomes equal to or higher than the reference value, charging of the power receiving unit 12 can be stopped. Figure 7A An operation example of temporarily stopping charging corresponding to the temperature of the power receiving unit 12 is shown.

[0080] When it is detected that the temperature of the power receiving unit 12 is equal to or higher than the reference value (step S21), charging is stopped regardless of whether the battery 30 is fully charged (step S22). Then, the charging stop state is maintained. When the temperature of the power receiving unit 12 decreases to below the reference value (YES in step S23), charging of the battery 30 is restarted (step S24). By this operation, heat generation during charging can be suppressed.

[0081] [Additional operation 2] In Figure 6 and Figure 7A , the operation of determining whether to stop charging based on the temperature of the power receiving unit 12 has been described, but whether to stop charging can also be determined based on other overcharging information. Figure 7B An operation example of determining whether to temporarily stop charging based on the reception time of the electromagnetic wave Wf is shown.

[0082] First, when it is detected that the period during which the power receiving unit 12 continuously receives the electromagnetic wave exceeds the reference value (step S31), charging is stopped regardless of whether the battery 30 is fully charged (step S32). When the charging stop state has passed a certain period (YES in step S33), charging of the battery 30 is restarted (step S34). By this operation, heat generation of the power receiving unit 12 can be prevented.

[0083] Note that the methods of stopping charging in step S22 and step S32 are not limited to this. For example, charging can be stopped by generating the electromagnetic wave Wc or by turning the switch 132 in Figure 4B1 and Figure 4B2 into the closed state, etc.

[0084] Figure 7A and Figure 7B The operations shown can be appropriately added as additional operations to Figure 6 the operations shown.

[0085] As described above, in one embodiment of the present invention, when the remaining power of the battery 30 is equal to or greater than a predetermined value, the deterioration and ignition of the power receiving unit 12 can be prevented by canceling the electromagnetic wave generated by the power supply unit 11. In addition, by using the power of the battery 30 to cancel the electromagnetic wave, the remaining power of the battery 30 can be maintained in a state where it is equal to or greater than the reference value and less than 100%, thereby preventing the deterioration of the battery.

[0086] This embodiment can be appropriately combined with any other embodiment.

[0087] (Embodiment 2) In this embodiment, a modified example of the power supply system described in the above embodiment will be described.

[0088] Figure 8A Another structural example of the power supply system 10 is shown. Figure 8A The shown power supply system 10 is different from Figures 1A to 1C the shown power supply system 10 in that Figure 8A the shown power receiving unit 12 has a function of generating an electromagnetic wave We. For other structures, reference can be made to the description of Embodiment 1.

[0089] As Figure 8A shown, the fully charged power receiving unit 12 (the power receiving unit 12 shaded in the drawing) has a function of transmitting the electromagnetic wave We to other power receiving units 12 that are not fully charged using the electromagnetic wave Wf. The electromagnetic wave We can enhance the electromagnetic wave Wf of the power receiving unit 12 that is not fully charged. As Figure 8B shown, the magnetic field Hf formed by the electromagnetic wave Wf is enhanced by the magnetic field He formed by the electromagnetic wave We, and the electromagnetic wave Wf received by the power receiving unit 12 that is not fully charged is enhanced. Thereby, the charging efficiency of the power receiving unit 12 that is not fully charged can be improved, and thus the charging speed can be increased.

[0090] The electromagnetic wave We can be any electromagnetic wave that can enhance the electromagnetic wave Wf. For example, as the electromagnetic wave We, an electromagnetic wave having the same frequency and phase as the electromagnetic wave Wf can be used. Note that the phases of the electromagnetic wave Wf and the electromagnetic wave We do not need to be exactly the same, as long as they are adjusted to a degree that can promote the charging of the power receiving unit 12 that is not fully charged.

[0091] Note that the power receiving unit 12 has a function of transmitting the electromagnetic wave Wf described in Embodiment 1 in addition to being able to transmit the electromagnetic wave We.

[0092] Figure 9 A specific structural example of the power receiving unit 12 having the function of transmitting the electromagnetic wave We is shown. Figure 9 The shown power receiving unit 12 is different from Figure 2 the shown power receiving unit 12 in that Figure 9The power receiving unit 12 shown includes a switch circuit 25, a delay circuit 26, and an antenna circuit 27. For other structures, reference can be made to Figure 2 for the description.

[0093] The switch circuit 25 has the function of controlling the antenna circuit 21 to supply an alternating current signal to the delay circuit 26. When generating the electromagnetic wave We, the switch circuit 25 becomes conductive, and the antenna circuit 21 supplies an alternating current signal to the delay circuit 26.

[0094] The condition for the antenna circuit 21 to supply an alternating current signal to the delay circuit 26 can be freely set. For example, it can be based on the condition that the battery 30 is fully charged.

[0095] The delay circuit 26 has the function of delaying the alternating current signal supplied from the antenna circuit 21 through the switch circuit 25. Thus, due to the phase shift of the alternating current signal generated according to the electromagnetic wave Wf, this signal is supplied to the antenna circuit 27. That is to say, the delay circuit 26 can control the phase of the alternating current signal supplied to the antenna circuit 27.

[0096] Figure 10A An example of the structure of the delay circuit 26 is shown. The delay circuit 26 includes a plurality of inverters 161. By connecting the plurality of inverters 161 in series, the signal output by the rectifier circuit 22 can be delayed to cause a phase shift. Note that there is no particular limitation on the number of inverters 161 connected in series, and the number of inverters 161 can be appropriately selected according to the desired phase shift amount. In addition, resistors or capacitors can be appropriately provided between the inverters 161.

[0097] Note that the delay circuit 26 can also use the power of the battery 30. At this time, during the generation of the electromagnetic wave We, the power of the battery 30 is supplied to the delay circuit 26.

[0098] The antenna circuit 27 has the function of converting the signal generated by the delay circuit 26 into the electromagnetic wave We and outputting this electromagnetic wave We to the outside. Figure 10B An example of the structure of the antenna circuit 27 is shown. The antenna circuit 27 includes an antenna coil 171 and a capacitor 172. The capacitor 172 has the function of a resonant capacitor. Note that as the antenna circuit 27, a resonant circuit is preferably used.

[0099] Although the antenna circuit 27 and the antenna circuit 21 are separately provided in this structure, the antenna circuit 27 can be omitted when the antenna circuit 21 has the function of the antenna circuit 27.

[0100] As described above, by causing the fully charged power receiving unit 12 to send the electromagnetic wave We to the power receiving unit 12 that is not fully charged, the charging efficiency of the power receiving unit 12 that is not fully charged can be improved. Thus, the charging speed can be increased.

[0101] This embodiment can be appropriately combined with any other embodiment.

[0102] (Embodiment 3) In this embodiment, a structural example of a power supply system in which artificial intelligence (AI: Artificial Intelligence) is used in the above-described embodiments will be described.

[0103] Note that artificial intelligence refers to the general term for computers that simulate human intelligence. In this specification and the like, artificial intelligence includes an artificial neural network (ANN: Artificial Neural Network). An artificial neural network refers to a circuit that simulates a neural network composed of neurons and synapses. In this specification and the like, "neural network" particularly refers to an artificial neural network.

[0104] <Structural example of the control circuit> Figure 11 A structural example of the control circuit 24 is shown. Figure 11 The shown control circuit 24 is different from Figure 5A the shown control circuit 24 in that Figure 11 the determination circuit 141 of the shown control circuit 24 has a neural network NN. For other structures, reference can be made to Figure 5A the description.

[0105] The neural network NN includes an input layer IL, an output layer OL, and a hidden layer (intermediate layer) HL. The input layer IL is input with data corresponding to overcharge information obtained by the sensor 40, the timer 50, and the like.

[0106] The output layer OL, the input layer IL, and the hidden layer HL each include one or more units (neuron circuits), and the output of each unit is multiplied by a weight (connection strength) and supplied to units in different layers. Note that the number of units in each layer can be arbitrarily set. The neural network NN can also be a network having a plurality of hidden layers HL (deep neural network (DNN)). Deep neural network learning is sometimes referred to as deep learning.

[0107] The neural network NN obtains a function of selecting whether to generate the electromagnetic wave Wc based on overcharge information (for example, the temperature measured by the sensor 40, the time measured by the timer 50, etc.). When the input layer of the neural network NN is input with data corresponding to overcharge information, each layer performs arithmetic processing. The arithmetic processing of each layer is performed, for example, by performing a product-sum operation of the data output from the units of the previous layer and the weight coefficients. Note that the inter-layer connection can be a full connection in which all units are connected to each other or a partial connection in which some units are connected to each other. And data corresponding to the determination result of whether to generate the electromagnetic wave Wc is output from the output layer OL.

[0108] Thus, by making the determination circuit 141 include the neural network NN, it is possible to appropriately determine whether to generate the electromagnetic wave Wc based on various information regarding overcharging. Thereby, the versatility of the control circuit 24 can be improved.

[0109] <Structural Example of Neural Network> Next, a more specific structural example of the neural network NN will be described. Figures 12A to 12C A structural example of the neural network is shown. The neural network is composed of neuron circuits NC and synaptic circuits SC provided between the neuron circuits.

[0110] Figure 12A Structural examples of the neuron circuit NC and the synaptic circuit SC are shown. Input data x 1 to x L (L is a natural number) are input to the synaptic circuit SC. In addition, each synaptic circuit SC has a function of storing weight coefficients w k (k is an integer of 1 or more and L or less). The weight coefficient w k corresponds to the bonding strength between the neuron circuits NC.

[0111] When input data x 1 to x L is input to the synaptic circuit SC, the neuron circuit NC is supplied with the following value: the product of the input data x k input to the synaptic circuit SC and the weight coefficient w k stored in the synaptic circuit SC (x k w k ), and the value obtained by adding them under the condition of k = 1 to L (x 1 w 1 +x 2 w 2 +...+x L w L ), that is, the value obtained by performing a product-sum operation using x k and w k . When this value exceeds the threshold θ of the neuron circuit NC, the neuron circuit NC outputs a high-level signal y. This phenomenon is called the firing of the neuron circuit NC.

[0112] Figure 12B A model of a hierarchical neural network using the above neuron circuit NC and synaptic circuit SC is shown. The neural network includes an input layer IL, a hidden layer HL, and an output layer OL. The input layer IL includes input neuron circuits IN. The hidden layer HL includes hidden synaptic circuits HS and hidden neuron circuits HN. The output layer OL includes output synaptic circuits OS and output neuron circuits ON. The thresholds θ of the input neuron circuit IN, the hidden neuron circuit HN, and the output neuron circuit ON are respectively denoted as θ I , θH , θ O .

[0113] Supply data x corresponding to overcharge information to the input layer IL 1 to x i (i is a natural number), the output of the input layer IL is supplied to the hidden layer HL. Also, a value obtained by performing a product-sum operation using the output data of the input layer IL and the weight coefficient w held in the hidden synaptic circuit HS is supplied to the hidden neuron circuit HN. A value obtained by performing a product-sum operation using the output of the hidden neuron circuit HN and the weight coefficient w held in the output synaptic circuit OS is supplied to the output neuron circuit ON. And data y corresponding to whether the electromagnetic wave Wc is generated is output from the output neuron circuit ON.

[0114] Thus, Figure 12B the neural network shown has the function of determining whether it is necessary to generate the electromagnetic wave Wc based on the overcharge information.

[0115] In addition, the gradient descent method or the like can be used for the learning of the neural network, and the backpropagation algorithm can be used for calculating the gradient. Figure 12C A model of a neural network for supervised learning using the backpropagation algorithm is shown.

[0116] The backpropagation algorithm is one of the methods for changing the weight coefficients of the synaptic circuit in such a way that the error between the output data of the neural network and the supervised data becomes smaller. Specifically, the weight coefficient w of the hidden synaptic circuit HS is changed according to the error δ determined based on the output data (data y) and the supervised data (data t). In addition, the weight coefficient w of the upper-level synaptic circuit SC is changed according to the change amount of the weight coefficient w of the hidden synaptic circuit HS. Thus, by sequentially changing the weight coefficients of the synaptic circuit SC based on the supervised data, the learning of the neural network NN can be performed. O Note that in

[0117] each, the hidden layer HL is one, but it can also be two or more. Therefore, deep learning can be performed. Figure 12B , Figure 12C This embodiment can be appropriately combined with any other embodiment.

[0118] This embodiment can be appropriately combined with any other embodiment.

[0119] (Embodiment 4) In this embodiment, a structural example of a semiconductor device that can be used for the neural network described in the above embodiment is described.

[0120] When the neural network is configured by hardware, the product-sum operation of the neural network can be performed using a product-sum operation element. In this embodiment, a structural example of a semiconductor device that can be used as the product-sum operation element in the neural network NN is described.

[0121] <Structural Example of Semiconductor Device> Figure 13 Shows a structural example of the semiconductor device 200. Figure 13 The shown semiconductor device 200 includes a storage circuit 210 (MEM), a reference storage circuit 220 (RMEM), a circuit 230, and a circuit 240. The semiconductor device 200 may further include a current source circuit 250 (CREF).

[0122] The storage circuit 210 (MEM) includes storage cells MC such as storage cells MC[p, q] and storage cells MC[p+1, q]. The storage cell MC includes an element having a function of converting an input potential into a current. As an element having the above function, for example, an active element such as a transistor can be used. Figure 13 Shows an example in which the storage cell MC includes a transistor Tr11.

[0123] A first analog potential is input to the storage cell MC through wirings WD such as the wiring WD[q]. The first analog potential corresponds to first analog data. The storage cell MC has a function of generating a first analog current corresponding to the first analog potential. Specifically, the drain current of the transistor Tr11 obtained when the first analog potential is supplied to the gate of the transistor Tr11 can be used as the first analog current. Hereinafter, the current flowing through the storage cell MC[p, q] is referred to as I[p, q], and the current flowing through the storage cell MC[p+1, q] is referred to as I[p+1, q].

[0124] Note that when the transistor Tr11 operates in the saturation region, the drain current does not depend on the voltage between the source and the drain, but is controlled by the difference between the gate voltage and the threshold voltage. Therefore, it is preferable to make the transistor Tr11 operate in the saturation region. The gate voltage and the voltage between the source and the drain are appropriately set to voltages that can make the transistor Tr11 operate in the saturation region.

[0125] Specifically, in Figure 13 In the shown semiconductor device 200, a first analog potential Vx[p, q] or a potential corresponding to the first analog potential Vx[p, q] is input to the storage cell MC[p, q] through the wiring WD[q]. The storage cell MC[p, q] has a function of generating a first analog current corresponding to the first analog potential Vx[p, q]. In other words, at this time, the current I[p, q] of the storage cell MC[p, q] corresponds to the first analog current.

[0126] In addition, in Figure 13In the semiconductor device 200 shown, a first analog potential Vx[p+1, q] or a potential corresponding to the first analog potential Vx[p+1, q] is input to the memory cell MC[p+1, q] through the wiring WD[q]. The memory cell MC[p+1, q] has a function of generating a first analog current corresponding to the first analog potential Vx[p+1, q]. In other words, at this time, the current I[p+1, q] of the memory cell MC[p+1, q] corresponds to the first analog current.

[0127] The memory cell MC has a function of holding the first analog potential. In other words, the memory cell MC has a function of holding the first analog current corresponding to the first analog potential.

[0128] In addition, a second analog potential is input to the memory cell MC through wirings RW such as the wiring RW[p] and the wiring RW[p+1]. The second analog potential corresponds to second analog data. The memory cell MC has a function of adding the second analog potential or a potential corresponding to the second analog potential to the held first analog potential and holding the third analog potential obtained by this addition. The memory cell MC also has a function of generating a second analog current corresponding to the third analog potential. In other words, the memory cell MC has a function of holding the second analog current corresponding to the third analog potential.

[0129] Specifically, in Figure 13 the semiconductor device 200 shown, the second analog potential Vw[p, q] is input to the memory cell MC[p, q] through the wiring RW[p]. The memory cell MC[p, q] has a function of holding the third analog potential corresponding to the first analog potential Vx[p, q] and the second analog potential Vw[p, q]. In addition, the memory cell MC[p, q] has a function of generating a second analog current corresponding to the third analog potential. In other words, at this time, the current I[p, q] of the memory cell MC[p, q] corresponds to the second analog current.

[0130] In addition, in Figure 13 the semiconductor device 200 shown, the second analog potential Vw[p+1, q] is input to the memory cell MC[p+1, q] through the wiring RW[p+1]. The memory cell MC[p+1, q] has a function of holding the first analog potential Vx[p+1, q] and the third analog potential corresponding to the second analog potential Vw[p+1, q]. In addition, the memory cell MC[p+1, q] has a function of generating a second analog current corresponding to the third analog potential. In other words, at this time, the current I[p+1, q] of the memory cell MC[p+1, q] corresponds to the second analog current.

[0131] A current I[p, q] flows between a wiring BL[q] and a wiring VR[q] through a memory cell MC[p, q]. A current I[p + 1, q] flows between the wiring BL[q] and the wiring VR[q] through a memory cell MC[p + 1, q]. Therefore, a current I[q] equivalent to the sum of the current I[p, q] and the current I[p + 1, q] flows between the wiring BL[q] and the wiring VR[q] through the memory cell MC[p, q] and the memory cell MC[p + 1, q].

[0132] The reference memory circuit 220 (RMEM) includes memory cells MCR such as a memory cell MCR[p] and a memory cell MCR[p + 1]. Note that a first reference potential VPR is input to the memory cell MCR through a wiring WDREF. The memory cell MCR has a function of generating a first reference current corresponding to the first reference potential VPR. Hereinafter, the current flowing through the memory cell MCR[p] is referred to as IREF[p], and the current flowing through the memory cell MCR[p + 1] is referred to as IREF[p + 1].

[0133] Specifically, in Figure 13 the semiconductor device 200 shown, the first reference potential VPR is input to the memory cell MCR[p] through the wiring WDREF. The memory cell MCR[p] has a function of generating a first reference current corresponding to the first reference potential VPR. In other words, the current IREF[p] of the memory cell MCR[p] at this time is equivalent to the first reference current.

[0134] In addition, in Figure 13 the semiconductor device 200 shown, the first reference potential VPR is input to the memory cell MCR[p + 1] through the wiring WDREF. The memory cell MCR[p + 1] has a function of generating a first reference current corresponding to the first reference potential VPR. In other words, the current IREF[p + 1] of the memory cell MCR[p + 1] at this time is equivalent to the first reference current.

[0135] The memory cell MCR has a function of holding the first reference potential VPR. In other words, the memory cell MCR has a function of holding a first reference current corresponding to the first reference potential VPR.

[0136] In addition, a second analog potential is input to the memory cell MCR through wirings RW such as a wiring RW[p] and a wiring RW[p + 1]. The memory cell MCR has a function of adding the second analog potential or a potential corresponding to the second analog potential to the held first reference potential VPR and holding a second reference potential obtained by this addition. The memory cell MCR also has a function of generating a second reference current corresponding to the second reference potential. In other words, the memory cell MCR has a function of holding a second reference current corresponding to the second reference potential.

[0137] Specifically, in the semiconductor device 200 shown in Figure 13 , a second analog potential Vw[p, q] is input to the memory cell MCR[p] through the wiring RW[p]. The memory cell MCR[p] has a function of holding a second reference potential corresponding to the first reference potential VPR and the second analog potential Vw[p, q]. In addition, the memory cell MCR[p] has a function of generating a second reference current corresponding to the second reference potential. In other words, the current IREF[p] of the memory cell MCR[p] at this time corresponds to the second reference current.

[0138] In addition, in the semiconductor device 200 shown in Figure 13 , a second analog potential Vw[p + 1, q] is input to the memory cell MCR[p + 1] through the wiring RW[p + 1]. The memory cell MCR[p + 1] has a function of holding the first reference potential VPR and a second reference potential corresponding to the second analog potential Vw[p + 1, q]. In addition, the memory cell MCR[p + 1] has a function of generating a second reference current corresponding to the second reference potential. In other words, the current IREF[p + 1] of the memory cell MCR[p + 1] at this time corresponds to the second reference current.

[0139] The current IREF[p] flows between the wiring BLREF and the wiring VRREF through the memory cell MCR[p]. The current IREF[p + 1] flows between the wiring BLREF and the wiring VRREF through the memory cell MCR[p + 1]. Therefore, a current IREF equivalent to the sum of the current IREF[p] and the current IREF[p + 1] flows between the wiring BLREF and the wiring VRREF through the memory cell MCR[p] and the memory cell MCR[p + 1].

[0140] The current source circuit 250 has a function of supplying a current having the same value as the current IREF flowing through the wiring BLREF or a current corresponding to the current IREF to the wiring BL. When the current I[q] flowing between the wiring BL[q] and the wiring VR[q] through the memory cells MC[p, q] and MC[p + 1, q] is different from the current IREF flowing between the wiring BLREF and the wiring VRREF through the memory cells MCR[p] and MCR[p + 1] and an offset current is set as described later, a differential current flows through the circuit 230 or the circuit 240. The circuit 230 has a function of a current source circuit, and the circuit 240 has a function of a current sink circuit.

[0141] Specifically, circuit 230 has a function of generating a current ΔI[q] equivalent to the difference between current I[q] and current IREF when current I[q] is greater than current IREF. In addition, circuit 230 has a function of supplying the generated current ΔI[q] to wiring BL[q]. In other words, circuit 230 has a function of holding current ΔI[q].

[0142] Circuit 240 has a function of generating a current ΔI[q] equivalent to the difference between current I[q] and current IREF when current I[q] is less than current IREF. In addition, circuit 240 has a function of sinking the generated current ΔI[q] from wiring BL[q]. In other words, circuit 240 has a function of holding current ΔI[q].

[0143] Next, Figure 13 a working example of the semiconductor device 200 shown will be described.

[0144] First, a potential corresponding to the first analog potential is stored in the memory cell MC[p, q]. Specifically, the potential VPR - Vx[p, q] obtained by subtracting the first analog potential Vx[p, q] from the first reference potential VPR is input to the memory cell MC[p, q] through the wiring WD[q]. The memory cell MC[p, q] holds the potential VPR - Vx[p, q]. In addition, the memory cell MC[p, q] generates a current I[p, q] corresponding to the potential VPR - Vx[p, q]. For example, the first reference potential VPR is set to a potential higher than the ground potential. Specifically, the first reference potential VPR is preferably higher than the ground potential and equal to or lower than the high-level potential VDD supplied to the current source circuit 250.

[0145] In addition, the first reference potential VPR is stored in the memory cell MCR[p]. Specifically, the first reference potential VPR is input to the memory cell MCR[p] through the wiring WDREF. The memory cell MCR[p] holds the first reference potential VPR. In addition, the memory cell MCR[p] generates a current IREF[p] corresponding to the first reference potential VPR.

[0146] In addition, a potential corresponding to the first analog potential is stored in the memory cell MC[p + 1, q]. Specifically, the potential VPR - Vx[p + 1, q] obtained by subtracting the first analog potential Vx[p + 1, q] from the first reference potential VPR is input to the memory cell MC[p + 1, q] through the wiring WD[q]. The memory cell MC[p + 1, q] holds the potential VPR - Vx[p + 1, q]. In addition, the memory cell MC[p + 1, q] generates a current I[p + 1, q] corresponding to the potential VPR - Vx[p + 1, q].

[0147] In addition, a first reference potential VPR is stored in the storage cell MCR[p+1]. Specifically, the first reference potential VPR is input to the storage cell MCR[p+1] through the wiring WDREF. The storage cell MCR[p+1] holds the first reference potential VPR. In addition, the storage cell MCR[p+1] generates a current IREF[p+1] corresponding to the first reference potential VPR.

[0148] In the above operation, the wirings RW[p] and RW[p+1] are each set to a reference potential. For example, a ground potential or a low-level potential VSS lower than the ground potential can be used as the reference potential. Alternatively, a potential between the potential VSS and the potential VDD can be used as the ground potential. Regardless of whether the second analog potential Vw is positive or negative, the potential of the wiring RW can be made higher than the ground potential, so it is easy to generate a signal, and multiplication can be performed on positive or negative analog data, so it is preferable.

[0149] Through the above operation, the total current of the currents generated in the respective storage cells MC connected to the wiring BL[q] flows through the wiring BL[q]. Specifically, in Figure 13 , the total current I[q] of the current I[p, q] generated in the storage cell MC[p, q] and the current I[p+1, q] generated in the storage cell MC[p+1, q] flows through the wiring BL[q]. In addition, through the above operation, the total current of the currents generated in the respective storage cells MCR connected to the wiring BLREF flows through the wiring BLREF. Specifically, in Figure 13 , the total current IREF of the current IREF[p] generated in the storage cell MCR[p] and the current IREF[p+1] generated in the storage cell MCR[p+1] flows through the wiring BLREF.

[0150] Next, in a state where the potentials of the wirings RW[p] and RW[p+1] are held at the reference potential, the differential offset current Ioffset[q] between the current I[q] obtained by inputting the first analog potential and the current IREF obtained by inputting the first reference potential is held in the circuit 230 or the circuit 240.

[0151] Specifically, when the current I[q] is greater than the current IREF, the circuit 230 supplies the current Ioffset[q] to the wiring BL[q]. In other words, the current ICM[q] flowing through the circuit 230 is equivalent to the current Ioffset[q]. This current ICM[q] is held in the circuit 230. When the current I[q] is less than the current IREF, the circuit 240 sinks the current Ioffset[q] from the wiring BL[q]. In other words, the current ICP[q] flowing through the circuit 240 is equivalent to the current Ioffset[q]. This current ICP[q] is held in the circuit 240.

[0152] Next, the second analog potential or the potential corresponding to the second analog potential is stored in the memory cell MC[p, q] by adding the second analog potential or the potential corresponding to the second analog potential to the first analog potential or the potential corresponding to the first analog potential already held in the memory cell MC[p, q]. Specifically, the second analog potential Vw[p] is input to the memory cell MC[p, q] through the wiring RW[p] by setting the potential of the wiring RW[p] to a potential obtained by adding Vw[p] to the reference potential. The memory cell MC[p, q] holds the potential VPR - Vx[p, q] + Vw[p]. In addition, the memory cell MC[p, q] generates a current I[p, q] corresponding to the potential VPR - Vx[p, q] + Vw[p].

[0153] In addition, the second analog potential or the potential corresponding to the second analog potential is stored in the memory cell MC[p + 1, q] by adding the second analog potential or the potential corresponding to the second analog potential to the first analog potential or the potential corresponding to the first analog potential already held in the memory cell MC[p + 1, q]. Specifically, the second analog potential Vw[p + 1] is input to the memory cell MC[p + 1, q] through the wiring RW[p + 1] by setting the potential of the wiring RW[p + 1] to a potential obtained by adding Vw[p + 1] to the reference potential. The memory cell MC[p + 1, q] holds the potential VPR - Vx[p + 1, q] + Vw[p + 1]. In addition, the memory cell MC[p + 1, q] generates a current I[p + 1, q] corresponding to the potential VPR - Vx[p + 1, q] + Vw[p + 1].

[0154] In the case of using a transistor Tr11 operating in the saturation region as an element for converting a potential into a current, since the drain current of the transistor Tr11 in the memory cell MC[p, q] is equivalent to the current I[p, q], the second analog current is represented by the following equation 1. Note that Vw[p] is the potential of the wiring RW[p], Vw[p + 1] is the potential of the wiring RW[p + 1], k is a coefficient, and Vth is the threshold voltage of the transistor Tr11.

[0155] I[p, q] = k(Vw[p] - Vth + VPR - Vx[p, q]) 2 (Equation 1)

[0156] In addition, the drain current of the transistor Tr11 in the storage cell MCR[p] is equivalent to the current IREF[p]. Therefore, the second reference current is represented by the following Equation 2.

[0157] IREF[p] = k(Vw[p] - Vth + VPR) 2 (Equation 2)

[0158] The current I[q] equivalent to the sum of the current I[p, q] flowing through the storage cell MC[p, q] and the current I[p+1, q] flowing through the storage cell MC[p+1, q] can be expressed as ΣiI[p, q]. The current IREF equivalent to the sum of the current IREF[p] flowing through the storage cell MCR[p] and the current IREF[p+1] flowing through the storage cell MCR[p+1] can be expressed as ΣiIREF[p]. Therefore, the current ΔI[q] equivalent to the difference between the current I[q] and the current IREF is represented by the following Equation 3.

[0159] ΔI[q] = IREF - I[q] = ΣiIREF[p] - ΣiI[p, q] (Equation 3)

[0160] Based on Equations 1 to 3, the current ΔI[q] can be obtained through the following Equation 4.

[0161] ΔI[q] = Σi{k(Vw[p] - Vth + VPR) 2 -k(Vw[p] - Vth + VPR - Vx[p, q]) 2} = 2kΣi(Vw[p]·Vx[p, q]) - 2kΣi(Vth - VPR)·Vx[p, q] - kΣiVx[p, q] 2 (Equation 4)

[0162] In Equation 4, the term represented by 2kΣi(Vw[p]·Vx[p, q]) is equivalent to the sum of the product of the first analog potential Vx[p, q] and the second analog potential Vw[p] and the product of the first analog potential Vx[p+1, q] and the second analog potential Vw[p+1].

[0163] In addition, if the current Ioffset[q] is defined as the current ΔI[q] when the potentials of the wirings RW[p] are all reference potentials (i.e., the second analog potential Vw[p] and the second analog potential Vw[p+1] are both 0), then the following Equation 5 can be obtained based on Equation 4.

[0164] Ioffset[q] = -2kΣi(Vth - VPR)·Vx[p, q] - kΣiVx[p, q] 2 (Equation 5)

[0165] Therefore, according to Equations 3 to 5, 2kΣi(Vw[p]·Vx[p, q]), which is equivalent to the sum of the products of the first analog data and the second analog data, is represented by the following Equation 6.

[0166] 2kΣi(Vw[p]·Vx[p, q]) = IREF - I[q] - Ioffset[q] (Equation 6)

[0167] When the current I[q] is the sum of the currents flowing through the memory cells MC, the current IREF is the sum of the currents flowing through the memory cells MCR, and the current Ioffset[q] is the current flowing through the circuit 230 or the circuit 240, the current Iout[q] flowing out from the wiring BL[q] when the potential of the wiring RW[p] is Vw[p] and the potential of the wiring RW[p + 1] is Vw[p + 1] is represented by IREF - I[q] - Ioffset[q]. According to Equation 6, the current Iout[q] is 2kΣi(Vw[p]·Vx[p, q]), which is equivalent to the sum of the product of the first analog potential Vx[p, q] and the second analog potential Vw[p] and the product of the first analog potential Vx[p + 1, q] and the second analog potential Vw[p + 1].

[0168] The transistor Tr11 preferably operates in the saturation region. However, even if the operating region of the transistor Tr11 is different from the ideal saturation region, as long as the current equivalent to the sum of the product of the first analog potential Vx[p, q] and the second analog potential Vw[p] and the product of the first analog potential Vx[p + 1, q] and the second analog potential Vw[p + 1] can be obtained with the desired accuracy, the transistor Tr11 can be regarded as operating in the saturation region.

[0169] Through an embodiment of the present invention, arithmetic processing can be performed without converting analog data into digital data. Therefore, the circuit scale of the semiconductor device can be reduced, or the time required for arithmetic processing of analog data can be shortened. In addition, through an embodiment of the present invention, it is possible to simultaneously achieve shortening of the time required for arithmetic processing of analog data and low power consumption of the semiconductor device.

[0170] <Structural Example of the Memory Circuit> Next, with reference to Figure 14 specific structural examples of the memory circuit 210 (MEM) and the reference memory circuit 220 (RMEM) will be described.

[0171] Figure 14It is shown that the storage circuit 210 (MEM) includes a plurality of memory cells MC arranged in y rows and x columns (x and y are natural numbers), and an example is given in which the reference storage circuit 220 (RMEM) includes a plurality of memory cells MCR arranged in y rows and 1 column.

[0172] Note that in this specification and the like, the source of a transistor refers to a source region that is a part of a semiconductor layer serving as a channel formation region, or a source electrode or the like connected to the semiconductor layer. Similarly, the drain of a transistor refers to a drain region that is a part of the semiconductor layer, or a drain electrode or the like connected to the semiconductor layer. The gate of a transistor refers to a gate electrode or the like.

[0173] The names of the "source" and "drain" of a transistor are interchanged according to the conductivity type of the transistor or the level of the potential applied to each terminal. Generally, in an n-channel transistor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. In a p-channel transistor, the terminal to which a low potential is applied is called the drain, and the terminal to which a high potential is applied is called the source. In this specification, although for convenience, in some cases, it is assumed that the source and drain are fixed to describe the connection relationship of the transistor, in fact, the names of the source and drain are interchanged according to the above potential relationship.

[0174] The storage circuit 210 is connected to the wiring RW, the wiring WW, the wiring WD, the wiring VR, and the wiring BL. In Figure 14 the example shown, the wiring RW[1] to the wiring RW[y] and the wiring WW[1] to the wiring WW[y] are respectively connected to the memory cells MC in each row. In addition, the wiring WD[1] to the wiring WD[x], the wiring BL[1] to the wiring BL[x], and the wiring VR[1] to the wiring VR[x] are respectively connected to the memory cells MC in each column. Note that the wiring VR[1] to the wiring VR[x] can be connected to each other.

[0175] The reference storage circuit 220 is connected to the wiring RW, the wiring WW, the wiring WDREF, the wiring VRREF, and the wiring BLREF. In Figure 14 the example shown, the wiring RW[1] to the wiring RW[y] and the wiring WW[1] to the wiring WW[y] are respectively connected to the memory cells MCR in each row. In addition, the wiring WDREF, the wiring BLREF, and the wiring VRREF are connected to the memory cells MCR in one column. Note that the wiring VRREF can also be connected to the wiring VR[1] to the wiring VR[x].

[0176] As an example, Figure 15 it is shown Figure 14 any two rows and two columns of the memory cells MC shown, and Figure 14The specific circuit structure and connection relationship of any two rows and one column of memory cells MCR shown.

[0177] Specifically, in Figure 15 it shows the memory cell MC[p, q] in the p-th row and q-th column, the memory cell MC[p + 1, q] in the (p + 1)-th row and q-th column, the memory cell MC[p, q + 1] in the p-th row and (q + 1)-th column, and the memory cell MC[p + 1, q + 1] in the (p + 1)-th row and (q + 1)-th column. Additionally, Figure 15 it shows the memory cell row MCR[p] in the p-th row and the memory cell row MCR[p + 1] in the (p + 1)-th row. Note that p and p + 1 are each any number from 1 to y, and q and q + 1 are each any number from 1 to x.

[0178] The memory cells MC[p, q], MC[p, q + 1], and MCR[p] in the p-th row are connected to the wiring RW[p] and the wiring WW[p]. The memory cells MC[p + 1, q], MC[p + 1, q + 1], and MCR[p + 1] in the (p + 1)-th row are connected to the wiring RW[p + 1] and the wiring WW[p + 1].

[0179] The memory cells MC[p, q] and MC[p + 1, q] in the q-th column are connected to the wiring WD[q], the wiring VR[q], and the wiring BL[q]. The memory cells MC[p, q + 1] and MC[p + 1, q + 1] in the (q + 1)-th column are connected to the wiring WD[q + 1], the wiring VR[q + 1], and the wiring BL[q + 1]. The memory cell rows MCR[p] in the p-th row and MCR[p + 1] in the (p + 1)-th row are connected to the wiring WDREF, the wiring VRREF, and the wiring BLREF.

[0180] Each of the memory cell MC and the memory cell row MCR includes a transistor Tr11, a transistor Tr12, and a capacitor C11. The transistor Tr12 has the function of controlling the input of a first analog potential to the memory cell MC or the memory cell row MCR. The transistor Tr11 has the function of generating an analog current according to the potential input to the gate. The capacitor C11 has the function of adding a second analog potential or a potential corresponding to the second analog potential to the first analog potential or the potential corresponding to the first analog potential held in the memory cell MC or the memory cell row MCR.

[0181] Specifically, in Figure 15In the memory cell MC shown, the gate of transistor Tr12 is connected to wiring WW, one of the source and drain of transistor Tr12 is connected to wiring WD, and the other of the source and drain of transistor Tr12 is connected to the gate of transistor Tr11. In addition, one of the source and drain of transistor Tr11 is connected to wiring VR, and the other of the source and drain of transistor Tr11 is connected to wiring BL. The first electrode of capacitor C11 is connected to wiring RW, and the second electrode of capacitor C11 is connected to the gate of transistor Tr11.

[0182] In addition, in Figure 15 In the memory cell MCR shown, the gate of transistor Tr12 is connected to wiring WW, one of the source and drain of transistor Tr12 is connected to wiring WDREF, and the other of the source and drain of transistor Tr12 is connected to the gate of transistor Tr11. In addition, one of the source and drain of transistor Tr11 is connected to wiring VRREF, and the other of the source and drain of transistor Tr11 is connected to wiring BLREF. The first electrode of capacitor C11 is connected to wiring RW, and the second electrode of capacitor C11 is connected to the gate of transistor Tr11.

[0183] In the memory cell MC, the gate of transistor Tr11 is referred to as node N. In the memory cell MC, a first analog potential is input to node N through transistor Tr12. Next, when transistor Tr12 is in the off state, node N is in a floating state, and node N holds the first analog potential or a potential corresponding to the first analog potential. In the memory cell MC, when node N is in the floating state, a second analog potential input to the first electrode of capacitor C11 is supplied to node N. Through the above operations, node N can have a potential obtained by adding the second analog potential or a potential corresponding to the second analog potential to the first analog potential or a potential corresponding to the first analog potential.

[0184] The potential of the first electrode of capacitor C11 is supplied to node N through capacitor C11. Therefore, in practice, the change amount of the potential of the first electrode is not exactly the same as the change amount of the potential of node N. Specifically, the change amount of the potential of node N can be correctly calculated by multiplying the change amount of the potential of the first electrode by a coupling coefficient determined to be a unique value according to the capacitance value of capacitor C11, the capacitance value of the gate capacitance of transistor Tr11, and the capacitance value of the parasitic capacitance. Hereinafter, for ease of understanding, a case where the change amount of the potential of the first electrode is approximately the same as the change amount of the potential of node N will be described.

[0185] The drain current of transistor Tr11 depends on the potential of node N. Therefore, when transistor Tr12 is in the off state, the potential of node N is held, and the value of the drain current of transistor Tr11 is also held. The first analog potential and the second analog potential are reflected in the above drain current.

[0186] In memory cell MCR, the gate of transistor Tr11 is referred to as node NREF. In memory cell MCR, the first reference potential or a potential corresponding to the first reference potential is input to node NREF through transistor Tr12. Then, when transistor Tr12 is in the off state, node NREF is in a floating state, and node NREF holds the first reference potential or a potential corresponding to the first reference potential. In memory cell MCR, when node NREF is in a floating state, the second analog potential input to the first electrode of capacitor C11 is supplied to node NREF. Through the above operations, node NREF can have a potential obtained by adding the second analog potential or a potential corresponding to the second analog potential to the first reference potential or a potential corresponding to the first reference potential.

[0187] The drain current of transistor Tr11 depends on the potential of node NREF. Therefore, when transistor Tr12 is in the off state, the potential of node NREF is held, and the value of the drain current of transistor Tr11 is also held. The first reference potential and the second analog potential are reflected in the above drain current.

[0188] When the drain current of transistor Tr11 flowing through memory cell MC[p, q] is referred to as current I[p, q], and the drain current of transistor Tr11 flowing through memory cell MC[p + 1, q] is referred to as current I[p + 1, q], the sum of the currents supplied to memory cell MC[p, q] and memory cell MC[p + 1, q] through wiring BL[q] is current I[q]. When the drain current of transistor Tr11 flowing through memory cell MC[p, q + 1] is referred to as current I[p, q + 1], and the drain current of transistor Tr11 flowing through memory cell MC[p + 1, q + 1] is referred to as current I[p + 1, q + 1], the sum of the currents supplied to memory cell MC[p, q + 1] and memory cell MC[p + 1, q + 1] through wiring BL[q + 1] is current I[q + 1]. When the drain current of transistor Tr11 flowing through memory cell MCR[p] is referred to as current IREF[p], and the drain current of transistor Tr11 flowing through memory cell MCR[p + 1] is referred to as current IREF[p + 1], the sum of the currents supplied to memory cell MCR[p] and memory cell MCR[p + 1] through wiring BLREF is current IREF.

[0189] <Structural examples of circuit 230, circuit 240, and current source circuit> Next, with reference to Figure 16 a specific structural example of the circuit 230, the circuit 240, and the current source circuit 250 (CREF) will be described.

[0190] Figure 16 There is shown Figure 15 a structural example of the circuit 230, the circuit 240, and the current source circuit 250 corresponding to the memory cell MC and the memory cell MCR shown. Specifically, in Figure 16 , the circuit 230[q] corresponding to the memory cell MC in the q-th column and the circuit 230[q + 1] corresponding to the memory cell MC in the (q + 1)-th column are shown as the circuit 230. In Figure 16 , the circuit 240[q] corresponding to the memory cell MC in the q-th column and the circuit 240[q + 1] corresponding to the memory cell MC in the (q + 1)-th column are shown as the circuit 240.

[0191] The circuit 230[q] and the circuit 240[q] are connected to the wiring BL[q]. The circuit 230[q + 1] and the circuit 240[q + 1] are connected to the wiring BL[q + 1].

[0192] The current source circuit 250 is connected to the wiring BL[q], the wiring BL[q + 1], and the wiring BLREF. The current source circuit 250 has a function of supplying the current IREF to the wiring BLREF and a function of supplying the same current as the current IREF or a current corresponding to the current IREF to each of the wiring BL[q] and the wiring BL[q + 1].

[0193] Specifically, each of the circuit 230[q] and the circuit 230[q + 1] includes a transistor Tr24, a transistor Tr25, a transistor Tr26, and a capacitor C22. The transistor Tr24 of the circuit 230[q] has a function of generating a current ICM[q] equivalent to the difference between the current I[q] and the current IREF when the current I[q] is greater than the current IREF and a set offset current. In addition, the transistor Tr24 of the circuit 230[q + 1] has a function of generating a current ICM[q + 1] equivalent to the difference between the current I[q + 1] and the current IREF when the current I[q + 1] is greater than the current IREF. The current ICM[q] and the current ICM[q + 1] are respectively supplied from the circuit 230[q] and the circuit 230[q + 1] to the wiring BL[q] and the wiring BL[q + 1].

[0194] In each of circuit 230[q] and circuit 230[q + 1], one of the source and drain of transistor Tr24 is connected to the corresponding wiring BL, and the other of the source and drain is connected to the wiring supplied with a specified potential. One of the source and drain of transistor Tr25 is connected to the corresponding wiring BL, and the other of the source and drain is connected to the gate of transistor Tr24. One of the source and drain of transistor Tr26 is connected to the gate of transistor Tr24, and the other of the source and drain is connected to the wiring supplied with a specified potential. The first electrode of capacitor C22 is connected to the gate of transistor Tr24, and the second electrode of capacitor C22 is connected to the wiring supplied with a specified potential.

[0195] The gate of transistor Tr25 is connected to wiring OSM, and the gate of transistor Tr26 is connected to wiring ORM.

[0196] Note that Figure 16 An example is shown in which transistor Tr24 is a p-channel transistor and transistors Tr25 and Tr26 are n-channel transistors.

[0197] Each of circuit 240[q] and circuit 240[q + 1] includes transistor Tr21, transistor Tr22, transistor Tr23, and capacitor C21. Transistor Tr21 of circuit 240[q] has a function of generating a current ICP[q] equivalent to the difference between current I[q] and current IREF when current I[q] is less than current IREF and a set offset current. In addition, transistor Tr21 of circuit 240[q + 1] has a function of generating a current ICP[q + 1] equivalent to the difference between current I[q + 1] and current IREF when current I[q + 1] is less than current IREF. Currents ICP[q] and ICP[q + 1] are respectively drawn into circuit 240[q] and circuit 240[q + 1] from wiring BL[q] and wiring BL[q + 1].

[0198] Note that current ICM[q] and current ICP[q] each correspond to current Ioffset[q], and current ICM[q + 1] and current ICP[q + 1] each correspond to current Ioffset[q + 1].

[0199] In each of circuit 240[q] and circuit 240[q + 1], one of the source and drain of transistor Tr21 is connected to the corresponding wiring BL, and the other of the source and drain is connected to the wiring supplied with a specified potential. One of the source and drain of transistor Tr22 is connected to the corresponding wiring BL, and the other of the source and drain is connected to the gate of transistor Tr21. One of the source and drain of transistor Tr23 is connected to the gate of transistor Tr21, and the other of the source and drain is connected to the wiring supplied with a specified potential. The first electrode of capacitor C21 is connected to the gate of transistor Tr21, and the second electrode of capacitor C21 is connected to the wiring supplied with a specified potential.

[0200] The gate of transistor Tr22 is connected to wiring OSP, and the gate of transistor Tr23 is connected to wiring ORP.

[0201] Note that Figure 16 An example is shown in which transistors Tr21 to Tr23 are n-channel transistors.

[0202] Current source circuit 250 includes transistor Tr27 corresponding to wiring BL and transistor Tr28 corresponding to wiring BLREF. Specifically, Figure 16 An example is shown in which current source circuit 250 uses transistor Tr27[q] corresponding to wiring BL[q] and transistor Tr27[q + 1] corresponding to wiring BL[q + 1] as transistor Tr27.

[0203] The gate of transistor Tr27 is connected to the gate of transistor Tr28. One of the source and drain of transistor Tr27 is connected to the corresponding wiring BL, and the other of the source and drain is connected to the wiring supplied with a specified potential. One of the source and drain of transistor Tr28 is connected to wiring BLREF, and the other of the source and drain is connected to the wiring supplied with a specified potential.

[0204] Transistors Tr27 and Tr28 have the same polarity. Figure 16 An example is shown in which transistors Tr27 and Tr28 are p-channel transistors.

[0205] The drain current of transistor Tr28 corresponds to current IREF. Since transistors Tr27 and Tr28 function as a current mirror circuit, the drain current of transistor Tr27 has a value substantially the same as or corresponding to the drain current of transistor Tr28.

[0206] <Operating example of semiconductor device> Next, with reference to Figure 15 , Figure 16 and Figure 17A specific working example of the semiconductor device 200 according to an embodiment of the present invention will be described.

[0207] Figure 17 is Figure 15 an example of the operation timing diagrams of the memory cell MC and the memory cell MCR, Figure 16 the circuits 230, 240, and the current source circuit 250 shown in. At Figure 17 At times T01 to T04, the first analog data is stored in the memory cell MC and the memory cell MCR. At times T05 to T10, the offset current Ioffset flowing through the circuits 230 and 240 is set. At times T11 to T16, data corresponding to the product sum value of the first analog data and the second analog data is obtained.

[0208] Note that a low-level potential VSS is supplied to the wirings VR[q] and VR[q + 1]. A high-level potential VDD is supplied to all the wirings having a specified potential connected to the circuit 230. A low-level potential VSS is supplied to all the wirings having a specified potential connected to the circuit 240. In addition, a high-level potential VDD is supplied to all the wirings having a specified potential connected to the current source circuit 250.

[0209] The transistors Tr11, Tr21, Tr24, Tr27[q], Tr27[q + 1], and Tr28 each operate in the saturation region.

[0210] First, at times T01 to T02, a high-level potential is supplied to the wiring WW[p], and a low-level potential is supplied to the wiring WW[p + 1]. By the above operation, Figure 15 the transistor Tr12 in the memory cell MC[p, q], the memory cell MC[p, q + 1], and the memory cell MCR[p] shown in becomes conductive. The transistor Tr12 in the memory cell MC[p + 1, q], the memory cell MC[p + 1, q + 1], and the memory cell MCR[p + 1] remains off.

[0211] In addition, at times T01 to T02, to Figure 15 each of the wirings WD[q] and WD[q + 1] shown, a potential obtained by subtracting the first analog potential from the first reference potential VPR is supplied. Specifically, the potential VPR - Vx[p, q] is supplied to the wiring WD[q], and the potential VPR - Vx[p, q + 1] is supplied to the wiring WD[q + 1]. The first reference potential VPR is supplied to the wiring WDREF, and a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2, is supplied as the reference potential to the wirings RW[p] and RW[p + 1].

[0212] Therefore, the potential VPR-Vx[p, q] is supplied to Figure 15 the node N[p, q] of the memory cell MC[p, q] shown, the potential VPR-Vx[p, q+1] is supplied to the node N[p, q+1] of the memory cell MC[p, q+1] through the transistor Tr12, and the first reference potential VPR is supplied to the node NREF[p] of the memory cell MCR[p] through the transistor Tr12.

[0213] After time T02, the potential supplied to Figure 15 the wiring WW[p] shown changes from a high-level potential to a low-level potential, whereby the transistor Tr12 in the memory cell MC[p, q], the memory cell MC[p, q+1], and the memory cell MCR[p] becomes in an off state. Through the above operation, the node N[p, q] holds the potential VPR-Vx[p, q], the node N[p, q+1] holds the potential VPR-Vx[p, q+1], and the node NREF[p] holds the first reference potential VPR.

[0214] Next, at time T03 to time T04, Figure 15 the potential of the wiring WW[p] shown is maintained at a low level, and a high-level potential is supplied to the wiring WW[p+1]. Through the above operation, Figure 15 the transistor Tr12 in the memory cell MC[p+1, q], the memory cell MC[p+1, q+1], and the memory cell MCR[p+1] shown becomes in an on state. The transistor Tr12 in the memory cell MC[p, q], the memory cell MC[p, q+1], and the memory cell MCR[p] remains in an off state.

[0215] In addition, at time T03 to time T04, a potential obtained by subtracting the first analog potential from the first reference potential VPR is supplied to Figure 15 the wiring WD[q] and the wiring WD[q+1] shown. Specifically, the potential VPR-Vx[p+1, q] is supplied to the wiring WD[q], and the potential VPR-Vx[p+1, q+1] is supplied to the wiring WD[q+1]. The first reference potential VPR is supplied to the wiring WDREF, and a potential between the potential VSS and the potential VDD, for example, the potential (VDD+VSS) / 2, is supplied as a reference potential to the wiring RW[p] and the wiring RW[p+1].

[0216] Therefore, the potential VPR-Vx[p+1, q] is supplied to Figure 15The node N[p+1, q] of the memory cell MC[p+1, q] shown, the potential VPR-Vx[p+1, q+1] is supplied to the node N[p+1, q+1] of the memory cell MC[p+1, q+1] through the transistor Tr12, and the first reference potential VPR is supplied to the node NREF[p+1] of the memory cell MCR[p+1] through the transistor Tr12.

[0217] After time T04, the potential supplied to Figure 15 the wiring WW[p+1] shown changes from a high-level potential to a low-level potential, whereby the transistor Tr12 becomes in an off state in the memory cell MC[p+1, q], the memory cell MC[p+1, q+1], and the memory cell MCR[p+1]. Through the above operation, the node N[p+1, q] holds the potential VPR-Vx[p+1, q], the node N[p+1, q+1] holds the potential VPR-Vx[p+1, q+1], and the node NREF[p+1] holds the first reference potential VPR.

[0218] Next, at time T05 to time T06, a high-level potential is supplied to Figure 16 the wiring ORP and the wiring ORM shown. In Figure 16 the circuits 230[q] and 230[q+1] shown, when the wiring ORM is supplied with a high-level potential, the transistor Tr26 becomes in an on state, whereby the gate of the transistor Tr24 is supplied with the potential VDD and is reset. In addition, in Figure 16 the circuits 240[q] and 240[q+1] shown, when the wiring ORP is supplied with a high-level potential, the transistor Tr23 becomes in an on state, whereby the gate of the transistor Tr21 is supplied with the potential VSS and is reset.

[0219] After time T06, the potentials supplied to Figure 15 the wiring ORP and the wiring ORM shown change from a high-level potential to a low-level potential, whereby the transistor Tr26 in the circuits 230[q] and 230[q+1], and the transistor Tr23 in the circuits 240[q] and 240[q+1] become in an off state. Through the above operation, the gate of the transistor Tr24 in each of the circuits 230[q] and 230[q+1] holds the potential VDD, and the gate of the transistor Tr21 in each of the circuits 240[q] and 240[q+1] holds the potential VSS.

[0220] At time T07 to time T08, a high-level potential is supplied to Figure 16 the wiring OSP shown. In addition, to Figure 15The shown wirings RW[p] and RW[p + 1] serve as a potential between the reference potential supply potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2. Since a high-level potential is supplied to the wiring OSP, the transistors Tr22 of the circuits 240[q] and 240[q + 1] become in an on state.

[0221] When the current I[q] flowing through the wiring BL[q] is less than the current IREF flowing through the wiring BLREF, that is, when the current ΔI[q] is positive, this means Figure 15 The sum of the current that the transistor Tr28 of the shown memory cell MC[p, q] can sink and the current that the transistor Tr28 of the memory cell MC[p + 1, q] can sink is less than the value of the drain current of the transistor Tr27[q]. Therefore, when the current ΔI[q] is positive and the transistor Tr22 of the circuit 240[q] is in an on state, a part of the drain current of the transistor Tr27[q] flows into the gate of the transistor Tr21, causing the gate potential of the transistor Tr21 to start rising. When the drain current of the transistor Tr21 rises to a value approximately equal to the current ΔI[q], the gate potential of the transistor Tr21 converges to a specified value. The gate potential of the transistor Tr21 at this time corresponds to the potential when the drain current of the transistor Tr21 is the current ΔI[q] (i.e., the current Ioffset[q] (= ICP[q])). In other words, the transistor Tr21 of the circuit 240[q] is set to a state of a current source capable of flowing the current ICP[q].

[0222] Similarly, when the current I[q + 1] flowing through the wiring BL[q + 1] is less than the current IREF flowing through the wiring BLREF, that is, when the current ΔI[q + 1] is positive, when the transistor Tr22 of the circuit 240[q + 1] is in an on state, a part of the drain current of the transistor Tr27[q + 1] flows into the gate of the transistor Tr21, causing the gate potential of the transistor Tr21 to start rising. When the drain current of the transistor Tr21 rises to a value approximately equal to the current ΔI[q + 1], the gate potential of the transistor Tr21 converges to a specified value. The gate potential of the transistor Tr21 at this time corresponds to the potential when the drain current of the transistor Tr21 is the current ΔI[q + 1] (i.e., the current Ioffset[q + 1] (= ICP[q + 1])). In other words, the transistor Tr21 of the circuit 240[q + 1] is set to a state of a current source capable of flowing the current ICP[q + 1].

[0223] After the time T08, supplied to Figure 16The potential of the wiring OSP shown changes from a high-level potential to a low-level potential, whereby the transistors Tr22 of circuits 240[q] and 240[q + 1] become in an off state. Through the above operation, the gate potential of the transistor Tr21 is maintained. Therefore, circuit 240[q] maintains the state of a current source set to be able to flow current ICP[q], and circuit 240[q + 1] maintains the state of a current source set to be able to flow current ICP[q + 1].

[0224] At time T09 to time T10, to Figure 16 the wiring OSM shown is supplied with a high-level potential. Additionally, for each of Figure 15 the wiring RW[p] and the wiring RW[p + 1] shown, a potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2, is supplied as a reference potential. Since the wiring OSM is supplied with a high-level potential, the transistors Tr25 of circuits 230[q] and 230[q + 1] become in an on state.

[0225] When the current I[q] flowing through the wiring BL[q] is greater than the current IREF flowing through the wiring BLREF, that is, when the current ΔI[q] is negative, this means that Figure 15 the sum of the currents that the transistor Tr28 of the memory cell MC[p, q] shown can sink and the current that the transistor Tr28 of the memory cell MC[p + 1, q] shown can sink is greater than the value of the drain current of the transistor Tr27[q]. Therefore, when the current ΔI[q] is negative, when the transistor Tr25 of circuit 230[q] becomes in an on state, current flows out from the gate of the transistor Tr24 to the wiring BL[q], causing the gate potential of the transistor Tr24 to start to decrease. When the drain current of the transistor Tr24 drops to approximately equal to the value of the current ΔI[q], the gate potential of the transistor Tr24 converges to a specified value. The gate potential of the transistor Tr24 at this time corresponds to the potential when the drain current of the transistor Tr24 is the current ΔI[q] (i.e., the current Ioffset[q](= ICM[q])). In other words, the transistor Tr24 of circuit 230[q] is set to the state of a current source capable of flowing current ICM[q].

[0226] Similarly, when the current I[q+1] flowing through the wiring BL[q+1] is greater than the current IREF flowing through the wiring BLREF, that is, when the current ΔI[q+1] is negative, when the transistor Tr25 in the circuit 230[q+1] becomes conductive, the current flows out from the gate of the transistor Tr24 to the wiring BL[q+1], causing the gate potential of the transistor Tr24 to start to decrease. When the drain current of the transistor Tr24 drops to approximately equal to the absolute value of the current ΔI[q+1], the gate potential of the transistor Tr24 converges to a specified value. The gate potential of the transistor Tr24 at this time corresponds to the potential when the drain current value of the transistor Tr24 is the same as the absolute value of the current ΔI[q+1] (i.e., the current Ioffset[q+1] (= ICM[q+1])). In other words, the transistor Tr24 in the circuit 230[q+1] is set to a state of a current source capable of flowing the current ICM[q+1].

[0227] After the time T08, the potential supplied to Figure 16 the potential of the shown wiring OSM changes from a high-level potential to a low-level potential, whereby the transistors Tr25 in the circuit 230[q] and the circuit 230[q+1] become non-conductive. Through the above operation, the gate potential of the transistor Tr24 is maintained. Therefore, the circuit 230[q] remains in a state of a current source capable of flowing the current ICM[q], and the circuit 230[q+1] remains in a state of a current source capable of flowing the current ICM[q+1].

[0228] In each of the circuits 240[q] and 240[q+1], the transistor Tr21 has a function of sinking current. Therefore, from time T07 to time T08, when the current I[q] flowing through the wiring BL[q] is greater than the current IREF flowing through the wiring BLREF, that is, when the current ΔI[q] is negative, or when the current I[q+1] flowing through the wiring BL[q+1] is greater than the current IREF flowing through the wiring BLREF, that is, when the current ΔI[q+1] is negative, it may not be easy to supply the wiring BL[q] or the wiring BL[q+1] with the right amount of current from the circuit 240[q] or the circuit 240[q+1] without excess or deficiency. In this case, since the balance between the current flowing through the wiring BLREF and the current flowing through the wiring BL[q] or the wiring BL[q+1] is adjusted, it is possible that the transistors Tr11 of the memory cell MC, the transistors Tr21 and the transistors Tr27[q] or Tr27[q+1] of the circuit 240[q] or the circuit 240[q+1] may not be able to operate simultaneously in the saturation region.

[0229] In order to ensure that transistors Tr11, Tr21, and transistor Tr27[q] or Tr27[q + 1] operate in the saturation region even when the current ΔI[q] is negative from time T07 to time T08, the gate potential of transistor Tr24 can be set to a potential that can obtain a specified drain current from time T05 to time T06 without resetting the gate of transistor Tr24 to the potential VDD. By adopting the above structure, in addition to the drain current of transistor Tr27[q] or Tr27[q + 1], current can also be supplied from transistor Tr24. Therefore, transistor Tr21 can sink a certain amount of current that transistor Tr11 cannot sink to some extent, and thus it can be ensured that transistors Tr11, Tr21, and transistor Tr27[q] or Tr27[q + 1] operate in the saturation region.

[0230] Note that from time T09 to time T10, when the current I[q] flowing through the wiring BL[q] is less than the current IREF flowing through the wiring BLREF, that is, when the current ΔI[q] is positive, since the circuit 240[q] has been set as a current source capable of flowing the current ICP[q] from time T07 to time T08, the gate potential of the transistor Tr24 in the circuit 230[q] remains approximately the same value as the potential VDD. Similarly, when the current I[q + 1] flowing through the wiring BL[q + 1] is less than the current IREF flowing through the wiring BLREF, that is, when the current ΔI[q + 1] is positive, since the circuit 240[q + 1] has been set as a current source capable of flowing the current ICP[q + 1] from time T07 to time T08, the gate potential of the transistor Tr24 in the circuit 230[q + 1] remains approximately the same value as the potential VDD.

[0231] Next, from time T11 to time T12, a second analog potential Vw[p] is supplied to the Figure 15 shown wiring RW[p]. In addition, the potential between the potential VSS and the potential VDD, for example, the potential (VDD + VSS) / 2, is continuously supplied to the wiring RW[p + 1] as a reference potential. Specifically, the potential of the wiring RW[p] is the potential obtained by adding the potential difference Vw[p] to the potential between the potential VSS and the potential VDD (for example, the potential (VDD + VSS) / 2) as a reference potential. However, below, for the sake of easy understanding, it is assumed that the potential of the wiring RW[p] is the second analog potential Vw[p].

[0232] When the potential of the wiring RW[p] becomes the second analog potential Vw[p], it is assumed that the change amount of the potential of the first electrode of the capacitor C11 is approximately the same as the change amount of the potential of the node N. Figure 15The potential of the node N of the memory cell MC[p, q] shown becomes VPR - Vx[p, q] + Vw[p], and the potential of the node N of the memory cell MC[p, q+1] becomes VPR - Vx[p, q+1] + Vw[p]. According to Equation 6, it can be seen that the product-sum value of the first analog data and the second analog data corresponding to the memory cell MC[p, q] is reflected in the current obtained by subtracting the current Ioffset[q] from the current ΔI[q], that is, the current Iout[q] flowing out from the wiring BL[q]. In addition, it can be seen that the product-sum value of the first analog data and the second analog data corresponding to the memory cell MC[p, q+1] is reflected in the current obtained by subtracting the current Ioffset[q+1] from the current ΔI[q+1], that is, the current Iout[q+1] flowing out from the wiring BL[q+1].

[0233] After time T12, a potential between the potential VSS and the potential VDD (for example, the potential (VDD + VSS) / 2) which is used as a reference potential is supplied to the wiring RW[p] again.

[0234] Next, from time T13 to time T14, Figure 15 the second analog potential Vw[p+1] is supplied to the wiring RW[p+1] shown. In addition, the potential between the potential VSS and the potential VDD (for example, the potential (VDD + VSS) / 2) is continuously supplied to the wiring RW[p] as a reference potential. Specifically, the potential of the wiring RW[p+1] is the potential obtained by adding the potential difference Vw[p+1] to the potential between the potential VSS and the potential VDD (for example, the potential (VDD + VSS) / 2) which is used as a reference potential. However, hereinafter, for the sake of easy understanding, it is assumed that the potential of the wiring RW[p+1] is the second analog potential Vw[p+1].

[0235] When the potential of the wiring RW[p+1] becomes the second analog potential Vw[p+1], it is assumed that the change amount of the potential of the first electrode of the capacitor C11 is approximately the same as the change amount of the potential of the node N. Figure 15 The potential of the node N of the memory cell MC[p+1, q] shown becomes VPR - Vx[p+1, q] + Vw[p+1], and the potential of the node N of the memory cell MC[p+1, q+1] becomes VPR - Vx[p+1, q+1] + Vw[p+1]. According to Equation 6, it can be seen that the product-sum value of the first analog data and the second analog data corresponding to the memory cell MC[p+1, q] is reflected in the current obtained by subtracting the current Ioffset[q] from the current ΔI[q], that is, the current Iout[q]. In addition, it can be seen that the product-sum value of the first analog data and the second analog data corresponding to the memory cell MC[p+1, q+1] is reflected in the current obtained by subtracting the current Ioffset[q+1] from the current ΔI[q+1], that is, the current Iout[q+1].

[0236] After time T12, the potential between the potential VSS and the potential VDD, which is the reference potential (for example, the potential (VDD + VSS) / 2), is supplied to the wiring RW[p + 1] again.

[0237] Next, at time T15 to time T16, to Figure 15 the wiring RW[p] shown is supplied with the second analog potential Vw[p], and the wiring RW[p + 1] is supplied with the second analog potential Vw[p + 1]. Specifically, the potential of the wiring RW[p] is the potential obtained by adding the potential difference Vw[p] to the potential between the potential VSS and the potential VDD, which is the reference potential (for example, the potential (VDD + VSS) / 2), and the potential of the wiring RW[p + 1] is the potential obtained by adding the potential difference Vw[p + 1] to the potential between the potential VSS and the potential VDD, which is the reference potential (for example, the potential (VDD + VSS) / 2). However, hereinafter, for ease of understanding, it is assumed that the potential of the wiring RW[p] is the second analog potential Vw[p], and the potential of the wiring RW[p + 1] is the second analog potential Vw[p + 1].

[0238] When the potential of the wiring RW[p] becomes the second analog potential Vw[p], it is assumed that the change amount of the potential of the first electrode of the capacitor C11 is approximately the same as the change amount of the potential of the node N. Figure 15 The potential of the node N of the memory cell MC[p, q] shown becomes VPR - Vx[p, q] + Vw[p], and the potential of the node N of the memory cell MC[p, q + 1] becomes VPR - Vx[p, q + 1] + Vw[p]. In addition, when the potential of the wiring RW[p + 1] becomes the second analog potential Vw[p + 1], it is assumed that the change amount of the potential of the first electrode of the capacitor C11 is approximately the same as the change amount of the potential of the node N. Figure 15 The potential of the node N of the memory cell MC[p + 1, q] shown becomes VPR - Vx[p + 1, q] + Vw[p + 1], and the potential of the node N of the memory cell MC[p + 1, q + 1] becomes VPR - Vx[p + 1, q + 1] + Vw[p + 1].

[0239] According to Equation 6, it can be seen that the product-sum value of the first analog data and the second analog data corresponding to the memory cell MC[p, q] and the memory cell MC[p + 1, q] is reflected in the current obtained by subtracting the current Ioffset[q] from the current ΔI[q], that is, the current Iout[q]. In addition, it can be seen that the product-sum value of the first analog data and the second analog data corresponding to the memory cell MC[p, q + 1] and the memory cell MC[p + 1, q + 1] is reflected in the current obtained by subtracting the current Ioffset[q + 1] from the current ΔI[q + 1], that is, the current Iout[q + 1].

[0240] After time T16, a potential between the potential VSS and the potential VDD serving as a reference potential (for example, the potential (VDD + VSS) / 2) is supplied to the wirings RW[p] and RW[p+1] again.

[0241] With the above structure, the product-sum operation can be performed with a smaller circuit scale. With the above structure, the product-sum operation can be performed at high speed. With the above structure, the product-sum operation can be performed with low power consumption.

[0242] Note that transistors with an extremely low off-state current are preferably used as the transistors Tr12, Tr22, Tr23, Tr25, or Tr26. By using a transistor with an extremely low off-state current as the transistor Tr12, the potential of the node N can be maintained for a long time. By using transistors with an extremely low off-state current as the transistors Tr22 and Tr23, the gate potential of the transistor Tr21 can be maintained for a long time. By using transistors with an extremely low off-state current as the transistors Tr25 and Tr26, the gate potential of the transistor Tr24 can be maintained for a long time.

[0243] An OS transistor can be used as the transistor with an extremely low off-state current. In a state where the source-drain voltage is 10V and the room temperature (around 25°C), the leakage current of the OS transistor normalized by the channel width can be 10×10 -21 A / μm (10 zA / μm) or less.

[0244] By using the above semiconductor device, the product-sum operation in the neural network NN can be performed.

[0245] This embodiment can be appropriately combined with any other embodiment.

[0246] (Embodiment 5) In this embodiment, a structural example of the OS transistor that can be used in the above embodiment is described.

[0247] <Structural example of a transistor> Figure 18A is a top view showing a structural example of a transistor. Figure 18B is Figure 18A a cross-sectional view between the lines X1 - X2 of Figure 18C is Figure 18A a cross-sectional view between the lines Y1 - Y2 of . Sometimes the direction of the line X1 - X2 is referred to as the channel length direction, and the direction of the line Y1 - Y2 is referred to as the channel width direction. Figure 18B is a diagram showing the cross-sectional structure in the channel length direction of the transistor, Figure 18C is a diagram showing the cross-sectional structure in the channel width direction of the transistor. Note that in order to clearly show the device structure, some constituent elements are omitted in Figure 18A

[0248] A semiconductor device according to an embodiment of the present invention includes insulating layers 812 to 820, metal oxide films 821 to 824, and conductive layers 850 to 853. A transistor 801 is formed on an insulating surface. Figures 18A to 18C The case where the transistor 801 is formed on the insulating layer 811 is shown. The transistor 801 is covered with the insulating layer 818 and the insulating layer 819.

[0249] Note that the insulating layer, metal oxide film, conductive layer, etc. constituting the transistor 801 may each be a single layer or a stack of multiple films. These layers can be formed using various deposition methods such as sputtering, molecular beam epitaxy (MBE: Molecular Beam Epitaxy), pulsed laser ablation (PLA: Pulsed Laser Ablation), CVD method, atomic layer deposition (ALD) method, etc. Note that the CVD method includes plasma CVD method, thermal CVD method, metalorganic CVD method, etc.

[0250] The conductive layer 850 includes a region used as the gate electrode of the transistor 801. The conductive layers 851 and 852 include regions used as the source electrode and the drain electrode. The conductive layer 853 includes a region used as the back gate electrode. The insulating layer 817 includes a region used as the gate insulating layer on the side of the gate electrode (front gate electrode), and the insulating layer formed by the stack of the insulating layers 814 to 816 includes a region used as the gate insulating layer on the side of the back gate electrode. The insulating layer 818 is used as an interlayer insulating layer. The insulating layer 819 is used as a barrier layer.

[0251] The metal oxide films 821 to 824 are collectively referred to as the oxide layer 830. As Figure 18B and Figure 18C shown, the oxide layer 830 includes a region where the metal oxide film 821, the metal oxide film 822, and the metal oxide film 824 are sequentially stacked. In addition, a pair of metal oxide films 823 are located on the conductive layers 851 and 852. When the transistor 801 is in the on state, the channel formation region is mainly formed in the metal oxide film 822 of the oxide layer 830.

[0252] The metal oxide film 824 covers the metal oxide films 821 to 823, the conductive layers 851 and 852. The insulating layer 817 is located between the metal oxide film 823 and the conductive layer 850. Both the conductive layers 851 and 852 include regions overlapping the conductive layer 850 with the metal oxide film 823, the metal oxide film 824, and the insulating layer 817 interposed therebetween.

[0253] The conductive layer 851 and the conductive layer 852 are formed by using the hard mask used to form the metal oxide film 821 and the metal oxide film 822. Thus, the conductive layer 851 and the conductive layer 852 do not include the regions in contact with the sides of the metal oxide film 821 and the metal oxide film 822. For example, the metal oxide films 821, 822 and the conductive layers 851, 852 can be formed through the following steps. First, a conductive film is formed on the stacked two-layer metal oxide film. The conductive film is processed (etched) into a desired shape to form a hard mask. The hard mask is used to process the shapes of the two-layer metal oxide film to form a stack of the metal oxide film 821 and the metal oxide film 822. Then, the hard mask is processed into a desired shape to form the conductive layer 851 and the conductive layer 852.

[0254] As the insulating materials for the insulating layers 811 to 818, there are the following materials: aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. The insulating layers 811 to 818 are composed of a single layer or a stack including any of these insulating materials. The layers constituting the insulating layers 811 to 818 may contain a plurality of insulating materials.

[0255] In this specification, etc., oxynitride refers to a compound in which the oxygen content is greater than the nitrogen content, and nitride oxide refers to a compound in which the nitrogen content is greater than the oxygen content.

[0256] In order to suppress the increase in oxygen vacancies in the oxide layer 830, the insulating layers 816 to 818 preferably contain oxygen. The insulating layers 816 to 818 are more preferably formed using an insulating film that can release oxygen by heating (hereinafter, such an insulating film is also referred to as an insulating film containing excess oxygen). By supplying oxygen from the insulating film containing excess oxygen to the oxide layer 830, the oxygen vacancies in the oxide layer 830 can be filled. Therefore, the reliability and electrical characteristics of the transistor 801 can be improved.

[0257] The insulating film containing excess oxygen is a film in which the release amount of oxygen molecules is 1.0×10 18 molecules / cm 3 or more in the range where the film surface temperature is 100 °C or higher and 700 °C or lower or 100 °C or higher and 500 °C or lower when using thermal desorption spectroscopy (TDS: Thermal Desorption Spectroscopy). The release amount of oxygen molecules is preferably 3.0×10 20 atoms / cm 3 or more.

[0258] An insulating film containing excess oxygen can be formed by performing a process of adding oxygen to the insulating film. As the oxygen addition process, heat treatment in an oxygen atmosphere, plasma treatment, or a process using ion implantation, ion doping, plasma immersion ion implantation, etc. can be used. As the gas for adding oxygen, 16 O 2 or 18 O 2 and other oxygen gases, nitrous oxide gas, ozone gas, etc. can be used.

[0259] In order to prevent an increase in the hydrogen concentration in the oxide layer 830, it is preferable to reduce the hydrogen concentration in the insulating layers 812 to 819. In particular, it is preferable to reduce the hydrogen concentration in the insulating layers 813 to 818. Specifically, the hydrogen concentration is 2×10 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, and even more preferably 5×10 18 atoms / cm 3 or less.

[0260] The above hydrogen concentration is measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry).

[0261] In the transistor 801, the oxide layer 830 is preferably surrounded by an insulating layer having barrier properties against oxygen and hydrogen (hereinafter, such an insulating layer is also referred to as a barrier layer). By adopting this structure, the release of oxygen from the oxide layer 830 can be suppressed and the intrusion of hydrogen into the oxide layer 830 can be suppressed. Thereby, the reliability and electrical characteristics of the transistor 801 can be improved.

[0262] For example, the insulating layer 819 is used as a barrier layer, and at least one of the insulating layers 811, 812, 814 is used as a barrier layer. The barrier layer can be formed of materials such as alumina, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, silicon nitride.

[0263] Here, a structural example of the insulating layers 811 to 818 is shown. In this example, the insulating layers 811, 812, 815, and 819 are all used as barrier layers. The insulating layers 816 to 818 are oxide layers containing excess oxygen. The insulating layer 811 is formed of silicon nitride. The insulating layer 812 is formed of aluminum oxide. The insulating layer 813 is formed of silicon oxynitride. The insulating layers 814 to 816, which are used as the gate insulating layer on the back gate electrode side, are formed of a stack of silicon oxide, aluminum oxide, and silicon oxide. The insulating layer 817, which is used as the gate insulating layer on the front gate electrode side, is formed of silicon oxynitride. The insulating layer 818, which is used as the interlayer insulating layer, is formed of silicon oxide. The insulating layer 819 is formed of aluminum oxide.

[0264] As the conductive materials for the conductive layers 850 to 853, there are metals such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, and metal nitrides (tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride) containing any of the above metals as components. Conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon oxide can be used.

[0265] Here, a structural example of the conductive layers 850 to 853 is shown. The conductive layer 850 is a single layer of tantalum nitride or tungsten. Alternatively, the conductive layer 850 is a stack of tantalum nitride, tantalum, and tantalum nitride. The conductive layer 851 is a single layer of tantalum nitride or a stack of tantalum nitride and tungsten. The structure of the conductive layer 852 is the same as that of the conductive layer 851. The conductive layer 853 is a single layer of tantalum nitride or a stack of tantalum nitride and tungsten.

[0266] In order to reduce the off-state current of the transistor 801, the metal oxide film 822 preferably has a large energy gap, for example. The energy gap of the metal oxide film 822 is 2.5 eV or more and 4.2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, and more preferably 3 eV or more and 3.5 eV or less.

[0267] The oxide layer 830 preferably has crystallinity. Preferably, at least the metal oxide film 822 has crystallinity. By having the above structure, a transistor 801 with high reliability and excellent electrical characteristics can be realized.

[0268] Oxides that can be used for the metal oxide film 822 are, for example, In-Ga oxides, In-Zn oxides, In-M-Zn oxides (M is Al, Ga, Y, or Sn). The metal oxide film 822 is not limited to an oxide layer containing indium. The metal oxide film 822 can be formed, for example, using Zn-Sn oxides, Ga-Sn oxides, Zn-Mg oxides, and the like. The metal oxide films 821, 823, and 824 can also be formed using the same oxides as the metal oxide film 822. In particular, the metal oxide films 821, 823, and 824 can be formed using Ga oxides, respectively.

[0269] When an interface energy level is formed at the interface between the metal oxide film 822 and the metal oxide film 821, since the channel formation region is also formed in the region near the interface, the threshold voltage of the transistor 801 changes. The metal oxide film 821 preferably contains at least one of the metal elements constituting the metal oxide film 822 as its constituent element. Thereby, it is not easy to form an interface energy level at the interface between the metal oxide film 822 and the metal oxide film 821, and the deviation of electrical characteristics such as the threshold voltage of the transistor 801 can be reduced.

[0270] The metal oxide film 824 preferably contains at least one of the metal elements constituting the metal oxide film 822 as its constituent element because interface scattering is not likely to occur at the interface between the metal oxide film 822 and the metal oxide film 824, and it is not likely to impede the migration of carriers. Therefore, the field-effect mobility of the transistor 801 can be improved.

[0271] Preferably, among the metal oxide films 821 to 824, the metal oxide film 822 has the highest carrier mobility. Thereby, a channel can be formed in the metal oxide film 822 far from the insulating layers 816 and 817.

[0272] For example, metal oxides containing In such as In-M-Zn oxides can increase the carrier mobility by increasing the content of In. In In-M-Zn oxides, the s orbitals of heavy metals mainly drive carrier conduction. By increasing the indium content, the overlap of the s orbitals of In atoms can be increased. Therefore, the mobility of the oxide with a higher indium content is higher than that of the oxide with a lower indium content. Thus, by using the oxide with a higher indium content as the metal oxide film, the carrier mobility can be increased.

[0273] Therefore, for example, a metal oxide film 822 is formed using In-Ga-Zn oxide, and metal oxide films 821 and 823 are formed using Ga oxide. For example, when forming metal oxide films 821 to 823 using In-M-Zn oxide, the In content in the metal oxide film 822 is higher than that in the metal oxide films 821 and 823. When forming In-M-Zn oxide by sputtering, the In content can be changed by changing the atomic number ratio of the metal elements in the target.

[0274] For example, the atomic number ratio of the metal elements in the target used to deposit the metal oxide film 822 is preferably In:M:Zn = 1:1:1, 3:1:2, or 4:2:4.1. For example, the atomic number ratio of the metal elements in the target used to deposit the metal oxide films 821 and 823 is preferably In:M:Zn = 1:3:2 or 1:3:4. The atomic number ratio of the In-M-Zn oxide deposited using a target with In:M:Zn = 4:2:4.1 is approximately In:M:Zn = 4:2:3.

[0275] To endow the transistor 801 with stable electrical characteristics, it is preferable to reduce the impurity concentration in the oxide layer 830. In metal oxides, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main components are impurities. For example, hydrogen and nitrogen form donor energy levels, resulting in an increase in carrier density. In addition, silicon and carbon form impurity energy levels in the metal oxide. This impurity energy level becomes a trap and sometimes deteriorates the electrical characteristics of the transistor.

[0276] For example, the oxide layer 830 has a silicon concentration of 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less in a region. The same applies to the carbon concentration in the oxide layer 830.

[0277] The oxide layer 830 has an alkali metal concentration of 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less in a region. The same applies to the alkaline earth metal concentration of the oxide layer 830.

[0278] The oxide layer 830 has a hydrogen concentration lower than 1×10 20 atoms / cm 3 , preferably lower than 1×10 19 atoms / cm 3 , more preferably lower than 5×10 18 atoms / cm 3, more preferably below 1×10 18 atoms / cm 3 region.

[0279] The impurity concentration in the oxide layer 830 is measured by SIMS.

[0280] In the case where the metal oxide film 822 has oxygen vacancies, sometimes donor energy levels are formed because hydrogen enters the oxygen vacancy portion. The oxygen vacancies become a factor in reducing the on-state current of the transistor 801. Note that the oxygen vacancy portion is more stable when oxygen enters than when hydrogen enters. Therefore, by reducing the oxygen vacancies in the metal oxide film 822, sometimes the on-state current of the transistor 801 can be increased. Thus, the method of preventing hydrogen from entering the oxygen vacancy portion by reducing hydrogen in the metal oxide film 822 is effective in improving the on-state current characteristics.

[0281] The hydrogen contained in the metal oxide reacts with the oxygen bonded to the metal atoms to generate water, so sometimes oxygen vacancies are formed. When hydrogen enters the oxygen vacancies, sometimes electrons are generated as carriers. In addition, sometimes a part of the hydrogen bonds with the oxygen bonded to the metal atoms, and electrons are generated as carriers. Since the metal oxide film 822 includes a channel formation region, when the metal oxide film 822 contains hydrogen, the transistor 801 tends to have a normally-on characteristic. Therefore, it is preferable to reduce the hydrogen in the metal oxide film 822 as much as possible.

[0282] Note that the metal oxide film 822 may also include an n-type region 822n in the region in contact with the conductive layer 851 or the conductive layer 852. The region 822n is formed by a phenomenon in which oxygen in the metal oxide film 822 is extracted by the conductive layer 851 or the conductive layer 852, or a phenomenon in which the conductive material in the conductive layer 851 or the conductive layer 852 bonds with the elements in the metal oxide film 822. By forming the region 822n, the contact resistance between the conductive layer 851 or the conductive layer 852 and the metal oxide film 822 can be reduced.

[0283] Figures 18A to 18C An example in which the oxide layer 830 has a four-layer structure is shown, but one embodiment of the present invention is not limited thereto. For example, the oxide layer 830 may also have a three-layer structure without the metal oxide film 821 or the metal oxide film 823. Or, one or more metal oxide films similar to the metal oxide films 821 to 824 may be provided at any two or more positions among between any layers of the oxide layer 830, above the oxide layer 830, and below the oxide layer 830.

[0284] Refer to Figure 19 to describe the stacking effect of the metal oxide films 821, 822, and 824. Figure 19It is a schematic diagram of the energy band structure of the channel formation region of transistor 801.

[0285] In Figure 19 , Ec816e, Ec821e, Ec822e, Ec824e, and Ec817e respectively represent the energies of the conduction band bottoms of insulating layer 816, metal oxide film 821, metal oxide film 822, metal oxide film 824, and insulating layer 817.

[0286] Here, the energy difference between the vacuum level and the conduction band bottom (this difference is also called the electron affinity) is the value obtained by subtracting the energy gap from the energy difference between the vacuum level and the top of the valence band (this difference is also called the ionization potential). The energy gap can be measured using a spectroscopic ellipsometer (UT-300 manufactured by HORIBA JOBIN YVON). The energy difference between the vacuum level and the top of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultraviolet Photoelectron Spectroscopy) apparatus (VersaProbe manufactured by PHI).

[0287] Since insulating layers 816 and 817 are insulators, Ec816e and Ec817e are closer to the vacuum level than Ec821e, Ec822e, and Ec824e (that is, the electron affinities of insulating layers 816 and 817 are smaller than those of metal oxide films 821, 822, and 824).

[0288] The electron affinity of metal oxide film 822 is larger than those of metal oxide films 821 and 824. For example, the difference in electron affinity between metal oxide film 822 and metal oxide film 821 and the difference in electron affinity between metal oxide film 822 and metal oxide film 824 are both 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less. Note that the electron affinity is the energy difference between the vacuum level and the conduction band bottom.

[0289] When a voltage is applied to the gate electrode (conductive layer 850) of transistor 801, the channel is mainly formed in metal oxide film 822 having the largest electron affinity among metal oxide films 821, 822, and 824.

[0290] Indium gallium oxide has a small electron affinity and high oxygen barrier properties. Therefore, metal oxide film 824 preferably contains indium gallium oxide. The ratio of gallium atoms [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, more preferably 90% or more.

[0291] Sometimes, there is a mixed region of the metal oxide film 821 and the metal oxide film 822 between the metal oxide film 821 and the metal oxide film 822. Additionally, sometimes, there is a mixed region of the metal oxide film 824 and the metal oxide film 822 between the metal oxide film 824 and the metal oxide film 822. The interface state density of the mixed region is low. Therefore, in the energy band structure of the region where the metal oxide films 821, 822, and 824 are stacked, the energy at each interface and its vicinity changes continuously (continuously joined).

[0292] In the oxide layer 830 having the above energy band structure, electrons mainly migrate in the metal oxide film 822. Therefore, even if there are interface energy levels at the interface between the metal oxide film 821 and the insulating layer 816 or at the interface between the metal oxide film 824 and the insulating layer 817, these interface energy levels are not likely to impede the electron migration in the oxide layer 830. Thus, the on-state current of the transistor 801 can be increased.

[0293] As Figure 19 shown, although trap energy levels Et826e and Et827e caused by impurities or defects may be formed near the interface between the metal oxide film 821 and the insulating layer 816 and near the interface between the metal oxide film 824 and the insulating layer 817, the presence of the metal oxide films 821 and 824 can keep the metal oxide film 822 away from the trap energy levels Et826e and Et827e.

[0294] Note that when the energy difference between Ec821e and Ec822e is small, sometimes electrons in the metal oxide film 822 cross this energy difference to reach the trap energy level Et826e. Since the electrons are captured by the trap energy level Et826e, fixed negative charges are generated at the interface of the insulating film, which causes the threshold voltage of the transistor to drift in the positive direction. The same applies when the energy difference between Ec822e and Ec824e is small.

[0295] To reduce the variation in the threshold voltage of the transistor 801 and improve the electrical characteristics of the transistor 801, the energy difference between Ec821e and Ec822e and the energy difference between Ec824e and Ec822e are preferably 0.1 eV or more, and more preferably 0.15 eV or more.

[0296] Note that the transistor 801 may not include a back gate electrode.

[0297] <Examples of the stacked structure> Next, the structure of a semiconductor device in which an OS transistor and other transistors are stacked will be described.

[0298] Figure 20An example of the stacked structure of the semiconductor device 860 is shown, in which the transistor Tr100 for the Si transistor, the Tr200 for the OS transistor, and the capacitor C100 are stacked.

[0299] The semiconductor device 860 is composed of a stacked structure of the CMOS layer 871, the wiring layers W 1 to W 5 , the transistor layer 872, and the wiring layers W 6 , W 7 .

[0300] The transistor Tr100 is provided in the CMOS layer 871. The channel formation region of the transistor Tr100 is provided in the single crystal silicon wafer 870. The gate electrode 873 of the transistor Tr100 is connected to one electrode 875 of the capacitor C100 through the wiring layers W 1 to W 5 .

[0301] The transistor Tr200 is provided in the transistor layer 872. In Figure 20 , the transistor Tr200 and the transistor 801 ( Figures 18A to 18C ) have the same structure. An electrode 874 corresponding to one of the source and drain of the transistor Tr200 is connected to one electrode 875 of the capacitor C100. Note that in Figure 20 , the transistor Tr200 has a back gate electrode in the wiring layer W 5 . The capacitor C100 is provided in the wiring layer W 6 .

[0302] As described above, by stacking the OS transistor and other components, the circuit area can be reduced.

[0303] The above structure can be applied to the semiconductor device 200 and the like described in Embodiment 3. For example, as the transistor Tr11, the transistor Tr12, and the capacitor C11 in Figure 15 , the transistor Tr100, the transistor Tr200, and the capacitor C100 can be used respectively. In addition, as the transistor Tr21 or Tr24, the transistors Tr22, Tr23, Tr25 or Tr26, and the capacitor C21 or C22 in Figure 16 , the transistor Tr100, the transistor Tr200, and the capacitor C100 can be used respectively.

[0304] This embodiment can be appropriately combined with any other embodiment.

[0305] (Embodiment 6) In this embodiment, metal oxides that can be used for the OS transistor described in the above embodiment are described. In particular, metal oxides and cloud-aligned composite oxide semiconductor (CAC-OS) are described in detail below.

[0306] CAC-OS or CAC metal oxide has a conductive function in a part of the material and an insulating function in another part of the material, and CAC-OS or CAC metal oxide has a semiconductor function as a whole. When CAC-OS or CAC metal oxide is used in the channel formation region of a transistor, the conductive function is to allow electrons (or holes) used as carriers to flow through, and the insulating function is to prevent electrons used as carriers from flowing through. Through the complementary effects of the conductive function and the insulating function, CAC-OS or CAC metal oxide can have a switching function (on / off function). By separating each function in CAC-OS or CAC metal oxide, each function can be maximized.

[0307] CAC-OS or CAC metal oxide includes a conductive region and an insulating region. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In the material, the conductive region and the insulating region are sometimes separated at the nanoparticle level. The conductive region and the insulating region are sometimes unevenly distributed in the material. Sometimes, the conductive region is observed to be connected in a cloud-like manner with blurred edges.

[0308] In CAC-OS or CAC metal oxide, the conductive region and the insulating region each have a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, and are dispersed in the material.

[0309] CAC-OS or CAC metal oxide is composed of components with different band gaps. For example, CAC-OS or CACmetal oxide is composed of a component with a wide gap caused by an insulating region and a component with a narrow gap caused by a conductive region. In this structure, when carriers are allowed to flow through, the carriers mainly flow through the component with the narrow gap. The component with the narrow gap interacts with the component with the narrow gap through the complementary effect with the component with the wide gap, and also allows carriers to flow through the component with the wide gap. Therefore, when the above-mentioned CAC-OS or CAC metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-state current and a high field effect mobility can be obtained in the on state of the transistor.

[0310] That is to say, CAC-OS or CAC metal oxide can also be referred to as matrix composite or metal matrix composite.

[0311] CAC-OS, for example, has a structure in which elements contained in the oxide semiconductor are unevenly distributed. Each of the materials containing unevenly distributed elements has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less or an approximate size. Note that in the following description of metal oxides, the state of a region in which one or more metal elements are unevenly distributed and mixed is referred to as mosaic or patchy. Each of these regions has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less or an approximate size.

[0312] Note that the metal oxide preferably contains at least indium. Particularly preferably, it contains indium and zinc. In addition, it may also contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium, etc.

[0313] For example, in CAC-OS, the In-Ga-Zn oxide having the CAC-OS structure (in particular, such In-Ga-Zn oxide can be referred to as CAC-IGZO) has a structure in which the material is divided into indium oxide (InO X1 , where X1 is a real number greater than 0) or indium zinc oxide (In X2 Zn Y2 O Z2 , where X2, Y2, and Z2 are real numbers greater than 0) and gallium oxide (GaO X3 , where X3 is a real number greater than 0) or gallium zinc oxide (Ga X4 Zn Y4 O Z4 , where X4, Y4, and Z4 are real numbers greater than 0), etc., to form a mosaic structure. And the formed mosaic InO X1 or In X2 Zn Y2 O Z2 is uniformly distributed in the film. This structure is also referred to as a cloud-like structure.

[0314] In other words, CAC-OS is a material having regions mainly composed of GaO X3 and regions mainly composed of In X2 Zn Y2 O Z2 or InO X1A composite metal oxide formed by mixing regions with [a certain] main component. Note that in this specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the In concentration in the first region is higher than that in the second region.

[0315] Note that compounds containing In, Ga, Zn, and O are also known as IGZO. As a typical example, there can be cited crystalline compounds represented by InGaO 3 (ZnO) m1 (where m1 is a natural number) and crystalline compounds represented by In (1+x0) Ga (1-x0) O 3 (ZnO) m0 (-1 ≤ x0 ≤ 1, and m0 is an arbitrary number).

[0316] The above-mentioned crystalline compounds have a single crystal structure, a polycrystalline structure, or a c-axis-aligned crystal (CAAC) structure. Note that the CAAC structure is a crystalline structure in which the nanocrystals of multiple IGZOs have c-axis orientation and are connected in a non-oriented manner on the a-b plane.

[0317] On the other hand, CAC-OS is related to the material composition of the metal oxide. In the material composition of CAC-OS containing In, Ga, Zn, and O, regions of nanoparticles mainly composed of Ga and regions of nanoparticles mainly composed of In are partially observed. These regions of nanoparticles are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0318] Note that CAC-OS does not include a laminated structure composed of two or more films with different atomic ratios. For example, it does not include a two-layer structure of a film mainly composed of In and a film mainly composed of Ga.

[0319] Sometimes, a clear boundary between the region mainly composed of GaO X3 and the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 cannot be observed.

[0320] When one or more of aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium are included in CAC-OS to replace gallium, nanoparticle-like regions mainly composed of the metal element are observed in a part of CAC-OS, and nanoparticle-like regions mainly composed of In are observed in a part, and these nanoparticle-like regions are irregularly dispersed in a mosaic pattern in CAC-OS.

[0321] CAC-OS can be formed, for example, by sputtering under conditions where the substrate is not intentionally heated. When forming CAC-OS by sputtering, as the deposition gas, one or more selected from inert gases (typically argon), oxygen gas, and nitrogen gas can be used. The lower the flow ratio of oxygen gas in the total flow rate of the deposition gas during deposition, the better. For example, the flow ratio of oxygen gas is preferably 0% or more and less than 30%, more preferably 0% or more and 10% or less.

[0322] CAC-OS has the following characteristics: When measured by the Out-of-plane method, one of the X-ray diffraction (XRD: X-ray diffraction) measurement methods, using θ / 2θ scanning, no distinct peak is observed. That is, according to X-ray diffraction, it can be known that there is no orientation in the a-b plane direction and the c-axis direction in the measurement region.

[0323] In the electron diffraction pattern of CAC-OS obtained by irradiating an electron beam with a beam diameter of 1 nm (also called a nano-sized electron beam), a bright annular region and multiple bright spots within the annular region are observed. Thus, from the electron diffraction pattern, it can be known that the crystal structure of CAC-OS includes a nanocrystal (nc: nanocrystal) structure without orientation in the plane direction and the cross-sectional direction.

[0324] For example, from the surface analysis image obtained by energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy), it can be confirmed that the In-Ga-Zn oxide having a CAC composition has regions mainly composed of GaO X3 and regions mainly composed of In X2 Zn Y2 O Z2 or InO X1 distributed unevenly and mixed.

[0325] The structure of CAC-OS is different from that of the IGZO compound in which metal elements are uniformly distributed, and it has properties different from those of the IGZO compound. In other words, in CAC-OS, regions mainly composed of GaO X3 etc. and regions mainly composed of InX2 Zn Y2 O Z2 or InO X1 Region separation with the above as the main component forms a mosaic pattern.

[0326] With In X2 Zn Y2 O Z2 or InO X1 as the main component, the conductivity of the region is higher than that of the region with GaO X3 etc. as the main component. In other words, when carriers flow through the region with In X2 Zn Y2 O Z2 or InO X1 as the main component, it exhibits the conductivity of an oxide semiconductor. Therefore, when the region with In X2 Zn Y2 O Z2 or InO X1 as the main component is distributed in the oxide semiconductor in a cloud-like manner, high field-effect mobility (μ) can be achieved.

[0327] On the other hand, the insulation of the region with GaO X3 etc. as the main component is higher than that of the region with In X2 Zn Y2 O Z2 or InO X1 as the main component. In other words, when the region with GaO X3 etc. as the main component is distributed in the oxide semiconductor, the off-state current can be suppressed to achieve good switching operation.

[0328] Therefore, when CAC-OS is used in a semiconductor device, through the complementary action of the insulation caused by GaO X3 etc. and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 high on-state current (I on ) and high field-effect mobility (μ) can be achieved.

[0329] The semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable for various semiconductor devices.

[0330] This embodiment can be appropriately combined with any other embodiment.

[0331] (Embodiment 7) In this embodiment, a structural example of an electronic device that can be used in the power receiving unit described in the above embodiment is described.

[0332] Figures 21A to 21F This is a diagram showing electronic devices. These electronic devices may include a housing 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including a power switch and operation switches), connection terminals 5006, a sensor 5007 (a sensor having a function of measuring factors such as force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays), a microphone 5008, etc.

[0333] Figure 21A This shows a mobile computer, which may further include a switch 5009, an infrared port 5010, etc. in addition to the above. Figure 21B This shows a portable image reproduction device (such as a DVD reproduction device) having a recording medium, which may further include a second display unit 5002, a recording medium reading unit 5011, etc. in addition to the above. Figure 21C This shows a goggle-type display, which may further include a second display unit 5002, a support unit 5012, earphones 5013, etc. in addition to the above. Figure 21D This shows a portable game console, which may further include a recording medium reading unit 5011, etc. in addition to the above. Figure 21E This shows a digital camera having a television reception function, which may further include an antenna 5014, a shutter button 5015, an image receiving unit 5016, etc. in addition to the above. Figure 21F This shows a portable game console, which may further include a second display unit 5002, a recording medium reading unit 5011, etc. in addition to the above.

[0334] Figures 21A to 21FThe electronic device shown can have various functions. For example, it can have the following functions: displaying various data (static images, dynamic images, text images, etc.) on the display unit; a touch panel; displaying a calendar, date, time, etc.; controlling processing by using various software (programs); performing wireless communication; connecting to various computer networks by using the wireless communication function; sending and receiving various data by using the wireless communication function; reading out programs or data stored in a recording medium and displaying them on the display unit, etc. Furthermore, in an electronic device having a plurality of display units, it can have the following functions: one display unit mainly displays image data, while the other display unit mainly displays text data; or, displaying images considering parallax on the plurality of display units to display a stereoscopic image, etc. Furthermore, in an electronic device having an image receiving unit, it can have the following functions: taking a static image; taking a dynamic image; automatically or manually correcting the taken image; storing the taken image in a recording medium (external recording medium or recording medium built in the camera); displaying the taken image on the display unit, etc. Note that, Figures 21A to 21F The functions that the electronic device shown can have are not limited to the above functions, but can have various functions.

[0335] The electronic device described in this embodiment incorporates a battery and can perform the wireless power supply described in the above embodiment.

[0336] Figure 22A and Figure 22B An example of the use of the electronic device is shown.

[0337] Figure 22A An example of operating an information terminal in a moving object such as a vehicle is shown.

[0338] 5103 is a steering wheel with an antenna inside. The antenna inside the steering wheel 5103 can supply power to the electronic device 5100. The electronic device 5100 includes a battery and can be charged by using wireless power supply. A bracket capable of fixing the electronic device 5100 can be provided on the steering wheel 5103. When the electronic device 5100 is fixed to the steering wheel 5103, a call or a video call can be made without using hands. In addition, by using voice recognition with the microphone of the electronic device 5100, the driver's voice can be used for driving.

[0339] For example, when the vehicle is parked, the electronic device 5100 can be operated to cause the display unit 5102 to display position information. In addition, information that is not displayed on the in-vehicle display unit 5101, such as engine speed, steering wheel angle, temperature, tire pressure, etc., can be displayed on the display unit 5102. The display unit 5102 has a touch input function. In addition, images outside the vehicle can be displayed on the display unit 5102 using one or more cameras that photograph the outside of the vehicle. That is, for example, the display unit 5102 can be used as a rear monitor. In addition, in order to prevent drowsy driving, the electronic device 5100 can operate as follows: when monitoring the driving speed while receiving information such as the driving speed from the vehicle wirelessly, the electronic device 5100 photographs the driver while driving, and when the driver has his eyes closed for a long time, the electronic device 5100 vibrates, emits a warning sound, plays music, etc. (according to settings that can be appropriately selected by the driver). In addition, photographing of the driver can be stopped when the vehicle is parked to save power. Also, the battery of the electronic device 5100 can be wirelessly charged when the vehicle is parked.

[0340] As described above, the electronic device 5100 is expected to be applied to moving objects such as vehicles in various ways. In order for the electronic device 5100 to have multiple functions, it is preferable that the electronic device 5100 incorporates a plurality of sensors and a plurality of antennas. Although moving objects such as vehicles have a power source, the power source is limited. Considering the power required to drive the moving object, it is preferable that the power consumed by the electronic device 5100 be as low as possible. Especially in the case of an electric vehicle, the power consumption of the electronic device 5100 will shorten the driving distance. Even if the electronic device 5100 has multiple functions, the chance of using all functions simultaneously is rare, and mostly only 1 or 2 functions are used as needed. In the case where the electronic device 5100 having a plurality of batteries has multiple functions by preparing a battery for each function, power can be saved by only turning on the function to be used and supplying power from the battery corresponding to that function. Furthermore, the battery corresponding to the function that is not used among the plurality of batteries can be wirelessly charged using an antenna provided on the vehicle.

[0341] Figure 22B An example of operating an information terminal inside an aircraft or the like is shown. Since there are restrictions on the time when a personal information terminal can be used inside an aircraft or the like, it is preferable that the aircraft have an information terminal that passengers can use when the flight time is long.

[0342] The electronic device 5200 is an information terminal that can display images such as movies, games, and advertisements on the display unit 5202 and can instantaneously obtain information on the current flight position and remaining flight time using the communication function. The display unit 5202 has a touch input function.

[0343] By embedding the electronic device 5200 in the recess of the seat 5201 and providing the antenna setting unit 5203 at a position overlapping with the electronic device 5200, the electronic device 5200 can be wirelessly powered while it is embedded in the recess. When the user is unwell and wants to contact the flight attendant, etc., the electronic device 5200 can also be used as a phone or communication tool. When the electronic device 5200 has a translation function, etc., passengers who speak different languages from the flight attendant can also communicate with the flight attendant using the display unit 5202 of the electronic device 5200. In addition, passengers in adjacent seats who speak different languages can also communicate using the display unit 5202 of the electronic device 5200. Additionally, the display unit 5202 can be used as a message board. For example, when the user is sleeping, an English message such as "Do Not Disturb" can be continuously displayed using the display unit 5202.

[0344] The electronic device 5200 can be provided with multiple batteries according to each function. By only turning on the functions to be used and turning off the functions not to be used, power can be saved. Furthermore, the batteries corresponding to the functions that are not working among the multiple batteries can be wirelessly powered using the antenna setting unit 5203.

[0345] The batteries of the electronic devices 5200 provided in multiple seats can be designed to be used as emergency power sources when an abnormality occurs in the aircraft's power system. Since the electronic devices 5200 provided in multiple seats are all the same products with the same design, a system can be constructed in such a way that the electronic devices 5200 can be connected in series as emergency power sources.

[0346] As the multiple small batteries included in the electronic device 5200, one or more selected from lithium ion secondary batteries such as lithium polymer batteries, lithium ion capacitors, electric double layer capacitors, and redox capacitors can be used.

[0347] Next, another example of an electronic device for a power receiving unit that can be used for the above-described embodiments will be described. Figure 23 It is a cross-sectional schematic diagram showing an example of a pacemaker.

[0348] The pacemaker main body 5300 includes at least a battery 5301a, a battery 5301b, a regulator, a control circuit, an antenna 5304, a lead 5302 for the right atrium, and a lead 5303 for the right ventricle.

[0349] The pacemaker main body 5300 is implanted in the body through surgery. The front ends of the two leads are implanted into the right ventricle and the right atrium respectively through the subclavian vein 5305 and the superior vena cava 5306 of the human body.

[0350] Power can be received through the antenna 5304 to charge the battery 5301a and the battery 5301b, thereby reducing the replacement frequency of the pacemaker. Since the pacemaker main body 5300 has multiple batteries and has high safety, even if one battery fails, the other battery can still work. Thus, multiple batteries can be used as auxiliary power sources. When the battery for the pacemaker is further divided into multiple thin batteries and installed on the printed circuit board provided with a control circuit containing a CPU, etc., the pacemaker main body 5300 can be made smaller and thinner.

[0351] In addition to the antenna 5304 capable of receiving power, the pacemaker may further include an antenna capable of transmitting physiological signals. For example, a system for monitoring cardiac activity that can utilize an external monitor to monitor physiological signals such as pulse, respiration rate, heart rate, body temperature, etc. can be configured.

[0352] Note that the method of setting the pacemaker is only an example and can be changed in various ways according to heart disease patients.

[0353] This embodiment is not limited to pacemakers. Cochlear implants are more popular artificial organs than pacemakers. Cochlear implants convert sound into electrical signals and directly stimulate the auditory nerve using a stimulation device implanted in the cochlea.

[0354] A cochlear implant includes a first device surgically implanted in the ear and a second device that picks up sound using a microphone and transmits the picked-up sound to the implanted first device. The first device and the second device are not electrically connected to each other, and transmission and reception between the two are performed wirelessly. The first device includes at least an antenna for receiving the electrical signal after the sound is converted and a wire leading to the cochlea. The second device includes at least a sound processing unit for converting sound into an electrical signal and a transmission circuit for transmitting the electrical signal to the first device.

[0355] This embodiment can be appropriately combined with any other embodiment. Symbol Explanation

[0356] 10: Power supply system, 11: Power supply unit, 12: Power receiving unit, 20: Transceiver circuit, 21: Antenna circuit, 22: Rectifier circuit, 23: Charging circuit, 24: Control circuit, 25: Switching circuit, 26: Delay circuit, 27: Antenna circuit, 30: Battery, 40: Sensor, 50: Timer, 101: Receiving circuit, 102: Transmitting circuit, 111: Antenna coil, 112: Capacitor, 113: Antenna coil, 114: Capacitor, 121: Diode, 122: Capacitor, 123: Diode, 131: Regulator, 132: Switch, 141: Judgment circuit, 142: Signal generation circuit, 143: Switching circuit, 150: Buffer circuit, 151: Transistor, 152: Transistor, 153: Transistor, 154: Transistor, 155: Transistor, 156: Transistor, 157: Inverter, 161: Inverter, 171: Antenna coil, 172: Capacitor, 200: Semiconductor device, 210: Storage circuit, 220: Reference storage circuit, 230: Circuit, 240: Circuit, 250: Current source circuit, 801: Transistor, 811: Insulating layer, 812: Insulating layer, 813: Insulating layer, 814: Insulating layer, 815: Insulating layer, 816: Insulating layer, 817: Insulating layer, 818: Insulating layer, 819: Insulating layer, 820: Insulating layer, 821: Metal oxide film, 822: Metal oxide film, 822n: Region, 823: Metal oxide film, 824: Metal oxide film, 830: Oxide layer, 850: Conductive layer, 851: Conductive layer, 852: Conductive layer, 853: Conductive layer, 860: Semiconductor device, 870: Monocrystalline silicon wafer, 871: CMOS layer, 872: Transistor layer, 873: Gate electrode, 874: Electrode, 875: Electrode, 5000: Housing, 5001: Display unit, 5002: Display unit, 5003: Speaker, 5004: LED lamp, 5005: Operation key, 5006: Connection terminal, 5007: Sensor, 5008: Microphone, 5009: Switch, 5010: Infrared port, 5011: Recording medium reading unit, 5012: Support unit, 5013: Headphone, 5014: Antenna, 5015: Shutter button, 5016: Image receiving unit, 5100: Electronic device, 5101: Display unit, 5102: Display unit, 5103: Steering wheel, 5200: Electronic device, 5201: Seat, 5202: Display unit, 5203: Antenna setting unit, 5300: Pacemaker main body, 5301a: Battery, 5301b: Battery, 5302: Lead wire, 5303: Lead wire, 5304: Antenna, 5305: Subclavian vein, 5306: Superior vena cava This application is based on Japanese Patent Application No. 2017-092025 filed with the Japan Patent Office on May 3, 2017, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: a transceiver circuit; and a battery, wherein the transceiver circuit is configured to receive a first electromagnetic wave transmitted by a power supply unit to supply power to the battery and generate a second electromagnetic wave using the power of the battery, the second electromagnetic wave is generated using the power of the battery when the charging of the battery is completed, and the second electromagnetic wave is configured to cancel the first electromagnetic wave.

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