Power switch control circuit, power switch control method, chip and electronic equipment

Abstract

The invention relates to a power switch control circuit, a power switch control method, a chip and electronic equipment, the power switch control circuit comprises a power domain, the power domain comprises P power switch units, and the P power switch units are arranged into Q power switch chains connected in parallel; the control signal input end is used for receiving a control signal and outputting the control signal to the Q power switch chains so as to perform on-off control on the power switch units in the power switch chains; and the Q confirmation signal output ends are used for outputting confirmation signals of the power switch chains, and the confirmation signals are used for representing switching states of the power switch chains. According to the power switch control circuit, the overall opening and closing speed of the power domain can be increased, the power-on and power-off time of the power domain is saved, and whether power-on and power-off of the power domain are completed or not can be judged conveniently.

Description

Technical Field

[0001] This application relates to the technical field of power switch control, and particularly to a power switch control circuit, a power switch control method, a chip, and an electronic device. Background Art

[0002] With the continuous progress of chip technology in electronic devices, the power consumption problem has become increasingly important. The power switch is one of the important means to achieve low-power design. It can independently control the power-on or power-off of the power domains not used inside the chip, effectively saving the power consumption of the chip. Compared with directly controlling an external power switch, the on-chip power switch has a faster control speed and a finer partitioning granularity, and can complete the rapid switching of power domains within the microsecond or even nanosecond level. Although the power switch performs well in power consumption management, its control speed needs to be improved. Summary of the Invention

[0003] This application provides a power switch control circuit, a power switch control method, a chip, and an electronic device. The technical solution of this application is as follows:

[0004] In one aspect, an embodiment of this application provides a power switch control circuit, including:

[0005] A power domain, where the power domain includes P power switch units, and the P power switch units are arranged in Q parallel-connected power switch chains;

[0006] A control signal input terminal, configured to receive a control signal and output the control signal to the Q power switch chains to perform switch control on the power switch units in each power switch chain;

[0007] Q confirmation signal output terminals, configured to output the confirmation signals of each power switch chain, where the confirmation signal is used to represent the switch state of each power switch chain;

[0008] Wherein, P≥Q, and both P and Q are positive integers.

[0009] In another aspect, an embodiment of this application provides a power switch control method, including:

[0010] Receiving a control signal through the control signal input terminal and outputting the control signal to Q parallel-connected power switch chains formed by P power switch units in the power domain to perform switch control on the power switch units in each power switch chain;

[0011] Outputting the corresponding confirmation signals of each power switch chain through the Q confirmation signal output terminals, where the confirmation signal is used to represent the switch state of each power switch chain;

[0012] Wherein, P≥Q, and both P and Q are positive integers.

[0013] In another embodiment of the present application, a chip is proposed, and the chip includes the above-mentioned power switch control circuit.

[0014] In another embodiment of the present application, an electronic device is proposed, including: a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the above-mentioned power switch control method is implemented.

[0015] In another embodiment of the present application, a non-transitory computer-readable storage medium is proposed, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned power switch control method is implemented.

[0016] For the power switch control circuit, chip, electronic device, and power switch control method proposed in the present application, P power switch units in a power domain including P power switch units are arranged into Q parallel-connected power switch chains. A control signal is received through a control signal input terminal and output to the Q power switch chains to perform on-off control on the power switch units in each power switch chain. Confirmation signals of each power switch chain are output through Q confirmation signal output terminals, and the confirmation signals are used to represent the on-off states of the respective power switch chains. Thus, the power switch control circuit of the present application can accelerate the overall turn-on and turn-off speeds of the power domain, save the power-on and power-off times of the power domain, and facilitate determining whether the power domain has completed power-on and power-off.

[0017] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above-mentioned and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description of the embodiments in conjunction with the drawings, where:

[0019] Figure 1 is a schematic diagram of a power switch control circuit provided by an embodiment of the present application;

[0020] Figure 2 is a schematic diagram of another power switch control circuit provided by an embodiment of the present application;

[0021] Figure 3 is a schematic diagram of another power switch control circuit provided by an embodiment of the present application;

[0022] Figure 4 is a schematic diagram of another power switch control circuit provided by an embodiment of the present application;

[0023] Figure 5 Flow chart of a power switch control method provided by an embodiment of the present application;

[0024] Figure 6 Schematic structural diagram of an electronic device provided by an embodiment of the present application;

[0025] Figure 7 Schematic structural diagram of a chip provided by an embodiment of the present application. Detailed implementation manners

[0026] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present application, and should not be construed as a limitation to the present application.

[0027] The power switch control circuit, power switch control method, chip and electronic device according to the embodiments of the present application will be described below with reference to the accompanying drawings.

[0028] Figure 1 Schematic diagram of a power switch control circuit provided by an embodiment of the present application.

[0029] As Figure 1 shown, the power switch control circuit according to the embodiment of the present application includes:

[0030] Power domain 100, the power domain 100 includes P power switch units 101, each power switch unit 101 has a control input terminal and an acknowledgement output terminal, forming a set of control signal - acknowledgement signal (Ctrl - Ack signal), and the P power switch units 101 are arranged in Q parallel - connected power switch chains (taking 4 in the figure as an example);

[0031] Control signal input terminal, the control signal input terminal is used to receive the control signal Ctrl and output the control signal Ctrl to the Q power switch chains to perform switch control on the power switch units 101 in each power switch chain;

[0032] Q acknowledgement signal output terminals, each power switch chain is correspondingly provided with an acknowledgement signal output terminal, and the acknowledgement signal output terminal is used to output the acknowledgement signal Ack (such as Ack1 - Ack4) of each power switch chain, and the acknowledgement signal Ack is used to represent the switch state of each power switch chain;

[0033] Among them, P≥Q, and both P and Q are positive integers.

[0034] In the embodiments of the present application, in the Q parallel-connected power switch chains, the number of power switch units 101 on each power switch chain may be different, and the specific number is set according to actual requirements. This flexibility enables the power switch chains to be optimally configured according to different application scenarios.

[0035] The power switch units 101 in each power switch chain are connected and controlled in the following manner:

[0036] The first power switch unit 101: The control input terminal of the first power switch unit 101 in each power switch chain receives the global control signal Ctrl and performs a switching operation according to the control signal Ctrl. The confirmation output terminal of the first power switch unit 101 outputs a confirmation signal Ack, which is used to represent the state of the first power switch unit 101.

[0037] Subsequent power switch units: The control input terminal of the second power switch unit 101 uses the confirmation signal Ack output by the confirmation output terminal of the previous power switch unit as its own control signal Ctrl and performs a switching operation according to the control signal Ctrl. The confirmation output terminal of the second power switch unit 101 outputs a confirmation signal Ack, which is used to represent the state of the second power switch unit 101. And so on, until the last power switch unit 101 outputs the confirmation signal Ack.

[0038] Thus, the power switch control circuit of the embodiments of the present application, through the parallel-connected power switch chain method, enables all power switch chains to receive the same control signal Ctrl simultaneously, thereby realizing a fast power-on operation or power-off operation of the power domain; through this cascaded control mechanism, the power switch units on the power switch chains can perform switching operations in sequence, ensuring that the switching states of each power switch chain can be accurately fed back, enhancing the reliability and stability of the system; the number of power switch chains and the number of power switch units on each power switch chain can be flexibly configured according to actual requirements to adapt to different chip design requirements; by independently controlling the power-on or power-off of the unused power domains inside the chip, the chip power consumption is effectively saved, meeting the dual requirements of low power consumption and high performance of electronic devices.

[0039] In multiple parallel-connected power switch chains, all power switch chains receiving the same control signal Ctrl simultaneously may cause multiple power switch units 101 to turn on or off almost simultaneously. This synchronous operation may cause a large transient current change, which may in turn lead to problems such as voltage fluctuations and current spikes, affecting the stability and reliability of the system. For this reason, the present application inserts a delay unit 102 in front of the first power switch unit 101 of each power switch chain to delay the turn-on and turn-off times of each power switch chain, thereby smoothing the transient current change.

[0040] As Figure 2 shown, the power switch control circuit further includes: Q delay units 102, each delay unit 102 is connected to the first power switch unit 101 in each power switch chain. The delay unit 102 is configured to delay and output the control signal Ctrl to the first power switch unit 101 in the corresponding connected power switch chain after receiving the control signal Ctrl. Among them, the first power switch unit 101 in the power switch chain refers to the first power switch unit 101 counted from the control signal input end. In other words, the first power switch unit 101 in the power switch chain is the first power switch unit 101 directly connected to the control signal input end and is located closest to the control signal input end in the power switch chain. By setting the extension unit, the opening and closing times of different power switch chains can be staggered, and the transient current change can be smoothed.

[0041] In the embodiments of the present application, each delay unit 102 includes at least one delay subunit. The delay subunit is used to provide a fixed or configurable delay time, usually at the nanosecond level. However, in an actual chip, due to process, voltage, and temperature variations, the delay time will also fluctuate. Among them,

[0042] the number of delay subunits connected in series in each delay unit 102 is determined according to the total delay time required for the corresponding power switch chain.

[0043] Example: The delay subunit provides a fixed delay time.

[0044] The first power switch chain: includes 10 power switch units 101, the delay time of each delay subunit is 3 nanoseconds, and the required total delay time is 18 nanoseconds. Then, 6 delay subunits need to be connected in series in the corresponding delay unit 102.

[0045] The second power switch chain: includes 8 power switch units 101, the delay time of each delay subunit is 3 nanoseconds, and the required total delay time is 15 nanoseconds. Then, 5 delay subunits need to be connected in series in the corresponding delay unit 102.

[0046] The third power switch chain: includes 6 power switch units 101, the delay time of each delay subunit is 3 nanoseconds, and the required total delay time is 12 nanoseconds. Then, 4 delay subunits need to be connected in series in the corresponding delay unit 102.

[0047] The fourth power switch chain: includes 5 power switch units 101, the delay time of each delay subunit is 3 nanoseconds, and the required total delay time is 9 nanoseconds. Then, 3 delay subunits need to be connected in series in the corresponding delay unit 102.

[0048] In a plurality of parallel-connected power switch chains, each power switch chain usually has an acknowledgement signal Ack to indicate whether the power switch chain has been successfully powered on or off. However, when it is necessary to support any number of power switch chains, if each power switch chain has an independent acknowledgement signal Ack output, it will complicate the external interface and increase the design difficulty. To solve this problem, a logic gate circuit 103 can be used outside the power domain 100. The logic gate circuit 103 aggregates the acknowledgement signals of all power switch chains into a unified power-on acknowledgement signal Ack_pu and a power-off acknowledgement signal Ack_pd, thereby simplifying the external interface design.

[0049] As Figure 3 shown, the power switch control circuit further includes:

[0050] The logic gate circuit 103 is configured to receive Q acknowledgement signals Ack and generate corresponding power-on acknowledgement signal Ack_pu and / or power-off acknowledgement signal Ack_pd according to the Q acknowledgement signals Ack. In this way, no matter how many power switch chains there are in the system, the external interface only needs to process two unified acknowledgement signals Ack, greatly simplifying the external function design.

[0051] As an example, as Figure 3 shown, the logic gate circuit 103 includes: an AND gate 103a and an OR gate 103b.

[0052] Among them, the AND gate 103a has Q first input terminals and one first output terminal. The AND gate 103a is configured to generate and output the power-on acknowledgement signal Ack_pu through the first output terminal according to the Q acknowledgement signals Ack input by the Q first input terminals. The working principle of the AND gate 103a is that only when all Q acknowledgement signals Ack are at a high level (i.e., all power switch chains are successfully powered on), the AND gate 103a will output a high-level power-on acknowledgement signal Ack_pu. If any one of the acknowledgement signals is at a low level, the AND gate 103a outputs a low level, indicating that at least one power switch chain fails to be successfully powered on.

[0053] The OR gate 103b has Q second input terminals and one second output terminal. The OR gate 103b is configured to generate and output the power-off acknowledgement signal Ack_pd through the second output terminal according to the Q acknowledgement signals Ack input by the Q second input terminals. The working principle of the OR gate 103b is that as long as any one of the acknowledgement signals Ack is at a high level (i.e., any one of the power switch chains is not powered off), the OR gate 103b will output a high-level power-off acknowledgement signal Ack_pd. If all the acknowledgement signals are at a low level, the OR gate 103b outputs a low level, indicating that all power switch chains are powered off.

[0054] For example:

[0055] The first power switch chain: confirmation signal Ack_1;

[0056] The second power switch chain: confirmation signal Ack_2;

[0057] The third power switch chain: confirmation signal Ack_3;

[0058] ……;

[0059] The Qth power switch chain: confirmation signal Ack_Q.

[0060] Suppose there are Q power switch chains, and the confirmation signals Ack for each power switch chain are Ack_1, Ack_2,..., Ack_Q respectively. The working process of the logic gate circuit 103 is as follows:

[0061] Power-on confirmation signal Ack_pu: When and only when all the confirmation signals Ack_1, Ack_2,..., Ack_Q are at high level, the AND gate 103a outputs a high-level power-on confirmation signal Ack_pu, indicating that all power switch chains have been successfully powered on. If any one of the confirmation signals Ack_1, Ack_2,..., Ack_Q is at low level, the AND gate 103a outputs a low-level power-on confirmation signal Ack_pu, indicating that at least one power switch chain fails to be successfully powered on.

[0062] Power-off confirmation signal Ack_pd: When and only when all the confirmation signals Ack_1, Ack_2,..., Ack_Q are at low level, the OR gate 103b outputs a low-level power-off confirmation signal Ack_pd, indicating that all power switch chains have been successfully powered off. If any one of the confirmation signals Ack_1, Ack_2,..., Ack_Q is at high level, the OR gate 103b will output a high-level power-off confirmation signal Ack_pd, indicating that at least one power switch chain fails to be successfully powered off.

[0063] For Figure 3 the circuit structure shown, an additional selector 104 can be added to complete the selection of the power-on and power-off confirmation signals. As Figure 4 shown, the power switch control circuit further includes:

[0064] Selector 104. Selector 104 (marked with MUX is selector 104) has a third input terminal (marked with sel as the third input terminal), a fourth input terminal (marked with 1 as the fourth input terminal), a fifth input terminal (marked with 0 as the fifth input terminal), and a third output terminal. Selector 104 is used to select one of the power-on confirmation signal Ack_pu received from the fourth input terminal and the power-off confirmation signal Ack_pd received from the fifth input terminal as the target signal according to the control signal Ctrl received from the third input terminal, and output the target signal through the third output terminal.

[0065] In the embodiment of the present application, selector 104 selects an appropriate confirmation signal as the target signal output according to the state of the received control signal Ctrl. The specific working principle is as follows:

[0066] When the control signal Ctrl is a high-level signal, selector 104 determines the power-on confirmation signal Ack_pu as the target signal and outputs the target signal through the third output terminal. This indicates that the battery domain 100 is currently in a power-on operation, and selector 104 will output a signal indicating whether all power switch chains have been successfully powered on.

[0067] When the control signal Ctrl is a low-level signal, the power-off confirmation signal Ack_pd is determined as the target signal and output through the third output terminal. This indicates that the power domain 100 is currently in a power-off operation, and selector 104 will output a signal indicating that at least one power switch chain has been powered off.

[0068] In the embodiment of the present application, by introducing selector 104, selector 104 can select the power-on confirmation signal Ack_pu or the power-off confirmation signal Ack_pd as the target signal output according to the state of the control signal Ctrl, effectively simplifying the external interface design and improving the flexibility and reliability of the system.

[0069] In order to ensure that the timing check of the input signals of selector 104 can effectively prevent unexpected signal glitches, correctly respond to the control signal Ctrl and select an appropriate confirmation signal Ack, meeting certain timing requirements. In the embodiment of the present application, the signals input to the third input terminal, the fourth input terminal, and the fifth input terminal of the selector meet the following conditions:

[0070] The sum of the path time of the control signal Ctrl to the third input terminal and the set time is less than the minimum of the path times of the control signal Ctrl to the third input terminal and the fourth input terminal respectively;

[0071] The absolute value of the difference between the path times of the control signal Ctrl to the third input terminal and the fourth input terminal respectively is less than the set time.

[0072] In the embodiments of the present application, path time is used to characterize the transmission time of a signal from the source to the target input terminal; setup time is used to characterize a preset time threshold to ensure the synchronization of signal transmission;

[0073] Time constraint condition 1:

[0074] The sum of the path time of the control signal Ctrl to the third input terminal and the setup time is less than the minimum of the path times of the control signal Ctrl to the third input terminal and the fourth input terminal respectively. This means that the time when the control signal Ctrl arrives at the third input terminal of the selector plus the setup time must be less than the minimum of the path times of the control signal Ctrl to the third input terminal and the fourth input terminal respectively. This can ensure that after the selector 104 receives the control signal Ctrl, there is enough time to wait for the power-on confirmation signal Ack_pu to arrive, thus avoiding misjudgment.

[0075] Time constraint condition 2:

[0076] The absolute value of the difference between the path times of the control signal Ctrl to the third input terminal and the fourth input terminal respectively is less than the setup time. This means that the difference in the path times of the control signal Ctrl to the third input terminal and the fourth input terminal cannot exceed the setup time. This can ensure that the timing relationship between the control signal and the power-on confirmation signal remains consistent, avoiding misoperation of the selector 104 caused by different path delays.

[0077] In summary, for the power switch control circuit proposed in the present application, P power switch units in a power domain including P power switch units are arranged into Q parallel-connected power switch chains, a control signal is received through a control signal input terminal and output to the Q power switch chains to control the on / off of the power switch units in each power switch chain, and confirmation signals of each power switch chain are output through Q confirmation signal output terminals, and the confirmation signal is used to characterize the on / off state of each power switch chain. The power switch control circuit of the embodiments of the present application is relatively simple to implement, without additional registers and dedicated clocks. By arranging P power switch units into Q parallel-connected power switch chains, all power switch chains receive the same control signal, thereby accelerating the overall turn-on and turn-off speed of the power domain, saving the power-on and power-off time of the power domain, and each power switch chain correspondingly outputs a confirmation signal, thereby facilitating the judgment of whether the power domain has completed power-on and power-off.

[0078] Figure 5 It is a flowchart of a power switch control method provided by the embodiments of the present application.

[0079] As Figure 5 shown, the power switch control method of the embodiments of the present application includes:

[0080] S1. Receive a control signal through a control signal input terminal, and output the control signal to Q parallel-connected power switch chains formed by P power switch units in a power domain, so as to perform on / off control on the power switch units in each power switch chain.

[0081] S2. Output confirmation signals corresponding to each power switch chain through Q confirmation signal output terminals, where the confirmation signals are used to represent the on / off states of the respective power switch chains. Here, P≥Q, and both P and Q are positive integers.

[0082] It should be noted that for details not disclosed in the power switch control method according to the embodiments of the present application, please refer to the details disclosed in the power switch control circuit according to the embodiments of the present application, which will not be elaborated here.

[0083] According to the power switch control method of the embodiments of the present application, a control signal is received through a control signal input terminal, and the control signal is output to Q parallel-connected power switch chains formed by P power switch units in a power domain, so as to perform on / off control on the power switch units in each power switch chain, and confirmation signals corresponding to each power switch chain are output through Q confirmation signal output terminals, where the confirmation signals are used to represent the on / off states of the respective power switch chains. This method can accelerate the overall turn-on and turn-off speeds of the power domain, save the power domain power-on and power-off times, and facilitate determining whether the power domain has completed power-on and power-off.

[0084] To implement the above embodiments, the present application also proposes an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the method described in the foregoing method embodiments is implemented.

[0085] Figure 6 It is a schematic structural diagram of an electronic device provided by the embodiments of the present application. For example, the electronic device 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0086] Refer to Figure 6 , the electronic device 800 may include one or more of the following components: a processing component 802, a memory 804, a power component 806, a multimedia component 808, an audio component 810, an input / output (I / O) interface 812, a sensor component 814, and a communication component 816.

[0087] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, telephone calls, data communication, camera operations, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the above methods. In addition, the processing component 802 may include one or more modules to facilitate the interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate the interaction between the multimedia component 808 and the processing component 802.

[0088] The memory 804 is configured to store various types of data to support the operation of the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disks, or optical disks.

[0089] The power component 806 provides power to the various components of the electronic device 800. The power component 806 may include a power management system, one or more power sources, and other components associated with generating, managing, and distributing power for the electronic device 800.

[0090] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can not only sense the boundaries of touch or swipe actions, but also detect the duration and pressure associated with the touch or swipe operations. In some embodiments, the multimedia component 808 includes a front camera and / or a rear camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each of the front camera and the rear camera can be a fixed optical lens system or have focal length and optical zoom capabilities.

[0091] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC) that is configured to receive external audio signals when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, the audio component 810 further includes a speaker for outputting audio signals.

[0092] The I / O interface 812 provides an interface between the processing component 802 and a peripheral interface module, and the peripheral interface module may be a keyboard, a click wheel, buttons, etc. These buttons may include, but are not limited to: a home button, a volume button, a power button, and a lock button.

[0093] The sensor component 814 includes one or more sensors for providing an assessment of various aspects of the status of the electronic device 800. For example, the sensor component 814 can detect the on / off state of the electronic device 800, the relative positioning of components, such as the display and keypad of the electronic device 800. The sensor component 814 can also detect a change in the position of the electronic device 800 or a component of the electronic device 800, the presence or absence of user contact with the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and the temperature change of the electronic device 800. The sensor component 814 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor component 814 can also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor component 814 can further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0094] The communication component 816 is configured to facilitate communication between the electronic device 800 and other devices in a wired or wireless manner. The electronic device 800 can access a wireless network based on communication standards, such as WiFi, 4G, or 5G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 further includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0095] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components for performing the above method.

[0096] To implement the above embodiments, the present application also proposes a chip, including: a power switch control circuit.

[0097] In one embodiment, the chip provided by the present application including the power switch control circuit is configured to execute the above power switch control method.

[0098] Figure 7 It is a schematic structural diagram of a chip provided by an embodiment of the present application. Reference may be made to Figure 7 the schematic structural diagram of the chip 1100 shown, but not limited thereto.

[0099] The chip 1100 includes a power switch control circuit 1101, and the power switch control circuit 1101 is configured to execute the above power switch control method.

[0100] In some embodiments, as Figure 7 shown, the chip 1100 further includes one or more interface circuits 1102. Optionally, the interface circuit 1102 is connected to the memory 1103. The interface circuit 1102 may be used to receive signals from the memory 1103 or other devices, and the interface circuit 1102 may be used to send signals to the memory 1103 or other devices. For example, the interface circuit 1102 may read the instructions stored in the memory 1103 and send the instructions to the power switch control circuit 1101.

[0101] In some embodiments, the interface circuit 1102 executes at least one of the communication steps such as sending and / or receiving in the above method, and the power switch control circuit 1101 executes other steps.

[0102] In some embodiments, terms such as interface circuit, interface, transceiver pin, transceiver, etc. may be used interchangeably.

[0103] In some embodiments, as Figure 7 shown, the chip 1100 further includes one or more memories 1103 for storing instructions. Optionally, all or part of the memories 1103 may be outside the chip 1100.

[0104] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, and the above instructions can be executed by a processor 820 of an electronic device 800 to complete the above method. For example, the non-transitory computer-readable storage medium may be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0105] To implement the above embodiment, the present application also proposes a non-transitory computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the above method is implemented.

[0106] To implement the above embodiment, the present application also proposes a computer program product, including a computer program, and when the computer program is executed by a processor, the above method is implemented.

[0107] In the description of this specification, the description with reference to terms such as "an embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0108] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present application, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0109] Any process or method description shown in a flowchart or described in other ways herein can be understood as representing a module, segment, or part of code including one or more executable instructions for implementing a customized logic function or process, and the scope of the preferred embodiments of the present application includes additional implementations, where the functions may be executed in a manner that is not shown or discussed, including in a substantially simultaneous manner according to the involved functions or in a reverse order, which should be understood by those skilled in the art to which the embodiments of the present application belong.

[0110] The logic and / or steps represented in the flowchart or otherwise described herein can, for example, be considered as a definable sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in conjunction with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: electrical connection parts with one or more wirings (electronic devices), portable computer disk cartridges (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber devices, and portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other appropriate processing as necessary, and then stored in a computer memory.

[0111] It should be understood that various parts of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0112] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the methods of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0113] In addition, each functional unit in various embodiments of the present application may be integrated into a processing module, may exist physically alone for each unit, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0114] The above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disc, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

[0115] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present application. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include well-known common general knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present application are pointed out by the appended claims.

[0116] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.

Claims

1. A power switch control circuit, characterized in that: include: A power domain, the power domain comprising P power switch units, the P power switch units being arranged into Q parallel-connected power switch chains; A control signal input terminal, used for receiving a control signal and outputting the control signal to the Q power switch chains, so as to perform switch control on the power switch units in each of the power switch chains; Q confirmation signal output terminals, used to output confirmation signals of each of the power switch chains, wherein the confirmation signals are used to represent the switch states of each of the power switch chains; Wherein, P≥Q, P and Q are both positive integers.

2. The power switch control circuit according to claim 1, characterized in that: The power switch control circuit also includes: Q delay units, each of which is connected to the first power switch unit in each power switch chain, and is used for delaying the control signal and outputting it to the first power switch unit in the correspondingly connected power switch chain after receiving the control signal; The first power switch unit in the power switch chain refers to the first power switch unit counted from the control signal input terminal.

3. The power switch control circuit according to claim 2, characterized in that: Each of the delay units includes at least one delay subunit, and the delay subunit is used to provide a fixed or configurable delay time; wherein, The number of the delay sub-units connected in series in each of the delay units is determined according to the total delay time required by the corresponding power switch chain.

4. The power switch control circuit according to claim 2, characterized in that: The power switch control circuit also includes: A logic gate circuit, wherein the logic gate circuit is used to receive the Q confirmation signals and generate a corresponding power-on confirmation signal and / or a power-off confirmation signal according to the Q confirmation signals.

5. The power switch control circuit according to claim 4, characterized in that: The logic gate circuit comprises: An AND gate, the AND gate having Q first input terminals and a first output terminal, the AND gate being used for generating, according to the Q confirmation signals inputted from the Q first input terminals, the power-on confirmation signal being outputted through the first output terminal; An OR gate having Q second input terminals and a second output terminal, and the OR gate is used to generate and output the power-off confirmation signal through the second output terminal according to the Q confirmation signals inputted from the Q second input terminals.

6. The power switch control circuit according to claim 4 or 5, characterized in that: The power switch control circuit also includes: A selector, the selector having a third input terminal, a fourth input terminal, a fifth input terminal and a third output terminal, the selector being used to select one of the power-on confirmation signal received at the fourth input terminal and the power-off confirmation signal received at the fifth input terminal as a target signal according to the control signal received at the third input terminal, and output the target signal through the third output terminal.

7. The power switch control circuit according to claim 6, characterized in that: The selector is used to: In response to the control signal being a high level signal, determining the power-on confirmation signal as the target signal; In response to the control signal being a low level signal, the power-off confirmation signal is determined as the target signal.

8. The power switch control circuit according to claim 6, characterized in that: The signals inputted by the third input terminal, the fourth input terminal and the fifth input terminal of the selector meet the following time constraints: The sum of the path time from the control signal to the third input terminal and the setting time is less than the minimum value of the path time from the control signal to the third input terminal and the fourth input terminal respectively; An absolute value of a difference between path times of the control signal to the third input terminal and the fourth input terminal is smaller than the set time.

9. A power switch control method, characterized in that: include: receiving a control signal through a control signal input terminal, and outputting the control signal to Q parallel-connected power switch chains formed by P power switch units in a power domain, so as to perform switch control on the power switch units in each of the power switch chains; Outputting confirmation signals corresponding to each of the power switch chains through Q confirmation signal output terminals, wherein the confirmation signals are used to represent the switch states of each of the power switch chains; Wherein, P≥Q, P and Q are both positive integers.

10. A chip, characterized in that: The chip includes a power switch control circuit as claimed in any one of claims 1 to 8.

11. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method according to claim 9 is implemented.

12. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to claim 9 is implemented.

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