Hardware protection method for preventing large-power switching damage of electronic switch

Abstract

The invention discloses a hardware protection method for preventing high-power switching damage of an electronic switch, and belongs to the field of communication product design. According to the invention, a special pulse control signal is designed through a programmable logic device (FPGA), the pulse width of the signal is at least greater than the sum of on-off time of a power amplifier (module or chip) in a radio frequency front end, and a certain margin is reserved, so that a window opening latch with enough width is obtained after a delay circuit and logic operation; the electronic switch switching signal in the window can be sent to the electronic switch driver, and the electronic switch switching signal outside the window cannot be sent to the electronic switch driver. The method is a system-level hardware high-reliability reinforcement scheme for avoiding the electronic switch with high-power switching, and can ensure that the electronic switch cannot execute switching when the power amplifier outputs high power. The method has high universality, solves the problems of weight and power consumption of the radio frequency front end of the integrated high-power base station especially in the design of high-integration-level products such as deep space exploration, and has wide application prospects.

Description

Technical Field

[0001] The present invention belongs to the field of communication product design, and relates to a hardware protection method for preventing damage caused by high-power switching of an electronic switch. Background Art

[0002] For the construction requirements of extraterrestrial bases in China's future deep space exploration missions, it is necessary to build an extraterrestrial mobile networking communication system to realize the development of communication "base stations" in the system. Limited by rocket carrying capacity, etc., the specific implementation of the project needs to face extremely harsh factors such as weight and power consumption. At this time, how to adopt a "base station" product solution that is as miniaturized and lightweight as possible has become the most core factor restricting the success or failure of the mission.

[0003] For typical scenarios of such tasks, it is necessary to consider establishing a communication network that supports about 3 - 10 communication nodes to support the transmission of services such as pictures, voice, remote control and telemetry, and images of devices within the network. Traditional ground base station solutions, from 3G, 4G, LTE to 5G, have formed a mature architecture that is serialized, productized and continuously evolving after years of continuous optimization. In order to increase the coverage distance as much as possible, ground base stations usually need to be equipped with large power amplification devices. At the same time, in order to take into account 360-degree omnidirectional coverage and meet the communication requirements of multiple sectors, each antenna needs to be equipped with an independent radio frequency front-end RRU and an independent digital processing board to achieve coverage of multiple cells. This solution usually requires the support of an entire ground computer room and consumes more than a thousand watts of power. Whether in terms of weight or power consumption, it far exceeds the engineering cost that can be borne by space missions.

[0004] In order to solve the development of communication base station equipment in China's current extraterrestrial base construction, this paper innovatively proposes a hardware protection method for preventing damage caused by high-power switching of an electronic switch, aiming to ensure the reliability of switching with an electronic switch in a high-power system to achieve the goal of meeting aerospace engineering application requirements. The design of this solution can effectively ensure the realization of a lightweight base station, adopt the method with the smallest aerospace engineering cost, and prevent the electronic switch, which is a single point in the system, from being in the working condition of switching with high-power signals due to abnormal software functions, thus avoiding the problem of burnout. It greatly improves the system reliability and avoids situations that seriously affect the mission execution. Summary of the Invention

[0005] The present invention provides a hardware protection method for preventing damage caused by high-power switching of an electronic switch, aiming to ensure the reliability of switching implemented by the electronic switch in a high-power system, so as to achieve the goal of meeting aerospace engineering application requirements; the design of this solution can effectively ensure the realization of a lightweight base station, and prevent the electronic switch, which is a single point in the system, from being in the working condition of switching with high-power signals due to abnormal software functions, thus avoiding the problem of burnout, greatly improving the system reliability, and preventing the occurrence of situations that seriously affect the mission execution.

[0006] The technical solution adopted by the present invention includes:

[0007] A hardware protection method for preventing damage caused by high-power switching of an electronic switch, used to control the electronic switch and the power amplifier, includes the following steps:

[0008] Taking the sum of the maximum switch switching delay, the maximum power amplifier switch time, and the window opening time as the pulse width of the original control signal to generate the original control signal;

[0009] The original control signal is processed by delay to obtain an output signal 1 and a delayed signal;

[0010] The delay time of the output signal 1 is the maximum switch switching delay, which is used for the control of the power amplifier switch;

[0011] The delay time of the delayed signal is the sum of the maximum switch switching delay and the maximum power amplifier switch time. The original control signal and the delayed signal are subjected to an AND operation to obtain an output signal 2, and the output signal 2 controls the on / off of the electronic switch through a latch.

[0012] Optionally, the method for obtaining the maximum switch switching delay, the maximum power amplifier switch time, and the window opening time includes:

[0013] Obtain the maximum switch switching delay △t1, the maximum power amplifier turn-off time △t_RFoff, and the maximum power amplifier turn-on time △t_RFon related to the hardware, which can be known by testing the indicators of the switch and the power amplifier; the maximum power amplifier switch time △t2 is the larger value of the maximum power amplifier turn-off time △t_RFoff and the maximum power amplifier turn-on time △t_RFon, that is, △t2 = max[△t_RFoff, △t_RFon];

[0014] The window opening time considers the minimum processing clock cycle of the processor, and 1us is selected as a typical value.

[0015] Optionally, the method for generating the original control signal is:

[0016] Calculate the pulse width of the original control signal: △t = △t1 + △t2 + △t3;

[0017] Among them, △t1 is the maximum switch switching delay; △t2 is the maximum power amplifier switch time; △t3 is the window opening time, with a typical value of 1 us.

[0018] The original control signal is at a high level within the pulse width and at a low level outside the pulse width.

[0019] Optionally, the specific methods for obtaining the output signal 1 and the delay signal are as follows:

[0020] For the original control signal, through a delay circuit, a delay of △t1 time is achieved to obtain the output signal 1, which realizes the switching operation of the external power amplifier;

[0021] For the original control signal, through a delay circuit, a delay of △t1 + △t2 time is achieved to obtain the delay signal, which is used for subsequent operations.

[0022] Optionally, the specific method for the output signal 2 to control the on / off of the electronic switch through a latch includes:

[0023] The output signal of the latch allows the signal within the window to pass through normally, and the signal outside the window cannot pass through. The specific method is as follows:

[0024] The original control signal and the delay signal are respectively sent to the "AND gate"; the output of the "AND gate" is the output signal 2; the output signal 2 is sent to the latch to realize the on / off control of the control signal of the electronic switch.

[0025] Optionally, the processor generates an original pulse signal, the switch control signal is the output signal 1, and the switch control signal after being latched by the latch is the output signal 2. The start of time slot M represents the start of the Mth time slot; the start of time slot N represents the start of the Nth time slot, the maximum switch switching delay △t1 and the maximum power amplifier switch time △t2. The specific control process includes:

[0026] When the switching opportunity occurs within the window where the output signal 2 is at a high level, normal switching can be achieved. When the "switch control signal" falls within the latch control window S_LE, at this time, the "switch control signal" can pass through the latch normally, and the "switch control signal after being latched" can effectively control the electronic switch. At this time, more than △t2 time has passed since the power amplifier was turned off, and the output power of the power amplifier has decreased to 0, and the electronic switch can achieve a safe switch; at the same time, a protection time of more than △t1 is reserved for the electronic switch to ensure that the switch is completed before the power amplifier is turned on;

[0027] Similarly, at the starting time N of a time slot, when the "switch control signal" falls within the latch control window S_LE, the "switch control signal" can pass through the latch normally at this time. The "switch control signal after latching" effectively controls the electronic switch. At this time, more than Δt2 time has passed since the power amplifier was turned off, and the output power of the power amplifier has decreased to 0, so the electronic switch can achieve a safe switch. At the same time, the electronic switch switch has a protection time of more than Δt1 reserved to ensure that the switch is completed before the power amplifier is turned on.

[0028] Optionally, the processor generates an original pulse signal. The switch control signal is output signal 1, and the switch control signal after being latched by the latch is output signal 2. The starting time M of a time slot represents the start of the Mth time slot; the starting time N of a time slot represents the start of the Nth time slot, the maximum switch switching delay Δt1 and the maximum power amplifier switching time Δt2. The specific control process includes: The specific control process includes:

[0029] When the switching opportunity is earlier than the window when output signal 2 is at a high level, the switch can be achieved, but it needs to be delayed until the window arrives to take effect; when the switching opportunity is later than the window when output signal 2 is at a high level, the switch cannot be achieved. At the starting time M of a time slot, when the "switch control signal" is earlier than the latch control window S_LE, the "switch control signal after latching" needs to wait until the latch control window S_LE is high valid before the "switch control signal" can pass through effectively. At this time, Δt2 time has passed since the power amplifier was turned off, and the output power of the power amplifier has decreased to 0, so the electronic switch can achieve a safe switch. At the same time, the electronic switch switch has a protection time of more than Δt1 reserved to ensure that the switch is completed before the power amplifier is turned on;

[0030] Similarly, at the starting time N of a time slot, when the "switch control signal" is later than the latch control window S_LE, the "switch control signal" cannot pass through the latch normally at this time, and the switch cannot be switched at this time, effectively protecting the electronic switch.

[0031] Optionally, the processor generates an original pulse signal. The switch control signal is output signal 1, and the switch control signal after being latched by the latch is output signal 2. The starting time M of a time slot represents the start of the Mth time slot; the starting time N of a time slot represents the start of the Nth time slot, the maximum switch switching delay Δt1 and the maximum power amplifier switching time Δt2. The specific control process includes:

[0032] When the switching timing is exactly at the trailing edge of the window where the output signal 2 is high, the switching can be achieved immediately. At the start time M of the time slot, when the "switch control signal" is later than the latch control window S_LE, the most extreme case is that it is pulled high at the last position of the latch control window S_LE but has not been pulled low yet. At this time, it can be intuitively seen that △t1 = △t_SWITCH; at this time, the "switch control signal" can pass through the latch normally, and the "switched control signal after latching" effectively controls the electronic switch. At this time, △t2 time has passed since the power amplifier was turned off, and the output power of the power amplifier has decreased to 0, and the electronic switch realizes a safe switch; at the same time, the electronic switch switch reserves a protection time of △t1 to ensure that the switch is completed before the power amplifier is turned on;

[0033] Similarly, at the start time N of the time slot, when the "switch control signal" is much earlier than the latch control window S_LE, at this time, the "switched control signal after latching" needs to wait until the latch control window S_LE is high-effective to make the "switch control signal" pass effectively. △t2 time has passed since the power amplifier was turned off, and the output power of the power amplifier has decreased to 0, and the electronic switch can realize a safe switch; at the same time, the electronic switch switch reserves a protection time exceeding △t1 to ensure that the switch is completed before the power amplifier is turned on and ensure safety.

[0034] The advantages of the present invention compared with the prior art are as follows:

[0035] (1) The present invention can solve the problem that when designing the communication "base station" in the construction of extraterrestrial bases for deep space exploration, due to the requirement of ultra-high integration, a radio frequency architecture that places the electronic switch at the end stage of the power amplifier to reduce system overhead is likely to cause the electronic switch to be burned due to high-power switching.

[0036] (2) This method is based on a pulse control signal designed by a programmable logic device (FPGA). After a series of delays and logical operations, the required electronic switch drive window and power amplifier switch control signal are obtained, so that the electronic switch control signal within the window can pass and the electronic switch control signal outside the window cannot pass.

[0037] (3) This method is a hardware reinforcement solution. When the software control is abnormal, it can ensure that the electronic switch is always switched without power.

[0038] (4) By adopting this method, on the premise of meeting the high reliability requirements of aerospace, it can support the product architecture using electronic switches at the end stage of the power amplifier, and is especially suitable for reducing the complexity of the design of ultra-high integration products in deep space exploration, with strong versatility. Brief Description of the Drawings

[0039] The accompanying drawings are used to provide a further understanding of the present disclosure and form a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure, but do not constitute a limitation to the present disclosure. In the accompanying drawings:

[0040] Figure 1 It is a specific implementation architecture of the hardware protection method for preventing damage caused by high-power switching of electronic switches in the present invention;

[0041] Figure 2 The present invention generates the required original control signals with the aid of an external processor;

[0042] Figure 3 The present invention delays the operation process;

[0043] Figure 4 It is the relative relationship among the original control signal, output signal 1, and output signal 2 in the present invention;

[0044] Figure 5 It is the effective switching that occurs within the window in the present invention;

[0045] Figure 6 It is the delayed switching that occurs before the window and the invalid switching that occurs after the window in the present invention;

[0046] Figure 7 It is the origin of the delay of △t1 under the window limit switching in the present invention. Specific Embodiments

[0047] The following detailed description of the present invention is exemplary and does not limit the scope of implementation of the present invention. Based on the embodiments in the present invention, for those of ordinary skill in the art, all improvements that do not involve creative efforts should be regarded as the protection scope of the present invention.

[0048] The delay circuit used in the present invention mainly refers to the hardware circuit built on the circuit board for achieving the expected delay time for a certain input signal. This delay circuit only realizes the delay of the signal and should not change the characteristics of the signal (such as signal period, steepness of signal edges, etc.) as much as possible.

[0049] The "AND gate" used in the present invention belongs to a simple logic digital circuit in integrated circuits and realizes the logical operation of multi-input AND. The specific form is not limited as long as it satisfies the logical AND operation.

[0050] The "latch" used in the present invention belongs to a simple logic digital circuit in integrated circuits and realizes the normal output or prohibited output of the input signal according to the control requirements.

[0051] The hardware protection method for preventing damage caused by high-power switching of electronic switches in the present invention is a hardware high-reliability reinforcement solution, which can ensure that when the power amplifier outputs high power, the electronic switch cannot be switched. It has strong versatility. Especially in the design of high-integration products such as deep space exploration, it solves the problems of the weight and power consumption of the radio frequency front end of the integrated high-power base station, and has broad application prospects.

[0052] In the present invention, a dedicated pulse control signal is designed through a programmable logic device (FPGA). The pulse width of this signal should be at least greater than the sum of the turn-on and turn-off times of the power amplifier (module or chip) in the radio frequency front end, and a certain margin is reserved to ensure that after passing through the delay circuit and logical operation, a window with sufficient width is obtained to enable the latch, so that the electronic switch switching signal within the window can be sent to the electronic switch driver, and the electronic switch switching signal outside the window cannot be sent to the electronic switch driver. This method is a hardware high-reliability reinforcement solution at the system level, which can ensure that when the power amplifier outputs high power, the electronic switch cannot perform switching. This method has strong versatility. Especially in the design of high-integration products such as deep space exploration, it solves the problems of the weight and power consumption of the radio frequency front end of the integrated high-power base station, and has broad application prospects.

[0053] The technical solution of the present invention is: design a pulse control signal through a programmable logic device (FPGA). The pulse width of this signal is at least greater than twice the switching time of the power amplifier in the radio frequency front end, so as to ensure that after passing through the subsequent delay circuit and logical operation, the required electronic switch drive window and power amplifier switch control signal are obtained, and the electronic switch control signal within the window can be sent to the electronic switch drive circuit, and the electronic switch control signal outside the window cannot be sent to the electronic switch drive circuit. This method is a hardware high-reliability reinforcement solution, which can ensure that when the power amplifier outputs high power, the electronic switch cannot be switched.

[0054] The hardware protection method for preventing damage caused by high-power switching of electronic switches in the present invention includes the following steps:

[0055] (1) Generate an original control signal according to the maximum switching delay, the maximum power amplifier switching time, and the window opening time;

[0056] (2) Obtain output signal 1 (for power amplifier switching) and a delay signal (for AND operation) according to the original control signal;

[0057] (3) Perform an AND operation on the original control signal and the delay signal to obtain output signal 2, which is used for the enable pin of the latch, so that the signal within the window can pass normally, and the signal outside the window cannot pass.

[0058] The maximum switch switching delay and the maximum power amplifier switch time are common known information in communication devices and can be obtained in advance through testing. The window opening time needs to consider the minimum processing clock cycle of the processor. Generally, the processing rate of common processors is higher than 1 MHz. Usually, 1 us is selected as the typical value here, with a certain margin reserved.

[0059] In step (1), according to the maximum switch switching delay, the maximum power amplifier switch time, and the window opening time, an original control signal is generated, including:

[0060] (1) Obtain the original signal pulse width: △t = △t1 + △t2 + △t3; where, △t1 is the maximum switch switching delay; △t2 is the maximum power amplifier switch time; △t3 is the window opening time, with a typical value of 1 us.

[0061] (2) The inside of the original signal pulse width is at a high level, and the outside of the pulse width is at a low level; the time of the rising edge of this pulse relative to the rising edge of the next pulse depends on the electronic switch switching interval.

[0062] In an actual system, the electronic switch switching interval depends on the respective system requirements and is different for each system. However, this time is not the focus of this patent. It only requires performing the operations required by this patent at each electronic switch switching moment.

[0063] In step (2), an output signal 1 (for power amplifier switching) and a delay signal (for AND operation) are obtained according to the original control signal, including:

[0064] (1) For the original control signal, through a hardware delay circuit, a delay of △t1 time is achieved, and the obtained signal is used for output, that is, output signal 1. This signal realizes the switching operation of the external power amplifier;

[0065] (2) For the original control signal, through a hardware delay circuit, a delay of △t1 + △t2 time is achieved, and the obtained signal is used for output, that is, the delay signal. This signal is used for subsequent AND operation;

[0066] In step (3) mentioned above, an AND operation is performed on the original control signal and the delay signal to obtain an output signal 2, including:

[0067] (1) The original control signal and the delay signal obtained in step (2) are respectively sent to an "AND gate" (hardware circuit);

[0068] (2) The output of the "AND gate" (hardware circuit) is the output signal 2;

[0069] (3) The output signal 2 is sent to the enable pin (LE) of a latch (hardware circuit) to realize the on / off control of the electronic switch control signal (such as switch main alternative gating, antenna gating control 1, antenna gating control 2, etc.).

[0070] The specific implementation steps of the present invention are carried out in accordance with Figure 1 as follows. Figure 1 In , the functions of each component are as follows: The "processor" is used to generate the original control signal; "level conversion" is mainly used to shape the signal to ensure a steep edge transition. "Delay △t1" delays the signal for a delay time of △t1; "Delay △t1 + △t2" delays the signal for a delay time of △t1 + △t2; "AND gate" is a logic gate circuit that performs an AND operation on the signals; "Latch" inputs the signal after the AND operation to the control terminal LE pin of the latch. When LE is high, the output signal changes with the state of the input signal; when LE is low, the output signal remains unchanged. The "interface transmission chip" can be directly externally connected to the interface transmission chip through the output signal of the latch, thereby realizing single-ended to differential output. The reason for selecting differential output is to improve the anti-interference ability, and any single-ended to differential chip can be used. The present invention mainly involves Figure 1 the original control signal generated by the "processor" in , "level conversion", "delay △t1", "delay △t1 + △t2", "AND gate", and "latch" in . The rest are not mandatory requirements and are for reference examples.

[0071] Step 1: Generate the original control signal

[0072] Generate the original control signal S_ctrl, and this signal refers to Figure 2 , pulse width: △t = △t1 + △t2 + △t3; where, △t1 is the maximum switch switching delay; △t2 is the maximum power amplifier switch time; △t3 is the window opening time, with a typical value of 1 us.

[0073] Step 2: Obtain output signal 1 (for power amplifier switching) and the delayed signal (for AND operation) based on the original control signal (input signal).

[0074] Obtain output signal 1: S_output, that is, perform a circuit delay on the input signal S_ctrl for a delay time of △t1 = △t_SWITCH;

[0075] Obtain the delayed signal S_delay, that is, perform a circuit delay on the input signal S_ctrl for a delay time of △t1 + △t2;

[0076] Step 3: Perform an AND operation on the input signal S_ctrl and the delayed signal S_delay to obtain the latch control window S_LE.

[0077] Step 4: Drive the enable pin LE of the latch through S_LE, so that the signals within the high-level window of S_LE can pass through normally, and the signals outside the high-level window cannot pass through.

[0078] The following is an implementation example of "A Hardware Protection Method for Preventing Damage Caused by High-Power Switching of Electronic Switches" according to the above process to obtain a reinforced circuit.

[0079] Input: The maximum power amplifier shutdown time △t_RFoff = 3 us, the maximum power amplifier startup time △t_RFon = 3.5 us, and the electronic switch switching time △t_SWITCH = 2 us.

[0080] According to the above design method, the following can be obtained:

[0081] △t1 = △t_SWITCH = 2 us,

[0082] △t2 = max[△t_RFoff, t_RFon] = 3.5 us,

[0083] △t3 can be considered according to a typical value of 1 us (usually, it is not recommended that △t3 < 1 us, and at the same time, the larger △t3 is, the greater the overhead).

[0084] The pulse width of the final required pulse control signal is △t = △t1 + △t2 + △t3 = 6.5 us.

[0085] Therefore, it is necessary to generate an original control signal with a pulse width of 6.5 us, and the pulse period depends on the electronic switch switching period, such as 1 ms.

[0086] The original pulse signal is as Figure 2 , and the original control signal is a high-low level signal generated by the "processor". Among them, the duration of each high level is generated according to Step 1, and the time interval between the previous high level and the next high level is a time slot (the minimum time unit for communication transmission).

[0087] The delay operation process is as Figure 3 , and the original control signal is a high-low level signal generated by the "processor". This signal passes through a delay circuit and is delayed by △t1 time to obtain the "output signal 1" for power amplifier switch control; the output signal 1 is further delayed by △t2 to obtain the "delayed signal", and the original control signal and the "delayed signal" are subjected to a logical AND operation to obtain the "output signal 2" for the LE pin of the latch.

[0088] The relative relationship between the original pulse signal (input signal, generated by the processor), the power amplifier switch signal (output signal 1), and the latch control signal (output signal 2) obtained after delay and AND operation is as Figure 4, the start of time slot M represents the start of the Mth time slot (the minimum time unit for communication transmission); similarly, the start of time slot N represents the start of the Nth time slot. As shown in the figure, the original control signal is generated by the processor according to the first specific implementation step of the present invention. The output signal 1 is the signal obtained by delaying the original control signal by △t1 according to step two, and the delayed signal is the signal obtained by delaying the original control signal by △t1 + △t2. The output signal 2 is the latch control window S_LE obtained according to step three. The signal delayed by △t1 is used for the power amplifier switch. When the power amplifier is turned off, the actual signal power gradually decreases, and the time is about △t_RFoff = 3us in the figure. When the power amplifier is turned on, the actual signal power gradually rises, and the time is about △t_RFon = 3.5us in the figure. The "switch control signal" is used to switch the backend electronic switch, which can be generated by the "processor" in this article or by any circuit that can generate it.

[0089] When the switching opportunity occurs within the window where the latch control signal (output signal 2) is high level, normal switching can be achieved, such as Figure 5 , at the start of time slot M, when the "switch control signal" falls within the latch control window S_LE, at this time the "switch control signal" can pass through the latch normally, and the "switch control signal after latching" can effectively control the electronic switch. At this time, more than △t2 time has passed since the power amplifier was turned off, and the power amplifier output power has decreased to 0. Therefore, the electronic switch can achieve safe switching. At the same time, the electronic switch switching reserves a protection time of more than △t1, which can ensure that the switching is completed before the power amplifier is turned on, ensuring safety. Similarly, at the start of time slot N, when the "switch control signal" falls within the latch control window S_LE, at this time the "switch control signal" can pass through the latch normally, and the "switch control signal after latching" can effectively control the electronic switch. At this time, more than △t2 time has passed since the power amplifier was turned off, and the power amplifier output power has decreased to 0. Therefore, the electronic switch can achieve safe switching. At the same time, the electronic switch switching reserves a protection time of more than △t1, which can ensure that the switching is completed before the power amplifier is turned on, ensuring safety.

[0090] When the switching opportunity is earlier than the window where the latch control signal (output signal 2) is high level, switching can be achieved, but it needs to be delayed until the window arrives to take effect; when the switching opportunity is later than the window where the latch control signal (output signal 2) is high level, switching cannot be achieved, such as Figure 6, at the starting moment M of the time slot, when the "switch control signal" is ahead of the latch control window S_LE, at this time the "latched switch control signal" needs to wait until the latch control window S_LE is high-effective to enable the "switch control signal" to pass effectively. The time of △t2 has passed since the power amplifier was turned off, and the output power of the power amplifier has decreased to 0. Therefore, the electronic switch can achieve a safe switch. At the same time, the electronic switch switch has a protection time exceeding △t1 reserved, which can ensure that the switch is completed before the power amplifier is turned on to ensure safety. Similarly, at the starting moment N of the time slot, when the "switch control signal" is later than the latch control window S_LE, at this time the "switch control signal" cannot pass through the latch normally, and the "latched switch control signal" cannot effectively transmit the "switch control signal". That is, the switch cannot be switched at this time, but the electronic switch can be effectively protected.

[0091] When the switching opportunity is exactly at the trailing edge of the window where the latch control signal (output signal 2) is at a high level, the switch can be immediately realized. At this time, it can be intuitively seen that △t1 = △t_SWITCH, as Figure 7 , at the starting moment M of the time slot, when the "switch control signal" is later than the latch control window S_LE, the most extreme case is that it is close to the last raised position (trailing edge) of the latch control window S_LE but has not been pulled low. At this time, it can be intuitively seen that △t1 = △t_SWITCH. At this time, the "switch control signal" can pass through the latch normally, and the "latched switch control signal" can effectively control the electronic switch. And the time of △t2 has passed since the power amplifier was turned off, and the output power of the power amplifier has decreased to 0. Therefore, the electronic switch can achieve a safe switch. At the same time, the electronic switch switch has a protection time of △t1 reserved, which can ensure that the switch is completed before the power amplifier is turned on to ensure safety. Similarly, at the starting moment N of the time slot, when the "switch control signal" is much earlier than the latch control window S_LE, at this time the "latched switch control signal" needs to wait until the latch control window S_LE is high-effective to enable the "switch control signal" to pass effectively. The time of △t2 has passed since the power amplifier was turned off, and the output power of the power amplifier has decreased to 0. Therefore, the electronic switch can achieve a safe switch. At the same time, the electronic switch switch has a protection time exceeding △t1 reserved, which can ensure that the switch is completed before the power amplifier is turned on to ensure safety.

[0092] The content not described in detail in the specification of the present invention belongs to the well-known technology of those skilled in the art.

[0093] Although the present invention has been described in detail above with general descriptions and specific embodiments, based on the present invention, some modifications or improvements can be made, which are obvious to those skilled in the art. Therefore, these modifications or improvements made without departing from the spirit of the present invention all fall within the protection scope of the present invention.

Claims

1. A hardware protection method for preventing damage caused by high-power switching of an electronic switch, characterized in that: Used to control electronic switches and power amplifiers, including the following steps: The original control signal is generated by taking the sum of the maximum switch switching delay, the maximum power amplifier switching time and the window opening time as the pulse width of the original control signal; The original control signal is processed by delay to obtain output signal 1 and delayed signal; The delay time of output signal 1 is the maximum switch switching delay, which is used to control the power amplifier switch; The delay time of the delayed signal is the sum of the maximum switch switching delay and the maximum power amplifier switching time. The original control signal and the delayed signal are ANDed to obtain the output signal 2. The output signal 2 controls the on and off of the electronic switch through the latch.

2. The hardware protection method for preventing damage caused by high-power switching of electronic switches according to claim 1, characterized in that: The method for obtaining the maximum switch switching delay, the maximum power amplifier switching time and the window opening time includes: The maximum switch delay △t1, the maximum power amplifier off time △t_RFoff and the maximum power amplifier on time △t_RFon related to the hardware are obtained by testing the indicators of the switch and the power amplifier; the maximum power amplifier switch time △t2 is the larger value of the maximum power amplifier off time △t_RFoff and the maximum power amplifier on time △t_RFon, that is, △t2 = max[△t_RFoff,△t_RFon]; The window opening time takes into account the minimum processing clock cycle of the processor and selects 1us as the typical value.

3. The hardware protection method for preventing damage caused by high-power switching of an electronic switch according to claim 1 or 2, characterized in that: The method for generating the original control signal is: Calculate the pulse width of the original control signal: △t=△t1+△t2+△t3; Among them, △t1 is the maximum switch switching delay; △t2 is the maximum power amplifier switching time; △t3 is the window opening time, with a typical value of 1us. The original control signal is at a high level within the pulse width and at a low level outside the pulse width.

4. The hardware protection method for preventing damage caused by high-power switching of electronic switches according to claim 3 is characterized in that: The specific method of obtaining the output signal 1 and the delayed signal is: The original control signal is delayed by a time of △t1 through a delay circuit to obtain an output signal 1, which realizes the switching operation of the external power amplifier; The original control signal is delayed by a time of △t1+△t2 through a delay circuit to obtain a delayed signal, which is used for subsequent AND operations.

5. The hardware protection method for preventing damage caused by high-power switching of an electronic switch according to claim 1 or 2, characterized in that: The output signal 2 controls the on / off of the electronic switch through the latch, specifically including: The output signal of the latch allows the signal within the window to pass normally, and the signal outside the window cannot pass. The specific method is: The original control signal and the delayed signal are sent to the "AND gate" respectively; the output of the "AND gate" is the output signal 2; the output signal 2 is sent to the latch to realize the on-off control of the electronic switch control signal.

6. The hardware protection method for preventing damage caused by high-power switching of an electronic switch according to claim 1 or 2, characterized in that: The processor generates an original pulse signal, the switch control signal is output signal 1, the switch control signal after being latched by the latch is output signal 2, the time slot start M indicates the start of the Mth time slot; the time slot start N indicates the start of the Nth time slot, the maximum switch switching delay △t1 and the maximum power amplifier switching time △t2, the specific control process includes: When the switching timing occurs within the window where the output signal 2 is at a high level, normal switching can be achieved. When the "switch control signal" falls within the latch control window S_LE, the "switch control signal" can pass through the latch normally, and the "switch control signal after latching" can effectively control the electronic switch. At this time, more than △t2 time has passed since the power amplifier was turned off, and the output power of the power amplifier has been reduced to 0, so the electronic switch can achieve safe switching. At the same time, the electronic switch switching reserves a protection time of more than △t1 to ensure that the switching is completed before the power amplifier is turned on. Similarly, at the start time N of the time slot, when the "switch control signal" falls within the latch control window S_LE, the "switch control signal" can pass through the latch normally, and the "switch control signal after latching" effectively controls the electronic switch. At this time, more than △t2 time has passed since the power amplifier was turned off, and the output power of the power amplifier is reduced to 0, so the electronic switch can be switched safely. At the same time, the electronic switch switching reserves a protection time of more than △t1 to ensure that the switching is completed before the power amplifier is turned on.

7. The hardware protection method for preventing damage caused by high-power switching of an electronic switch according to claim 1 or 2, characterized in that: The processor generates an original pulse signal, the switch control signal is output signal 1, the switch control signal after being latched by the latch is output signal 2, the time slot start M indicates the start of the Mth time slot; the time slot start N indicates the start of the Nth time slot, the maximum switch switching delay △t1 and the maximum power amplifier switching time △t2, the specific control process includes: the specific control process includes: When the switching timing is ahead of the window where the output signal 2 is at a high level, the switching can be realized, but it needs to be delayed until the window arrives to take effect; when the switching timing is later than the window where the output signal 2 is at a high level, the switching cannot be realized. At the start time M of the time slot, when the "switch control signal" is ahead of the latch control window S_LE, the "switch control signal after latching" needs to wait until the latch control window S_LE is high and effective before the "switch control signal" can pass effectively. △t2 time has passed since the power amplifier was turned off, and the output power of the power amplifier has been reduced to 0. The electronic switch can realize safe switching; at the same time, the electronic switch switching reserves a protection time of more than △t1 to ensure that the switching is completed before the power amplifier is turned on; Similarly, at the start time N of the time slot, when the "switch control signal" is later than the latch control window S_LE, the "switch control signal" cannot pass through the latch normally, and the "switch control signal after latching" cannot be switched at this time, thus achieving effective protection for the electronic switch.

8. The hardware protection method for preventing damage caused by high-power switching of an electronic switch according to claim 1 or 2, characterized in that: The processor generates an original pulse signal, the switch control signal is output signal 1, the switch control signal after being latched by the latch is output signal 2, the time slot start M indicates the start of the Mth time slot; the time slot start N indicates the start of the Nth time slot, the maximum switch switching delay △t1 and the maximum power amplifier switching time △t2, the specific control process includes: When the switching timing happens to be at the trailing edge of the window where the output signal 2 is at a high level, the switching can be realized immediately. At the start time M of the time slot, when the "switch control signal" is later than the latch control window S_LE, the most extreme case is that it is close to the last high position of the latch control window S_LE, but has not yet been pulled down. At this time, it can be intuitively seen that △t1 = △t_SWITCH; at this time, the "switch control signal" can pass through the latch normally, and the "switch control signal after latching" effectively realizes the control of the electronic switch. At this time, △t2 time has passed since the power amplifier was turned off, and the output power of the power amplifier has been reduced to 0, and the electronic switch has realized safe switching; at the same time, the electronic switch switching reserves a protection time of △t1 to ensure that the switching is completed before the power amplifier is turned on; Similarly, at the start of the time slot N, when the "switch control signal" is much earlier than the latch control window S_LE, the "switch control signal after latching" needs to wait until the latch control window S_LE is high and effective before the "switch control signal" can pass effectively. △t2 time has passed since the power amplifier was turned off, and the output power of the power amplifier has been reduced to 0, and the electronic switch can achieve safe switching; at the same time, the electronic switch switching reserves a protection time of more than △t1 to ensure that the switching is completed before the power amplifier is turned on, ensuring safety.

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