A method and system for long-distance interconnection of a memory and a storage controller based on optical communication

Abstract

The present application relates to the field of computer storage and optical communication technology, and discloses a memory and storage controller long-distance interconnection method and system based on optical communication. The method encapsulates high-speed, medium-speed and low-speed signals between the memory and the storage controller, converts them into optical signals, and then transmits them over optical fibers. The receiving end converts the optical signals back into electrical signals through an optical module, and restores the original signals. The system includes a sending end and a receiving end, both of which contain special circuit modules and optical modules to complete signal encapsulation, conversion, transmission and recovery. The present application can effectively solve the problem of low-speed signals that cannot be directly transmitted over optical fibers, is suitable for various types and protocols of memories, and supports long-distance memory interconnection in cross-cabinet distributed storage and large-scale computing environments. The system has a long transmission distance, strong anti-interference ability, can reduce hardware complexity and cost, and improve the reliability and expandability of the system.

Description

Technical Field

[0001] This invention relates to the fields of computer storage systems and optical communication technology, and in particular to a method and system for long-distance interconnection between a memory and a memory controller based on optical communication. Background Technology

[0002] With the rapid development of technologies such as big data, cloud computing, and artificial intelligence, the demand for memory capacity and bandwidth in data centers and high-performance computing systems continues to rise. Traditionally, memory and storage controllers are connected via parallel buses or short-distance cables, typically located on the same motherboard or in adjacent positions. While this approach can meet system requirements within a typical server chassis, it exposes many technical challenges when long-distance layouts or cross-rack expansion of memory sharing are needed.

[0003] First, with the increase in transmission rates, the cable connection between the memory and the memory controller faces high impedance requirements. Long-distance cable transmission inevitably leads to severe signal attenuation and crosstalk, resulting in degraded memory performance and reduced system reliability. Second, in addition to high-speed and medium-speed signals, traditional interfaces also need to transmit low-speed signals. These low-speed signals are easily interfered with during long-distance transmission and may even be impossible to transmit directly through optical fiber. Finally, although the transmission distance of electrical signals can be extended using timers or repeaters, these methods are still limited by the transmission rate and significantly increase hardware costs and system design complexity. Therefore, overcoming the bottlenecks of traditional cable transmission methods and achieving efficient long-distance communication between different types of memory and memory controllers has become a key challenge for improving the performance of data centers and high-performance computing systems. Summary of the Invention

[0004] This invention provides a method and system for long-distance interconnection between a memory and a memory controller based on optical communication. It aims to solve the bottleneck problems of traditional cable transmission methods in long-distance, high-speed, medium-speed, and low-speed signal transmission. By applying optical modules, it achieves efficient, reliable, and low-cost long-distance interconnection between the memory and the memory controller. This invention not only meets the needs of long-distance transmission but also ensures compatibility with different memory types and protocols, improving the system's reliability, stability, and scalability.

[0005] This invention provides a method for long-distance interconnection between a memory and a memory controller based on optical communication. This method encapsulates the signals between the memory and the memory controller, converts them into optical signals, and transmits them over long distances via optical fiber, overcoming the problems of signal attenuation, crosstalk, and low-speed signal transmission difficulties inherent in long-distance cable transmission. The specific steps are as follows:

[0006] Step S100: Receive high-speed, medium-speed, and low-speed signals. At the transmitting end, first receive high-speed, medium-speed, and low-speed signals from between the memory and the memory controller. High-speed and medium-speed signals include, but are not limited to, data transmission signals and address control signals, while low-speed signals include, but are not limited to, reset signals and I / O signals. 2 C signal, training-related control signals, calibration pins, detection and testing, etc.

[0007] Step S200: Signal encapsulation. High-speed, medium-speed, and low-speed signals are encapsulated using a dedicated circuit module. The encapsulation steps include:

[0008] Step S210: Collect parallel signals and converge high-speed, medium-speed, and low-speed signals.

[0009] Step S220: Form a preliminary data frame structure according to the preset bit width and bandwidth parameters;

[0010] Step S230: Insert a low-speed signal into the data frame structure to ensure that the low-speed signal is encapsulated together with the high-speed and medium-speed signals;

[0011] Step S240: Add frame header, frame trailer and checksum information to ensure data integrity and reliability;

[0012] Step S250: Perform serial-to-parallel conversion and encoding operations to convert parallel data into a serial stream, ready for long-distance transmission via optical fiber.

[0013] Step S300: Optical Signal Conversion and Transmission: The encapsulated signal is converted into an optical signal by an optical module and transmitted to the receiving end via optical fiber. Single-mode or multi-mode optical fiber is used for optical signal transmission to accommodate different distance requirements.

[0014] Step S400: Reception and Resolution: At the receiving end, the optical signal is converted back into an electrical signal by the optical module. The receiving end resolves and recovers the high-speed, medium-speed, and low-speed signals using a dedicated circuit module, and outputs them to the memory or memory controller. The resolution steps include:

[0015] Step S410: Extract the low-speed signal and distribute it to the management port or functional module;

[0016] Step S420: Map the remaining main payload portion back to the target data bit width and output it to the memory or memory controller;

[0017] Step S500: Ensure that the low-speed signal is synchronized with the high-speed and medium-speed signals in terms of timing to ensure the correctness of data interaction.

[0018] This invention also provides a long-distance interconnection system between a memory and a memory controller based on optical communication. The system includes a transmitter and a receiver, and mainly comprises the following components:

[0019] The sending end includes:

[0020] The first dedicated circuit module is used to encapsulate high-speed signals, medium-speed signals and low-speed signals to meet the input requirements of the first optical module and the provisions of the communication protocol, and to convert the encapsulated signals into electrical signals that conform to a preset format.

[0021] The first optical module is used to convert the encapsulated electrical signal into an optical signal and transmit it through optical fiber.

[0022] The receiving end includes:

[0023] The second optical module is used to receive optical signals and convert them into electrical signals;

[0024] The second dedicated circuit module is used to analyze the converted electrical signal to meet the requirements of the communication protocol and storage system, and to output the high-speed signal, medium-speed signal and low-speed signal to the memory or storage controller after recovery.

[0025] To accommodate different types of memory and protocol requirements, the first dedicated circuit module (transmitter) and the second dedicated circuit module (receiver) can adopt a variety of programmable or customized hardware structures, including but not limited to field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), digital signal processors (DSPs), or other types of application-specific integrated circuits (ICs).

[0026] Among them, FPGAs are suitable for rapid adaptation and field upgrades to different memory protocols, ASICs offer higher integration and energy efficiency, DSPs provide efficient digital signal processing capabilities, and other types of dedicated ICs, such as custom SoCs (System on Chip), can be optimized for specific application requirements. These hardware modules can be used independently or in combination to meet the requirements of different memory architectures and optimize power consumption, performance, and transmission efficiency.

[0027] This invention transmits signals via optical fiber, which can significantly increase the transmission distance and avoid the problems of signal attenuation and crosstalk in long-distance transmission of traditional cable transmission. It supports transmission distances from a few meters to tens of meters or even longer.

[0028] The system of this invention supports various types of memory to meet different computing environments and storage needs, including but not limited to DDR (Double Data Rate), HBM (High Bandwidth Memory), LPDDR (Low Power DDR), GDDR (Graphics DDR), NAND flash memory, phase-change memory (PCM), resistive random access memory (RRAM), and ferroelectric memory (FeRAM). These memory types cover the main storage needs in high-performance computing, data centers, embedded devices, and consumer electronics.

[0029] The system can be adapted to the characteristics of different memories. For example, DDR and LPDDR are widely used in servers and mobile devices, with high requirements for timing and bus protocols; HBM and GDDR are suitable for high-performance computing, artificial intelligence, and graphics processing, with high bandwidth requirements; NAND and PCM are used in non-volatile memory scenarios, requiring additional error correction coding (ECC) and protocol management; RRAM and FeRAM are new storage technologies suitable for low-power, high-endurance storage needs. Through dedicated circuitry, the system enables different types of memories to efficiently transmit data under the long-distance storage interconnect architecture of this invention.

[0030] The system of this invention supports multiple memory data transfer protocols to achieve flexible interconnection between the memory and the memory controller. The system can be configured for different protocols, adapting to different types of memory and controllers, and ensuring the reliability and compatibility of signal transmission.

[0031] This invention employs dedicated circuit modules and optical modules, reducing reliance on high-cost timers, repeaters, and other equipment in traditional transmission systems, thereby lowering system complexity and hardware costs. Simultaneously, optical communication possesses strong anti-interference capabilities, ensuring the stability and reliability of data transmission.

[0032] This invention supports massively parallel computing and distributed storage environments, and is suitable for various application scenarios such as data centers, server racks, and cross-rack distributed storage. The system can also add or adjust signal transmission channels as needed, supporting the expansion and optimization of high-performance computing systems.

[0033] This invention ensures the integrity and reliability of data during optical signal transmission by adding check information (such as CRC or ECC) to the data frame, thus avoiding data loss and transmission errors.

[0034] In summary, this invention provides a method and system for long-distance interconnection between a memory and a memory controller based on optical communication, which has significant technical advantages and can effectively improve the long-distance communication performance between the memory and the memory controller, providing strong support for the efficient operation of data centers and high-performance computing systems. Attached Figure Description

[0035] Figure 1 This is a flowchart of the long-distance interconnection method between a memory and a memory controller based on optical communication as described in this invention;

[0036] Figure 2 This is a structural diagram of the long-distance interconnection system between a memory and a memory controller based on optical communication as described in this invention;

[0037] Figure 3 This is a schematic diagram of the transmitter end of a long-distance interconnection system between a memory and a memory controller based on optical communication in an embodiment of the present invention. The design shown represents only one feasible solution.

[0038] Figure 4 This is a schematic diagram of the receiver of a long-distance interconnection system between a memory and a memory controller based on optical communication in an embodiment of the present invention. The design shown represents only one feasible solution.

[0039] Figure 5 This is a schematic diagram illustrating a specific implementation of long-distance interconnection between a memory and a memory controller based on optical communication in an embodiment of the present invention. It shows an example using DDR memory, and the design shown represents only one feasible solution. Detailed Implementation

[0040] To make the objectives and technical solutions of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. The specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0041] Example

[0042] This invention achieves long-distance fiber optic transmission of high-speed, medium-speed, and low-speed signals by uniformly encapsulating and converting them into optical signals at the transmitting end, and then restoring the optical signals to their original electrical signals at the receiving end. This solution fully leverages the advantages of optical fiber in terms of long distance, high bandwidth, and low attenuation, solving the bottleneck problems of high loss, high interference, and the difficulty of long-distance transmission of low-speed signals in traditional cables.

[0043] See Figure 1 The long-distance interconnection method between a memory and a memory controller based on optical communication provided in this embodiment mainly includes the following steps:

[0044] Step S100: Receive high-speed, medium-speed, and low-speed signals at the transmitting end.

[0045] Between the memory and the memory controller, there are typically numerous high-speed and medium-speed signals, as well as several low-speed management and control signals. High-speed and medium-speed signals include, but are not limited to, the memory's data lines and address control lines; low-speed signals include, but are not limited to, reset signals, I / O signals, etc. 2 C signal, training-related control signals, calibration pin, detection and testing, and other management signals.

[0046] Step S200: Encapsulate the high-speed, medium-speed, and low-speed signals into a signal to be transmitted.

[0047] Using dedicated circuit modules (such as FPGAs, ASICs, or DSPs), the received high-speed, medium-speed, and low-speed signals are uniformly processed and encapsulated to form data frames that can be transmitted through optical fibers. This encapsulation process includes:

[0048] Step S210: Collect parallel signals.

[0049] High-speed, medium-speed, and low-speed signals from different parallel buses or parallel ports are collected and aggregated to form a unified signal data stream.

[0050] Step S220: Form a preliminary data frame structure.

[0051] Based on preset bit width, bandwidth, and protocol requirements (such as DDR, HBM, LPDDR, etc.), high-speed, medium-speed data, and low-speed management information are allocated to different fields of the data frame.

[0052] Step S230: Insert a low-speed signal.

[0053] In the data frame structure, specific time slots or fields are allocated to low-speed signals to ensure that low-speed, medium-speed, and high-speed signals are encapsulated and transmitted together, so as to ensure the timing correlation of management commands and data.

[0054] Step S240: Add frame header, frame trailer and check information.

[0055] Identifiers (frame header / frame tail) are added to the beginning and end of the data frame to distinguish frame boundaries, and CRC or ECC check information is inserted to ensure the integrity and reliability of data during long-distance transmission.

[0056] Step S250: Serial-to-parallel conversion and encoding.

[0057] The results of the above parallel data encapsulation are then converted from serial to parallel and encoded (e.g., 8B / 10B, 64B / 66B or other encoding methods suitable for high-speed transmission) to output a serial data stream suitable for transmission by the optical module.

[0058] Step S300: Convert the encapsulated signal into an optical signal and transmit it through an optical fiber.

[0059] The serial data stream obtained in step S200 is converted into an optical signal by the optical module (first optical module) at the transmitting end. The optical signal can be transmitted through single-mode or multi-mode fiber according to the application scenario and distance requirements of the system, supporting distances from several meters to tens of meters or even longer.

[0060] Step S400: Convert and parse the optical signal at the receiving end.

[0061] After the optical signal reaches the receiving end, it is converted back into an electrical signal by the receiving end optical module (second optical module), and then the dedicated circuit module (second dedicated circuit module) analyzes and recovers the high-speed signal, medium-speed signal, and low-speed signal. Specifically, this includes:

[0062] Step S410: Extract the low-speed signal and distribute it.

[0063] By parsing the reserved fields or time slots in the data frame, low-speed management and control information is extracted and distributed to the corresponding management ports or functional modules.

[0064] Step S420: Map back to the target data bit width.

[0065] The remaining main payload portion is mapped back to the bit width or protocol format required by the corresponding memory or storage controller and sent to the target module for normal data read and write operations.

[0066] Step S500: Ensure timing synchronization of low-speed and high-speed signals, as well as medium-speed signals.

[0067] Throughout the transmission and parsing process, necessary synchronization markers, timestamps, or protocol handshake mechanisms are added to ensure that low-speed signals, medium-speed signals, and high-speed signals maintain consistency in timing. This prevents mismatches between management commands and data during data reconstruction at the receiving end, thus ensuring stable system operation.

[0068] like Figure 2 As shown, the system consists of a storage controller (400) and a memory (500) forming two remote interconnected ends, with two pairs of transmitting and receiving ends (labeled 100 and 200 respectively) set up between them. The system achieves long-distance transmission of bidirectional high-speed, medium-speed and low-speed signals through optical fiber (labeled 300).

[0069] In the direction from the storage controller to the memory, the storage controller (400) generates high-speed, medium-speed, and low-speed signals. The transmitting end (100) on the storage controller side performs unified encapsulation, encoding, and serial-to-parallel conversion on these signals to generate a serial electrical signal suitable for optical signal transmission. The electrical signal is converted into an optical signal by an optical module and transmitted to the memory side via optical fiber (300). The receiving end (200) on the memory side performs photoelectric conversion, deserialization, decoding, and frame parsing on the received optical signal, restores the original signal, and sends it to the memory (500) to complete write or configuration operations.

[0070] In the memory-to-memory controller direction, the memory (500) generates read data or status management information. These signals are encapsulated and encoded by the transmitter (100) on the memory side, converted into serial electrical signals suitable for optical transmission, and output as optical signals via an internal optical module. The optical signals are transmitted along the optical fiber (300) to the memory controller side. The receiver (200) on the memory controller side completes photoelectric conversion, decoding, deserialization, and data parsing, transmitting the restored high-speed, medium-speed, and low-speed signals to the memory controller (400) for subsequent data processing and control.

[0071] By configuring the hardware logic of the transmitter (100) and receiver (200), compatibility with various memory standards and rate ranges can be achieved. Simplifying the numerous parallel interfaces between the storage controller (400) and the memory (500) into fiber optic links significantly reduces cabling complexity and reliance on repeaters, while also minimizing electromagnetic interference and power consumption. The system can flexibly increase or decrease the number of fiber optic channels, upgrade bandwidth, or be deployed across more distant racks and buildings as needed, enabling large-scale distributed storage and memory sharing in high-performance computing environments.

[0072] The following is combined with Figure 3 and Figure 4 The structural diagrams of the transmitter 100 and receiver 200 in the implementation case are described in detail. Each module and its sub-modules are numbered as follows. The design shown represents only one feasible solution, and other implementation methods are also within the protection scope of this invention.

[0073] The transmitter 100 mainly consists of two parts: a first dedicated circuit module (110) and a first optical module (120).

[0074] The first dedicated circuit module (110) is used to encapsulate high-speed, medium-speed and low-speed signals from the memory and storage controller into signals of a preset format. Its internal structure includes: an interface unit (111) connected to the high-speed and medium-speed data lines, address lines and low-speed management ports of the memory and storage controller, used to receive various signals; a signal encapsulation unit (112) which aggregates and encapsulates the received high-speed, medium-speed and low-speed signals according to a predetermined frame structure, and inserts frame headers, frame tails and CRC / ECC verification information to ensure data integrity; and a parallel-to-serial conversion unit (113) which converts the internally parallel encapsulated data stream into a high-speed serial code stream to adapt to the input interface standard of the optical module.

[0075] The first optical module (120) receives the packaged high-speed serial electrical signal from the first dedicated circuit module (110), converts it into an optical signal, and transmits it over a long distance to the receiving end via optical fiber.

[0076] The receiver 200 mainly consists of two parts: a second optical module (210) and a second dedicated circuit module (220).

[0077] The second optical module (210) is used to convert optical signals transmitted through optical fibers into electrical signals and transmit the converted signals to the second dedicated circuit module.

[0078] The second dedicated circuit module (220) is used to unpack, decode, and restore the electrical signals output by the second optical module (210), thereby recovering the original high-speed, medium-speed, and low-speed signals. Its internal structure includes: a serial-to-parallel conversion unit (221) for decoding and parallelizing the serial data stream output by the second optical module (210) to obtain a complete data frame; a signal restoration unit (222) for restoring the high-speed, medium-speed, and low-speed signals at the time of encapsulation by combining the frame header, frame tail, and verification information; and an interface unit (223) for outputting the restored high-speed, medium-speed, and low-speed signals to the corresponding interface of the memory or storage controller to complete data interaction and management control.

[0079] Through the coordinated work of the above modules, the sending end ( Figure 3 The first dedicated circuit module (110) and the first optical module (120) (as shown) encapsulate and convert various signals from the memory and memory controller into optical signals, and then transmit them to the receiving end via optical fiber. Figure 4(As shown); the second optical module (210) and the second dedicated circuit module (220) at the receiving end are responsible for photoelectric conversion, unpacking, decoding and restoration of the received optical signal, thereby recovering the original high-speed, medium-speed and low-speed signals. This structural design can effectively ensure the integrity and timing synchronization of the signal during long-distance transmission, and is suitable for long-distance interconnection of various high-speed, medium-speed data and low-speed signals.

[0080] In this embodiment, combined with Figure 5 The optical communication-based long-distance interconnection method between the memory and the memory controller proposed in this invention is applied to the DDR protocol. It utilizes an optical module to encapsulate high-speed, medium-speed, and low-speed signals between the memory and the memory controller, and then transmits them over long distances via optical fiber. The specific implementation will describe in detail how to encapsulate the high-speed, medium-speed, and low-speed signals in the DDR protocol together and transmit them via the optical module. The system includes a memory controller (400), a transmitter (100), a receiver (200), an optical fiber (300), and a DDR memory (510). The protocol between the memory controller and the transmitter and receiver is the DFI protocol (600), and the signals between the DDR memory and the transmitter and receiver are DDR physical layer signals (700).

[0081] The transmitting end includes a first dedicated circuit module and a first optical module. The first dedicated circuit module is responsible for receiving high-speed, medium-speed, and low-speed signals output from the storage controller, encapsulating these signals, and adjusting them into electrical signals suitable for transmission by the optical module. These adjustments include, but are not limited to, clock synchronization, level conversion, serial-to-parallel conversion, link training, and equalization compensation. Afterward, the signals are converted into optical signals by the first optical module and transmitted through optical fiber.

[0082] The receiver includes a second dedicated circuit module and a second optical module. The second optical module receives the optical signal and converts it into an electrical signal. Then, the second dedicated circuit module analyzes and recovers the original high-speed, medium-speed, and low-speed signals, and finally transmits the recovered signals to the DDR memory.

[0083] At the transmitting end, high-speed, medium-speed, and low-speed signals are first received from the memory controller. Major high-speed signals include, but are not limited to: DQS (Data Strobe), DQ (Data Transfer Line), DBI (Data Inversion Indication), and ECC (Error Correction Code). Major medium-speed signals include, but are not limited to: CK (Clock Signal), CA (Command Address Bus, including row and column addresses), and PAR (Address Parity Check). Low-speed signals include, but are not limited to: ALERT_n (Error Warning Signal), RESET_n (Reset Signal), CKE (Clock Enable Signal), CS_n (Chip Select Signal), and ODT (On-Chip Termination Signal).

[0084] The operation of DDR memory can be divided into several stages to ensure efficient data transfer and management. The first stage is initialization, which includes power-up initialization to start the device, a reset to clear the state, and a training process to adjust timing and signal integrity. During the address and command transmission stage, DDR selects the target row by activating (ACT) and then executes a read (RD) or write (WR) command to access the data. After entering the data transfer stage, the memory completes the read data transfer or write data transfer and controls the valid data bits through data masking (DM / DQS). To maintain data integrity, DDR performs refresh and precharge operations, including self-refresh (SR), auto refresh (REF), and precharge (PRE), ensuring that data remains stable in the memory cells. DDR also features LowPower Mode to optimize power management, such as Deep Power Down (DPD) to minimize power consumption, Low-Power Self-Refresh (LP-SR) to maintain data in low-power states, and Clock Stop (CK Stop) to pause the clock signal and reduce power consumption. During testing and debugging, DDR supports JTAG / BoundaryScan (IEEE 1149.1 / 1500) for fault detection and Built-In Self-Test (BIST) for self-testing. Finally, DDR's Mode Register Configuration allows setting the Mode Register Set (MRS) to adjust the operating mode, including Precharge Command and On-Die Termination (ODT) configurations to optimize signal quality. These operating states work together to enable DDR memory to achieve high-speed, stable, and efficient performance in various application scenarios.

[0085] These high-speed, medium-speed, and low-speed signals are encapsulated together in all operating states of the DDR. During encapsulation, the signals are aggregated into a data frame structure, which includes: collecting parallel signals to unify high-speed, medium-speed, and low-speed signals; forming a data frame structure by organizing the high-speed, medium-speed, and low-speed signals into a preliminary data frame according to preset bit width and bandwidth parameters; inserting low-speed signals into the data frame structure to ensure that low-speed signals are encapsulated together with high-speed and medium-speed signals; and adding frame headers, frame trailers, and checksum information to ensure data integrity and guarantee signal accuracy during transmission.

[0086] Subsequently, these encapsulated signals are converted from serial to parallel, encoded, and then converted into optical signals by an optical module. After processing including but not limited to clock synchronization, level conversion, serial-to-parallel conversion, link training, and equalization compensation, the signals are transmitted to the receiving end via optical fiber.

[0087] Optical fiber media can operate stably over a range of several meters to tens of meters or even longer, and will not cause significant attenuation or crosstalk to high-speed signals due to external electromagnetic interference, cable impedance mismatch or other factors, making system layout more flexible.

[0088] This invention employs dedicated circuit modules (FPGA, ASIC, DSP, etc.) in conjunction with configurable optical modules, which can easily adapt to various memory protocols such as DDR, HBM, LPDDR, and GDDR and different speed requirements, providing a unified solution for cross-platform and cross-rack distributed storage and large-scale computing.

[0089] Traditional long-distance high-speed cable methods often require multiple timers or repeaters to achieve long-distance transmission, resulting in complex hardware design and high costs. This invention simplifies cabling and repeater requirements, and reduces hardware complexity and overall cost by encapsulating all signals into a single fiber optic channel for transmission.

[0090] In data centers and massively parallel computing systems, the connectivity requirements between racks or boards often change as business expands. The fiber optic connection method of this invention is more flexible, allowing bandwidth and distance to be adjusted according to needs; at the same time, by inserting low-speed signals into data frames, it simplifies the control and monitoring of remote devices and improves system maintainability.

[0091] By adding frame header and frame tail identifiers and CRC / ECC checks to data frames, this invention can promptly detect and correct bit errors during transmission. In addition, by retaining a timing synchronization guarantee mechanism for low-speed signals at the transmission protocol level, the interaction between management commands and high-speed data can be accurately paired at the receiving end, thereby enhancing system reliability.

[0092] This invention is applicable to various scenarios requiring long-distance and high-speed, medium-speed, and low-speed signal synchronous transmission, including but not limited to: storage expansion within or between server racks; when cabling within the same server rack is complex or expansion to adjacent racks is required, long-distance fiber optic transmission can significantly reduce the number of cables and interference; large-scale distributed storage in data centers, where frequent, high-bandwidth interactions are needed between different nodes and the storage cluster in a distributed storage architecture; and high-performance computing (HPC) scenarios, where HPC systems often require extremely high data bandwidth and low latency, while also demanding long-distance transmission and flexible configuration. This invention can encapsulate low-speed signals while maintaining high-speed data transmission, simplifying the connection and control of distributed computing systems.

[0093] As can be seen from the above embodiments and accompanying drawings, the optical communication-based long-distance interconnection method and system for memory and memory controller provided by the present invention can effectively solve many limitations of traditional long-distance cable connections in terms of high bandwidth and low-speed signal transmission, and improve the overall performance of the system in terms of long distance, high speed, low interference, and multi-protocol compatibility. The present invention has broad application prospects and economic value in fields such as big data centers, cloud computing platforms, artificial intelligence training nodes, and high-performance computing systems.

[0094] The above description is merely a preferred embodiment of the present invention and is not intended to limit the technical scope of the present invention. Any equivalent substitutions or modifications made to the technical solutions of the present invention within the spirit and principles of the present invention shall fall within the protection scope of the present invention.

Claims

1. A method for long-distance interconnection between a memory and a memory controller based on optical communication, characterized in that, The method includes the following steps: Step S100: At the transmitting end, receive high-speed signals, medium-speed signals and low-speed signals between the memory and the memory controller; Step S200: Encapsulate the high-speed signal, medium-speed signal, and low-speed signal into a signal to be transmitted, wherein the encapsulation step includes: Step S210: Collect parallel signals and converge high-speed, medium-speed, and low-speed signals. Step S220: Based on the preset bit width and bandwidth parameters, form a preliminary data frame structure; Step S230: Insert a low-speed signal into the data frame structure to ensure that the low-speed signal is encapsulated together with the medium-speed signal and the high-speed signal; Step S240: Add frame header, frame trailer and checksum information to ensure data integrity; Step S300: Convert the encapsulated signal into an optical signal and transmit it to the receiving end via optical fiber; Step S400: At the receiving end, the optical signal is converted back into an electrical signal, and the original high-speed signal, medium-speed signal, and low-speed signal are analyzed. The analysis step includes: Step S410: Extract the low-speed signal and distribute it to the management port or functional module; Step S420: Map the remaining main payload portion back to the target data bit width and output it; Step S500: Ensure that the low-speed signal is synchronized with the medium-speed and high-speed signals in terms of timing, so as to achieve correct management control and data interaction.

2. The method according to claim 1, characterized in that, The encapsulation steps include, but are not limited to, performing serial-to-parallel conversion and encoding operations to convert parallel data into a serial stream and prepare it for long-distance transmission via optical fiber.

3. The method according to claim 1, characterized in that, The high-speed signals and medium-speed signals include, but are not limited to, data transmission signals and address control signals. The low-speed signals include reset signals, I²C signals, training-related control signals, calibration pins, and detection and testing signals.

4. The method according to claim 1, characterized in that, The frame header and frame trailer identifiers are used to distinguish frame boundaries, and the verification information includes, but is not limited to, CRC or ECC verification to ensure the integrity and reliability of data during transmission.

5. The method according to claim 1, characterized in that, The high-speed, medium-speed, and low-speed signals are encapsulated and uncapsulated using dedicated circuit modules, and the optical signals are transmitted using, but not limited to, single-channel optical modules and multi-channel optical modules.

6. The method according to any one of claims 1 to 5, characterized in that, The optical signal is transmitted through single-mode or multimode optical fiber.

7. A long-distance interconnection system for a memory and a memory controller based on optical communication, characterized in that, The system includes a transmitter and a receiver; The transmitting end is used to receive high-speed, medium-speed and low-speed signals between the memory and the memory controller, encapsulate them, convert them into optical signals and output them. The receiving end is used to receive optical signals and convert them back into electrical signals, recovering the original high-speed signal, medium-speed signal and low-speed signal, and outputting them to the memory or memory controller.

8. The system according to claim 7, characterized in that, The sending end includes: The first dedicated circuit module is used to encapsulate high-speed signals, medium-speed signals and low-speed signals to meet the input requirements of the first optical module and the provisions of the communication protocol, and to convert the encapsulated signals into electrical signals that conform to a preset format. The first optical module is used to convert the encapsulated electrical signal into an optical signal and transmit it through optical fiber.

9. The system according to claim 7, characterized in that, The receiving end includes: The second optical module is used to receive optical signals and convert them into electrical signals; The second dedicated circuit module is used to analyze the converted electrical signal to meet the requirements of the communication protocol and storage system, and to output the high-speed, medium-speed and low-speed signals to the memory or storage controller after recovery.

10. The system according to claim 8, characterized in that, The first dedicated circuit module includes, but is not limited to, FPGA, ASIC, digital signal processor (DSP) or other application-specific integrated circuit (IC) to accommodate different types of memory and protocol requirements.

11. The system according to claim 7, characterized in that, The system supports multiple memory types, including but not limited to DDR, HBM, LPDDR, GDDR, NAND, PCM, RRAM, and FeRAM, and is compatible with data transmission protocols of different types.

12. The system according to claim 7, characterized in that, The system supports flexible configuration through different protocols to adapt to signal transmission between different memories and memory controllers.

13. The system according to claim 7, characterized in that, The system is suitable for various application scenarios, including server rack storage, cross-rack distributed storage, data centers, and massively parallel computing, and supports long-distance memory interconnection.

14. The system according to claim 7, characterized in that, The system includes a power supply module and a clock module, which provide stable power and clock signals to the optical module and dedicated circuit module to ensure signal synchronization and stability.

15. The system according to claim 7, characterized in that, The optical signal is transmitted through single-mode or multimode optical fiber.

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