HASH algorithm implementation method and device based on FPGA platform

Abstract

The invention discloses a HASH algorithm implementation method and device based on an FPGA (Field Programmable Gate Array) platform, and relates to the technical field related to computers, the method comprises the following steps: performing conversion processing on a predetermined Key through a predetermined HASH function to obtain a hash value; performing query operation on the hash value to obtain a query result; performing release adjustment on the predetermined Value storage space to obtain an initial Value storage space; obtaining an adding operation type of the predetermined Key, and adding a corresponding Value to an initial Value storage space to obtain a target Value storage space; and obtaining an agreed read-write mechanism, and performing read-write control on the target Value storage space according to the agreed read-write mechanism. The technical problems of low calculation efficiency, inflexible storage space management and high query operation delay of the HASH algorithm in the prior art are solved, and the technical effects of improving the calculation efficiency, optimizing the storage utilization rate and improving the query speed and performance are achieved.

Description

Technical Field

[0001] This application relates to the field of computer-related technologies, and in particular, to a method and device for implementing a HASH algorithm based on an FPGA platform. Background Art

[0002] As a commonly used data encryption and storage technology, the hash algorithm is widely applied in various scenarios such as data verification, encryption, and storage. Especially when dealing with large-scale data, how to efficiently implement hash calculation and storage management has become a key issue in current technical research. The hash algorithm can perform a fixed-length output (i.e., hash value) on the input predetermined data (such as a Key), making the data storage and search processes more efficient. However, in large-scale data processing and storage systems, conventional hash algorithms have limitations in aspects such as storage space management, query efficiency, and control of concurrent operations. And in modern hardware acceleration platforms, the acceleration technology based on FPGA (Field Programmable Gate Array) provides important support for high-performance computing. Through its parallel computing ability and flexible hardware configuration, FPGA can greatly improve the processing speed in data processing tasks and shows great potential in the calculation, storage space management, and query update of the hash algorithm. However, traditional applications are mainly based on the CPU platform or ASIC chips, facing bottlenecks in comprehensive performance indicators such as data processing efficiency and implementation flexibility.

[0003] In the related technologies at the present stage, there are technical problems such as low calculation efficiency of the HASH algorithm, inflexible storage space management, and high query operation latency. Summary of the Invention

[0004] This application provides a method and device for implementing a HASH algorithm based on an FPGA platform, solving the technical problems of low calculation efficiency of the HASH algorithm, inflexible storage space management, and high query operation latency existing in the prior art, and achieving the technical effects of improving calculation efficiency, optimizing storage utilization rate, and enhancing query speed and performance.

[0005] The present application provides a method for implementing a HASH algorithm based on an FPGA platform, including: reading a predetermined HASH function, and performing conversion processing on a predetermined Key through the predetermined HASH function to obtain a hash value; introducing a pipeline mechanism, and performing a query operation on the hash value in combination with a predetermined HASH table to obtain a query result; releasing and adjusting a predetermined Value storage space according to the hash value and the query result to obtain an initial Value storage space; obtaining an increment operation type of the predetermined Key, and applying for a corresponding Value in combination with the query result, and adding the corresponding Value to the initial Value storage space to obtain a target Value storage space; obtaining a predefined read / write mechanism, and performing read / write control on the target Value storage space according to the predefined read / write mechanism.

[0006] In a possible implementation manner, the method for implementing a HASH algorithm based on an FPGA platform further performs the following processing: obtaining a corresponding address of the corresponding Value in an internal RAM; caching the corresponding address and the predetermined Key to an external storage DDR.

[0007] In a possible implementation manner, the method for implementing a HASH algorithm based on an FPGA platform further performs the following processing: using a Cache mechanism to use the external storage DDR as an external DDR cache, denoted as Cache cache RAM0.

[0008] In a possible implementation manner, the method for implementing a HASH algorithm based on an FPGA platform further performs the following processing: storing a record for read / write controlling the target Value storage space to an internal cache RAM1.

[0009] In a possible implementation manner, the method for implementing a HASH algorithm based on an FPGA platform further performs the following processing: reading the Cache cache RAM0 of the hash value; determining whether the Cache cache RAM0 meets a hit constraint; if it does not meet the hit constraint, reading the external storage DDR based on the pipeline mechanism; obtaining the query result according to the external storage DDR.

[0010] In a possible implementation manner, the method for implementing a HASH algorithm based on an FPGA platform further performs the following processing: storing read / write records of the predetermined Key to the external storage DDR in a decoupled manner.

[0011] In a possible implementation manner, the method for implementing a HASH algorithm based on an FPGA platform further performs the following processing: storing read / write records of the corresponding Value to the internal cache RAM1 in a decoupled manner.

[0012] The present application also provides a device for implementing the HASH algorithm based on the FPGA platform, including: a hash value calculation unit for reading a predetermined HASH function and performing a conversion process on a predetermined Key through the predetermined HASH function to obtain a hash value; a lookup entry unit for introducing a pipeline mechanism and performing a query operation on the hash value in combination with a predetermined HASH table to obtain a query result; a delete entry unit for performing a release adjustment on a predetermined Value storage space according to the hash value and the query result to obtain an initial Value storage space; an add entry unit for obtaining the add operation type of the predetermined Key, applying for and obtaining a corresponding Value in combination with the query result, and adding the corresponding Value to the initial Value storage space to obtain a target Value storage space; and a read / write operation aggregation unit for obtaining an agreed read / write mechanism and performing read / write control on the target Value storage space according to the agreed read / write mechanism.

[0013] It is intended to propose a method and device for implementing the HASH algorithm based on the FPGA platform in the present application. A conversion process is performed on a predetermined Key through a predetermined HASH function to obtain a hash value; a query operation is performed on the hash value to obtain a query result; a release adjustment is performed on a predetermined Value storage space to obtain an initial Value storage space; the add operation type of the predetermined Key is obtained, and the corresponding Value is added to the initial Value storage space to obtain a target Value storage space; an agreed read / write mechanism is obtained, and read / write control is performed on the target Value storage space according to the agreed read / write mechanism. The technical problems of low calculation efficiency of the HASH algorithm, inflexible storage space management, and high query operation latency existing in the prior art are solved, and the technical effects of improving the calculation efficiency, optimizing the storage utilization rate, and enhancing the query speed and performance are achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments of the present invention will be briefly introduced below. Flowcharts are used in the present application to illustrate the operations performed by the devices according to the embodiments of the present application. It should be understood that the operations before or below do not necessarily need to be executed precisely in sequence. On the contrary, according to the needs, they can be executed in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or one or several steps of operations can be removed from these processes.

[0015] Figure 1 It is a schematic flowchart of a method for implementing the HASH algorithm based on the FPGA platform provided by an embodiment of the present application.

[0016] Figure 2 It is a schematic structural diagram of a device for implementing the HASH algorithm based on the FPGA platform provided by an embodiment of the present application.

[0017] Explanation of the reference numerals: hash value calculation unit 10 , entry search unit 20 , entry deletion unit 30 , entry addition unit 40 , read / write operation aggregation unit 50 . DETAILED DESCRIPTION

[0018] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below.

[0019] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of this application.

[0020] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict, and the terms "first\second" involved are merely to distinguish similar objects and do not represent a specific ordering of objects. The terms "including" and "having" and any variations are intended to cover non-exclusive inclusions, for example, a process, method, product, or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, devices, products, or equipment. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of this application. The terms used herein are for the purpose of describing the embodiments of the present application only.

[0021] The present application embodiment provides a method for implementing a HASH algorithm based on an FPGA platform, such as Figure 1 As shown, the method includes:

[0022] Step S100, reading a predetermined HASH function, and converting a predetermined Key using the predetermined HASH function to obtain a hash value.

[0023] Preferably, the predetermined HASH function refers to a component of a preset hash algorithm, which is a method for converting input data (usually of any length) into a hash value of a fixed length. The output is the hash value (hash value). Among them, the predetermined hash function may be a standard hash algorithm, such as MD5, SHA-256, etc., or it may be a custom hash function designed according to the application scenario. Specifically, the predetermined Key is input into the predetermined HASH function, and the predetermined HASH function is used to perform conversion processing on it to obtain the corresponding hash value, that is, the fixed-length output obtained after the hash function processes the input data (Key). It is usually a unique identifier used to identify or index the input data. For example, it is used for data storage, data comparison, data verification, etc. Among them, the predetermined Key is the key original data to be searched and matched, such as a string, a number, or a digest of file content, etc. Generally speaking, by using a known hash algorithm ("predetermined HASH function"), the given input data (i.e., "predetermined Key") is hashed to finally obtain a hash value (hash value), which is used as the key data in subsequent query and storage operations.

[0024] Step S200, introduce a pipeline mechanism, and combine the predetermined HASH table to perform a query operation on the hash value to obtain a query result.

[0025] Preferably, the pipeline mechanism is used to improve the parallelism and processing efficiency of computing tasks. Especially in hardware implementation, the pipeline mechanism decomposes tasks into multiple stages, and each stage processes different tasks in parallel. For the hash algorithm, the introduction of the pipeline mechanism means that during the hash value calculation and query process, multiple steps can be executed simultaneously instead of sequentially, thereby significantly reducing operation latency and enhancing the overall computing throughput. Specifically, the pipeline mechanism may include a calculation stage (calculating the hash function and obtaining the hash value), a query stage (querying a predetermined hash table through the hash value), and a response stage (returning the query result and further performing operations related to storage or calculation); then, a query operation is performed on the hash value in combination with the predetermined HASH table. Here, the predetermined HASH table refers to a hash table that has been constructed. A hash table is a data structure that maps a Key to a hash value and is used to store data items related to the hash value, that is, the Key is stored in an array in an associated manner, and each Key has a unique index. In the hash table, each input data (Key) indexes or locates the storage location of the data according to the hash value calculated by the hash function, that is, the calculated hash value is matched with the entries in the hash table to query the data record corresponding to the hash value. Specifically, the storage location in the hash table is determined according to the hash value (through hash value mapping), it is checked whether there is valid data at this location or whether further processing is required (such as conflict handling, linked list search, etc.), and the query result related to the hash value is obtained (for example, whether the Key already exists in the hash table; if it exists, the original Value storage location and its status; if it does not exist, the storage location of the Key). In the FPGA hardware platform, the query steps of the hash algorithm are accelerated through the pipeline mechanism, and the data corresponding to the hash value is quickly located and obtained by using the predetermined hash table, thereby improving the query efficiency and overall performance.

[0026] Step S300, release and adjust the predetermined Value storage space according to the hash value and the query result to obtain the initial Value storage space.

[0027] Preferably, in a hash table, each hash value (Key) corresponds to a storage location (i.e., the Value storage space) for storing the value associated with that Key (i.e., Value). For example, it is usually the actual content of a data record, such as the specific data of a certain file, a numerical value, or other types of information. The hash value is not only used to locate the storage location of the data but may also be related to the size of the stored data, the data storage status, etc. When performing a query operation, the storage location obtained through the hash value may need to be dynamically adjusted according to the query result; the query result provides status information about the storage space corresponding to the current hash value. For example, the query result may indicate whether the current storage space is full, whether there are conflicts, or whether the space can be released, etc. Specifically, when the predetermined Value storage space queried by the hash value has been occupied or no longer needs to store certain data, it is necessary to "release" or "clean up" the storage area, including releasing the data space that is no longer in use (e.g., deleting some invalid or expired entries); reallocating or merging spaces to provide sufficient storage for new data; adjusting the layout of the storage space to improve access efficiency or reduce storage waste; after releasing or adjusting the storage space, finally obtaining the initial Value storage space, that is, a cleaned and optimized storage area that can be used to store the data (i.e., Value) associated with the current hash value, thereby ensuring the efficient use of the storage space.

[0028] Step S400: Obtain the type of increment operation for the predetermined Key, and apply for the corresponding Value in combination with the query result, and add the corresponding Value to the initial Value storage space to obtain the target Value storage space.

[0029] Preferably, a data storage operation is performed based on a hash algorithm, including determining the data addition type, utilization of query results, and acquisition and storage of Value data. Specifically, in a hash table, the operation type indicates different operation requirements for data. The addition operation type of a predetermined Key is obtained to determine how to process the data of that Key, including an insertion operation. When there is no data corresponding to the given Key in the hash table, the insertion operation is performed, that is, the Key and the corresponding Value are stored in the hash table; an update operation. If there is already data corresponding to the given Key in the hash table (the Key already exists), the update operation is performed to replace or modify the corresponding Value; an expansion operation, expanding or appending data to the existing Value. Then, the corresponding Value is obtained by applying the query results, that is, it is determined whether a new Value needs to be created based on the query results, or the Value is updated based on the existing storage location. For example, if the query results indicate that no corresponding data has been stored for this Key, a new storage space needs to be applied for and allocated to store the Value corresponding to this Key; finally, the corresponding Value is added to the initial Value storage space, that is, the corresponding Value obtained through the query operation (whether it is a newly created Value or an update of an existing Value) is placed in the previously adjusted storage space. For example, if it is an insertion operation, the new Value is written into the initial storage space; if it is an update operation, the Value in the original storage space is overwritten; finally, the target Value storage space (the storage location finally storing this Key and the corresponding Value) is obtained, that is, the data is inserted or updated in the hash table, and the state of the storage space is also updated.

[0030] Step S500, obtain a predefined read / write mechanism and perform read / write control on the target Value storage space according to the predefined read / write mechanism.

[0031] Preferably, read and write operation management is performed on the data storage space (i.e., the target Value storage space), including obtaining a read and write mechanism and accessing the storage space according to the agreed read and write mechanism (read and write control). Among them, the agreed read and write mechanism is a pre-designed access and operation rule for the storage space (especially the Value storage space) to ensure the efficiency, accuracy, and consistency of data operations. Specifically, the agreed read and write mechanism may include read-write locks, that is, controlling concurrent access to data through a locking mechanism to ensure that only one thread can write data at the same time, while multiple threads can perform read operations simultaneously; atomic operations to ensure that the update operation of the target storage space is uninterruptible and avoid data inconsistency in a multi-threaded environment; transaction mechanism. In some applications, it is necessary to ensure the atomicity of operations, that is, the read and write operations are either completely successful or completely failed as a whole, thus avoiding inconsistencies caused by partial updates; cache mechanism, using a cache to control access to the storage space and reduce frequent read and write operations. For example, when data is modified, it will be first written to the buffer area, and then the data in the buffer will be synchronized to the final storage location at an appropriate time; sequential access or random access, defining the access method of data according to the storage type and requirements. For example, for sequential storage, it is operated through linear access, while for random storage structures such as hash tables or databases, direct access through key values is allowed.

[0032] Preferably, the read and write control of the target Value storage space is performed according to the agreed read and write mechanism. Specifically, when reading the data stored in the target Value storage space, the agreed read and write mechanism will determine the operation for smooth reading. For example, if a read-write lock is used, the read lock is first acquired to ensure that reading can be performed without interference from write operations; if a caching mechanism is used, the data in the cache is first read, and if the cache hits, it is directly returned, otherwise the data is obtained from long-term storage such as a disk. When writing data to the target Value storage space, the agreed read and write mechanism ensures the effectiveness and security of the write operation. For example, if a write lock is used, the write lock is acquired before performing the write operation to ensure that no other thread modifies the same storage space at the same time, thus avoiding data competition or inconsistency problems; if a transaction mechanism is used, the write operation is regarded as part of a transaction, either completely committed successfully or completely rolled back. If it is a multi-threaded or multi-process environment (such as a parallel program running on an FPGA or a multi-core processor), special attention needs to be paid to the control of concurrent operations. The read and write mechanism will particularly focus on how to avoid concurrent conflicts and how to ensure data consistency. For example, some mechanisms may limit that other threads cannot perform write operations when a write operation is in progress; or, when reading data, the write operation is delayed until after the reading operation is completed. In a database or a distributed storage system, the agreed read and write mechanism also ensures data consistency and persistence. For the written Value, it is ensured that it is persisted to the storage medium (such as the synchronization from memory to hard disk), and if a system failure occurs, the data will not be lost. Through these controls, the reading and writing operations of data can be effectively managed, ensuring data consistency, integrity, improving concurrent processing efficiency, and ensuring smooth data access and correctness in a multi-threaded, multi-process or distributed environment.

[0033] Further, step S400 further includes step S410 of obtaining the corresponding address of the corresponding Value in the internal RAM; and step S420 of caching the corresponding address and the predetermined Key to the external storage DDR.

[0034] Preferably, the internal RAM (memory) is a high-speed memory for storing temporary data, usually processing frequently accessed data. For example, in hardware platforms such as FPGAs and processors, the internal RAM is used to store the data information being processed, and its access speed is faster than that of external storage devices. Specifically, obtaining the memory address corresponding to a certain data (i.e., Value) stored in the internal RAM may be a pointer or a memory location identifier pointing to the specific data stored in the internal RAM; then caching the corresponding address and the predetermined Key to the external storage DDR, that is, storing the storage address of a certain value in the internal RAM (the memory address of Value) and the Key (as an identifier) associated with this value together to the external storage (DDR), so as to release the internal RAM space, reduce the internal RAM pressure, balance the storage capacity and speed, and improve the data access efficiency. Among them, the external storage DDR (Double Data Rate Memory) is a type of high-speed external memory, applied in computers and embedded systems as a medium for data storage, usually connected to hardware components such as processors or FPGAs through a bus, and used to store larger and long-term preserved data. Compared with the internal RAM, the access speed of DDR is slower, but its storage capacity is larger, suitable for storing medium- and long-term data that is not frequently accessed.

[0035] Further, step S420 further includes using the Cache mechanism to use the external storage DDR as an external DDR cache, denoted as Cache cache RAM0.

[0036] Preferably, combining the external storage (DDR) with the cache (Cache) mechanism, that is, using the external storage (DDR) as a cache and naming it Cache cache RAM0 to improve the data access efficiency. Specifically, Cache (cache) is a high-speed temporary storage area, usually located between the processor and the main memory, used to store frequently accessed data to reduce the latency of the processor accessing the memory and improve the data access speed. The Cache mechanism refers to the multi-level caches in the computer architecture (such as L1 Cache, L2 Cache, etc.) to determine the location where the data is stored according to the access frequency and importance of the data. The Cache will cache the most frequently used data, thus avoiding repeated access to the slower main storage (such as RAM or hard disk); using the Cache mechanism to store the DDR as an external cache, and naming the external DDR as a cache, Cache cache RAM0. Specifically, more frequent data accesses will be completed in the Cache cache first, and only when the data is not in the Cache cache will the external main storage (such as DDR) be accessed to reduce the direct access to the DDR and improve the data access efficiency.

[0037] Further, step S420 further includes storing the record of reading and writing to control the target Value storage space to the internal cache RAM1.

[0038] Preferably, operation information of the target Value storage space during read-write control is recorded, such as the type of operation (read operation, write operation), timestamp, accessed data content (such as storage location, offset, etc.), operation status (whether successful, whether a conflict occurs, etc.). Then, these records are stored in the internal cache RAM1, that is, the internal cache storage space, which usually has a high access speed. It is used to store frequently accessed data or operation records, with lower latency and higher throughput. Storing the read-write operation records in RAM1 means efficiently storing and managing the read-write operation records through the internal cache to improve the access speed, reduce the access frequency to the main storage (such as DDR), and ensure that the operation records can be quickly accessed and processed in subsequent operations.

[0039] Further, step S200 further includes step S210 of reading the Cache cache RAM0 of the hash value; step S220 of determining whether the Cache cache RAM0 meets the hit constraint; step S230 of, if it does not meet the hit constraint, reading the external storage DDR based on the pipeline mechanism; and step S240 of obtaining the query result according to the external storage DDR.

[0040] Preferably, the Cache cache RAM0 is queried through the hash value to find out whether relevant data has been stored in the cache, and an attempt is made to directly obtain the data from the cache, and then it is determined whether the Cache cache RAM0 meets the hit constraint. Among them, the hit constraint refers to the standard for judging whether the data in the cache meets the current query requirements, such as whether the data already exists (judging whether there is data corresponding to the hash value in the cache), whether the data is valid (sometimes the data in the cache may expire or be replaced, checking whether the data in the cache is still valid), and whether the data meets certain preset conditions to be used for query. If the data in the cache meets these constraint conditions, it is considered a hit; otherwise, it is a miss, that is, it does not meet the hit constraint. Then, the pipeline mechanism is used to decompose the task into multiple stages for parallel processing to improve the throughput and reduce the latency, accelerate the data reading from the external storage DDR, and reduce the latency of waiting for the reading to complete. Finally, the data read from the external storage DDR is returned to the caller as the query result, that is, the data (i.e., Value) corresponding to the hash value is queried and retrieved from the external storage according to the hash value, so that while ensuring efficient access, the access frequency to the slower external storage can be minimized to the greatest extent.

[0041] Further, step S400 further includes step S430 of storing the read / write records of the predetermined Key to the external storage DDR in a decoupled manner, and further includes step S440 of storing the read / write records of the corresponding Value to the internal cache RAM1 in a decoupled manner.

[0042] Preferably, decoupling means separating different operations, tasks or data for processing to reduce the dependencies between them. Through decoupling, operation optimization and resource allocation can be carried out more flexibly, that is, separating the read / write records of Key and Value and storing them in different storage media - Key is stored in the external storage (DDR), and Value is stored in the internal cache (RAM1). Specifically, when performing read / write operations on Key, the corresponding operation records (such as operation time, operation type, read / write result, etc.) are stored in the external storage (DDR) to avoid excessive storage of read / write records in memory, thus avoiding waste of memory resources; when performing read / write operations on Value, the corresponding operation records (such as operation timestamp, read / write status, etc.) are recorded in the internal cache RAM1, which helps to quickly retrieve and operate on these records to ensure the efficiency of data access. Through decoupling, resource utilization can be optimized, and different types of data or operations can be stored in more suitable storage media respectively, facilitating the effective use of storage resources, optimizing storage resource management, reducing excessive occupation of memory space, further better supporting concurrent access, reducing storage access conflicts, and enhancing the scalability and flexibility of the system in high-concurrency and large-data-volume scenarios.

[0043] In the above text, with reference to Figure 1 a method for implementing the HASH algorithm based on the FPGA platform according to an embodiment of the present invention is described in detail. Next, with reference to Figure 2 a device for implementing the HASH algorithm based on the FPGA platform according to an embodiment of the present invention will be described.

[0044] A device for implementing the HASH algorithm based on the FPGA platform according to an embodiment of the present invention is used to solve the technical problems of low calculation efficiency of the HASH algorithm, inflexible storage space management and high query operation latency in the prior art, and achieves the technical effects of improving calculation efficiency, optimizing storage utilization, and enhancing query speed and performance. As Figure 2 shown, a device for implementing the HASH algorithm based on the FPGA platform includes: a hash value calculation unit 10, a search entry unit 20, a delete entry unit 30, an add entry unit 40, and a read / write operation aggregation unit 50.

[0045] The hash value calculation unit 10 is configured to read a predetermined HASH function and perform a conversion process on a predetermined Key through the predetermined HASH function to obtain a hash value; the lookup entry unit 20 is configured to introduce a pipeline mechanism and perform a query operation on the hash value in combination with a predetermined HASH table to obtain a query result; the delete entry unit 30 is configured to perform a release adjustment on a predetermined Value storage space according to the hash value and the query result to obtain an initial Value storage space; the add entry unit 40 is configured to obtain an add operation type of the predetermined Key, apply for a corresponding Value in combination with the query result, and add the corresponding Value to the initial Value storage space to obtain a target Value storage space; the read / write operation aggregation unit 50 is configured to obtain a predefined read / write mechanism and perform read / write control on the target Value storage space according to the predefined read / write mechanism.

[0046] Next, the specific configuration of the add entry unit 40 will be described in detail. The add entry unit 40 may further include: an external storage DDR unit configured to obtain a corresponding address of the corresponding Value in an internal RAM, and cache the corresponding address and the predetermined Key to the external storage DDR.

[0047] Next, the specific configuration of the add entry unit 40 will be further described in detail. The add entry unit 40 may further include: a Cache cache RAM0 unit of the external storage DDR configured to store a record for read / write controlling the target Value storage space to an internal cache RAM1.

[0048] Next, the specific configuration of the add entry unit 40 will be further described in detail. The add entry unit 40 may further include: storing a record for read / write controlling the target Value storage space to an internal cache RAM1.

[0049] Next, the specific configuration of the lookup entry unit 20 will be described in detail. The lookup entry unit 20 may further include: a Cache cache RAM0 for reading the hash value; determining whether the Cache cache RAM0 meets a hit constraint; if the Cache cache RAM0 does not meet the hit constraint, reading the external storage DDR based on the pipeline mechanism; and obtaining the query result according to the external storage DDR.

[0050] Next, the specific configuration of the add entry unit 40 will be further described in detail. The add entry unit 40 may further include: storing read / write records of the predetermined Key to the external storage DDR in a decoupled manner.

[0051] Next, the specific configuration of the adding entry unit 40 will be further described in detail. The adding entry unit 40 may further include: storing the read and write records of the corresponding Value in a decoupled manner to the internal cache RAM1.

[0052] The above specific embodiments do not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present application shall be included within the protection scope of the present application. In some cases, the actions or steps recited in the present application may be executed in a different order than in the embodiments and still achieve the desired results. Additionally, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A method for implementing a HASH algorithm based on an FPGA platform, characterized in that: include: Read a predetermined HASH function, and convert the predetermined Key through the predetermined HASH function to obtain a hash value; Introducing a pipeline mechanism, and performing a query operation on the hash value in combination with a predetermined HASH table to obtain a query result; Release and adjust the predetermined Value storage space according to the hash value and the query result to obtain an initial Value storage space; Obtain the addition operation type of the predetermined Key, apply for the corresponding Value in combination with the query result, and add the corresponding Value to the initial Value storage space to obtain the target Value storage space; Acquire the agreed read-write mechanism, and perform read-write control on the target Value storage space according to the agreed read-write mechanism.

2. The method for implementing a HASH algorithm based on an FPGA platform according to claim 1, characterized in that: Also includes: Get the corresponding address of the corresponding Value in the internal RAM; The corresponding address and the predetermined Key are cached in an external memory DDR.

3. The method for implementing a HASH algorithm based on an FPGA platform according to claim 2, characterized in that: Also includes: The external storage DDR is used as an external DDR cache using a Cache mechanism, which is recorded as Cache RAM0.

4. The method for implementing a HASH algorithm based on an FPGA platform according to claim 3, characterized in that: Also includes: The records of the target Value storage space that are read and written to control are stored in the internal cache RAM1.

5. The method for implementing the HASH algorithm based on an FPGA platform according to claim 3, characterized in that: The pipeline mechanism is introduced, and the hash value is queried in combination with the predetermined HASH table to obtain the query results, including: Read the Cache RAM0 of the hash value; Determine whether the Cache RAM0 meets the hit constraint; If the hit constraint is not met, reading the external storage DDR based on the pipeline mechanism; The query result is obtained according to the external storage DDR.

6. The method for implementing a HASH algorithm based on an FPGA platform according to claim 4, characterized in that: include: The read and write records of the predetermined Key are stored in the external storage DDR in a decoupled manner.

7. The method for implementing a HASH algorithm based on an FPGA platform according to claim 6, characterized in that: include: The read and write records of the corresponding Value are stored in the internal cache RAM1 in a decoupled manner.

8. A HASH algorithm implementation device based on FPGA platform, characterized in that: The device is used to perform the steps of any one of the methods described in claims 1 to 7, and the device comprises: A hash value calculation unit, used to read a predetermined HASH function and convert a predetermined Key through the predetermined HASH function to obtain a hash value; A search entry unit is used to introduce a pipeline mechanism and perform a query operation on the hash value in combination with a predetermined HASH table to obtain a query result; An entry deletion unit, used to release and adjust the predetermined Value storage space according to the hash value and the query result to obtain an initial Value storage space; An adding entry unit is used to obtain the adding operation type of the predetermined Key, apply for obtaining the corresponding Value in combination with the query result, and add the corresponding Value to the initial Value storage space to obtain the target Value storage space; The read-write operation aggregation unit is used to obtain the agreed read-write mechanism and perform read-write control on the target Value storage space according to the agreed read-write mechanism.

9. A HASH algorithm implementation device based on FPGA platform, characterized in that: The device is used to execute the steps of any one of the methods in claims 2 to 3, and the device also includes an external storage DDR unit, which is used to obtain the corresponding address of the corresponding Value in the internal RAM, and cache the corresponding address and the predetermined Key to the external storage DDR.

10. A HASH algorithm implementation device based on FPGA platform, characterized in that: The device is used to execute the method steps as claimed in claim 4, and the device also includes a Cache RAM0 unit of an external storage DDR, which is used to store the records of the read and write control of the target Value storage space into the internal cache RAM1.

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