Memory and manufacturing method thereof

Abstract

The invention provides a memory and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem of low yield of memories. The memory comprises bit lines, transistors, capacitors, contact structures and support structures, the plurality of bit lines are arranged at intervals along a first direction, the plurality of transistors are arranged at intervals along the first direction and are arranged at intervals along a second direction, and the plurality of transistors along the first direction are correspondingly and electrically connected with one bit line; the capacitor is correspondingly and electrically connected with each transistor, and the capacitor and the bit line are located on the two sides of the transistor in the third direction; each contact structure is correspondingly connected with one bit line; the plurality of supporting structures are arranged at intervals in the second direction and penetrate through the plurality of bit lines, and at least one supporting structure is arranged between every two adjacent contact structures to support the plurality of bit lines, so that every two adjacent bit lines are kept at intervals, contact caused by collapse of the bit lines is avoided, the stability of a memory manufacturing process is improved, and the performance of the memory is ensured; and the yield of the memory is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and particularly to a memory and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor technologies, memories, especially dynamic random access memories (DRAMs), are widely used in various electronic devices due to their high storage density and fast read / write speed.

[0003] A dynamic random access memory includes a plurality of memory cells, and each memory cell generally includes a transistor and a capacitor. Among them, the gate of the transistor is connected to a word line (WL), the drain is connected to a bit line (BL), the source is connected to the capacitor, and the voltage signal on the word line can control the opening or closing of the transistor. Further, data information stored in the capacitor can be read through the bit line, or data information can be written into the capacitor through the bit line for storage.

[0004] To reduce the size of the memory and improve its storage density, the memory generally adopts a three-dimensional memory with horizontally placed capacitors, and one end of the capacitor is connected to the transistor. A plurality of transistors in the horizontal direction are connected to one bit line, and the bit line is connected to the peripheral circuit through a bit line plug in the vertical direction. However, during the manufacturing process of the memory, especially during the manufacturing process of the bit line, the stability of the structure is poor and it is prone to collapse, which affects the yield of the memory. Summary of the Invention

[0005] In view of the above problems, embodiments of the present disclosure provide a memory and a manufacturing method thereof to improve the yield of the memory.

[0006] According to some embodiments, the present disclosure provides a memory, which includes: a plurality of bit lines spaced apart along a first direction; a plurality of transistors spaced apart along the first direction and spaced apart along a second direction, and a plurality of the transistors along the first direction are correspondingly electrically connected to one of the bit lines; a capacitor correspondingly electrically connected to each of the transistors, along a third direction, the capacitor and the bit line are located on both sides of the transistor, and the first direction, the second direction, and the third direction are pairwise crossed; a plurality of contact structures spaced apart along the second direction and penetrating through part of the bit lines, and each contact structure is correspondingly connected to one of the bit lines; a plurality of support structures spaced apart along the second direction and penetrating through the plurality of bit lines, and there is at least one support structure between two adjacent contact structures.

[0007] In some possible embodiments, sidewalls of at least a part of the support structure are formed with a plurality of first annular grooves spaced along the first direction; each bit line includes a first part filled in the first annular groove and a second part located outside the first annular groove, and along the first direction, the thickness of the first part is less than that of the second part.

[0008] In some possible embodiments, the second part includes an extension part and a connection part, the connection part connects two adjacent first parts along the second direction, the extension part connects the transistor, and the first part or the connection part opposite to the transistor.

[0009] In some possible embodiments, sidewalls of a part of the contact structure opposite to the bit line are recessed from sidewalls of the remaining contact structure, so that the sidewalls of the contact structure are wavy.

[0010] In some possible embodiments, the memory further includes a plurality of word lines spaced along the second direction, each word line corresponds to a plurality of transistors along the first direction, and forms gates of the corresponding transistors; each transistor includes a gate dielectric layer surrounding the corresponding gate, and a channel region surrounding the gate dielectric layer, and the channel region is correspondingly connected to the bit line and the capacitor.

[0011] In some possible embodiments, the gate dielectric layer includes a body surrounding the gate, and epitaxial parts connected to two ends of the body along the first direction, the epitaxial parts adjacent to each other of two adjacent gate dielectric layers along the first direction are in contact with each other, and a plurality of gate dielectric layers along the first direction form an integral body.

[0012] In some possible embodiments, the channel region covers opposite surfaces of the corresponding epitaxial parts facing each other, and an outer peripheral surface of the body, the channel region encloses a second annular groove, along the third direction, the bit line and a connection layer are respectively arranged on two sides of the channel region, and the bit line and the connection layer extend into the second annular groove and are in corresponding contact with a surface of the second annular groove, and the connection layer is also in corresponding contact with the capacitor.

[0013] The memory provided by the embodiments of the present disclosure has at least the following advantages:

[0014] The memory provided by the embodiments of the present disclosure supports multiple bit lines by providing a plurality of support structures penetrating through the multiple bit lines, so that adjacent two bit lines are kept spaced apart, avoiding contact due to bit line collapse, improving the stability in the memory manufacturing process, ensuring the performance of the memory, and improving the yield of the memory.

[0015] According to some embodiments, the present disclosure also provides a method for manufacturing a memory, which includes: forming a stacked structure on a substrate, the stacked structure including a plurality of first sacrificial layers and a plurality of second sacrificial layers alternately arranged in sequence along a first direction; forming a plurality of contact structures, a plurality of first intermediate structures and a plurality of second intermediate structures in the stacked structure; wherein the plurality of contact structures, the plurality of first intermediate structures and the plurality of second intermediate structures are all arranged at intervals along the second direction, and along a third direction, the plurality of second intermediate structures are located on a side of the plurality of first intermediate structures away from the plurality of contact structures, each of the contact structures contacts a corresponding layer of the second sacrificial layer, the first intermediate structures and the second intermediate structures both penetrate the stacked structure, and the first direction, the second direction and the third direction intersect each other; forming at least one supporting structure between two adjacent contact structures along the second direction, the supporting structure at least penetrates the stacked structure; removing part of the stacked structure between two adjacent first intermediate structures and two adjacent second intermediate structures along the second direction, forming a support structure that penetrates the stacked structure and is connected to the first The intermediate structures are alternately provided with first isolation grooves, along the third direction, one end of the first isolation groove facing the support structure protrudes from one end of the first intermediate structure facing the support structure, and one end of the first isolation groove facing away from the support structure penetrates the stacked structure; the remaining second sacrificial layer is removed to form a first filling space; a first conductive layer is formed in the first filling space, the first conductive layer located between the support structures, between the support structure and the contact structure, and between the support structure or the contact structure and the first intermediate structure forms a bit line, and the first conductive layer located between the first intermediate structure and the second intermediate structure forms a connecting layer; a first isolation layer is formed in the first isolation groove, the first isolation layer fills the first isolation groove; the first intermediate structure is removed to form a plurality of transistors spaced apart along the first direction, the second intermediate structure is removed to form a plurality of capacitors spaced apart along the second direction, and the remaining first sacrificial layer is removed to form a second isolation layer, along the third direction, each of the transistors is connected to one of the capacitors through the connecting layer.

[0016] In some possible embodiments, at least one support structure is formed between two adjacent contact structures along the second direction, including: etching the stacked structure to form a plurality of first filling holes penetrating the stacked structure, the plurality of first filling holes being arranged at intervals along the second direction, and at least one of the first filling holes being provided between two adjacent contact structures; etching the first sacrificial layer exposed in the first filling hole to expand the first filling hole; thinning the second sacrificial layer exposed in the expanded first filling hole along the first direction to further expand the first filling hole and increase the distance between adjacent portions of the second sacrificial layer exposed in the expanded first filling hole; depositing the support structure, and the support structure filling the further expanded first filling hole.

[0017] In some possible embodiments, a plurality of contact structures, a plurality of first intermediate structures and a plurality of second intermediate structures are formed in the stacked structure, including: etching the stacked structure to form a plurality of second filling holes arranged at intervals along the second direction, each of the second filling holes corresponding to expose one of the second sacrificial layers; forming a contact structure in the second filling hole, and the contact structure filling the corresponding second filling hole; etching the stacked structure to form a plurality of first intermediate holes on both sides of the contact structure along the third direction, the plurality of first intermediate holes on each side being arranged at intervals along the second direction, and each of the first intermediate holes exposing the substrate; forming the first intermediate structure in the first intermediate hole, and the first intermediate structure filling the first intermediate hole; etching the stacked structure to form a plurality of second intermediate holes on one side of the plurality of first intermediate structures away from the plurality of contact structures, the plurality of second intermediate holes on each side being arranged at intervals along the second direction, and along the third direction, each of the second intermediate holes being opposite to the first intermediate structure; forming the second intermediate structure in the second intermediate hole, and the second intermediate structure filling the second intermediate hole.

[0018] The method for manufacturing a memory provided by the embodiments of the present disclosure has at least the following advantages:

[0019] In the method for manufacturing a memory provided by the embodiments of the present disclosure, by forming a plurality of support structures to support adjacent first sacrificial layers, adjacent two first sacrificial layers are kept at intervals, so as to maintain the space for forming bit lines. After the bit lines are formed, the collapse and contact of the bit lines are avoided, the stability of the memory manufacturing process is improved, the performance of the memory is ensured, and the yield of the memory is increased. In addition, by forming the first isolation layer and the second isolation layer, the insulation isolation between adjacent bit lines along the first direction, and the insulation isolation between two adjacent transistors and two adjacent capacitors along the second direction can be ensured, so as to ensure the performance of the memory. Description of the Drawings

[0020] Figure 1 is the architecture diagram of the memory in an embodiment of the present disclosure;

[0021] Figure 2 is the simplified structural diagram of the memory in an embodiment of the present disclosure;

[0022] Figure 3 is the vertical cross-sectional schematic diagram of a structure of the memory in an embodiment of the present disclosure;

[0023] Figure 4 is the vertical cross-sectional schematic diagram of another structure of the memory in an embodiment of the present disclosure;

[0024] Figure 5 is the top-down cross-sectional schematic diagram of the memory in an embodiment of the present disclosure;

[0025] Figure 6 is Figure 5 the partial enlarged view at M in

[0026] Figure 7 is the flowchart of the manufacturing method of the memory in an embodiment of the present disclosure;

[0027] Figure 8 is the three-dimensional diagram of the substrate and the stacked structure in an embodiment of the present disclosure;

[0028] Figure 9 is the cross-sectional schematic diagram of the substrate and the stacked structure in an embodiment of the present disclosure;

[0029] Figure 10 is the three-dimensional diagram after forming the first photoresist layer in an embodiment of the present disclosure;

[0030] Figure 11 is the formation process diagram of the second filling hole in an embodiment of the present disclosure;

[0031] Figure 12 is the formation process diagram of the contact structure in an embodiment of the present disclosure;

[0032] Figure 13 is the three-dimensional diagram after forming the second photoresist layer in an embodiment of the present disclosure;

[0033] Figure 14 is the formation process diagram of the first intermediate hole in an embodiment of the present disclosure;

[0034] Figure 15 is the formation process diagram of the first intermediate structure in an embodiment of the present disclosure;

[0035] Figure 16 is the three-dimensional diagram after forming the third photoresist layer in an embodiment of the present disclosure;

[0036] Figure 17 Schematic diagram of the formation process of the second intermediate hole in an embodiment of the present disclosure;

[0037] Figure 18 Schematic diagram of the formation process of the second intermediate structure in an embodiment of the present disclosure;

[0038] Figure 19 Stereogram after the formation of the second intermediate structure in an embodiment of the present disclosure;

[0039] Figure 20 Stereogram after the formation of the fourth photoresist layer in an embodiment of the present disclosure;

[0040] Figure 21 Schematic diagram of the formation process of the first filling hole in an embodiment of the present disclosure;

[0041] Figure 22 Schematic diagram of the thinning process of the second sacrificial layer in an embodiment of the present disclosure;

[0042] Figure 23 Schematic diagram of the formation process of the support structure in an embodiment of the present disclosure;

[0043] Figure 24 Stereogram after the formation of the fifth photoresist layer in an embodiment of the present disclosure;

[0044] Figure 25 Stereogram after the formation of the first isolation groove in an embodiment of the present disclosure;

[0045] Figure 26 Cross-sectional schematic diagram after the formation of the first filling space in an embodiment of the present disclosure;

[0046] Figure 27 Schematic diagram after the first conductive layer in an embodiment of the present disclosure;

[0047] Figure 28 Stereogram after the formation of the first isolation layer in an embodiment of the present disclosure;

[0048] Figure 29 Cross-sectional schematic diagram after the formation of the first etching hole in an embodiment of the present disclosure;

[0049] Figure 30 Cross-sectional schematic diagram after the expansion of the first etching hole in an embodiment of the present disclosure;

[0050] Figure 31 Cross-sectional schematic diagram after the transistor in an embodiment of the present disclosure;

[0051] Figure 32 Cross-sectional schematic diagram after removing the first sacrificial layer in an embodiment of the present disclosure;

[0052] Figure 33 Cross-sectional schematic diagram after forming the second isolation layer in an embodiment of the present disclosure;

[0053] Figure 34 Process diagram of forming the lower electrode in an embodiment of the present disclosure;

[0054] Figure 35 Cross-sectional schematic diagram after forming the lower electrode in an embodiment of the present disclosure.

[0055] Explanation of reference numerals:

[0056] 10 - Substrate; 11 - Substrate; 12 - Protective layer; 13 - Etch stop layer; 20 - Stacked structure; 21 - First sacrificial layer; 22 - Second sacrificial layer; 23 - Second filling hole; 24 - Third sacrificial layer; 25 - Fourth sacrificial layer; 26 - Fifth sacrificial layer; 27 - Sixth sacrificial layer; 31 - First mask layer; 32 - Second mask layer; 33 - First photoresist layer; 34 - Third mask layer; 35 - Fourth mask layer; 36 - Second photoresist layer; 37 - Fifth mask layer; 38 - Sixth mask layer; 39 - Third photoresist layer; 41 - Seventh mask layer; 42 - Eighth mask layer; 43 - Ninth mask layer; 44 - Fourth photoresist layer; 45 - Tenth mask layer; 46 - Eleventh mask layer; 47 - Fifth photoresist layer; 50 - Contact structure; 51 - Insulating layer; 52 - Conductive pillar; 53 - First intermediate hole; 54 - First intermediate structure; 55 - Second intermediate hole; 56 - Second intermediate structure; 57 - First filling hole; 58 - Support structure; 61 - First isolation groove; 62 - First filling space; 63 - First isolation layer; 64 - First isolation sublayer; 65 - Second isolation sublayer; 66 - First etch hole; 67 - Second filling space; 68 - Second isolation layer; 69 - Second etch hole; 70 - First conductive layer; 71 - First conductive sublayer; 72 - Second conductive sublayer; 73 - Bit line; 74 - Connection layer; 75 - First part; 76 - Second part; 77 - Extension part; 78 - Connection part; 80 - Transistor; 81 - Channel layer; 82 - Gate dielectric layer; 83 - Body; 84 - Epitaxial part; 85 - Gate; 86 - Channel region; 90 - Capacitor; 91 - Lower electrode layer; 92 - Lower electrode; 93 - Capacitance dielectric layer; 94 - Upper electrode; 95 - Capacitance plug. Detailed implementation manners

[0057] The embodiments of the present disclosure provide a memory. By providing a plurality of support structures penetrating multiple bit lines to support the multiple bit lines, adjacent bit lines are kept spaced apart, preventing the bit lines from collapsing and contacting each other, improving the stability of the memory manufacturing process, ensuring the performance of the memory, and increasing the yield of the memory.

[0058] In order to make the above - mentioned objects, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts belong to the scope of protection of the present disclosure.

[0059] Referring to Figures 1 to 5 , an embodiment of the present disclosure provides a memory, including a plurality of bit lines 73, a plurality of transistors 80, a plurality of capacitors 90, a plurality of contact structures 50 and a plurality of support structures 58. The plurality of bit lines 73 are arranged at intervals along a first direction. The plurality of transistors 80 are arranged at intervals along the first direction and also at intervals along a second direction, forming a transistor array with multiple rows and multiple columns. The plurality of transistors 80 along the first direction are correspondingly electrically connected to one bit line 73.

[0060] Among them, the first direction intersects with the second direction, for example, is perpendicular. Exemplarily, the first direction is the Z direction as shown in Figure 2 , and the second direction is the Y direction as shown in Figure 1 and Figure 2 . In the transistor array formed by the plurality of transistors 80, the plurality of transistors 80 along the first direction are in end - face contact with the corresponding bit lines 73. As shown in Figure 1 , the left end faces of the plurality of transistors 80 along the first direction are in contact with the right end faces of the corresponding bit lines 73.

[0061] The plurality of transistors 80 also respectively correspond to the plurality of capacitors 90, and each transistor 80 is correspondingly electrically connected to one capacitor 90. Along a third direction, the capacitors 90 and the bit lines 73 are respectively located on both sides of the transistors 80. As shown in Figure 1 , the transistors 80 are arranged between the corresponding capacitors 90 and bit lines 73. Among them, the third direction intersects with both the first direction and the second direction, that is, the first direction, the second direction and the third direction intersect pairwise, for example, are perpendicular, to improve the storage density of the memory. In the example where the first direction is the Z direction as shown in Figure 2 , the second direction is the Y direction as shown in Figure 1 and Figure 2 , the third direction is the X direction as shown in Figure 1 .

[0062] The plurality of contact structures 50 respectively correspond to the plurality of bit lines 73, and each contact structure 50 is correspondingly connected to one bit line 73 to externally connect each bit line 73. The plurality of contact structures 50 are arranged at intervals along the second direction. Along the first direction, one end ( Figure 2 the upper end as shown) of the plurality of contact structures 50 extends outside the plurality of bit lines 73, and the other end (Figure 2 The lower end shown penetrates the partial bit line 73 and is in corresponding contact with one of the bit lines 73. The surfaces of the multiple contact structures 50 in corresponding contact with the bit line 73 form a stepped shape.

[0063] It can be understood that the contact structure 50 corresponding to each bit line 73 penetrates the bit line 73 on one side (e.g., above) of the bit line 73 and is insulated from the bit line 73 above the bit line 73, so as to achieve electrical connection between the corresponding contact structure 50 and the bit line 73 and electrical isolation from other bit lines 73. The bit line 73 located at the bottommost along the first direction is not penetrated, and the contact structure 50 corresponding to the bit line 73 penetrates the remaining bit lines 73 and is insulated from all the remaining bit lines 73. The contact structure 50 corresponding to the bit line 73 located at the topmost along the first direction does not penetrate any bit line 73.

[0064] Exemplarily, there are N bit lines 73, and N is a positive integer greater than 1. Along Figure 2 the direction from top to bottom as shown, these N bit lines are the 1st bit line, the 2nd bit line,..., the Nth bit line in sequence, and the 1st bit line and the Nth bit line are respectively located outside these N bit lines 73. The number of contact structures 50 is greater than or equal to N. For example, there are N contact structures 50, and these N contact structures 50 are the 1st contact structure, the 2nd contact structure,..., the Nth contact structure respectively. Among them, the ith contact structure is in corresponding contact with the ith bit line and is electrically insulated from other bit lines 73, where i is greater than or equal to 1 and less than N.

[0065] Specifically, the 1st contact structure is in corresponding contact with the 1st bit line, the 2nd contact structure is in corresponding contact with the 2nd bit line, the 3rd contact structure is in corresponding contact with the 3rd bit line, and so on. The Nth contact structure is in corresponding contact with the Nth bit line. To achieve the contact between the corresponding contact structure 50 and the bit line 73, the ith contact structure penetrates the bit lines 73 above the ith bit line. That is, the 2nd contact structure penetrates the 1st bit line to achieve the contact between the lower end of the 2nd contact structure and the 2nd bit line. The 3rd contact structure penetrates the 2nd bit line and the 1st bit line to achieve the contact between the lower end of the 3rd contact structure and the 3rd bit line, and so on.

[0066] In some examples, the side walls of some contact structures 50 opposite to the bit line 73 are recessed from the side walls of the remaining contact structures 50, so that the side walls of the contact structures 50 are wavy. With such a setting, the contact structure 50 contacts the side surface of the corresponding bit line 73 and can also contact the surface part opposite to the corresponding bit line 73 along the first direction, increasing the contact area between the contact structure 50 and the corresponding bit line 73 and reducing the contact resistance between the contact structure 50 and the corresponding bit line 73.

[0067] Continue to refer to Figure 1 and 2, a plurality of support structures 58 are arranged at intervals in the second direction, and the plurality of support structures 58 all penetrate through a plurality of bit lines 73 to provide support for all the bit lines 73, avoid the collapse of related film layers during the manufacturing process of the bit lines 73, and ensure the quality of the bit lines 73. Along the second direction, there is at least one support structure 58 between two adjacent contact structures 50 to improve the uniformity of the distribution of the support structures 58 and the support effect. Among them, the plurality of support structures 58 and the plurality of contact structures 50 can be arranged at intervals in the second direction. For example, along the third direction, the plurality of support structures 58 and the plurality of contact structures 50 are respectively located in a column of a plurality of transistors 80 along the first direction. As Figure 1 shown, five columns of transistors 80 in six columns of transistors 80 respectively correspond to one support structure 58, and the other column of transistors 80 corresponds to the contact structure 50.

[0068] Taking the plane perpendicular to the first direction as the cross-section, the cross-sectional shape of the support structure 58 can be rectangular, circular, elliptical, etc. The cross-sectional size of the support structure 58 is larger than the cross-sectional size of the contact structure 50, so that the support structure 58 is relatively thick and has a good support effect. The material of the support structure 58 can be a low dielectric constant (low-k) material.

[0069] In some possible examples, refer to Figure 3 and Figure 4 , a plurality of first annular grooves are formed on the side walls of at least some of the support structures 58, and the plurality of first annular grooves are arranged at intervals in the first direction. The first annular grooves surround the side walls of the support structures 58, that is, the first annular grooves are formed on the outer peripheral surface of the support structures 58 to accommodate part of the bit lines 73. For example, the plurality of first annular grooves on one support structure 58 respectively correspond to a plurality of bit lines 73, and each bit line 73 includes a first part 75 filled in the first annular groove and a second part 76 located outside the first annular groove. Along the first direction, the thickness of the first part 75 is less than the thickness of the second part 76.

[0070] Among them, along the first direction, the thickness of the first part 75 is less than the thickness of the second part 76, that is, the first part 75 is thinner and the second part 76 is thicker. With such a setting, along the first direction, the distance between two adjacent first parts 75 is greater than the distance between two adjacent second parts 76, reducing the parasitic capacitance between the first parts 75.

[0071] In some examples, the second part 76 can completely surround or the first part 75, that is, the second part 76 circumferentially surrounds the first part 75, and both the support structure 58 and the contact structure 50 penetrate through the second part 76. The outer peripheral surface of the first part 75 is in contact with the inner peripheral surface of the second part 76, and the inner peripheral surface of the second part 76 covers the outer peripheral surface of the first part 75 to increase the contact area between the first part 75 and the second part 76 and reduce the manufacturing difficulty of the bit lines 73.

[0072] In some other examples, refer to Figure 5 and Figure 6 , the second part 76 can partially surround the first part 75. For example, the second part 76 includes an extension 77 and a connection part 78. The connection part 78 connects two adjacent first parts 75 along the second direction. The extension 77 connects the transistor 80 and the first part 75 or the connection part 78 opposite to the transistor 80. As Figure 5 shown, the connection part 78 connects two adjacent first parts 75 along the second direction, and the contact structure 50 penetrates through the connection part 78. The extension 77 is located between the first part 75 and the transistor 80, or between the connection part 78 and the transistor 80. With such an arrangement, the volume of the support structure 58 can be increased to provide stable support for the bit line 73.

[0073] It can be understood that when the transistor 80 and the support structure 58 are opposite to each other along the third direction, both ends of the extension 77 are respectively connected to the transistor 80 and the first part 75. When the transistor 80 and the contact structure 50 are opposite to each other along the third direction, both ends of the extension 77 are respectively connected to the transistor 80 and the connection part 78. Along the second direction, the width of the extension 77 can be smaller than the width of the first part 75.

[0074] In order to improve the storage density of the memory, in some examples, as Figure 1 and Figure 5 shown, along the third direction, a plurality of transistors 80 and a plurality of capacitors 90 are arranged on both sides of a plurality of bit lines 73, and the plurality of transistors 80 and the plurality of capacitors 90 on the same side are correspondingly electrically connected. Among them, a plurality of transistors 80 are arranged on both sides of each bit line 73 along the third direction, and the plurality of transistors 80 on each side along the second direction are correspondingly connected to one bit line 73. A transistor array is arranged on each of the two sides of the plurality of bit lines 73 along the third direction, and the transistors 80 in the same row in the two transistor arrays are correspondingly connected to one bit line 73, that is, the two transistor arrays share the bit line 73 to improve the utilization rate of the memory space and the storage density.

[0075] One side of each transistor 80 away from the bit line 73 is correspondingly electrically connected to a capacitor 90. As Figure 1 shown, along the third direction, the capacitors 90, transistors 80, bit lines 73, transistors 80, and capacitors 90 are arranged in sequence. The transistors 80, capacitors 90, and bit lines 73 can be symmetrically distributed along the third direction to improve the structural symmetry and compactness of the memory.

[0076] Continue to refer to Figure 3 , Figure 4 and Figure 5, in some examples, the memory further includes a plurality of word lines spaced apart along a second direction. For example, each word line extends along a first direction. Each word line corresponds to a plurality of transistors 80 along the first direction and forms the gate 85 of the corresponding transistor 80. Each transistor 80 includes a gate dielectric layer 82 surrounding the corresponding gate 85 and a channel region 86 surrounding the gate dielectric layer 82. The channel region 86 is correspondingly connected to the bit line 73 and the capacitor 90.

[0077] Among them, each word line is surrounded by a gate dielectric layer 82, and a channel region 86 is surrounded on the gate dielectric layer 82. The transistor 80 forms a Channel all Around (CAA) transistor 80 to improve the control ability of the gate 85 over the channel region 86. A plurality of channel regions 86 are surrounded on the same gate dielectric layer 82. The plurality of channel regions 86 are spaced apart along the first direction. Each channel region 86 is correspondingly connected to the bit line 73 and the capacitor 90 on both sides along the third direction. The material of the channel region 86 may include Indium Gallium Zinc Oxide (IGZO), which has a high carrier mobility and improves the performance of the channel region 86.

[0078] Continue to refer to Figure 3 and Figure 4 , in some examples, the gate dielectric layer 82 includes a main body 83 surrounding the gate 85 and epitaxial portions 84 connected to both ends of the main body 83 along the first direction. The epitaxial portions 84 of two adjacent gate dielectric layers 82 along the first direction are in contact with each other, and the plurality of gate dielectric layers 82 along the first direction form an integral body. Among them, the main body 83 surrounds the gate 85 and is in contact with the gate 85, that is, the main body 83 is sleeved on the gate 85. Along the first direction, one epitaxial portion 84 is connected to each of the opposite ends of the main body 83, and the main body 83 and the corresponding two epitaxial portions 84 enclose a third annular groove. Along the first direction, the opposite surfaces of the epitaxial portions 84 of two adjacent gate dielectric layers 82 are in contact with each other, so that the plurality of gate dielectric layers 82 along the first direction are of an integral structure, which is convenient for the formation of the gate dielectric layer 82.

[0079] Based on the above examples, the channel region 86 covers the opposite surfaces of the corresponding epitaxial portions 84 and the outer peripheral surface of the main body. The channel region 86 encloses a second annular groove. Along the third direction, the bit line 73 and the connection layer 74 are respectively arranged on both sides of the channel region 86, and the bit line 73 and the connection layer 74 extend into the second annular groove and are in corresponding contact with the surface of the second annular groove. The transistor 80 is also in corresponding contact with the capacitor 90.

[0080] Among them, the channel region 86 conformally covers the sidewall and bottom wall of the third annular groove to increase the area of the channel region 86. The channel region 86 located within the third annular groove encloses a second annular groove. The bottom wall of the third annular groove is the outer peripheral surface of the body, and the sidewalls of the third annular groove are the opposite surfaces of the two extension portions 77 at both ends of the body.

[0081] Along the third direction, both sides of the channel region 86 are respectively connected to the bit line 73 and the connection layer 74, and the bit line 73 and the connection layer 74 are independent of each other. The opposite ends of the bit line 73 and the connection layer 74 respectively extend into the second annular groove and are adapted to the second annular groove. In some examples, the second annular groove is a rectangular annular groove, that is, taking a plane perpendicular to the first direction as the cross-section, the cross-sectional shape of the second annular groove is a rectangular ring. The rectangular annular groove includes four groove segments connected end to end in sequence. The bit line 73 and the connection layer 74 are respectively located in two groove segments opposite to each other along the third direction. Along the first direction, the bit line 73 and the connection layer 74 fill the corresponding groove segments and extend out of the corresponding groove segments, that is, both the bit line 73 and the connection layer 74 are in contact with the bottom wall and sidewalls of the corresponding groove segments to increase the contact area between the bit line 73 and the channel region 86, and between the connection layer 74 and the channel region 86. Along the second direction, the lengths of the bit line 73 and the connection layer 74 are both less than the length of the corresponding groove segment.

[0082] Continue to refer to Figures 1 to 5 , the capacitor 90 includes an upper electrode 94, a capacitive dielectric layer 93 surrounding the upper electrode 94, and a lower electrode 92 surrounding the capacitive dielectric layer 93, that is, the capacitor 90 is a columnar capacitor, and the lower electrode 92 is electrically connected to the transistor 80 through the connection layer 74. In order to increase the surface area of the lower electrode 92 to increase the capacitance of the capacitor 90, a fourth annular groove is formed on the inner peripheral surface of the lower electrode 92. The capacitive dielectric layer 93 at least covers the sidewall and bottom wall of the fourth annular groove. The capacitive dielectric layer 93 located within the fourth annular groove encloses a fifth annular groove, and the upper electrode 94 at least covers the sidewall and bottom wall of the fifth annular groove.

[0083] In some examples, multiple upper electrodes 94 along the first direction are integrated, multiple capacitive dielectric layers 93 along the first direction are integrated, and multiple lower electrodes 92 along the first direction are arranged at intervals. Among them, along the second direction, a sixth annular groove is formed between two adjacent lower electrodes 92, and the depth of the sixth annular groove can be greater than the depth of the fourth annular groove. The capacitive dielectric layer 93 also covers the sidewall and bottom wall of the sixth annular groove and the inner peripheral surface of the lower electrode 92 to form an integral body. The upper electrode 94 conformally covers the capacitive dielectric layer 93 to form an integral body.

[0084] To achieve the external connection of the capacitor 90, the memory further includes capacitor plugs 95, which are arranged at intervals along the second direction and are electrically connected to the upper electrode 94. For example, the upper electrode 94 surrounds the corresponding capacitor plug 95. For ease of fabrication, the material of the capacitor plug 95 can be polysilicon, and the materials of the upper electrode 94 and the lower electrode 92 can be metal or its compound, such as titanium nitride, etc., and the material of the capacitor dielectric layer 93 can be a high dielectric constant (high-k) material, such as hafnium oxide, etc.

[0085] In summary, in the memory according to the embodiments of the present disclosure, by providing a plurality of support structures 58 penetrating through a plurality of bit lines 73 to support the plurality of bit lines 73, adjacent two bit lines 73 are kept at intervals, avoiding the collapse and contact of the bit lines 73, improving the stability in the memory fabrication process, ensuring the performance of the memory, and improving the yield of the memory.

[0086] The embodiments of the present disclosure also provide a method for fabricating a memory. Refer to Figures 7 to 35 , the fabrication method includes:

[0087] Step S100: Form a stacked structure on a substrate, the stacked structure including a plurality of first sacrificial layers and a plurality of second sacrificial layers alternately arranged along a first direction.

[0088] The substrate 10 provides support for the structures thereon (such as the contact structure 50, the bit line 73, etc.). The substrate 10 may include a substrate 11, a protective layer 12, and an etch stop layer 13 arranged in sequence. Before forming the protective layer 12, the substrate 11 may be cleaned first. The material of the substrate 11 may be a semiconductor material such as single crystal silicon, polysilicon, germanium, germanium silicon, silicon on insulator (SOI for short), or germanium on insulator (GOI for short). The material of the protective layer 12 may be silicon oxide, and the material of the etch stop layer 13 may be aluminum oxide. Its material is relatively hard and can also be used as a hard mask layer.

[0089] Refer to Figure 8 and Figure 9 , the stacked structure 20 is formed on the substrate 10, which includes a plurality of first sacrificial layers 21 and a plurality of second sacrificial layers 22, and the first sacrificial layer 21 and the plurality of second sacrificial layers 22 are alternately arranged along the first direction. Among them, the first direction may be the Figure 8 Z direction shown, the material of the first sacrificial layer 21 may be an oxide, such as silicon oxide, and the material of the second sacrificial layer 22 may be a nitride, such as silicon nitride. The first sacrificial layer 21 may be located on the substrate 10.

[0090] Step S200: Form a plurality of contact structures, a plurality of first intermediate structures, and a plurality of second intermediate structures within the stacked structure; wherein, the plurality of contact structures, the plurality of first intermediate structures, and the plurality of second intermediate structures are all arranged at intervals along the second direction, and along the third direction, the plurality of second intermediate structures are located on a side of the plurality of first intermediate structures away from the plurality of contact structures, each contact structure correspondingly contacts one layer of the second sacrificial layer, the first intermediate structures and the second intermediate structures both penetrate through the stacked structure, and the first direction, the second direction, and the third direction are pairwise crossed.

[0091] Refer to Figures 8 to 19 , etch away a part of the stacked structure 20 and backfill to form a plurality of contact structures 50, a plurality of first intermediate structures 54, and a plurality of second intermediate structures 56. The contact structures 50 are used to externally connect the bit lines 73, the first intermediate structures 54 are used to form transistors 80, and the second intermediate structures 56 are used to form capacitors 90.

[0092] Among them, the plurality of contact structures 50 are arranged at intervals along the second direction, the plurality of first intermediate structures 54 are arranged at intervals along the second direction, and the plurality of second intermediate structures 56 are arranged at intervals along the second direction, that is, the plurality of contact structures 50 form a row along the second direction, the plurality of first intermediate structures 54 form a row along the second direction, and the plurality of second intermediate structures 56 form a row along the second direction. And along the third direction, the plurality of second intermediate structures 56 are located on a side of the plurality of first intermediate structures 54 away from the plurality of contact structures 50, that is, along the third direction, the contact structures 50, the first intermediate structures 54, and the second intermediate structures 56 are arranged in sequence. The first direction, the second direction, and the third direction are pairwise crossed, for example, perpendicular. Exemplarily, the first direction is like Figure 8 the Z direction shown in Figure 8 , the second direction is like Figure 8 the Y direction shown in

[0093] In some possible examples, the plurality of first intermediate structures 54 and the plurality of second intermediate structures 56 may be symmetrically arranged relative to the plurality of contact structures 50 to improve the compactness of the memory and increase the storage capacity. As Figure 18 shown, first intermediate structures 54 are respectively formed on two opposite sides of the contact structure 50 along the third direction, and second intermediate structures 56 are respectively formed on sides of the first intermediate structures 54 away from the contact structure 50. Along the third direction, the second intermediate structures 56, the first intermediate structures 54, the contact structure 50, the first intermediate structures 54, and the second intermediate structures 56 are arranged in sequence.

[0094] Step S300: Form at least one support structure between two adjacent contact structures along the second direction, and the support structure at least penetrates through the stacked structure.

[0095] Refer to Figures 20 to 22The support structure 58 runs through the stacked structure 20. When the second sacrificial layer 22 is subsequently removed, the first sacrificial layers 21 arranged at intervals can be supported to prevent the adjacent first sacrificial layers 21 from collapsing or even contacting each other, thereby ensuring space for filling the bit lines 73. Along the second direction, there is at least one support structure 58 between two adjacent contact structures 50 to improve the uniformity of the distribution of the support structures 58 and improve the support effect. Among them, multiple support structures 58 and multiple contact structures 50 can be arranged at intervals along the second direction, and the multiple support structures 58 and multiple contact structures 50 correspond to multiple first intermediate structures 54 respectively.

[0096] Taking the plane perpendicular to the first direction as the cross section, the cross-sectional shape of the support structure 58 can be rectangular, circular, elliptical, etc. The cross-sectional size of the support structure 58 is larger than the cross-sectional size of the contact structure 50, so that the support structure 58 is relatively strong and has a better supporting effect. The material of the support structure 58 can be a low dielectric constant material.

[0097] Step S400: remove part of the laminated structure between two adjacent first intermediate structures and two adjacent second intermediate structures along the second direction to form first isolation grooves that penetrate the laminated structure and are alternately arranged with the first intermediate structures; along the third direction, one end of the first isolation groove facing the supporting structure protrudes from one end of the first intermediate structure facing the supporting structure, and one end of the first isolation groove facing away from the supporting structure penetrates the laminated structure.

[0098] See also Figures 23 to 25 , the first isolation groove 61 is used to isolate two first intermediate structures 54 adjacent to each other along the second direction, and two second intermediate structures 56 adjacent to each other along the second direction. Along the third direction, the end of the first isolation groove 61 away from the support structure 58 extends to the end of the stacked structure 20 away from the support structure 58 to form an opening, and the distance between the end of the first isolation groove 61 facing the support structure 58 and the support structure 58 is smaller than the distance between the end of the first intermediate structure 54 facing the support structure 58 and the support structure 58.

[0099] Combine the following Figure 23 and Figure 24 , a formation process of the first isolation groove 61 is described.

[0100] See also Figure 23 , a fourth sacrificial layer 25, a tenth mask layer 45, an eleventh mask layer 46 and a fifth photoresist layer 47 are sequentially deposited on the stacked structure 20, and the fifth photoresist layer 47 has a fifth mask pattern. Among them, the material of the fourth sacrificial layer 25 can be silicon oxide, which is formed by at least two depositions. The tenth mask layer 45 is a hard mask layer, and its material can be amorphous carbon (Amorphous Carbon Layer, referred to as ACL). The eleventh mask layer 46 is a conventional mask layer, and its material can be silicon oxynitride.

[0101] Refer to Figure 24 Using the fifth photoresist layer 47 as a mask, etch the underlying film layer until the substrate 10 to form a plurality of first isolation grooves 61.

[0102] Remove the film layer above the fourth sacrificial layer 25 to expose the fourth sacrificial layer 25. During the formation of the first isolation grooves 61, at least part of the fifth photoresist layer 47 is removed. After the formation of the first isolation grooves 61, remove all the film layers on the fourth sacrificial layer 25. The fourth sacrificial layer 25 covers at least the support structure 58 and the second intermediate structure 56, which can be protected by it and can be used as a mask.

[0103] It can be understood that in the example where the third sacrificial layer 24 is provided on the stacked structure 20, the fourth sacrificial layer 25, the tenth mask layer 45, the eleventh mask layer 46, and the fifth photoresist layer 47 are sequentially deposited on the third sacrificial layer 24. Among them, the third sacrificial layer 24 covers the contact structure 50 and the first intermediate structure 54, and the fourth sacrificial layer 25 covers the third sacrificial layer 24, the support structure 58, and the second intermediate structure 56. The subsequent process is the same as the process of directly forming on the stacked structure 20, which will not be elaborated here.

[0104] Step S500: Remove the remaining second sacrificial layer to form a first filling space.

[0105] Refer to Figure 25 and Figure 26 Using the first isolation grooves 61, etch and remove the exposed second sacrificial layer 22 to remove all of the second sacrificial layer 22 and form a first filling space 62, and the first filling space 62 communicates with the first isolation grooves 61.

[0106] Step S600: Form a first conductive layer in the first filling space. The first conductive layer located between the support structures, between the support structure and the contact structure, and between the support structure or the contact structure and the first intermediate structure forms a bit line, and the first conductive layer located between the first intermediate structure and the second intermediate structure forms a connection layer.

[0107] Refer to Figure 26 and Figure 27 and

[0108] It can be understood that along the third direction, part of the first intermediate structure 54 faces the support structure 58, and another part of the first intermediate structure 54 faces the contact structure 50. A bit line 73 is connected between the support structure 58 and the opposite first intermediate structure 54, and a bit line 73 is also connected between the first intermediate structure 54 opposite to the contact structure 50, so as to ensure that each first intermediate structure 54 is connected to the bit line 73. A first conductive layer 70 is also formed on the side of the second intermediate structure 56 away from the first intermediate structure 54. This part of the first conductive layer 70 is only used to fill between adjacent first sacrificial layers 21 and does not conduct signal transmission.

[0109] In some possible implementation manners, forming the first conductive layer 70 in the first filling space 62 includes: depositing a first conductive sub-layer 71 on the side wall and bottom wall of the first isolation groove 61 and on the inner wall of the first filling space 62, and depositing a second conductive sub-layer 72 on the first conductive sub-layer 71, and the second conductive sub-layer 72 fills the remaining first filling space 62; removing the first conductive sub-layer 71 and the second conductive sub-layer 72 in the first isolation groove 61, and the remaining first conductive sub-layer 71 and second conductive sub-layer 72 form the first conductive layer 70.

[0110] Wherein, the material of the first conductive sub-layer 71 can be titanium nitride, and the material of the second conductive sub-layer 72 can be tungsten. When removing the first conductive sub-layer 71 and the second conductive sub-layer 72 in the first isolation groove 61, partial regions at both ends of the first conductive sub-layer 71 and the second conductive sub-layer 72 in the first filling space 62 along the second direction will be removed. At this time, part of the region of the first isolation groove 61 expands to between adjacent first sacrificial layers 21.

[0111] Step S700: Form a first isolation layer in the first isolation groove, and the first isolation layer fills the first isolation groove.

[0112] Refer to Figure 28 , the first isolation layer 63 can be a NON structure to improve the isolation effect. In some possible implementation manners, the first isolation layer 63 can be formed through the following process: depositing a first isolation sub-layer 64 in the first isolation groove 61, and the first isolation sub-layer 64 covers the side wall and bottom wall of the first isolation layer 63; depositing a second isolation sub-layer 65 in the remaining first isolation groove 61, and the second isolation sub-layer 65 fills the first isolation groove 61, and the first isolation sub-layer 64 and the second isolation sub-layer 65 form the first isolation layer 63. The material of the first isolation sub-layer 64 is silicon nitride, and the material of the second isolation sub-layer 65 is silicon oxide.

[0113] In some examples, the first isolation layer 64 also covers the fourth sacrificial layer 25. After forming the second isolation layer 65, the first isolation layer 64 and the second isolation layer 65 on the fourth sacrificial layer 25 are removed, and then the fifth sacrificial layer 26 is formed. After planarizing the fifth sacrificial layer 26, the material of the fifth sacrificial layer 26 is the same as that of the second isolation layer 65, so as to facilitate the subsequent removal of the fifth sacrificial layer 26 and the second isolation layer 65 together. The material of the fifth sacrificial layer 26 and the material of the second isolation layer 65 are also the same as the material of the seventh mask layer 41, so as to facilitate the subsequent removal.

[0114] Step S800: Remove the first intermediate structure to form a plurality of transistors arranged at intervals along the first direction, remove the second intermediate structure to form a plurality of capacitors arranged at intervals along the second direction, and remove the remaining first sacrificial layer to form a second isolation layer. Along the third direction, each transistor is connected to a capacitor through a connection layer.

[0115] Refer to Figures 29 to 35 , each transistor 80 includes a gate 85, a gate dielectric layer 82 surrounding the corresponding gate 85, and a channel region 86 surrounding the gate dielectric layer 82, that is, the transistor 80 is a fully-depleted surround-gate transistor 80 to improve the control ability of the gate 85 over the channel region 86. The gates 85 of the transistors 80 along the first direction are formed integrally and serve as word lines. The material of the channel region 86 may include indium gallium zinc oxide, which has a high carrier mobility to improve the performance of the channel region 86.

[0116] Each capacitor 90 includes an upper electrode 94, a capacitive dielectric layer 93 surrounding the upper electrode 94, and a lower electrode 92 surrounding the capacitive dielectric layer 93, that is, the capacitor 90 is a columnar capacitor, and the lower electrode 92 is electrically connected to the channel region 86 of the transistor 80 through a connection layer 74. The plurality of upper electrodes 94 along the first direction are formed integrally, and the plurality of capacitive dielectric layers 93 along the first direction are formed integrally.

[0117] In some possible implementation manners, as Figures 29 to 35 shown, removing the first intermediate structure 54 to form a plurality of transistors 80 arranged at intervals along the first direction, removing the second intermediate structure 56 to form a plurality of capacitors 90 arranged at intervals along the second direction, and removing the remaining first sacrificial layer 21 to form a second isolation layer 68 (step S800) includes:

[0118] Step S801: Use a patterning process to form a first etch hole 66 in each first intermediate structure 54, and use a first etch to remove the remaining first intermediate structure 54. Among them, the first etch hole 66 at least penetrates the corresponding first intermediate structure 54. In an example where the substrate 10 includes a substrate 11, a protective layer 12, and an etch stop layer 13, the first etch hole 66 also penetrates the etch stop layer 13 to expose the protective layer 12.

[0119] Step S802: Form a channel layer 81, a gate capacitance dielectric layer, and a gate 85. The channel layer 81 covers the sidewalls and the bottom wall of the first etching hole 66. The gate dielectric layer 82 covers the channel layer 81. The gate 85 covers the initial gate dielectric layer 82 and fills the remaining first etching hole 66. Among them, the channel layer 81, the gate dielectric layer 82, and the gate 85 can be formed by deposition and back-etching. The channel layer 81 conformally covers the sidewalls and the bottom wall of the first etching hole 66. The gate dielectric layer 82 conformally covers the channel layer 81. In an example where the stacked structure 20 is provided with a fourth sacrificial layer 25, the channel layer 81 also covers the top surface of the fourth sacrificial layer 25.

[0120] Step S803: Use a patterning process to form a second isolation groove in each first isolation layer 63. The second isolation groove is located within the first isolation groove 61, and the second isolation groove exposes the first sacrificial layer 21. In an example where the first isolation layer 63 includes a first isolation sub-layer 64 and a second isolation sub-layer 65, etch a part of the second isolation sub-layer 65 to form an initial second isolation groove. The initial second isolation groove exposes the first isolation sub-layer 64 and the remaining second isolation sub-layer 65, and then etch the first isolation sub-layer 64 exposed in the initial second isolation groove to form the second isolation groove. The remaining second isolation sub-layer 65 and the remaining first isolation sub-layer 64 are located between adjacent first sacrificial layers 21.

[0121] Step S804: Use the second isolation groove to etch away the remaining first sacrificial layer 21 to form a second filling space 67, and etch away the channel layer 81 exposed in the second filling space 67. The remaining channel layer 81 forms a plurality of channel regions 86 spaced apart along the first direction. Among them, the second filling space 67 communicates with the second isolation groove.

[0122] Step S805: Form a second isolation layer 68 in the second filling space 67 and the second isolation groove. The second isolation layer 68 fills the second filling space 67 and the second isolation groove. Among them, the second isolation layer 68 can be formed by deposition and back-etching. A part of the second isolation layer 68 is used to isolate adjacent first conductive layers 70, and another part of the second isolation layer 68 and the first isolation layer 63 are used to isolate two transistors 80 adjacent along the second direction or two capacitors 90 adjacent along the second direction formed subsequently.

[0123] Step S806: Use a patterning process to form a second etching hole 69 in each second intermediate structure 56, and use the second etching to remove the remaining second intermediate structure 56. Among them, the second etching hole 69 at least penetrates the corresponding second intermediate structure 56. In an example where the substrate 10 includes a substrate 11, a protective layer 12, and an etch stop layer 13, the second etching hole 69 also penetrates the etch stop layer 13 to expose the protective layer 12.

[0124] Step S807: Form a lower electrode layer 91 on the sidewall and bottom wall of the second etching hole 69, and remove the part of the lower electrode layer 91 that contacts the inner peripheral surface of the second isolation layer 68. The remaining lower electrode layer 91 forms a plurality of lower electrodes 92 arranged at intervals along the first direction. As Figure 34 shown, the second etching hole 69 is wavy. The sixth sacrificial layer 27 is used to protect the protruding part of the lower electrode layer 91, so that the lower electrode layer 91 is disconnected along the first direction to form the lower electrode 92.

[0125] Step S808: Form a capacitive dielectric layer 93 on the sidewall and bottom wall of the second etching hole 69 where the lower electrode 92 is formed, form an upper electrode 94 on the capacitive dielectric layer 93, and form a capacitive plug 95 on the upper electrode 94. The capacitive plug 95 fills the second etching hole 69.

[0126] In summary, the method for manufacturing a memory in the embodiments of the present disclosure includes: forming a stacked structure 20 on a substrate 10, the stacked structure 20 including a plurality of first sacrificial layers 21 and a plurality of second sacrificial layers 22 alternately arranged in sequence along a first direction, and the first sacrificial layer 21 is located on the substrate 10; forming a plurality of contact structures 50, a plurality of first intermediate structures 54, and a plurality of second intermediate structures 56 in the stacked structure 20; wherein, the plurality of contact structures 50, the plurality of first intermediate structures 54, and the plurality of second intermediate structures 56 are all spaced apart along a second direction, and along a third direction, the plurality of second intermediate structures 56 are located on a side of the plurality of first intermediate structures 54 away from the plurality of contact structures 50, each contact structure 50 correspondingly contacts one layer of the second sacrificial layer 22, both the first intermediate structure 54 and the second intermediate structure 56 penetrate the stacked structure 20, and the first direction, the second direction, and the third direction are pairwise cross; forming at least one support structure 58 between two adjacent contact structures 50 along the second direction, the support structure 58 at least penetrates the stacked structure 20; removing a part of the stacked structure 20 between two adjacent first intermediate structures 54 and two adjacent second intermediate structures 56 along the second direction to form a first isolation groove 61 penetrating the stacked structure 20 and alternately arranged with the first intermediate structure 54; removing the remaining second sacrificial layer 22 to form a first filling space 62, and forming a first conductive layer 70 in the first filling space 62, the first conductive layer 70 located between the support structures 58, between the support structure 58 and the contact structure 50, and between the support structure 58 or the contact structure 50 and the first intermediate structure 54 forms a bit line 73, and the first conductive layer 70 located between the first intermediate structure 54 and the second intermediate structure 56 forms a connection layer 74; forming a first isolation layer 63 in the first isolation groove 61, and the first isolation layer 63 fills the first isolation groove 61; removing the first intermediate structure 54 to form a plurality of transistors 80 spaced apart along the first direction, removing the second intermediate structure 56 to form a plurality of capacitors 90 spaced apart along the second direction, and removing the remaining first sacrificial layer 21 to form a second isolation layer 68, along the third direction, each transistor 80 is connected to one capacitor 90 through the connection layer 74. By using the plurality of support structures 58 to support the adjacent first sacrificial layers 21, the adjacent two first sacrificial layers 21 are kept spaced apart, so as to keep the space for forming the bit line 73. After the bit line 73 is formed, the collapse and contact of the bit line 73 are avoided, the stability of the memory manufacturing process is improved, the performance of the memory is ensured, and the yield of the memory is increased. In addition, the first isolation layer 63 and the second isolation layer 68 can ensure the insulation isolation between the bit lines 73 adjacent along the first direction, and the insulation isolation between two adjacent transistors 80 and two adjacent capacitors 90 adjacent along the second direction, so as to ensure the performance of the memory.

[0127] In some possible examples, refer to Figures 8 to 19, forming a plurality of contact structures 50, a plurality of first intermediate structures 54, and a plurality of second intermediate structures 56 in the stacked structure 20 (step S200), including:

[0128] Step S201: Etch the stacked structure 20 to form a plurality of second filling holes 23 spaced along a second direction, and each second filling hole 23 correspondingly exposes a second sacrificial layer 22.

[0129] Refer to Figure 10 and Figure 11 , the depths of the plurality of second filling holes 23 can be different, so that at least one second filling hole 23 correspondingly exposes a second sacrificial layer 22 therein, that is, each second sacrificial layer 22 is at least exposed in one second filling hole 23. Exemplarily, the depths of the plurality of second filling holes 23 are different from each other, and the plurality of second filling holes 23 correspond to the plurality of second sacrificial layers 22 one by one. Each second filling hole 23 correspondingly exposes a second sacrificial layer 22 therein, and each second sacrificial layer 22 is correspondingly exposed in one second filling hole 23.

[0130] Refer to Figure 10 and Figure 11 , in some possible implementation manners, the plurality of second filling holes 23 can be formed through the following steps:

[0131] Step S2011: Sequentially form a first mask layer 31, a second mask layer 32, and a first photoresist layer 33 on the stacked structure 20, and the first photoresist layer 33 has a first mask pattern.

[0132] The first mask layer 31 covers the stacked structure 20, the second mask layer 32 covers the first mask layer 31, and the first photoresist layer 33 covers the second mask layer 32. The first mask layer 31 is a hard mask layer, and its material can be silicon nitride, and the second mask layer 32 is a conventional mask layer, and its material can be silicon oxynitride. The thickness of the first mask layer 31 can be greater than the thickness of the second mask layer 32.

[0133] Step S2012: Using the first photoresist layer 33 as a mask, etch the second mask layer 32, the first mask layer 31, and the stacked structure 20 to form a plurality of second filling holes 23 in the stacked structure 20.

[0134] Exemplarily, the depths of the respective second filling holes 23 are all different, so that each of the second sacrificial layers 22 can correspondingly be exposed in one second filling hole 23, so as to ensure that each second sacrificial layer 22 can be in contact with the subsequently formed contact structure 50 after replacement, thereby ensuring that each bit line 73 formed after replacement of each second sacrificial layer 22 can be externally connected through the corresponding contact structure 50.

[0135] Step S2013: Remove the film layer on the stacked structure 20 to expose the stacked structure 20.

[0136] In some examples, the film layers on the stacked structure 20 include a first mask layer 31, a second mask layer 32, and a first photoresist layer 33. Correspondingly, the first mask layer 31, the second mask layer 32, and the first photoresist layer 33 are removed to expose the stacked structure 20. In other examples, the first photoresist layer 33 is etched away while forming the plurality of second filling holes 23. The film layers on the stacked structure 20 include the first mask layer 31 and the second mask layer 32. Correspondingly, the first mask layer 31 and the second mask layer 32 are removed to expose the stacked structure 20. In still other examples, the first photoresist layer 33 and the second mask layer 32 are etched away while forming the plurality of second filling holes 23. The film layer on the stacked structure 20 is the first mask layer 31. Correspondingly, the first mask layer 31 is removed to expose the stacked structure 20.

[0137] Step S202: A contact structure 50 is formed in the second filling hole 23, and the contact structure 50 fills the corresponding second filling hole 23.

[0138] Refer to Figure 12 , the contact structure 50 includes an insulating layer 51 and a conductive pillar 52, and the insulating layer 51 is filled between the conductive pillar 52 and the second filling hole 23. The material of the insulating layer 51 can be silicon oxide or a low dielectric constant material, such as hafnium oxide, etc. The material of the conductive pillar 52 can be a metal, such as tungsten.

[0139] Providing the insulating layer 51 can prevent the conductive pillar 52 from contacting other second sacrificial layers 22, thereby isolating the conductive pillar 52 from the second sacrificial layer 22 on the sidewall of the second filling hole 23 formed, so that each conductive pillar 52 only contacts the second sacrificial layer 22 at the bottom of the corresponding second filling hole 23, ensuring the correspondence between the contact structure 50 and the subsequent formed bit line 73, and avoiding one contact structure 50 being electrically connected to multiple bit lines 73.

[0140] Refer to Figure 12 , in some possible implementation manners, the insulating layer 51 is deposited on the sidewall and the bottom wall of the second filling hole 23, and on the stacked structure 20. The insulating layer 51 located in the second filling hole 23 encloses a third filling hole. The insulating layer 51 is etched back to remove the insulating layer 51 on the stacked structure 20 and the bottom wall of the second filling hole 23, and the insulating layer 51 on the sidewall of the second filling hole 23 is retained to expose the corresponding second sacrificial layer 22. A second conductive layer is deposited in the third filling hole and on the stacked structure 20, and the second conductive layer fills the third filling hole. The second conductive layer on the stacked structure 20 is etched away, and the remaining second conductive layer forms a plurality of spaced-apart conductive pillars 52.

[0141] In some possible examples, before forming the contact structure 50 in the second filling hole 23 (step S202), the method for manufacturing a memory may further include: etching the first sacrificial layer 21 exposed in the second filling hole 23 to expand the second filling hole 23. With such a setting, the side wall of the second filling hole 23 forms a wavy shape, its space expands, and the contact structure 50 is filled in the expanded second filling hole 23, which can increase the contact area between the contact structure 50 and the corresponding second sacrificial layer 22 and reduce the contact resistance.

[0142] Step S203: Etch the stacked structure 20 to form a plurality of first intermediate holes 53 on both sides of the contact structure 50 along the third direction. The plurality of first intermediate holes 53 on each side are arranged at intervals along the second direction, and each first intermediate hole 53 exposes the substrate 10.

[0143] Refer to Figure 13 and Figure 14 , etch the stacked structure 20 to form a plurality of first intermediate holes 53 on the first side of the contact structure 50 and a plurality of first intermediate holes 53 on the second side of the contact structure 50. The first side of the contact structure 50 ( Figure 13 the left side shown) and the second side of the contact structure 50 ( Figure 13 the right side shown) are opposite to each other along the third direction. The plurality of first intermediate holes 53 on the first side of the contact structure 50 are symmetric with the plurality of first intermediate holes 53 on the second side of the contact structure 50. The plurality of first intermediate holes 53 on each side of the contact structure 50 are arranged at intervals along the second direction, and each first intermediate hole 53 penetrates through the stacked structure 20 to expose the substrate 10.

[0144] Refer to Figure 13 and Figure 14 , in some possible implementation manners, the plurality of first intermediate holes 53 may be formed through the following process:

[0145] Form a third mask layer 34, a fourth mask layer 35, and a second photoresist layer 36 on the stacked structure 20 and the contact structure 50 in sequence. The second photoresist layer 36 has a second mask pattern. The third mask layer 34 covers the stacked structure 20 and the contact structure 50, the fourth mask layer 35 covers the third mask layer 34, and the second photoresist layer 36 covers the fourth mask layer 35. The third mask layer 34 is a hard mask layer, and its material may be silicon nitride. The fourth mask layer 35 is a conventional mask layer, and its material may be silicon oxynitride. The thickness of the third mask layer 34 may be greater than the thickness of the fourth mask layer 35.

[0146] Using the second photoresist layer 36 as a mask, etch the fourth mask layer 35, the third mask layer 34, and the stacked structure 20 to form a plurality of first intermediate holes 53 in the stacked structure 20. The plurality of first intermediate holes 53 all penetrate through the stacked structure 20 and expose the substrate 10.

[0147] Remove the film layers on the stacked structure 20 and the contact structure 50 to expose the stacked structure 20 and the contact structure 50.

[0148] In some possible examples, before forming the first intermediate structure 54 (step S204), the manufacturing method of the memory further includes: etching the first sacrificial layer 21 exposed in the first intermediate hole 53 to expand the first intermediate hole 53. In this way, the side wall of the expanded first intermediate hole 53 forms a wavy shape to increase the contact area between the subsequently formed transistor 80 and the bit line 73 and reduce the contact resistance.

[0149] Step S204: Form a first intermediate structure 54 in the first intermediate hole 53, and the first intermediate structure 54 fills the first intermediate hole 53.

[0150] Refer to Figure 15 , the first intermediate structure 54 fills the first intermediate hole 53, that is, the top surface of the first intermediate structure 54 is flush with the top surface of the stacked structure 20. The material of the first intermediate structure 54 can be the same as the material of the substrate 10 exposed in the first intermediate hole 53, so as to facilitate the subsequent removal of part of the substrate 10 and reduce the connection between the formed transistor 80 and the substrate 10.

[0151] In some possible implementation manners, forming the first intermediate structure 54 in the first intermediate hole 53 includes: depositing a first intermediate layer in the first intermediate hole 53, on the stacked structure 20, and on the contact structure 50, and the first intermediate layer fills the first intermediate hole 53; back-etching the first intermediate layer to remove the first intermediate layer on the stacked structure 20 and the contact structure 50, exposing the stacked structure 20 and the contact structure 50, and the remaining first intermediate layer forms a plurality of independent first intermediate structures 54.

[0152] Step S205: Etch the stacked structure 20 to form a plurality of second intermediate holes 55 on the side of the plurality of first intermediate structures 54 away from the plurality of contact structures 50 respectively. The plurality of second intermediate holes 55 on each side are arranged at intervals along the second direction, and along the third direction, each second intermediate hole 55 is opposite to the first intermediate structure 54.

[0153] The following combines Figure 16 and Figure 17 , and elaborates on a formation process of the plurality of second intermediate holes 55.

[0154] First, a third sacrificial layer 24, a fifth mask layer 37, a sixth mask layer 38, and a third photoresist layer 39 are sequentially formed on the stacked structure 20 and the contact structure 50. The third photoresist layer 39 has a third mask pattern. Among them, the third sacrificial layer 24 covers the stacked structure 20 and the contact structure 50, the fifth mask layer 37 covers the third sacrificial layer 24, the sixth mask layer 38 covers the fifth mask layer 37, and the third photoresist layer 39 covers the sixth mask layer 38. The material of the third sacrificial layer 24 includes silicon. The fifth mask layer 37 is a hard mask layer, and its material can be silicon nitride. The sixth mask layer 38 is a conventional mask layer, and its material can be silicon oxynitride.

[0155] Then, using the third photoresist layer 39 as a mask, the sixth mask layer 38, the fifth mask layer 37, the third sacrificial layer 24, and the stacked structure 20 are etched to form a plurality of second intermediate holes 55 in the stacked structure 20. Among them, the plurality of second intermediate holes 55 all penetrate through the sixth mask layer 38, the fifth mask layer 37, the third sacrificial layer 24, and the stacked structure 20, and expose the substrate 10.

[0156] Then, the film layer on the third sacrificial layer 24 is removed to expose the third sacrificial layer 24.

[0157] In some possible examples, before forming the second intermediate structure 56 (step S206), the manufacturing method of the memory further includes: etching the second sacrificial layer 22 exposed in the second intermediate hole 55 to expand the second intermediate hole 55. Thus arranged, the side wall of the expanded second intermediate hole 55 forms a wavy shape to increase the surface area of the lower electrode 92 of the capacitor 90 formed subsequently and increase the capacitance of the capacitor 90.

[0158] Step S206: Form a second intermediate structure 56 in the second intermediate hole 55, and the second intermediate structure 56 fills the second intermediate hole 55

[0159] Refer to Figure 18 , the second intermediate structure 56 fills the second intermediate hole 55, and the top surface of the second intermediate structure 56 can be flush with the top surface of the stacked structure 20. The material of the second intermediate structure 56 can be the same as that of the first intermediate structure 54. In some possible implementation manners, forming the second intermediate structure 56 in the second intermediate hole 55 includes: depositing a second intermediate layer in the second intermediate hole 55 and on the third sacrificial layer 24, and the second intermediate layer fills the second intermediate hole 55; back-etching the second intermediate layer to remove the second intermediate layer on the third sacrificial layer 24 and expose the third sacrificial layer 24, and the remaining second intermediate layer forms a plurality of independent second intermediate structures 56.

[0160] Next, in conjunction with Figures 19 to 22, a process of forming the support structure 58 is described. In some possible exemplary embodiments, forming at least one support structure 58 between two contact structures 50 adjacent to each other along the second direction (step S300) includes the following steps:

[0161] Step S301 : etching the stacked structure 20 to form a plurality of first filling holes 57 penetrating the stacked structure 20 . The plurality of first filling holes 57 are arranged at intervals along the second direction, and there is at least one first filling hole 57 between two adjacent contact structures 50 .

[0162] See also Figure 18 , illustratively, a seventh mask layer 41, an eighth mask layer 42, a ninth mask layer 43 and a fourth photoresist layer 44 are deposited, and the fourth photoresist layer 44 has a fourth mask pattern. Using the fourth photoresist as a mask, the film layer below the fourth photoresist is etched until the substrate 10 is exposed to form a plurality of first filling holes 57. The film layer above the seventh mask layer 41 is removed to expose the seventh mask layer 41.

[0163] The seventh mask layer 41 covers the film layer below it, such as the stacked structure 20. In the example where the third sacrificial layer 24 is provided on the stacked structure 20, the seventh mask layer 41 covers the third sacrificial layer 24 and the second intermediate layer, the eighth mask layer 42 covers the seventh mask layer 41, the ninth mask layer 43 covers the eighth mask layer 42, and the fourth photoresist layer 44 covers the ninth mask layer 43. The material of the seventh mask layer 41 includes polysilicon, the eighth mask layer 42 is a hard mask layer, and its material can be silicon nitride, and the ninth mask layer 43 is a conventional mask layer, and its material can be silicon oxynitride.

[0164] The plurality of first filling holes 57 are directly opposite to the contact structure 50 along the second direction. The plurality of first filling holes 57 all penetrate the ninth mask layer 43, the eighth mask layer 42, the seventh mask layer 41 and the stacked structure 20, and expose the substrate 10. In the example where the third sacrificial layer 24 is disposed on the stacked structure 20, the plurality of first filling holes 57 also all penetrate the third sacrificial layer 24.

[0165] Step S302 : etching the first sacrificial layer 21 exposed in the first filling hole 57 to enlarge the first filling hole 57 .

[0166] like Figure 20 As shown, the first sacrificial layer 21 is etched along the first filling hole 57 to expand the first filling hole 57. In the expanded first filling hole 57, the second sacrificial layer 22 protrudes from the first sacrificial layer 21, and the protruding second sacrificial layer 22 is ring-shaped.

[0167] Step S303: Thinning the second sacrificial layer 22 exposed in the enlarged first filling hole 57 along the first direction, further enlarging the first filling hole 57, and increasing the distance between adjacent portions of the second sacrificial layer 22 exposed in the enlarged first filling hole 57.

[0168] As Figure 21 shown, etch the surface of the second sacrificial layer 22 exposed in the enlarged support hole to thin the second sacrificial layer 22. Among them, the wet etching process is used to etch the protruding second sacrificial layer 22. Since the contact surfaces of the two opposite surfaces of the exposed second sacrificial layer 22 along the first direction with the etching solution are relatively large, the removed thickness is relatively large, and the contact surface of the inner peripheral surface of the exposed second sacrificial layer 22 with the etching solution is relatively small, and the removed thickness is relatively small and can be ignored, so that the second sacrificial layer 22 is thinned along the first direction, increasing the distance between adjacent second sacrificial layers 22 exposed in the first filling hole 57. When the second sacrificial layer 22 is subsequently replaced with the bit line 73, the spacing between the portions of the bit line 73 extending into the support structure 58 can be increased to reduce the parasitic capacitance between adjacent bit lines 73 and improve the performance of the memory.

[0169] Step S304: Deposit the support structure 58, and the support structure 58 fills the further enlarged first filling hole 57.

[0170] Refer to Figure 22 , the support structure 58 can be formed by deposition and etch-back. Exemplarily, a support layer is deposited in the enlarged first filling hole 57 and on the seventh mask layer 41, and the support layer fills the enlarged first filling hole 57. Remove the seventh mask layer 41 and the support layer on the seventh mask layer 41, and the remaining support layer forms a plurality of spaced support structures 58.

[0171] Among them, the material of the support layer can be a low dielectric constant material to facilitate subsequent separate removal of the first sacrificial layer 21 in contact with the support layer. In the example where the third sacrificial layer 24 is provided on the stacked structure 20, the top surface of the support structure 58, the top surface of the third sacrificial layer 24, and the top surface of the second intermediate structure 56 are flush.

[0172] The embodiments or implementation manners in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other. The descriptions with reference to terms such as "one implementation manner", "some implementation manners", "illustrative implementation manner", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples. Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A memory device, characterized in that, it includes: Multiple bit lines, which are arranged at intervals along a first direction; Multiple transistors, which are arranged at intervals along the first direction and also at intervals along a second direction, and multiple transistors along the first direction are correspondingly electrically connected to one of the bit lines; Capacitors correspondingly electrically connected to each transistor, along a third direction, the capacitor and the bit line are located on both sides of the transistor, and the first direction, the second direction, and the third direction are pairwise perpendicular; Multiple contact structures, which are arranged at intervals along the second direction and penetrate through part of the bit lines, and each contact structure is correspondingly connected to one of the bit lines; Multiple support structures, which are arranged at intervals along the second direction and penetrate through the multiple bit lines, and there is at least one support structure between two adjacent contact structures.

2. The memory device according to claim 1, characterized in that, Multiple first annular grooves arranged at intervals along the first direction are formed on the side walls of at least part of the support structures; Each bit line includes a first part filled in the first annular groove and a second part located outside the first annular groove, and along the first direction, the thickness of the first part is less than the thickness of the second part.

3. The memory device according to claim 2, characterized in that, The second part includes an extension part and a connection part, the connection part connects two adjacent first parts along the second direction, the extension part connects the transistor, and the first part or the connection part opposite to the transistor.

4. The memory device according to any one of claims 1-3, characterized in that, The side walls of part of the contact structures opposite to the bit lines are recessed from the side walls of the remaining contact structures, so that the side walls of the contact structures are wavy.

5. The memory device according to any one of claims 1-3, characterized in that, The memory device further includes multiple word lines arranged at intervals along the second direction, each word line corresponds to multiple transistors along the first direction, and forms the gate of the corresponding transistors; Each transistor includes a gate dielectric layer surrounding the corresponding gate, and a channel region surrounding the gate dielectric layer, and the channel region is correspondingly connected to the bit line and the capacitor.

6. The memory device according to claim 5, characterized in that, The gate dielectric layer includes a main body surrounding the gate, and epitaxial parts connected to both ends of the main body along the first direction, the epitaxial parts adjacent to each other of two adjacent gate dielectric layers along the first direction are in contact with each other, and multiple gate dielectric layers along the first direction form an integral body.

7. The memory device according to claim 6, characterized in that, The channel region covers the surfaces of the corresponding epitaxial portions that are opposite to each other, and the outer peripheral surface of the main body, and the channel region encloses a second annular groove. Along the third direction, the bit line and the connection layer are respectively arranged on both sides of the channel region, and the bit line and the connection layer extend into the second annular groove and are in corresponding contact with the surface of the second annular groove, and the connection layer is also in corresponding contact with the capacitor.

8. A method for manufacturing a memory, It is characterized in that include: forming a stacked structure on a substrate, the stacked structure comprising a plurality of first sacrificial layers and a plurality of second sacrificial layers alternately arranged in sequence along a first direction; A plurality of contact structures, a plurality of first intermediate structures and a plurality of second intermediate structures are formed in the stacked structure; wherein the plurality of contact structures, the plurality of first intermediate structures and the plurality of second intermediate structures are arranged at intervals along the second direction, and along the third direction, the plurality of second intermediate structures are located on a side of the plurality of first intermediate structures away from the plurality of contact structures, each of the contact structures contacts a layer of the second sacrificial layer, the first intermediate structures and the second intermediate structures both penetrate the stacked structure, and the first direction, the second direction and the third direction intersect each other; At least one supporting structure is formed between two of the contact structures adjacent to each other along the second direction, and the supporting structure at least penetrates the stacked structure; removing a portion of the stacked structure between two adjacent first intermediate structures and two adjacent second intermediate structures along the second direction, to form first isolation grooves penetrating the stacked structure and arranged alternately with the first intermediate structures, wherein along the third direction, one end of the first isolation groove facing the support structure protrudes from one end of the first intermediate structure facing the support structure, and one end of the first isolation groove facing away from the support structure penetrates the stacked structure; removing the remaining second sacrificial layer to form a first filling space; forming a first conductive layer in the first filling space, wherein the first conductive layer between the support structures, between the support structure and the contact structure, and between the support structure or the contact structure and the first intermediate structure forms a bit line, and the first conductive layer between the first intermediate structure and the second intermediate structure forms a connecting layer; forming a first isolation layer in the first isolation trench, wherein the first isolation layer fills the first isolation trench; The first intermediate structure is removed to form a plurality of transistors spaced apart along the first direction, the second intermediate structure is removed to form a plurality of capacitors spaced apart along the second direction, and the remaining first sacrificial layer is removed to form a second isolation layer, and along the third direction, each of the transistors is connected to one of the capacitors through the connection layer.

9. The method according to claim 8, It is characterized in that At least one supporting structure is formed between two of the contact structures adjacent to each other along the second direction, comprising: Etch the stacked structure to form a plurality of first filling holes penetrating the stacked structure. The plurality of first filling holes are arranged at intervals along the second direction, and there is at least one first filling hole between two adjacent contact structures; Etch the first sacrificial layer exposed in the first filling hole to expand the first filling hole; Thin the second sacrificial layer exposed in the expanded first filling hole along the first direction to further expand the first filling hole and increase the distance between adjacent portions of the second sacrificial layer exposed in the expanded first filling hole; Deposit the support structure, and the support structure fills the further expanded first filling hole.

10. The manufacturing method according to claim 8 or 9, wherein, forming a plurality of contact structures, a plurality of first intermediate structures and a plurality of second intermediate structures in the stacked structure, including: Etch the stacked structure to form a plurality of second filling holes arranged at intervals along the second direction, and each second filling hole correspondingly exposes one second sacrificial layer; Form a contact structure in the second filling hole, and the contact structure fills the corresponding second filling hole; Etch the stacked structure to form a plurality of first intermediate holes on both sides of the contact structure along the third direction. The plurality of first intermediate holes on each side are arranged at intervals along the second direction, and each first intermediate hole exposes the substrate; Form the first intermediate structure in the first intermediate hole, and the first intermediate structure fills the first intermediate hole; Etch the stacked structure to form a plurality of second intermediate holes on one side of the plurality of first intermediate structures away from the plurality of contact structures. The plurality of second intermediate holes on each side are arranged at intervals along the second direction, and along the third direction, each second intermediate hole is opposite to the first intermediate structure; Form the second intermediate structure in the second intermediate hole, and the second intermediate structure fills the second intermediate hole.

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