Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and relates to the field of semiconductor devices, and the semiconductor device comprises a plurality of transistors which are distributed on a substrate along a first direction and a second direction in an array manner; the transistor comprises a semiconductor column and a gate electrode; the plurality of word lines extend along the second direction and are formed by connecting the gate electrodes of a column of transistors which are distributed along the second direction at intervals, and the gate electrodes are only positioned on the same side of the column of transistors which are distributed along the second direction at intervals. The parasitic capacitance effect between the gate electrodes of the semiconductor device is small, higher integration density can be achieved, and the semiconductor device has good performance.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor devices, and particularly to a semiconductor device, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking day by day, and the types and quantities of devices included in a single chip are increasing accordingly. As a result, small differences in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's Law came out, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements of current products. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this document. This overview is not intended to limit the protection scope of the present application.

[0005] Embodiments of the present application provide a semiconductor device, a manufacturing method thereof, and an electronic device. The parasitic capacitance effect between the gate electrodes of the semiconductor device is small, higher integration density can be achieved, and it has good performance.

[0006] Embodiments of the present application provide a semiconductor device, including:

[0007] Multiple transistors, which are arrayed on a substrate in a first direction and a second direction; the transistors include semiconductor columns and gate electrodes;

[0008] Multiple word lines, which extend along the second direction and are formed by connecting the gate electrodes of a column of the transistors spaced apart along the second direction, and the gate electrodes are only located on the same side of a column of the transistors spaced apart along the second direction.

[0009] In an exemplary embodiment of the present application, the sidewall of the semiconductor column may include two first side surfaces extending along the second direction and a second side surface located between the first side surfaces;

[0010] The word line partially surrounds the semiconductor column of the transistor connected to the word line, and the word line exposes at least one of the first side surfaces.

[0011] In an exemplary embodiment of the present application, the word line may also expose at least a part of the second side surface of the semiconductor column.

[0012] In an exemplary embodiment of the present application, the word line only surrounds the other first side surface of the semiconductor column.

[0013] In an exemplary embodiment of the present application, adjacent two of the word lines are isolated from each other by a first insulating layer, and the adjacent two word lines may be symmetrically distributed on both sides of the first insulating layer therebetween.

[0014] The embodiment of the present application further provides a manufacturing method of the semiconductor device provided in the embodiment of the present application. The manufacturing method includes:

[0015] Form semiconductor pillars arrayed along a first direction and a second direction on a substrate, and use a first insulating layer to space adjacent two columns of the semiconductor pillars distributed along the first direction;

[0016] Deposit a gate insulating layer and a gate electrode layer in sequence on side walls of the semiconductor pillars, and the gate electrode layer entirely surrounds side walls of the semiconductor pillars;

[0017] Etch the gate electrode layer to form a gate electrode partially surrounding side walls of the semiconductor pillars, and gate electrodes on side walls of a column of the semiconductor pillars spaced along the second direction are only connected together on the same side of the column of the semiconductor pillars to form a word line extending along the second direction.

[0018] In an exemplary embodiment of the present application, etching the gate electrode layer to form a gate electrode partially surrounding side walls of the semiconductor pillars, and gate electrodes on side walls of a column of the semiconductor pillars spaced along the second direction are only connected together on the same side of the column of the semiconductor pillars to form a word line extending along the second direction may include:

[0019] Etch and remove the gate electrode layer on side walls of adjacent two columns of the semiconductor pillars close to each other in the first direction, so that the gate electrode layers surrounding side walls of the adjacent two columns of the semiconductor pillars are disconnected on both sides of the same first insulating layer;

[0020] Back-etch the remaining gate electrode layer, and only retain the gate electrode layer corresponding to a channel region of the semiconductor pillar to form a gate electrode partially surrounding a side wall of the channel region of the semiconductor pillar, and gate electrodes on side walls of a column of the semiconductor pillars spaced along the second direction are only connected together on a side of the column of the semiconductor pillars away from the same first insulating layer to form a word line extending along the second direction.

[0021] In an exemplary embodiment of the present application, forming semiconductor pillars arrayed along a first direction and a second direction on a substrate, and using a first insulating layer to space adjacent two columns of the semiconductor pillars distributed along the first direction may include:

[0022] Provided is a substrate including a semiconductor material, on which a plurality of first trenches extending in the first direction and spaced apart in the second direction are formed, and the plurality of first trenches divide the upper portion of the substrate into a plurality of semiconductor walls;

[0023] Fill the first trenches with a second insulating layer;

[0024] Form a plurality of second trenches on the substrate, the plurality of second trenches extending in the second direction and spaced apart in the first direction, and the plurality of second trenches divide the semiconductor walls into a plurality of semiconductor pillars arrayed in the first direction and the second direction;

[0025] Deposit the second insulating layer with a set thickness on the sidewalls of the second trenches, and fill the first insulating layer in the second trenches; wherein, the set thickness is the sum of the thicknesses of the gate insulating layer and the gate electrode layer to be formed.

[0026] In an exemplary embodiment of the present application, sequentially depositing a gate insulating layer and a gate electrode layer on the sidewalls of the semiconductor pillars may include:

[0027] Remove the second insulating layer on the upper sidewalls of the semiconductor pillars to expose the upper sidewalls of the semiconductor pillars;

[0028] Deposit a gate insulating layer on the exposed upper sidewalls of the semiconductor pillars, and fill the gate electrode layer in the blank spaces of the first trenches and the second trenches.

[0029] In an exemplary embodiment of the present application, the manufacturing method may further include: after forming the plurality of semiconductor pillars and before depositing the second insulating layer on the sidewalls of the second trenches, performing the following process,

[0030] Etch the substrate between two of the semiconductor pillars in the second trenches to form a bit line groove extending in the first direction and located below a column of the semiconductor pillars distributed in the first direction, and form a bit line in the bit line groove that contacts the bottoms of the semiconductor pillars.

[0031] In an exemplary embodiment of the present application, the manufacturing method may further include: after forming the word lines, performing the following process:

[0032] Fill the first insulating layer in the spaces vacated by back-etching the gate electrode layer and in the first trenches.

[0033] An embodiment of the present application further provides an electronic device, and the electronic device includes the semiconductor device provided by the embodiment of the present application.

[0034] The semiconductor device according to the embodiment of the present application improves the current fully surrounding gate electrode to a partially surrounding one, which can increase the distance between two adjacent word lines, thereby reducing or even avoiding the gate electrode parasitic capacitance effect. In addition, a smaller-sized memory cell can be realized, thereby improving the integration degree of the device.

[0035] The manufacturing method of the semiconductor device according to the embodiment of the present application obtains the gate electrode and word line of the partially surrounding semiconductor column by etching the gate electrode layer of the fully surrounding semiconductor column, which can reduce or even avoid the gate electrode parasitic capacitance effect, and realize a smaller-sized memory cell, thereby improving the integration degree of the device. Moreover, the process flow of the manufacturing method of the semiconductor device according to the embodiment of the present application is simple and can be realized by simply adjusting the existing manufacturing process of vertical channel transistors. For example, adding one photomask and one etching step can achieve it.

[0036] Other features and advantages of the present application will be described in the following specification, and will become more clear partly from the specification, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the specification and the drawings. Description of the Drawings

[0037] The drawings are used to provide an understanding of the technical solutions of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solutions of the present application and do not constitute a limitation to the technical solutions of the present application.

[0038] Figure 1 It is a partial cross-sectional schematic diagram of a current 4F2 structure dynamic random access memory;

[0039] Figure 2A It is a three-dimensional structure schematic diagram of a semiconductor device according to an exemplary embodiment of the present application;

[0040] Figure 2B is Figure 2A a partial cross-sectional schematic diagram of;

[0041] Figure 2C is Figure 2A a longitudinal cross-sectional schematic diagram of the semiconductor device shown in the a-a' cross-section;

[0042] Figure 2D is Figure 2A a longitudinal cross-sectional schematic diagram of the semiconductor device shown in the b-b' cross-section;

[0043] Figure 2E is Figure 2A a longitudinal cross-sectional schematic diagram of the semiconductor device shown in the c-c' cross-section;

[0044] Figure 3Process flow chart of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application;

[0045] Figure 4 Longitudinal cross-sectional schematic diagram of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application on the c-c' cross-section after forming the first trench;

[0046] Figure 5A Longitudinal cross-sectional schematic diagram of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application on the a-a' cross-section after forming the semiconductor pillar;

[0047] Figure 5B Longitudinal cross-sectional schematic diagram of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application on the c-c' cross-section after forming the semiconductor pillar;

[0048] Figure 6 Longitudinal cross-sectional schematic diagram of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application on the a-a' cross-section after forming the bit line;

[0049] Figure 7 Longitudinal cross-sectional schematic diagram of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application on the a-a' cross-section after filling the first insulating layer in the second trench;

[0050] Figure 8A Longitudinal cross-sectional schematic diagram of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application on the a-a' cross-section after forming the gate electrode layer;

[0051] Figure 8B Longitudinal cross-sectional schematic diagram of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application on the b-b' cross-section after forming the gate electrode layer;

[0052] Figure 8C Longitudinal cross-sectional schematic diagram of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application on the c-c' cross-section after forming the gate electrode layer;

[0053] Figure 9A Longitudinal cross-sectional schematic diagram of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application on the a-a' cross-section after forming the partially surrounding gate electrode layer;

[0054] Figure 9B Longitudinal cross-sectional schematic diagram of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application on the b-b' cross-section after forming the partially surrounding gate electrode layer;

[0055] Figure 10AA longitudinal cross-sectional view of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application after forming a word line, taken along the a-a' cross-section;

[0056] Figure 10B A longitudinal cross-sectional view of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application after forming a word line, taken along the b-b' cross-section;

[0057] Figure 10C A longitudinal cross-sectional view of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present application after forming a word line, taken along the c-c' cross-section.

[0058] The meanings of the reference symbols in the drawings are as follows:

[0059] 10 - semiconductor pillar; 11 - first insulating layer; 12 - second insulating layer; 13 - substrate; 14 - first side; 15 - second side; 20 - word line; 21 - gate electrode layer; 22 - gate insulating layer; 30 - bit line; 41 - first trench; 42 - second trench. Detailed implementation manners

[0060] To make the objectives, technical solutions, and advantages of the present application clearer and more understandable, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be arbitrarily combined with each other.

[0061] The implementation manners of the present application do not necessarily limit the sizes shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the implementation manners of the present application are not limited to the shapes or values shown in the drawings.

[0062] The size and proportional relationships between the various film layers or components in the drawings of the present application can be used as a reference in actual processes, which are implementation manners with better technical effects, but are not limited thereto. For example: the aspect ratio of the semiconductor pillar, the thickness and spacing of each film layer, can be adjusted according to actual needs.

[0063] The ordinal numbers such as "first" and "second" in the present application are set to avoid confusion of the components and do not represent any order, quantity, or importance.

[0064] In this application, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the constituent elements with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to this application. The positional relationships of the constituent elements are appropriately changed according to the directions describing the constituent elements. Therefore, it is not limited to the terms described in the disclosure and can be appropriately replaced according to the circumstances.

[0065] In this application, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" shall be construed in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate member, or a communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0066] In this application, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region where current mainly flows.

[0067] In this application, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, etc., the functions of the "source electrode" and the "drain electrode" sometimes swap with each other. Therefore, in this application, unless otherwise specified, the "source electrode" and the "drain electrode" can swap with each other.

[0068] In this application, "electrically connected" or "connected" includes the case where the constituent elements are connected together through an element having a certain electrical effect. For example, an electrical signal connection (coupled connection, such as coupled to), or a physical direct connection. There is no particular limitation on the "element having a certain electrical effect" as long as it can transfer electrical signals between the constituent elements that can be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0069] In this application, "parallel" means approximately parallel or almost parallel. For example, the state where the angle formed by two straight lines is more than -10° and less than 10°, and thus, it also includes the state where the angle is more than -5° and less than 5°. Additionally, "perpendicular" means approximately perpendicular. For example, the state where the angle formed by two straight lines is more than 80° and less than 100°, and thus, it also includes the state where the angle is more than 85° and less than 95°.

[0070] In this application, "film" and "layer" can be interchanged. For example, sometimes "insulating layer" can be replaced with "insulating film".

[0071] In the embodiments of this application, "A and B are an integral structure" can mean that there is no obvious fault or gap, etc., an obvious boundary interface in the microscopic structure. Generally, when a connected film layer is patterned and formed on a film layer, it is an integral body. For example, A and B are formed of the same material to form a film layer and are simultaneously formed into a structure with a connection relationship through the same patterning process, or B is directly grown on A by epitaxy, and the materials of the two may not be completely the same.

[0072] In this application, the spaced distribution can be understood as a separated and independent distribution, which can be achieved by physical disconnection in the physical structure or by electrical disconnection in electrical characteristics. For example, the semiconductor layer between the effective channels corresponding to two transistors is modified to achieve insulation to realize the electrical spacing between the two channels.

[0073] In this application, "cross-section" refers to a section parallel to the substrate; "longitudinal section" refers to a section perpendicular to the substrate.

[0074] Figure 1 is a top view of a current 4F2 structure dynamic random access memory (DRAM). As Figure 1 shown, the semiconductor device includes a vertical channel transistor array, including semiconductor columns 10 and word lines (WL) 20 that fully surround the semiconductor columns 10. Part of the region of the word lines 20 serves as the gate electrodes of the transistors, and adjacent two word lines 20 are isolated by a first insulating layer 11. Parasitic capacitance effects are likely to exist between adjacent two gate electrodes located on adjacent two word lines 20, thereby affecting the electrical performance of the transistors. With the miniaturization of semiconductor devices, the parasitic capacitance effects between the gate electrodes are more prominent, which is extremely disadvantageous for the miniaturization of DRAM to a smaller size. However, with the continuous miniaturization of transistor sizes and the improvement of storage density, without changing the material of the first insulating layer 11, the parasitic capacitance effects between the gate electrodes are inevitable and become more obvious. Therefore, there is an urgent need for a new solution to effectively reduce or avoid this parasitic capacitance effect.

[0075] An embodiment of the present application provides a semiconductor device. Figure 2A FIG. is a schematic three-dimensional structure diagram of a semiconductor device according to an exemplary embodiment of the present application; Figure 2B is Figure 2A a partial cross-sectional schematic diagram; Figure 2C is Figure 2A a longitudinal cross-sectional schematic diagram of the semiconductor device shown in the a-a' cross-section; Figure 2D is Figure 2A a longitudinal cross-sectional schematic diagram of the semiconductor device shown in the b-b' cross-section; Figure 2E is Figure 2A a longitudinal cross-sectional schematic diagram of the semiconductor device shown in the c-c' cross-section.

[0076] As Figures 2A to 2E shown, the semiconductor device includes: a plurality of transistors and a plurality of word lines 20;

[0077] The plurality of transistors are arranged in an array along a first direction and a second direction on a substrate 13; the transistor includes a semiconductor pillar 10 and a gate electrode;

[0078] The plurality of word lines 20 all extend along the second direction and are formed by connecting the gate electrodes of a column of the transistors spaced apart along the second direction, and the gate electrodes are only located on the same side of a column of the transistors spaced apart along the second direction.

[0079] The semiconductor device according to the embodiment of the present application improves the current fully surrounding gate electrode to a partially surrounding one, which can increase the distance between two adjacent word lines, thereby reducing or even avoiding the gate electrode parasitic capacitance effect. In addition, a smaller-sized memory cell can be realized, thereby improving the integration degree of the device.

[0080] Exemplarily, the gate electrodes are only connected together on the same side of a column of the transistors spaced apart along the second direction to form the word line 20.

[0081] Exemplarily, the first direction may be parallel to the substrate, the second direction may be parallel to the substrate, and the first direction and the second direction may be perpendicular to each other. For example, the first direction may be the a-a' direction as Figure 2A shown, and the second direction may be the c-c' direction as Figure 2A shown.

[0082] In an exemplary embodiment of the present application, as Figure 2B shown, the side wall of the semiconductor pillar 10 may include two first side surfaces 14 extending along the second direction and a second side surface 15 located between the two first side surfaces 14;

[0083] The word line 20 partially surrounds the semiconductor column 10 of the transistor connected to the word line 20, and the word line 20 exposes at least one first side surface 14.

[0084] In an exemplary embodiment of the present application, as Figure 2B shown, the word line 20 may also expose at least a part of the second side surface 15 of the semiconductor column 10.

[0085] In an exemplary embodiment of the present application, as Figure 2B shown, the word line 20 only surrounds the other first side surface of the semiconductor column 10.

[0086] In an exemplary embodiment of the present application, as Figure 2B shown, a gate insulating layer 22 having an insulating function is provided between the semiconductor column 10 and the word line 20.

[0087] In an exemplary embodiment of the present application, adjacent word lines 20 are isolated from each other by a first insulating layer 11, and the adjacent word lines 20 may be symmetrically distributed on both sides of the first insulating layer 11 therebetween.

[0088] In an exemplary embodiment of the present application, the transistor may be a vertical channel transistor. The transistor may sequentially include a source electrode region, a channel region, and a drain electrode region, and the source electrode region, the channel region, and the drain electrode region may be an integral structure.

[0089] In an exemplary embodiment of the present application, the semiconductor device may further include a bit line 30 extending in the first direction. The bit line 30 may be located between a column of the transistors spaced apart in the first direction and the substrate 13, and the bit line 30 may be connected to the source electrode region of the transistor.

[0090] The substrate in the embodiments of the present application may be a support structure, for example, a silicon substrate, or a support structure on which other film layers, functions, or circuits have been distributed on the silicon substrate. The device related to the inventive configuration of the embodiments of the present application is provided on the main surface of the support structure.

[0091] In an exemplary embodiment of the present application, the semiconductor column and the substrate may be an integral structure. For example, the semiconductor column may be formed by etching a semiconductor substrate; alternatively, a semiconductor layer may be deposited on the substrate, and then the semiconductor column may be formed by etching.

[0092] In the present application, the semiconductor layer may be understood as a semiconductor material, and its shape and structure are not emphasized here, only its function is emphasized.

[0093] Exemplarily, the material of the semiconductor layer may be silicon, polycrystalline silicon or the like with a bandgap less than 1.65 eV, or may be a wide-bandgap material, such as a metal oxide material with a bandgap greater than 1.65 eV.

[0094] For example, the material of the metal oxide semiconductor layer or the channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also include compounds containing other elements, such as elements N, Si, etc.; and may also include other trace doping elements.

[0095] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxide nitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc., as long as the leakage current of the transistor can meet the requirements, and specific adjustments can be made according to the actual situation.

[0096] These materials have a wide bandgap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of the dynamic memory.

[0097] The above materials of the metal oxide semiconductor layer or the channel only emphasize the element type of the material, and do not emphasize the atomic ratio in the material and the film quality of the material.

[0098] Exemplarily, the material of the bit line may be selected from any one or more of other metal materials with similar properties such as tungsten, molybdenum, cobalt, etc. The bit line may be a single-layer or multi-layer structure. For example, it may be a multi-layer structure formed by titanium (Ti), titanium nitride (TiN) and tungsten (W).

[0099] In an exemplary embodiment of the present application, the electrode material of the gate electrode may be any one or more of the following different types of materials:

[0100] For example, metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing these metals mentioned above;

[0101] It may also be metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as highly conductive metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), etc.; for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.;

[0102] Of course, it may also be polysilicon material; it may also be a semiconductor material doped with a conductive material, for example, silicon after conductive doping, germanium after conductive doping, silicon germanium after conductive doping, etc.; other materials showing conductivity, etc.

[0103] In an exemplary embodiment of the present application, the material of the gate insulating layer may include one or more layers of Low-K and / or High-K dielectric materials, or include two or more regions with different dielectric constants K. The characteristics of the gate insulating layer of the present application will be exemplarily described below.

[0104] Low-K material, such as silicon oxide.

[0105] High-K material, such as a dielectric material with a dielectric constant K≥3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include at least one of the following: hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0106] Exemplarily, the material of the first insulating layer may be any one or more of silicon oxide (for example, SiO 2 ), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN).

[0107] Exemplarily, the semiconductor device may be a memory including transistors, for example, memories such as DRAM. The transistor may be an access transistor, and the storage unit of the semiconductor device may further include other components, such as a capacitor in a 1T1C storage unit, or include a read transistor and a storage node in a 2T0C storage unit.

[0108] In addition, the semiconductor device according to the embodiment of the present application can improve the performance of the device through process adjustments such as adjusting the length or thickness of the channel region, the gate electrode material and the contact area between the gate electrode and the channel region, the material of the gate insulating layer and the isolation width, etc. For example, the electrical properties of the transistor, including the saturation current, switching ratio, etc., can be improved, and the adverse aspects such as the transistor leakage current and parasitic capacitance can be further reduced or improved.

[0109] The embodiment of the present application also provides a manufacturing method of the semiconductor device provided by the embodiment of the present application.

[0110] Figure 3 It is a process flow chart of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application. As Figure 3 shown, the manufacturing method may include:

[0111] Form semiconductor pillars arranged in an array along a first direction and a second direction on a substrate, and use a first insulating layer to space two adjacent columns of the semiconductor pillars distributed along the first direction;

[0112] Deposit a gate insulating layer and a gate electrode layer in sequence on the side walls of the semiconductor pillars, and the gate electrode layer completely surrounds the side walls of the semiconductor pillars;

[0113] Etch the gate electrode layer to form a gate electrode that partially surrounds the side walls of the semiconductor pillars, and the gate electrodes on the side walls of one column of the semiconductor pillars spaced apart along the second direction are only connected together on the same side of the column of the semiconductor pillars to form a word line extending along the second direction.

[0114] The manufacturing method of the semiconductor device according to the embodiment of the present application can obtain a gate electrode and a word line that partially surround the semiconductor pillar by etching the gate electrode layer that completely surrounds the semiconductor pillar, which can reduce or even avoid the gate electrode parasitic capacitance effect, and realize a smaller size storage unit, thereby improving the integration degree of the device. Moreover, the process flow of the manufacturing method of the semiconductor device according to the embodiment of the present application is simple and can be realized by simple adjustment in the existing manufacturing process of vertical channel transistors. For example, adding a photomask and one step of etching can achieve it.

[0115] In the exemplary embodiment of the present application, etching the gate electrode layer to form a gate electrode that partially surrounds the side walls of the semiconductor pillars, and the gate electrodes on the side walls of one column of the semiconductor pillars spaced apart along the second direction are only connected together on the same side of the column of the semiconductor pillars to form a word line extending along the second direction may include:

[0116] Etch and remove the gate electrode layer on the side walls of the two adjacent columns of the semiconductor pillars that are close to each other in the first direction, so that the gate electrode layer surrounding the side walls of the two adjacent columns of the semiconductor pillars is disconnected on both sides of the same first insulating layer;

[0117] Etch back the remaining gate electrode layer, only retaining the gate electrode layer corresponding to the channel region of the semiconductor pillar, to form a gate electrode partially surrounding the sidewall of the channel region of the semiconductor pillar, and the gate electrodes on the sidewalls of a column of the semiconductor pillars spaced apart along the second direction are only connected together on the side of the column of semiconductor pillars away from the same first insulating layer to form a word line extending along the second direction.

[0118] In an exemplary embodiment of the present application, forming semiconductor pillars arrayed along a first direction and a second direction on a substrate, and using a first insulating layer to space two adjacent columns of the semiconductor pillars distributed along the first direction may include:

[0119] Providing a substrate including a semiconductor material, forming a plurality of first trenches extending along the first direction and spaced apart along the second direction on the substrate, the plurality of first trenches spacing the upper portion of the substrate into a plurality of semiconductor walls;

[0120] Filling the first trenches with a second insulating layer;

[0121] Forming a plurality of second trenches extending along the second direction and spaced apart along the first direction on the substrate, the plurality of second trenches spacing the semiconductor walls into a plurality of semiconductor pillars arrayed along the first direction and the second direction;

[0122] Depositing the second insulating layer with a set thickness on the sidewalls of the second trenches, and filling the second trenches with the first insulating layer; wherein, the set thickness is the sum of the thicknesses of the gate insulating layer and the gate electrode layer to be formed. In an exemplary embodiment of the present application, sequentially depositing a gate insulating layer and a gate electrode layer on the sidewalls of the semiconductor pillars may include:

[0123] Removing the second insulating layer on the upper sidewalls of the semiconductor pillars to expose the upper sidewalls of the semiconductor pillars;

[0124] Depositing a gate insulating layer on the exposed upper sidewalls of the semiconductor pillars, and filling the blank spaces in the first trenches and the second trenches with the gate electrode layer.

[0125] In an exemplary embodiment of the present application, the manufacturing method may further include: after forming the plurality of semiconductor pillars, before depositing the second insulating layer on the sidewalls of the second trenches, performing the following process,

[0126] Etch the substrate between the two semiconductor pillars in the second trench to form a bit line trench that is located below a column of the semiconductor pillars distributed in the first direction and extends in the first direction, and form a bit line in the bit line trench that contacts the bottom of the semiconductor pillars.

[0127] In an exemplary embodiment of the present application, the manufacturing method may further include: after forming the word line, performing the following process:

[0128] Fill the first insulating layer in the space vacated by etching back the gate electrode layer and in the first trench.

[0129] The technical solution of the embodiment of the present application will be further described below through the manufacturing process of a semiconductor device in an exemplary embodiment. The "patterned etching" mentioned in this embodiment includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist, which are mature preparation processes in the related art. The "lithography" process mentioned in this embodiment includes coating a film layer, mask exposure, and development, which are mature preparation processes in the related art. Deposition can use known processes such as sputtering, evaporation, and chemical vapor deposition, coating can use known coating processes, and etching can use known methods, which are not specifically limited herein.

[0130] Figure 4 A longitudinal cross-sectional view of a manufacturing method of a semiconductor device provided in an exemplary embodiment of the present application on a c-c' cross-section after forming the first trench; Figure 5A A longitudinal cross-sectional view of a manufacturing method of a semiconductor device provided in an exemplary embodiment of the present application on an a-a' cross-section after forming the semiconductor pillars; Figure 5B A longitudinal cross-sectional view of a manufacturing method of a semiconductor device provided in an exemplary embodiment of the present application on a c-c' cross-section after forming the semiconductor pillars; Figure 6 A longitudinal cross-sectional view of a manufacturing method of a semiconductor device provided in an exemplary embodiment of the present application on an a-a' cross-section after forming the bit line; Figure 7 A longitudinal cross-sectional view of a manufacturing method of a semiconductor device provided in an exemplary embodiment of the present application on an a-a' cross-section after filling the first insulating layer in the second trench; Figure 8A A longitudinal cross-sectional view of a manufacturing method of a semiconductor device provided in an exemplary embodiment of the present application on an a-a' cross-section after forming the gate electrode layer; Figure 8B A longitudinal cross-sectional view of a manufacturing method of a semiconductor device provided in an exemplary embodiment of the present application on a b-b' cross-section after forming the gate electrode layer; Figure 8C A longitudinal cross-sectional view of a manufacturing method of a semiconductor device provided in an exemplary embodiment of the present application on a c-c' cross-section after forming the gate electrode layer;

[0131] Figure 9A A longitudinal cross-sectional view of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application after forming a partially surrounding gate electrode layer, taken along the a-a' section; Figure 9B A longitudinal cross-sectional view of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application after forming a partially surrounding gate electrode layer, taken along the b-b' section; Figure 10A A longitudinal cross-sectional view of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application after forming a word line, taken along the a-a' section; Figure 10B A longitudinal cross-sectional view of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application after forming a word line, taken along the b-b' section; Figure 10C A longitudinal cross-sectional view of a manufacturing method of a semiconductor device provided by an exemplary embodiment of the present application after forming a word line, taken along the c-c' section.

[0132] As Figures 4 to 10C shown, in an exemplary embodiment, the manufacturing method of the 3D stacked semiconductor device may include the following processes.

[0133] S10: Provide a substrate 13, for example, a substrate 13 made of a semiconductor material, and form a plurality of first trenches 41 on the substrate 13 that extend along the first direction (for example, the a-a' direction or the b-b' direction as shown) and are spaced apart along the second direction (for example, the c-c' direction or the d-d' direction as shown), and the plurality of first trenches 41 divide the upper part of the substrate 13 into a plurality of semiconductor walls, as Figure 2A shown. Figure 2A The plurality of first trenches 41 divide the upper part of the substrate 13 into a plurality of semiconductor walls, as Figure 4 shown.

[0134] S20: Fill the first trenches 41 with a second insulating layer 12; form a plurality of second trenches 42 on the substrate 13 that extend along the second direction and are spaced apart along the first direction, and the plurality of second trenches 42 divide the semiconductor walls into a plurality of semiconductor columns 10 that are arrayed along the first direction and the second direction, as Figure 5A and Figure 5B shown.

[0135] In step S20, different regions of the semiconductor columns 10 can be ion-doped to form a source electrode region, a drain electrode region, and a channel region located between the source electrode region and the drain electrode region with different ion doping concentrations. Moreover, the height of the channel region in the direction perpendicular to the substrate can be adjusted as needed. Additionally, in steps S10 and S20, the thickness of the semiconductor columns can be adjusted as needed. By adjusting the thickness of the semiconductor columns and the height in the direction perpendicular to the substrate, the performance of the device can be improved, for example, electrical properties such as the saturation current and the switching ratio of the transistor can be enhanced.

[0136] Exemplarily, the material of the second insulating layer 12 may be a low-K dielectric material, i.e., a dielectric material with a dielectric constant K < 3.9, including but not limited to oxides of silicon, such as silicon dioxide (SiO 2 ) or other silicon-containing film layers, etc. And the material of the second insulating layer 12 is different from that of the first insulating layer 11, so that when etching to remove one of the first insulating layer 11 and the second insulating layer 12 subsequently, the first insulating layer 11 and the second insulating layer 12 can have different etching rates, thereby removing the insulating layer that is desired to be removed. For example, in this embodiment, the material of the first insulating layer 11 may be silicon nitride, and the material of the second insulating layer 12 may be silicon oxide.

[0137] Exemplarily, both the first trench 41 and the second trench 42 may extend in a direction perpendicular to the substrate 13, and the depth of the first trench 41 may be greater than the depth of the second trench 42.

[0138] S30: Etch the substrate 13 located between the two semiconductor pillars 10 in the second trench 42 to form a bit line groove extending in the first direction and located below a column of semiconductor pillars 10 distributed in the first direction, and form a bit line 30 in the bit line groove that contacts the bottom of the semiconductor pillar 10, as Figure 6 shown.

[0139] S40: Deposit a second insulating layer 12 with a set thickness on the inner wall (including the bottom wall and the side wall) of the second trench 42, and the set thickness is the sum of the thicknesses of the gate insulating layer and the gate electrode layer to be formed;

[0140] Etch and remove the second insulating layer 12 on the bottom wall of the second trench 42 to expose the substrate 13, and fill the second trench 42 with the first insulating layer 11, as Figure 7 shown.

[0141] S50: Remove the second insulating layer 12 on the side wall of the upper part (corresponding to the positions of the drain electrode region and the channel region of the transistor to be formed subsequently) of the semiconductor pillar 10 to expose the side wall of the upper part of the semiconductor pillar 10;

[0142] Deposit a gate insulating layer 22 on the exposed upper side wall of the second insulating layer 12 of the semiconductor pillar 10, and fill the blank space in the first trench 41 and the second trench 42 with a gate electrode layer 21, and the gate electrode layer 21 completely surrounds the side wall of the semiconductor pillar 10, as Figures 8A to 8C shown.

[0143] Exemplarily, the material of the gate insulating layer 22 may be the same as that of the second insulating layer 12.

[0144] In step S50, appropriate gate insulating layer materials and gate electrode layer materials can be selected as needed to improve the performance of the device. For example, the electrical properties of the transistor, such as the saturation current and the switching ratio, can be enhanced.

[0145] S60: Etch away the gate electrode layer 21 on the sidewalls of the adjacent two columns of semiconductor pillars 10 that are close to each other in the first direction, so that the gate electrode layer 21 surrounding the sidewalls of each semiconductor pillar 10 is disconnected on both sides of the same first insulating layer 11, as Figure 9A and Figure 9B shown.

[0146] In step S60, the width of the etched-away gate electrode layer in the first direction can be adjusted as needed to adjust the isolation width between the diameters of the adjacent two word lines to be formed, thereby improving the performance of the device. For example, the electrical properties of the transistor, such as the saturation current and the switching ratio, can be enhanced.

[0147] S70: Perform an etch-back on the remaining gate electrode layer 21, and only retain the gate electrode layer 21 corresponding to the channel region of the semiconductor pillar 10 to form a gate electrode partially surrounding the sidewalls of the channel region of the semiconductor pillar 10, and the gate electrodes on the sidewalls of a column of semiconductor pillars 10 spaced apart in the second direction are only connected together on the side of the column of semiconductor pillars 10 away from the same first insulating layer 11 to form a word line 20 extending in the second direction, as Figures 10A to 10C shown.

[0148] In step S70, the height of the gate electrode in the direction perpendicular to the substrate can be adjusted as needed to adjust the contact area between the gate electrode and the channel region, thereby improving the performance of the device. For example, the electrical properties of the transistor, such as the saturation current and the switching ratio, can be enhanced.

[0149] S80: Fill the space vacated by the etch-back of the gate electrode layer 21 and the first trench 41 with the first insulating layer 11, as Figures 2A to 2E shown.

[0150] The embodiment of the present application further provides an electronic device, and the electronic device includes the semiconductor device provided by the embodiment of the present application.

[0151] In an exemplary embodiment of the present application, the electronic device can be: a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device can include the memory in a computer, etc., which is not limited herein.

[0152] Although the embodiments disclosed in this application are as described above, the content described is only an embodiment adopted for the convenience of understanding this application and is not used to limit this application. Any person skilled in the art within the scope of this application can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the scope of protection of this application shall still be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, It is characterized in that include: A plurality of transistors are distributed in an array along a first direction and a second direction on a substrate; the transistors include semiconductor columns and gate electrodes; A plurality of word lines extend along the second direction and are formed by connecting gate electrodes of a column of transistors spaced apart along the second direction, and the gate electrodes are only located on the same side of the column of transistors spaced apart along the second direction.

2. The semiconductor device according to claim 1, It is characterized in that The sidewall of the semiconductor column includes two first side surfaces extending along the second direction and a second side surface located between the first side surfaces; The word line portion surrounds the semiconductor column of the transistor connected to the word line, and the word line at least exposes one of the first side surfaces.

3. The semiconductor device according to claim 2, It is characterized in that The word line also exposes at least a portion of the second side surface of the semiconductor pillar.

4. The semiconductor device according to claim 3, It is characterized in that The word line surrounds only the other first side surface of the semiconductor pillar.

5. The semiconductor device according to any one of claims 1 to 4, It is characterized in that Two adjacent word lines are isolated from each other by a first insulating layer, and the two adjacent word lines are symmetrically distributed on both sides of the first insulating layer between them.

6. A method for manufacturing a semiconductor device according to any one of claims 1 to 5, It is characterized in that include: Forming semiconductor columns distributed in an array along a first direction and a second direction on a substrate, and using a first insulating layer to separate two adjacent columns of the semiconductor columns distributed along the first direction; Depositing a gate insulating layer and a gate electrode layer in sequence on the sidewall of the semiconductor column, wherein the gate electrode layer completely surrounds the sidewall of the semiconductor column; The gate electrode layer is etched to form a gate electrode that partially surrounds the side wall of the semiconductor column, and the gate electrodes on the side walls of a column of the semiconductor columns spaced apart along the second direction are connected together only on the same side of the column of the semiconductor columns to form a word line extending along the second direction.

7. The manufacturing method according to claim 6, It is characterized in that The gate electrode layer is etched to form a gate electrode partially surrounding the sidewall of the semiconductor pillar, and the gate electrodes on the sidewalls of a column of the semiconductor pillars spaced apart along the second direction are connected together only on the same side of the column of the semiconductor pillars to form a word line extending along the second direction, comprising: Etching and removing the gate electrode layer on the sidewalls of the semiconductor pillars in two adjacent columns in the first direction, so that the gate electrode layer surrounding the sidewalls of the semiconductor pillars in two adjacent columns is disconnected on both sides of the same first insulating layer; The remaining gate electrode layer is etched back to retain only the gate electrode layer corresponding to the channel region of the semiconductor column, forming a gate electrode that partially surrounds the side wall of the channel region of the semiconductor column, and the gate electrodes on the side walls of a column of the semiconductor columns spaced apart along the second direction are connected together only on one side of the column of semiconductor columns away from the same first insulating layer to form a word line extending along the second direction.

8. The manufacturing method according to claim 7, It is characterized in that Semiconductor columns distributed in an array along a first direction and a second direction are formed on a substrate, and two adjacent columns of semiconductor columns distributed along the first direction are separated by a first insulating layer, comprising: Providing a substrate comprising a semiconductor material, forming a plurality of first trenches extending along the first direction and spaced apart along the second direction on the substrate, wherein the plurality of first trenches separate an upper portion of the substrate into a plurality of semiconductor walls; Filling the first trench with a second insulating layer; forming a plurality of second trenches extending along the second direction and spaced apart along the first direction on the substrate, wherein the plurality of second trenches space the semiconductor wall into a plurality of semiconductor pillars arrayed along the first direction and the second direction; The second insulating layer of a set thickness is deposited on the sidewall of the second trench, and the first insulating layer is filled in the second trench; wherein the set thickness is the sum of the thicknesses of the gate insulating layer and the gate electrode layer to be formed.

9. The manufacturing method according to claim 8, It is characterized in that Sequentially depositing a gate insulating layer and a gate electrode layer on the sidewall of the semiconductor column comprises: removing the second insulating layer on the upper sidewall of the semiconductor column to expose the upper sidewall of the semiconductor column; A gate insulating layer is deposited on the exposed upper sidewall of the semiconductor pillar, and the gate electrode layer is filled in the empty spaces of the first trench and the second trench.

10. The manufacturing method according to claim 8, It is characterized in that Also includes: After forming the plurality of semiconductor pillars and before depositing the second insulating layer with a set thickness on the sidewall of the second trench, the following process is performed: The substrate between the two semiconductor pillars is etched in the second trench to form a bit line groove located below a column of the semiconductor pillars distributed along the first direction and extending along the first direction, and a bit line contacting the bottom of the semiconductor pillar is formed in the bit line groove.

11. The manufacturing method according to any one of claims 8 to 10, It is characterized in that Also includes: After forming the word line, the following process is performed: An insulating material is filled in the space vacated by etching back the gate electrode layer and in the first trench.

12. An electronic device, It is characterized in that include: A semiconductor device according to any one of claims 1 to 5.

Images