Semiconductor structure including bit line structure and method of fabricating same

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The semiconductor structure includes a base structure, a bit line structure and a spacer. The bit line structure is disposed over the base structure. The spacer is disposed around the bit line structure and includes a first layer, a second layer, and a third layer. The third layer is disposed over the second layer. A width of the third layer is substantially equal to a width of the second layer.

Description

Technical Field

[0001] This application claims the priority of U.S. Patent Application No. 18 / 518,721 (i.e., the priority date is "November 24, 2023"), the content of which is incorporated herein by reference in its entirety.

[0002] This disclosure relates to a semiconductor structure and a method for manufacturing the same. In particular, it relates to a semiconductor structure including a bit line structure and a method for manufacturing the same. Background Art

[0003] Semiconductor structures are used in various electronic applications, and the size of semiconductor structures is continuously reduced to meet current application requirements. However, various problems occur during the size reduction process, which affect the final electronic characteristics, quality, cost, and yield. A typical memory element (such as a dynamic random access memory (DRAM) element) includes signal lines, such as word lines and bit lines that cross the word lines. As the size of DRAM elements is reduced and the size and / or pitch of signal lines become smaller and smaller, parasitic capacitance will become a key issue.

[0004] The above description of "prior art" only provides background art and does not admit that the above description of "prior art" discloses the subject matter of this disclosure, does not constitute the prior art of this disclosure, and any description of the above "prior art" should not be regarded as any part of this case. Summary of the Invention

[0005] An embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a base structure, a bit line structure, and a spacer. The bit line structure is disposed above the base structure. The spacer is disposed around the bit line structure and includes a first layer, a second layer, and a third layer. The third layer is disposed above the second layer. A width of the third layer is substantially equal to a width of the second layer.

[0006] Another embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a base structure, a first bit line structure, a second bit line structure, a first spacer, and a second spacer. The first bit line structure is disposed above the base structure. The second bit line structure is disposed above the base structure. The first spacer is disposed around the first bit line structure and includes a first layer, a second layer, and a third layer. The third layer of the first spacer is disposed above the second layer of the first spacer. A width of the third layer of the first spacer is substantially equal to a width of the second layer of the first spacer. The second spacer is disposed around the second bit line structure and includes a first layer, a second layer, and a third layer. The third layer of the second spacer is disposed above the second layer of the second spacer. A width of the third layer of the second spacer is substantially equal to a width of the second layer of the second spacer.

[0007] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. The manufacturing method includes providing a base structure, wherein the base structure includes a base portion and at least one active region located in the base portion; forming at least one bit line structure above the at least one active region of the base structure; and forming at least one spacer around the at least one bit line structure, wherein the at least one spacer includes a first layer, a second layer, and a third layer, wherein the third layer is disposed above the second layer and a width of the third layer is substantially equal to a width of the second layer.

[0008] The technical features and advantages of the present disclosure have been outlined quite extensively above, so that a better understanding of the detailed description of the present disclosure below can be obtained. Other technical features and advantages constituting the subject matter of the claims of the present disclosure will be described below. Those of ordinary skill in the art to which the present disclosure pertains should understand that the concepts and specific embodiments disclosed below can be quite easily utilized as a basis for modifying or designing other structures or processes to achieve the same purposes as the present disclosure. Those of ordinary skill in the art to which the present disclosure pertains should also understand that such equivalent constructs cannot depart from the spirit and scope of the present disclosure as defined by the appended claims. Description of the Drawings

[0009] A more complete understanding of the present disclosure can be obtained by referring to the detailed description and the claims. The present disclosure should also be understood as being associated with the element numbers in the drawings, and the element numbers in the drawings represent similar elements throughout the description.

[0010] Figure 1 is a cross-sectional schematic diagram illustrating the semiconductor structure of some embodiments of the present disclosure.

[0011] Figure 2 is an enlarged schematic diagram illustrating Figure 1 region A of

[0012] Figure 3 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0013] Figure 4 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0014] Figure 5 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0015] Figure 6 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0016] Figure 7 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0017] Figure 8 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0018] Figure 9 is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0019] Figure 10 is a flow schematic diagram illustrating a method for fabricating a semiconductor structure according to some embodiments of the present disclosure.

[0020] Among them, the reference numerals are explained as follows:

[0021] 1: Semiconductor structure

[0022] 2: First bit line structure

[0023] 2a: Third bit line structure

[0024] 3: Second bit line structure

[0025] 3a: Fourth bit line structure

[0026] 4: First spacer

[0027] 4a: Third spacer

[0028] 5: Second spacer

[0029] 5a: Fourth spacer

[0030] 6: First cell contact structure

[0031] 6a: Second unit contact structure

[0032] 6b: Third unit contact structure

[0033] 6c: Fourth unit contact structure

[0034] 6d: Fifth unit contact structure

[0035] 10: Base structure

[0036] 11: First active area

[0037] 11a: Fourth active area

[0038] 12: Second active area

[0039] 12a: Fifth active area

[0040] 13: Third active area

[0041] 13a: Sixth active area

[0042] 21: Main part

[0043] 21a: Main part

[0044] 22: Covering part

[0045] 22a: Covering part

[0046] 23: Conductor

[0047] 23a: Conductor

[0048] 31: Main part

[0049] 31a: Main part

[0050] 32: Covering part

[0051] 32a: Covering part

[0052] 33: Insulator

[0053] 33a: Insulator

[0054] 41: First layer

[0055] 41a: First layer

[0056] 42: Second layer

[0057] 42a: Second layer

[0058] 43: Third layer

[0059] 43a: Third layer

[0060] 51: First layer

[0061] 51a: The first layer

[0062] 52: The second layer

[0063] 52a: The second layer

[0064] 53: The third layer

[0065] 53a: The third layer

[0066] 61: The first part

[0067] 61': The contact layer

[0068] 62: The second part

[0069] 70: The gap

[0070] 71: The gap

[0071] 73: The covering layer

[0072] 74: The opening

[0073] 100: The base part

[0074] 101: The first surface

[0075] 211: The upper surface

[0076] 311: The upper surface

[0077] 421: The upper surface

[0078] 521: The upper surface

[0079] 611: The upper surface

[0080] 900: The preparation method

[0081] S901: Step

[0082] S902: Step

[0083] S903: Step

[0084] W1: Width

[0085] W2: Width

[0086] W3: Width

[0087] W4: Width

[0088] W5: Width Specific implementation manners

[0089] Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these embodiments are for illustration only and are not intended to limit the scope of the present disclosure. For example, when it is described that the first component is formed on the second component, it may include embodiments where the first and second components are in direct contact, or it may include embodiments where additional components are formed between the first and second components such that the first and second components are not in direct contact. Additionally, the embodiments of the present disclosure may repeat reference numerals and / or letters in many examples. The purpose of these repetitions is to simplify and clarify, and unless otherwise specified in the text, they do not themselves represent a specific relationship between the various embodiments and / or the configurations being discussed.

[0090] It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. On the contrary, these terms are only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Thus, without departing from the teachings of the inventive concept of progressiveness, the first element, component, region, layer, or section discussed below may be referred to as the second element, component, region, layer, or section.

[0091] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprises" and / or "comprising" are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0092] Figure 1 is a cross-sectional schematic diagram illustrating a semiconductor structure 1 of some embodiments of the present disclosure. Figure 2 is an enlarged schematic diagram illustrating Figure 1 region A of. In some embodiments, the semiconductor structure 1 may be a semiconductor element including a circuit, such as a memory cell. In some embodiments, the memory cell may include a dynamic random access memory cell (DRAM cell).

[0093] Additionally, the semiconductor structure 1 can be or include a part of an integrated circuit (IC) wafer, which includes various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC components, or combinations thereof.

[0094] The semiconductor structure 1 can include a base structure 10, at least one bit line structure (e.g., a first bit line structure 2, a second bit line structure 3, a third bit line structure 2a, and a fourth bit line structure 3a), at least one spacer (e.g., a first spacer 4, a second spacer 5, a third spacer 4a, and a fourth spacer 5a), and at least one cell contact structure (e.g., a first cell contact structure 6, a second cell contact structure 6a, a third cell contact structure 6b, a fourth cell contact structure 6c, and a fifth cell contact structure 6d).

[0095] The base structure 10 can be a substrate and can include a dielectric material, such as an oxide material or a nitride material. Alternatively, the base structure 10 can be a substrate and can include, for example, silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other group IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the base structure 10 can include a base portion 100 and at least one active region (e.g., a first active region 11, a second active region 12, a third active region 13, a fourth active region 11a, a fifth active region 12a, and a sixth active region 13a) disposed in or embedded in the base portion 100. The base portion 100 can include a dielectric oxide material. Each active region (e.g., the first active region 11, the second active region 12, the third active region 13, the fourth active region 11a, the fifth active region 12a, and the sixth active region 13a) can include silicon (Si) material. For example, each of the first active region 11 and the fourth active region 11a can be a drain electrode. The second active region 12, the third active region 13, the fifth active region 12a, and the sixth active region 13a are all source electrodes.

[0096] In some embodiments, as Figure 1As shown, the base structure 10 may have a first surface 101 (e.g., an upper surface). Active regions (e.g., the first active region 11, the second active region 12, the third active region 13, the fourth active region 11a, the fifth active region 12a, and the sixth active region 13a) may be exposed from the first surface 101 (e.g., the upper surface) of the base structure 10.

[0097] At least one bit line structure may include a plurality of bit line structures, e.g., the first bit line structure 2, the second bit line structure 3, the third bit line structure 2a, and the fourth bit line structure 3a, and may be disposed above the base structure 10. The first bit line structure 2 may include a main portion 21 and a covering portion 22 disposed on the main portion 21. The main portion 21 may include tungsten (W), and the covering portion 22 may include silicon nitride (SiN). The main portion 21 of the first bit line structure 2 may be electrically connected to the first active region 11 via a conductor 23. The conductor 23 may be an electrical contact and may be disposed between the main portion 21 of the first bit line structure 2 and the first active region 11. Examples of materials of the conductor 23 may include polysilicon. The first active region 11 may be disposed directly below the first bit line structure 2. A width W1 of the first active region 11 may be smaller than a width W2 of the conductor 23. The width W2 of the conductor 23 may be substantially equal to a width of the first bit line structure 2. Thus, the first bit line structure 2 may be completely vertically overlapped with the first active region 11. The entire first active region 11 may be disposed within a vertical projection of the first bit line structure 2.

[0098] The first spacer 4 may be disposed around or adjacent to the first bit line structure 2. The first spacer 4 may include a first layer 41, a second layer 42, and a third layer 43. The first layer 41 may include silicon nitride (SiN), the second layer 42 may include an oxide material such as silicon oxide (SiO 2 )), and the third layer 43 may include silicon nitride (SiN). The third layer 43 may be disposed above or on the second layer 42. A width W3 of the third layer 43 may be substantially equal to a width W4 of the second layer 42.

[0099] The first layer 41 can be inserted between the second layer 42 and the first bit line structure 2. A width W5 of the first layer 41 can be smaller than a width W4 of the second layer 42. For example, the width W5 of the first layer 41 can be substantially equal to half of the width W4 of the second layer 42. The material of the first layer 41 can be different from the material of the second layer 42. Additionally, the first layer 41 can be inserted between the third layer 43 and the first bit line structure 2. The width W5 of the first layer 41 can be smaller than a width W3 of the third layer 43. For example, the width W5 of the first layer 41 can be substantially equal to half of the width W3 of the third layer 43. The material of the first layer 41 can be the same as the material of the third layer 43.

[0100] As Figure 2 shown, one side surface of the second layer 42 can be substantially aligned with one side surface of the third layer 43. The first layer 41 can contact the side surface of the second layer 42 and the side surface of the third layer 43. A length (or a height) of the first layer 41 can be substantially equal to the sum of a length (or a height) of the second layer 42 and a length (or a height) of the third layer 43. Additionally, a height of an upper surface 211 of a main portion 21 of the first bit line structure 2 can be lower than a height of an upper surface 421 of the second layer 42 of the first spacer 4. The upper surface 211 of the main portion 21 of the first bit line structure 2 can be an interface between the main portion 21 and the covering portion 22. The upper surface 421 of the second layer 42 of the first spacer 4 can be an interface between the second layer 42 and the third layer 43.

[0101] As Figure 1 and Figure 2 shown, the second bit line structure 3 can include a main portion 31 and a covering portion 32 disposed on the main portion 31. The structure of the second bit line structure 3 can be the same as or similar to the structure of the first bit line structure 2. The main portion 31 can include tungsten (W), and the covering portion 32 can include silicon nitride (SiN). The main portion 31 of the second bit line structure 3 can be electrically insulated from the second active region 12 and the third active region 13 via an insulator 33. The insulator 33 can be an electrical insulator and can be disposed in a gap between the main portion 31 of the second bit line structure 3 and the second active region 12 and the third active region 13. Examples of the material of the insulator 33 can include nitride materials.

[0102] The gap between the second active region 12 and the third active region 13 can be disposed below the second bit line structure 3. The width of the insulator 33 can be substantially equal to a width of the second bit line structure 3. Thus, the second bit line structure 3 can be partially vertically overlapped with the second active region 12 and the third active region 13. Additionally, the width of the insulator 33 can be substantially equal to the width W2 of the conductor 23, and the thickness of the insulator 33 can be substantially equal to the thickness of the conductor 23.

[0103] The structure of the second spacer 5 can be the same as or similar to that of the first spacer 4. The second spacer 5 can be disposed around or adjacent to the second bit line structure 3. The second spacer 5 can include a first layer 51, a second layer 52, and a third layer 53. The first layer 51 can include silicon nitride (SiN), and the second layer 52 can include an oxide material such as silicon oxide (SiO 2 ), and the third layer 53 can include silicon nitride (SiN). The third layer 53 can be disposed above or on the second layer 52. A width of the third layer 53 can be substantially equal to a width of the second layer 52.

[0104] The first layer 51 can be interposed between the second layer 52 and the second bit line structure 3. A width W5 of the first layer 51 can be less than a width W4 of the second layer 52. For example, the width W5 of the first layer 51 can be substantially equal to half of the width W4 of the second layer 52. The material of the first layer 51 can be different from the material of the second layer 52. Additionally, the first layer 51 can be interposed between the third layer 53 and the second bit line structure 3. The width W5 of the first layer 51 can be less than a width W3 of the third layer 53. For example, the width W5 of the first layer 51 can be substantially equal to half of the width W3 of the third layer 53. The material of the first layer 51 can be the same as the material of the third layer 53.

[0105] As Figure 2 shown, a side surface of the second layer 52 can be substantially aligned with a side surface of the third layer 53. The first layer 51 can contact the side surface of the second layer 52 and the side surface of the third layer 53. A length (or a height) of the first layer 51 can be substantially equal to the sum of a length (or a height) of the second layer 52 and a length (or a height) of the third layer 53. Additionally, a height of an upper surface 311 of a main portion 31 of the second bit line structure 3 can be lower than a height of an upper surface 521 of the second layer 52 of the second spacer 5. The upper surface 311 of the main portion 31 of the second bit line structure 3 can be an interface between the main portion 31 and a covering portion 32. The upper surface 521 of the second layer 52 of the second spacer 5 can be an interface between the second layer 52 and the third layer 53.

[0106] As Figure 1 and Figure 2As shown, at least one unit contact structure may include a plurality of unit contact structures. For example, a first unit contact structure 6, a second unit contact structure 6a, a third unit contact structure 6b, a fourth unit contact structure 6c, and a fifth unit contact structure 6d. The unit contact structure may be disposed or inserted between two spacer elements and may be electrically connected to an active region of the base structure 10. For example, the first unit contact structure 6 may be disposed or inserted between the first spacer element 4 and the second spacer element 5 and may be electrically connected to the second active region 12 of the base structure 10.

[0107] The first unit contact structure 6 may include a first portion 61 and a second portion 62 disposed on the first portion 61. The material of the first portion 61 may include a conductive material such as polysilicon. The material of the second portion 62 may include a conductive material of tungsten (W). The material of the first portion 61 may be the same as or different from the material of the second portion 62.

[0108] The upper surface 611 of the first portion 61 of the first unit contact structure 6 may not be aligned with the upper surface 421 of the second layer 42 of the first spacer element 4. In some embodiments, the height of the upper surface 611 of the first portion 61 of the first unit contact structure 6 may be higher than the height of the upper surface 421 of the second layer 42 of the first spacer element 4. Accordingly, the second portion 62 of the first unit contact structure 6 does not contact the second layer 42 of the first spacer element 4. Or, the second portion 62 of the first unit contact structure 6 does not horizontally overlap the second layer 42 of the first spacer element 4.

[0109] In addition, the upper surface 611 of the first portion 61 of the first unit contact structure 6 may not be aligned with the upper surface 521 of the second layer 52 of the second spacer element 5. In some embodiments, the height of the upper surface 611 of the first portion 61 of the first unit contact structure 6 may be higher than the height of the upper surface 521 of the second layer 52 of the second spacer element 5. Accordingly, the second portion 62 of the first unit contact structure 6 does not contact the second layer 52 of the second spacer element 5. Or, the second portion 62 of the first unit contact structure 6 does not horizontally overlap the second layer 52 of the second spacer element 5.

[0110] The third-bit line structure 2a may include a main portion 21a and a covering portion 22a disposed on the main portion 21a. The structure of the third-bit line structure 2a may be the same as or similar to the structure of the first-bit line structure 2. The main portion 21a of the third-bit line structure 2a may be electrically connected to the fourth active region 11a via a conductor 23a. The conductor 23a may be an electrical contact and may be disposed between the main portion 21a of the third-bit line structure 2a and the fourth active region 11a. Examples of the material of the conductor 23a may include polysilicon. The fourth active region 11a may be disposed directly below the third-bit line structure 2a. A width of the fourth active region 11a may be smaller than a width of the conductor 23a. The width of the conductor 23a may be substantially equal to a width of the third-bit line structure 2a. Thus, the third-bit line structure 2a may be completely vertically overlapped with the fourth active region 11a. The entire fourth active region 11a may be disposed within a vertical projection of the third-bit line structure 2a.

[0111] The third spacer 4a may be disposed around or adjacent to the third-bit line structure 2a. The third spacer 4a may include a first layer 41a, a second layer 42a, and a third layer 43a. The structure of the third spacer 4a may be the same as or similar to the structure of the first spacer 4. The third layer 43a may be disposed above the second layer 42a or on the second layer 42a. A width of the third layer 43a may be substantially equal to a width of the second layer 42a.

[0112] The first layer 41a may be interposed between the second layer 42a and the third-bit line structure 2a. A width of the first layer 41a may be smaller than the width of the second layer 42a. For example, the width of the first layer 41a may be substantially equal to half of the width of the second layer 42a. The material of the first layer 41a may be different from the material of the second layer 42a. Additionally, the first layer 41a may be interposed between the third layer 43a and the third-bit line structure 2a. The width of the first layer 41a may be smaller than the width of the third layer 43a. For example, the width of the first layer 41a may be substantially equal to half of the width of the third layer 43a. The material of the first layer 41a may be the same as the material of the third layer 43a.

[0113] One side surface of the second layer 42a may be substantially aligned with one side surface of the third layer 43a. The first layer 41a may contact the side surface of the second layer 42a and the side surface of the third layer 43a. A length (or a height) of the first layer 41a may be substantially equal to the sum of a length (or a height) of the second layer 42a and a length (or a height) of the third layer 43a. Additionally, a height of an upper surface of the main portion 21a of the third-bit line structure 2a may be lower than a height of an upper surface of the second layer 42a of the third spacer 4a.

[0114] The second unit contact structure 6a can be disposed or inserted between the third spacer 4a and the second spacer 5, and can be electrically connected to the third active region 13 of the base structure 10. The second unit contact structure 6a can include a first portion 61 and a second portion 62 disposed on the first portion 61. The structure of the second unit contact structure 6a can be the same as or similar to the structure of the first unit contact structure 6.

[0115] An upper surface of the first portion 61 of the second unit contact structure 6a may not be aligned with an upper surface of the second layer 42a of the third spacer 4a. In some embodiments, a height of the upper surface of the first portion 61 of the second unit contact structure 6a may be higher than a height of the upper surface of the second layer 42a of the third spacer 4a. Accordingly, the second portion 62 of the second unit contact structure 6a does not contact the second layer 42a of the third spacer 4a. Alternatively, the second portion 62 of the second unit contact structure 6a does not horizontally overlap with the second layer 42a of the third spacer 4a.

[0116] In addition, the upper surface of the first portion 61 of the second unit contact structure 6a may not be aligned with the upper surface 521 of the second layer 52 of the second spacer 5. In some embodiments, a height of the upper surface of the first portion 61 of the second unit contact structure 6a may be higher than a height of the upper surface 521 of the second layer 52 of the second spacer 5. Accordingly, the second portion 62 of the second unit contact structure 6a does not contact the second layer 52 of the second spacer 5. Alternatively, the second portion 62 of the second unit contact structure 6a does not horizontally overlap with the second layer 52 of the second spacer 5. In addition, the third unit contact structure 6b can contact the third spacer 4a.

[0117] The fourth bit line structure 3a can include a main portion 31a and a covering portion 32a disposed on the main portion 31a. The structure of the fourth bit line structure 3a can be the same as or similar to the structure of the second bit line structure 3. The main portion 31a of the fourth bit line structure 3a can be electrically insulated from the fifth active region 12a and the sixth active region 13a via an insulator 33a. The insulator 33a can be an electrical insulator and can be disposed in a gap between the main portion 31a of the fourth bit line structure 3a and the fifth active region 12a and a sixth active region 13a.

[0118] The gap between the fifth active region 12a and the sixth active region 13a can be disposed below the fourth bit line structure 3a. The width of the insulator 33a can be substantially equal to a width of the fourth bit line structure 3a. Accordingly, the fourth bit line structure 3a can be partially vertically overlapped with the fifth active region 12a and the sixth active region 13a.

[0119] The structure of the fourth spacer 5a can be the same as or similar to the structure of the second spacer 5. The fourth spacer 5a can be disposed around or adjacent to the fourth bit line structure 3a. The fourth spacer 5a can include a first layer 51a, a second layer 52a, and a third layer 53a. The third layer 53a can be disposed above or on the second layer 52a. The first layer 51a can be interposed between the second layer 52a and the fourth bit line structure 3a. A width of the first layer 51a can be smaller than a width of the second layer 52a. Additionally, the first layer 51a can be interposed between the third layer 53a and the fourth bit line structure 3a. The width of the first layer 51a can be smaller than the width of the third layer 53a.

[0120] The first layer 51a can contact a side surface of the second layer 52a and a side surface of the third layer 53a. A length (or a height) of the first layer 51a can be substantially equal to a sum of a length (or a height) of the second layer 52a and a length (or a height) of the third layer 53a. Additionally, a height of an upper surface of a main portion 31a of the fourth bit line structure 3a can be lower than a height of an upper surface of the second layer 52a of the fourth spacer 5a.

[0121] The fourth unit contact structure 6c can be disposed or interposed between the first spacer 4 and the fourth spacer 5a, and can be electrically connected to a sixth active region 13a of the base structure 10. The fourth unit contact structure 6c can include a first portion 61 and a second portion 62 disposed on the first portion 61. The structure of the fourth unit contact structure 6c can be the same as or similar to the structure of the first unit contact structure 6. Additionally, the fifth unit contact structure 6d can contact the fourth spacer 5a.

[0122] In some embodiments, a dielectric constant (k) of the first layer 41 (e.g., silicon nitride (SiN) material) of the first spacer 4 can be 7, and a dielectric constant (k) of the second layer 42 (e.g., oxide) of the first spacer 4 can be 3.9. Thus, the dielectric constant (k) of the first layer 41 (e.g., silicon nitride (SiN) material) of the first spacer 4 can be greater than the dielectric constant (k) of the second layer 42 (e.g., oxide material) of the first spacer 4. As Figure 1 and Figure 2 shown, only the first layer 41 (e.g., silicon nitride (SiN) material) and the second layer 42 (e.g., oxide material) are disposed between a main portion 21 (e.g., tungsten material) of the first bit line structure 2 and a first portion 61 (e.g., polysilicon material) of the first unit contact structure 6. Thus, the dielectric constant (k) between the main portion 21 of the first bit line structure 2 and the first portion 61 of the first unit contact structure 6 can be relatively low. As a result, the parasitic capacitance adjacent to the main portion 21 of the first bit line structure 2 is reduced, and the signal margin is improved or increased.

[0123] In a comparative embodiment, a spacer between a bit line and a cell contact may be a three-layer structure, such as a SiN-Ox-SiN structure. Since the dielectric constant (k) of SiN is 7 and the dielectric constant (k) of Ox is 3.9, the three-layer structure includes two high-k layers (i.e., SiN layers). Therefore, the dielectric constant (k) of the three-layer structure is relatively high, which results in a high parasitic capacitance, thereby reducing the signal margin. That is, the SiN layer is the main trigger for generating a high parasitic capacitance.

[0124] Figures 3 to 9 Illustrate a method of manufacturing a semiconductor structure 1 according to some embodiments of the present disclosure.

[0125] Please refer to Figure 3 , and provide a base structure 10. Figure 3 The base structure 10 of Figure 1 may be the same as or similar to the base structure 10 of Figure 1 . The base structure 10 may be a substrate and may include a dielectric material, such as an oxide material or a nitride material. Alternatively, the base structure 10 may be a substrate and may include, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), gallium (Ga), gallium arsenide (GaAs), indium (In), indium arsenide (InAs), indium phosphide (InP), or other Group IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the substrate structure 10 may include a base portion 100 and at least one active region (e.g., a first active region 11, a second active region 12, a third active region 13, a fourth active region 11a, a fifth active region 12a, and a sixth active region 13a) disposed in or embedded in the base portion 100. The base portion 100 may include a dielectric oxide material. Each active region (e.g., the first active region 11, the second active region 12, the third active region 13, the fourth active region 11a, the fifth active region 12a, and the sixth active region 13a) may include silicon (Si) material. For example, each of the first active region 11 and the fourth active region 11a may be a drain electrode. Each of the second active region 12, the third active region 13, the fifth active region 12a, and the sixth active region 13a is a source electrode.

[0126] In some embodiments, the base structure 10 may have a first surface 101 (e.g., an upper surface). The active regions (e.g., the first active region 11, the second active region 12, the third active region 13, the fourth active region 11a, the fifth active region 12a, and the sixth active region 13a) may be exposed from the first surface 101 (e.g., the upper surface) of the base structure 10.

[0127] Please refer toFigure 4 At least one bit line structure is formed above at least one active region of the base structure 10. The at least one bit line structure may include a plurality of bit line structures, such as a first bit line structure 2, a second bit line structure 3, a third bit line structure 2a, and a fourth bit line structure 3a, and may be disposed on a first surface 101 (e.g., the upper surface) of the base structure 10. The first bit line structure 2 may include a main portion 21 and a covering portion 22 disposed on the main portion 21. The main portion 21 may include tungsten (W), and the covering portion 22 may include silicon nitride (SiN). The main portion 21 of the first bit line structure 2 may be electrically connected to the first active region 11 via a conductor 23. The conductor 23 may be an electrical contact and may be disposed between the main portion 21 of the first bit line structure 2 and the first active region 11. Examples of the material of the conductor 23 may include polysilicon. The first active region 11 may be disposed directly below the first bit line structure 2. A width of the first active region 11 may be smaller than a width of the conductor 23. The width of the conductor 23 may be substantially equal to a width of the first bit line structure 2. Thus, the first bit line structure 2 may be completely vertically overlapped with the first active region 11. The entire first active region 11 may be disposed within a vertical projection of the first bit line structure 2.

[0128] The second bit line structure 3 may include a main portion 31 and a covering portion 32 disposed on the main portion 31. The structure of the second bit line structure 3 may be the same as or similar to the structure of the first bit line structure 2. The main portion 31 may include tungsten (W), and the covering portion 32 may include silicon nitride (SiN). The main portion 31 of the second bit line structure 3 may be electrically insulated from the second active region 12 and the third active region 13 via an insulator 33. The insulator 33 may be an electrical insulator and may be disposed in a gap between the main portion 31 of the second bit line structure 3 and the second active region 12 and the third active region 13. Examples of the material of the insulator 33 may include nitride materials.

[0129] The gap between the second active region 12 and the third active region 13 may be disposed below the second bit line structure 3. The width of the insulator 33 may be substantially equal to a width of the second bit line structure 3. Thus, the second bit line structure 3 may be partially vertically overlapped with the second active region 12 and the third active region 13. Additionally, the width of the insulator 33 may be substantially equal to the width of the conductor 23, and the thickness of the insulator 33 may be substantially equal to the thickness of the conductor 23.

[0130] The third bit line structure 2a may include a main portion 21a and a covering portion 22a disposed on the main portion 21a. The structure of the third bit line structure 2a may be the same as or similar to the structure of the first bit line structure 2. The main portion 21a of the third bit line structure 2a may be electrically connected to the fourth active region 11a via a conductor 23a. The conductor 23a may be an electrical contact and may be disposed between the main portion 21a of the third bit line structure 2a and the fourth active region 11a. Examples of the material of the conductor 23a may include polysilicon. The fourth active region 11a may be disposed directly below the third bit line structure 2a. A width of the fourth active region 11a may be smaller than a width of the conductor 23a. The width of the conductor 23a may be substantially equal to a width of the third bit line structure 2a. Accordingly, the third bit line structure 2a may be completely vertically overlapped with the fourth active region 11a. The entire fourth active region 11a may be disposed within a vertical projection of the third bit line structure 2a.

[0131] The fourth bit line structure 3a may include a main portion 31a and a covering portion 32a disposed on the main portion 31a. The structure of the fourth bit line structure 3a may be the same as or similar to the structure of the second bit line structure 3. The main portion 31a of the fourth bit line structure 3a may be electrically insulated from the fifth active region 12a and the sixth active region 13a via an insulator 33a. The insulator 33a may be an electrical insulator and may be disposed in a gap between the main portion 31a of the fourth bit line structure 3a and the fifth active region 12a and the sixth active region 13a.

[0132] The gap between the fifth active region 12a and the sixth active region 13a may be disposed below the fourth bit line structure 3a. The width of the insulator 33a may be substantially equal to a width of the fourth bit line structure 3a. Accordingly, the fourth bit line structure 3a may be partially vertically overlapped with the fifth active region 12a and the sixth active region 13a.

[0133] Please refer to Figure 5 , at least one first layer (e.g., a first layer 41, a first layer 51, a first layer 41a, and a first layer 51a) may be formed around at least one bit line structure (e.g., the first bit line structure 2, the second bit line structure 3, the third bit line structure 2a, and the fourth bit line structure 3a), respectively. The first layers 41, 51, 41a, 51a may include silicon nitride (SiN). In some embodiments, the first layers 41, 51, 41a, 51a may be formed or disposed on a first surface 101 (e.g., an upper surface) of the base structure 10 and may contact the bit line structures 2, 3, 2a, 3a, respectively.

[0134] Then, at least one second layer (e.g., a second layer 42, a second layer 52, a second layer 42a, and a second layer 52a) can be formed around the first layer (e.g., a first layer 41, a first layer 51, a first layer 41a, and a first layer 51a), respectively. The second layers 42, 52, 42a, 52a can include, for example, an oxide material such as silicon oxide (SiO 2 ). In some embodiments, the second layers 42, 52, 42a, 52a can be formed or disposed on the first surface 101 (e.g., the upper surface) of the base structure 10 and can contact the first layers 41, 51, 41a, 51a, respectively. A width W4 of the second layers 42, 52, 42a, 52a is greater than a width W5 of the first layers 41, 51, 41a, 51a. A height of the second layers 42, 52, 42a, 52a can be substantially equal to a height of the first layers 41, 51, 41a, 51a. Meanwhile, there is a gap 70 between the second layers 42, 52, 42a, 52a.

[0135] Please refer to Figure 6 , at least one contact layer 61' can be formed or disposed in the gap 70 between the second layers 42, 52, 42a, 52a. The contact layer 61' can contact the second layers 42, 52, 42a, 52a. A material of the contact layer 61' can include, for example, a conductive material such as polysilicon. In some embodiments, the contact layer 61' can be formed or disposed on the first surface 101 (e.g., the upper surface) of the base structure 10 and can fill the gap 70 between the second layers 42, 52, 42a, 52a. A height of the contact layer 61' can be substantially equal to the height of the second layers 42, 52, 42a, 52a and the height of the first layers 41, 51, 41a, 51a.

[0136] In some embodiments, a grinding or polishing process (e.g., chemical mechanical planarization (CMP)) can be performed on the upper surface of the contact layer 61', on the upper surfaces of the second layers 42, 52, 42a, 52a, on the upper surfaces of the first layers 41, 51, 41a, 51a, and on the upper surfaces of the covering portions 22, 32, 22a, 32a of the bit line structures 2, 3, 2a, 3a. Thus, the upper surface of the contact layer 61', the upper surfaces of the second layers 42, 52, 42a, 52a, the upper surfaces of the first layers 41, 51, 41a, 51a, and the upper surfaces of the covering portions 22, 32, 22a, 32a of the bit line structures 2, 3, 2a, 3a can be coplanar with each other.

[0137] Please refer to Figure 7, a part (e.g., an upper part) of the contact layer 61' can be removed to form a first part 61. A part (e.g., an upper part) of the second layers 42, 52, 42a, 52a can be removed. Accordingly, the height of the second layers 42, 52, 42a, 52a can be reduced. As Figure 7 shown, the first part 61 can protrude from the remaining second layers 42, 52, 42a, 52a. A height of the first part 61 can be greater than a height of the remaining second layers 42, 52, 42a, 52a. A height of the upper surface of the first part 61 can be higher than a height of the upper surface of the second layer 52. Meanwhile, there are gaps 71 between the upper parts of the first layers 41, 51, 41a, 51a.

[0138] Please refer to Figure 8 , a covering layer 73 can be formed or disposed in the gaps 71 between the upper parts of the first layers 41, 51, 41a, 51a. The covering layer 73 can include silicon nitride (SiN). In some embodiments, the covering layer 73 can fill the gaps 71 between the second layers 42, 52, 42a, 52a so as to cover and contact the first part 61 and the second layers 42, 52, 42a, 52a.

[0139] Please refer to Figure 9 , a part of the covering layer 73 on the first part 61 can be removed to form at least one opening 74 corresponding to the first part 61. That is, the opening 7 can be recessed from the upper surface of the covering layer 73 to expose the first part 61. The remaining covering layer 73 can become a third layer 43, 53, 43a, 53a formed on the second layers 42, 52, 42a, 52a. The opening 74 can be defined by the third layer 43, 53, 43a, 53a and the first part 61.

[0140] Meanwhile, at least one spacer (e.g., a first spacer 4, a second spacer 5, a third spacer 4a, and a fourth spacer 5a) can be respectively formed around at least one bit line structure (e.g., a first bit line structure 2, a second bit line structure 3, a third bit line structure 2a, and a fourth bit line structure 3a). Figure 9 The structures of the spacers 4, 5, 4a, 5a can be the same as or similar to the structures of the spacers 4, 5, 4a, 5a in Figure 1 . For example, the first spacer 4 can include a first layer 41, a second layer 42, and a third layer 43. The third layer 43 can be disposed above the second layer 42, and a width of the third layer 43 can be substantially equal to a width of the second layer 42.

[0141] Then, a second part 62 can be formed or disposed in the opening 74. Thus, the second part 62 can fill the opening 74 and can be formed or disposed on the first part 61 to form a unit contact structure 6, 6a, 6b, 6c, 6d. Thereby, the Figure 1 semiconductor structure 1 as shown is obtained. At the same time, the unit contact structure 6, 6a, 6b, 6c, 6d can include a first part 61 and a second part 62. A material of the second part 62 can include a conductive material of tungsten (W).

[0142] Figure 10 is a process schematic diagram illustrating a method 900 for manufacturing a semiconductor structure according to some embodiments of the present disclosure.

[0143] In some embodiments, the manufacturing method 900 can include a step S901 of providing a base structure, where the base structure includes a base part and at least one active region located in the base part.

[0144] For example, as Figure 3 shown, a base structure 10 is provided. The base structure 10 includes a base part 100 and at least one active region 11, 12, 13, 11a, 12a, 13a located in the base part 100.

[0145] In some embodiments, the manufacturing method 900 can include a step S902 of forming at least one bit line structure above the at least one active region of the base structure. For example, as Figure 4 shown, at least one bit line structure 2, 3, 2a, 3a is formed above at least one active region 11, 12, 13, 11a, 12a, 13a of the base structure 10.

[0146] In some embodiments, the manufacturing method 900 can include a step S903 of forming at least one spacer around the at least one bit line structure, where the at least one spacer includes a first layer, a second layer, and a third layer, where the third layer is disposed above the second layer, and a width of the third layer is substantially equal to a width of the second layer. For example, as Figure 1 shown, at least one spacer 4, 5, 4a, 5a is formed around at least one bit line structure 2, 3, 2a, 3a. At least one spacer 4, 5, 4a, 5a includes a first layer 41, 51, 41a, 51a, a second layer 42, 52, 42a, 52a, and a third layer 43, 53, 43a, 53a. The third layer 43, 53, 43a, 53a is disposed above the second layer 42, 52, 42a, 52a, and a width of the third layer 43, 53, 43a, 53a is substantially equal to a width of the second layer 42, 52, 42a, 52a.

[0147] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the spirit and scope of the present disclosure as defined by the claims. For example, many of the processes described above can be implemented in different ways, and many of the processes described above can be replaced by other processes or combinations thereof.

[0148] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art can understand from the disclosure of the present disclosure that existing or future-developed processes, machines, manufactures, compositions of matter, means, methods, or steps that can be used in accordance with the present disclosure and have the same function or achieve substantially the same result as the corresponding embodiments described herein. Accordingly, such processes, machines, manufactures, compositions of matter, means, methods, or steps are included in the claims of the present application.

Claims

1. A semiconductor structure comprising: a base structure; a bit line structure disposed above the base structure; as well as A spacer is disposed around the bit line structure and includes a first layer, a second layer and a third layer, wherein the third layer is disposed above the second layer and a width of the third layer is substantially equal to a width of the second layer.

2. The semiconductor structure of claim 1, wherein the base structure comprises a base portion and an active region located in the base portion, wherein the bit line structure is electrically connected to the active region via a conductor.

3. The semiconductor structure of claim 1, wherein the base structure comprises a base portion and an active region located in the base portion, wherein the bit line structure is electrically insulated from the active region via an insulator. 4 . The semiconductor structure as claimed in claim 1 , wherein the first layer is between the second layer and the bit line structure, and a width of the first layer is smaller than a width of the second layer. 5 . The semiconductor structure of claim 4 , wherein the width of the first layer is substantially equal to half of the width of the second layer. The semiconductor structure as claimed in claim 4 , wherein a material of the first layer is different from a material of the second layer. 7 . The semiconductor structure as claimed in claim 1 , wherein the first layer is between the third layer and the bit line structure, and a width of the first layer is smaller than a width of the third layer. 8 . The semiconductor structure of claim 7 , wherein the width of the first layer is substantially equal to half of the width of the third layer. 9 . The semiconductor structure as claimed in claim 7 , wherein a material of the first layer is the same as a material of the third layer.

10. The semiconductor structure of claim 1, wherein the bit line structure comprises a main portion and a covering portion disposed on the main portion, wherein a height of an upper surface of the main portion is lower than a height of an upper surface of the second layer of the spacer.

11. A method for preparing a semiconductor structure, comprising: Providing a base structure, wherein the base structure includes a base portion and at least one active area located in the base portion; forming at least one bit line structure above the at least one active region of the base structure; as well as At least one spacer is formed around the at least one bit line structure, wherein the at least one spacer includes a first layer, a second layer, and a third layer, wherein the third layer is disposed above the second layer and a width of the third layer is substantially equal to a width of the second layer.

12. The method of claim 11, wherein forming at least one spacer around the at least one bit line structure comprises: forming a first layer around the at least one bit line structure; forming a second layer around the first layer; removing a portion of the second layer; as well as A third layer is formed on the second layer. The preparation method as claimed in claim 12 , wherein a width of the second layer is greater than a width of the first layer.

14. The preparation method according to claim 12, further comprising: forming a contact layer to contact the second layer; removing a portion of the contact layer to form a first portion; as well as A second portion is formed on the first portion.

15. The method of claim 11, wherein forming the at least one spacer around the at least one bit line structure comprises: forming a first layer around the at least one bit line structure; forming a second layer around the first layer; forming a contact layer to contact the second layer; removing a portion of the second layer and a portion of the contact layer to form a first portion; forming a third layer on the second layer; as well as A second portion is formed on the first portion. The manufacturing method as claimed in claim 15 , wherein the first portion protrudes from the second layer.

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