Semiconductor device

Abstract

An example semiconductor device includes a stack structure including a plurality of layers stacked on a substrate. Each layer includes a bit line structure including a bit line extending in a first direction parallel to the substrate, a bit line connection portion connecting the bit line structure and the wiring layer and extending in a third direction perpendicular to the substrate, a semiconductor pattern, a word line structure, and a capacitor, the semiconductor pattern is electrically connected to the bit line and extends in a second direction intersecting the first direction, the word line structure includes a word line extending in a third direction and a word line protrusion protruding from the word line in the first direction, and the capacitor is electrically connected to the semiconductor pattern. The word line faces a first surface of the semiconductor pattern perpendicular to the substrate, and the word line protrusion faces a second surface of the semiconductor pattern parallel to the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0167241 filed in the Korean Intellectual Property Office on November 27, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to a semiconductor device. Background Art

[0004] There is a need for technology for increasing the integration degree of semiconductor devices. In the case of two-dimensional semiconductor devices, the integration degree is mainly determined by the area occupied by a unit memory cell, and the integration degree in this regard may depend on the level of micropatterning technology.

[0005] Micropatterning technology requires expensive equipment. Therefore, although the integration degree of two-dimensional semiconductor devices is increasing, it is still limited. Therefore, a three-dimensional memory device having memory cells arranged three-dimensionally is proposed. Summary of the invention

[0006] The present disclosure relates to semiconductor devices, including semiconductor devices having improved electrical characteristics and higher integration.

[0007] Generally, according to some aspects, a semiconductor device includes a stacked structure in which a plurality of layers are stacked on a substrate, and each of the plurality of layers includes a bit line structure, a bit line connection portion, a semiconductor pattern, a word line structure, and a capacitor, the bit line structure including a bit line extending in a first direction parallel to the substrate, the bit line connection portion connecting the bit line structure and a wiring layer and extending in a third direction perpendicular to the substrate, the semiconductor pattern electrically connected to the bit line and extending in a second direction intersecting the first direction, the word line structure including a word line extending in the third direction and a word line protrusion protruding from the word line in the first direction, the capacitor electrically connected to the semiconductor pattern, and the word line faces a surface of the semiconductor pattern perpendicular to the substrate, and the word line protrusion faces a surface of the semiconductor pattern parallel to the substrate.

[0008] Generally, according to some aspects, a semiconductor device includes a stacked structure in which a plurality of layers are stacked on a substrate, and each of the plurality of layers includes a bit line structure, a bit line connection portion, a semiconductor pattern, a word line structure, and a capacitor, the bit line structure including a bit line extending in a first direction parallel to the substrate and a bit line protrusion protruding from the bit line in a second direction intersecting the first direction, the bit line connection portion extending through the bit line protrusion in a third direction, the semiconductor pattern electrically connected to the bit line and extending in the second direction, the word line structure including a word line extending in a third direction perpendicular to the substrate and a word line protrusion protruding from the word line in the first direction, the capacitor electrically connected to the semiconductor pattern, and the word line faces a first surface of the semiconductor pattern, the word line protrusion faces a second surface of the semiconductor pattern, and the second surface extends vertically from the first surface.

[0009] Generally, according to some aspects, a semiconductor device includes a bit line structure, a bit line connection portion, a semiconductor pattern, a capacitor, and a word line structure, each of the bit line structures including a bit line extending in a first direction parallel to a substrate and a bit line protrusion protruding from the bit line in a second direction intersecting the first direction, each of the bit line connection portions extending from the bit line protrusion in a third direction perpendicular to the substrate, each of the semiconductor patterns is connected to the bit line and extends in the second direction, the capacitor is connected to the semiconductor pattern, and the word line structure includes a word line facing a side surface of the semiconductor pattern and extending in the third direction, and a word line protrusion protruding from the word line in the first direction and facing an upper surface of the semiconductor pattern.

[0010] Generally, according to some aspects, wiring layers to be connected to bit lines and word lines can be separately provided above and below the cell region, thereby reducing the area occupied by the region where the bit lines and wiring layers are connected to each other. Therefore, the integration of the semiconductor device can be improved.

[0011] Generally, according to some aspects, voltage wiring lines for supplying power to the capacitor can be respectively arranged above and below the cell area. In this case, the area occupied by the wiring lines on the plane can be minimized, thereby increasing the freedom of wiring, and since the wiring lines can be disconnected according to the charge, the accidental charge loss caused by the capacitor and the resistor can be minimized.

[0012] Generally, according to some aspects, a channel area can be increased, and thus electrical characteristics of a semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a perspective view showing an example of a semiconductor device.

[0014] Figure 2 yes Figure 1An enlarged perspective view of an example of a unit cell of a semiconductor device.

[0015] Figure 3 is a perspective view showing an example of a word line structure of a semiconductor device.

[0016] Figure 4 It is shown from Figure 1 An example diagram of a semiconductor device viewed in direction ①.

[0017] Figure 5 It is shown from Figure 1 An example diagram of a semiconductor device viewed in direction ②.

[0018] Figure 6 is a cross-sectional view illustrating an example of a semiconductor device.

[0019] Figure 7 is a cross-sectional view illustrating an example of a core / peripheral region of a semiconductor device.

[0020] Figure 8 , Fig.10 , Fig.12 , Fig.14 , Fig.17 , Fig.19 , Fig.21 , Fig.23 and Fig.25 is a perspective view illustrating an example of a method of manufacturing a semiconductor device.

[0021] Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.16 , Fig.18 , Fig. 20 , Fig. 22 , Fig.24 and Fig.26 is an exemplary cross-sectional view illustrating a method of manufacturing a semiconductor device. DETAILED DESCRIPTION

[0022] In the following detailed description, only certain implementations are shown and described by way of illustration. The present disclosure can be implemented in various ways and is not limited to the following implementations.

[0023] The drawings and description should be regarded as illustrative rather than restrictive.Throughout the specification, the same reference numerals refer to the same elements.

[0024] In addition, for the sake of understanding and ease of description, the size and thickness of each configuration shown in the drawings are arbitrarily shown, but the present disclosure is not limited thereto. In the drawings, for the sake of clarity, the thickness of layers, films, panels, regions, etc. are exaggerated. In addition, in the drawings, for the sake of understanding and ease of description, the thickness of some layers and regions is exaggerated.

[0025] In addition, it should be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, when an element is on a reference portion, the element is located above or below the reference portion, and it does not necessarily mean that the element is located "above" or "on" in a direction opposite to gravity.

[0026] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprising” or “including”, will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0027] In addition, throughout the specification, the case referred to as "on a plane" means the case where the target portion is observed from above, and the case referred to as "on a cross section" means the case where a cross section obtained by vertically cutting the target portion is observed from the side.

[0028] In the following, reference will be made to Figures 1 to 5 A cell structure of a semiconductor device according to some implementations is described. A semiconductor device according to some implementations may include memory cells stacked in three dimensions.

[0029] Figure 1 is a perspective view showing an example of a semiconductor device. Figure 2 yes Figure 1 An enlarged perspective view of an example of a unit cell of a semiconductor device. Figure 3 is a perspective view showing an example of a word line structure of a semiconductor device. Figure 4 It is shown from Figure 1 An example diagram of a semiconductor device viewed from the direction of ①, Figure 5 It is shown from Figure 1 An example diagram of a semiconductor device viewed in direction ②.

[0030] Reference Figures 1 to 5 The semiconductor device may include a stacked structure SS including a plurality of layers stacked on a substrate. The plurality of layers may be stacked in a direction perpendicular to the substrate (eg, in a third direction DR3).

[0031] Figure 1 , Figure 4 and Figure 5Some layers other than the uppermost layer and the lowermost layer of the stack structure SS may be shown. Figure 2 and Figure 3 It can be shown Figure 1 One of the layers shown in .

[0032] For convenience, in Figure 1 In FIG. 1 , two layers of a stacked structure SS and two units included in each layer are shown. Figure 4 and Figure 5 , four layers of the stacked structure SS and four units included in each layer are shown; however, the stacked structure SS may include more layers, and each layer may include more units. The multiple units in each layer may be arranged according to a first direction DR1 and a second direction DR2. The first direction DR1 and the second direction DR2 may be parallel to the substrate and intersect each other. For example, the second direction DR2 may be orthogonal to the first direction DR1. Since the multiple layers are stacked, the multiple units in the individual layers may be arranged along a third direction DR3. The third direction DR3 may be a direction perpendicular to the substrate.

[0033] In addition, Figure 1 , Figure 4 and Figure 5 In each layer of the stacked structure SS, one bit line structure BLS is shown; however, each layer may include a plurality of bit line structures BLS arranged along the second direction DR2. A plurality of cells arranged along the first direction DR1 may be connected to the same bit line structure BLS. A plurality of cells arranged along the first direction DR1 may even be connected to a bit line structure BLS adjacent to the bit line structure BLS shown in the figure in the second direction DR2.

[0034] In addition, Figure 1 In FIG. 1 , two word line structures WLS of the stacked structure SS are shown, and in FIG. Figure 4 and Figure 5 , four word line structures WLS of the stacked structure SS are shown; however, the stacked structure SS may include more word line structures WLS arranged along the first direction DR1. Each of the plurality of word line structures WLS arranged along the first direction DR1 may be connected to a plurality of cells arranged along the first direction DR1. A plurality of cells respectively included in a plurality of separate layers and arranged along the third direction DR3 may be connected to the same word line structure WLS.

[0035] exist Figure 1 , Figure 4 and Figure 5, a string of word line structures WLS arranged along the first direction DR1 is shown; however, a plurality of strings each including a word line structure WLS arranged along the first direction DR1 may be arranged along the second direction DR2. A plurality of cells arranged along the second direction DR2 may be respectively connected to a plurality of word line structures WLS arranged along the second direction DR2.

[0036] Reference Figure 1 , the stack structure SS of the semiconductor device may include a first layer L1 and a second layer L2. The first layer L1 and the second layer L2 may be sequentially stacked in the third direction DR3. The first layer L1 and the second layer L2 may be spaced apart in the third direction DR3 by an insulating layer. Each of the first layer L1 and the second layer L2 may include a bit line structure BLS, a bit line connection portion BLC, a semiconductor pattern SP, a word line structure WLS, and a capacitor CP.

[0037] The bit line structure BLS may include a bit line BL extending in a first direction DR1 and a bit line protrusion BL_P protruding from the bit line BL in a second direction DR2. The bit line protrusion BL_P may protrude from a surface of the bit line BL facing a surface thereof in contact with a semiconductor pattern SP to be described below in the second direction DR2. In other words, one side of each bit line BL may be connected to the semiconductor pattern SP, and the other side of the corresponding bit line BL may be connected to the bit line protrusion BL_P.

[0038] The bit line connection portion BLC can connect the bit line structure BLS and the wiring layer. Figure 6 and Figure 7 The structure in which the bit line connecting portion BLC connects the bit line structure BLS and the wiring layer is described in more detail.

[0039] The bit line connection portion BLC may extend through the plurality of layers of the stacked structure SS in the third direction DR3. The bit line connection portion BLC may extend through the bit line protrusion BL_P included in any one of the plurality of layers in the third direction DR3. For example, the bit line connection portion BLC may extend in the third direction DR3 to completely penetrate the upper and lower surfaces of the bit line protrusion BL_P; however, the bit line connection portion is not limited thereto. As another example, the bit line connection portion BLC may extend in the third direction DR3 so that one end of each bit line connection portion is located inside the bit line protrusion BL_P, and the other end thereof passes through only one of the upper and lower surfaces of the bit line protrusion BL_P.

[0040] The bit line connection portion BLC may be connected to the bit line BL via the bit line protrusion BL_P.

[0041] The bit line structure BLS and the bit line connection portion BLC may include conductive materials, respectively. For example, each conductive material may be any one of a doped semiconductor material (such as doped silicon or doped germanium), a conductive metal nitride (such as titanium nitride or tantalum nitride), a metal (such as tungsten, titanium or tantalum), and a metal-semiconductor compound (such as tungsten silicide, cobalt silicide or titanium silicide).

[0042] A plurality of bit line structures BLS may be stacked along the third direction DR3 while being spaced apart from each other. Specifically, a plurality of bit lines BL may overlap in the third direction DR3. A plurality of bit line protrusions BL_P may not overlap in the third direction DR3. A plurality of bit line connection portions BLC may not overlap in the third direction DR3.

[0043] The semiconductor pattern SP may extend in the second direction DR2. The semiconductor pattern SP may include, for example, silicon, germanium, silicon germanium, or indium gallium zinc oxide (IGZO). The semiconductor pattern SP may include impurity regions and channel regions between the impurity regions. The impurity regions may correspond to source / drain regions of the memory cell transistor.

[0044] The impurity region may be a region doped with impurities in the semiconductor pattern SP. The impurity region may have an n-type or p-type conductivity type. The impurity region may be formed adjacent to both ends of each semiconductor pattern SP.

[0045] Each semiconductor pattern SP may have a cubic shape having an upper surface, a lower surface, and four side surfaces. The upper surface and the lower surface of each semiconductor pattern SP may be parallel to the substrate, and the four side surfaces of each semiconductor pattern SP may be perpendicular to the substrate. Each semiconductor pattern SP may have a first side surface and a second side surface facing each other in the second direction DR2, and a third side surface and a fourth side surface facing each other in the first direction DR1. The third side surface may be connected to edges of the first side surface and the second side surface on one side, and the fourth side surface may be connected to edges of the first side surface and the second side surface on a side opposite to the one side.

[0046] The first side surface of the semiconductor pattern SP may be connected to the bit line BL. The semiconductor pattern SP may be electrically connected to the bit line BL. The second side surface of the semiconductor pattern SP may be connected to the capacitor CP to be described below. Specifically, the second side surface of the semiconductor pattern SP may be connected to the first capacitor electrode EL1 of the capacitor CP. The semiconductor pattern SP may be electrically connected to the capacitor CP.

[0047] The third side surface or the fourth side surface of the semiconductor pattern SP may face a word line structure WLS to be described below. The following description will be made on the assumption that the side surface of the semiconductor pattern SP facing the word line structure WLS is the third side surface.

[0048] Each of the first layer L1 and the second layer L2 may include a plurality of semiconductor patterns SP. In each layer, the plurality of semiconductor patterns SP may be arranged along the first direction DR1 while being spaced apart from each other. The plurality of semiconductor patterns SP arranged along the first direction DR1 may be connected to the same bit line BL.

[0049] Although not shown in the drawings, in each layer, a plurality of bit line structures BLS may be arranged along the second direction DR2 while being spaced apart from each other. A plurality of semiconductor patterns SP arranged along the first direction DR1 may even be connected to a bit line BL adjacent to the bit line BL shown in each layer in the second direction DR2.

[0050] The plurality of semiconductor patterns SP included in the first layer L1 may overlap the plurality of semiconductor patterns SP included in the second layer L2 in the third direction DR3, respectively. In other words, the plurality of semiconductor patterns SP may be included in the first layer L1 and the second layer L2, respectively, and may be arranged along the third direction DR3. The plurality of semiconductor patterns SP arranged along the third direction DR3 may face the same word line structure WLS.

[0051] The word line structure WLS may include a word line WL extending through the stack structure SS in the third direction DR3 and a word line protrusion WL_P protruding from the word line WL in the first direction DR1. Each word line WL may face a third side surface of a plurality of semiconductor patterns SP arranged along the third direction DR3. The plurality of semiconductor patterns SP arranged along the third direction DR3 may be respectively included in a plurality of layers of the stack structure SS. For example, the word line WL may extend along the third direction to face a third side surface of the semiconductor pattern SP included in the first layer L1 and a third side surface of the semiconductor pattern SP included in the second layer L2.

[0052] A plurality of word line protrusions WL_P may be connected to one word line WL. The plurality of word line protrusions WL_P connected to one word line WL may respectively face upper surfaces of a plurality of semiconductor patterns SP arranged along the third direction DR3. For example, any one of the plurality of word line protrusions WL_P protruding from one word line WL may face an upper surface of a semiconductor pattern SP included in the first layer L1, and another one of the plurality of word line protrusions WL_P protruding from the one word line WL may face an upper surface of a semiconductor pattern SP included in the second layer L2.

[0053] In some implementations, the word line protrusion WL_P is shown to face the upper surface of the semiconductor pattern SP; however, they are not limited thereto. As an example, the word line protrusion WL_P may face the lower surface of the semiconductor pattern SP. As another example, two word line protrusions WL_P may be provided to face the upper and lower surfaces of the semiconductor pattern SP.

[0054] The word line structure WLS may include a conductive material, which may be any one of, for example, a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound.

[0055] Although not shown in the drawings, a gate insulating layer may be disposed between the word line structure WLS and the surface of the semiconductor pattern SP facing each other. For example, a gate insulating layer may be disposed between the word line WL and the third side surface of the semiconductor pattern SP and between the word line protrusion WL_P and the upper surface of the semiconductor pattern SP.

[0056] A plurality of word line structures WLS may be arranged along the first direction DR1 while being spaced apart from each other. A plurality of word lines WL may be disposed adjacent to a plurality of semiconductor patterns SP disposed along the first direction DR1, respectively. Although not shown in the drawings, a plurality of word line structures WLS may be arranged along the second direction DR2 while being spaced apart from each other. The word line structures WLS disposed along the second direction DR2 may be disposed adjacent to a plurality of semiconductor patterns SP disposed along the second direction DR2, respectively.

[0057] The capacitor CP may be a memory element for storing data. Each capacitor CP may include a first capacitor electrode EL1 in the form of a pillar surrounded by sidewalls, a second capacitor electrode EL2 passing through the first capacitor electrode EL1 in a third direction DR3, and a dielectric layer DL between the first capacitor electrode EL1 and the second capacitor electrode EL2.

[0058] The first capacitor electrode EL1 may contact the semiconductor pattern SP. As described above, the second side surface of the semiconductor pattern SP may contact the first capacitor electrode EL1. The second side surface of the semiconductor pattern SP may contact the sidewall of the first capacitor electrode EL1. Therefore, the semiconductor pattern SP and the capacitor CP may be electrically connected to each other.

[0059] For example, the sidewall of each first capacitor electrode EL1 may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2 , whereby the first capacitor electrode EL1 may have a square pillar shape; however, the first capacitor electrode is not limited thereto.

[0060] The first capacitor electrode EL1 may have a hollow column shape. The second capacitor electrode EL2 may extend through the first capacitor electrode EL1 in the third direction DR3. The second capacitor electrode EL2 may be located in an inner space of the first capacitor electrode EL1 having a hollow column shape. Figure 1, two separated second capacitor electrodes EL2 are shown to pass through one first capacitor electrode EL1; however, the present disclosure is not limited thereto. As another example, one second capacitor electrode EL2 may pass through one first capacitor electrode EL1, or a plurality of second capacitor electrodes EL2 may pass through one first capacitor electrode EL1.

[0061] Each of the first and second capacitor electrodes EL1 and EL2 may include at least one of a metal material such as titanium, tantalum, tungsten, copper, or aluminum, a conductive metal nitride such as titanium nitride or tantalum nitride, and a doped semiconductor material such as doped silicon or doped germanium.

[0062] The dielectric layer DL may be located between the first capacitor electrode EL1 and the second capacitor electrode EL2 to insulate the first capacitor electrode EL1 and the second capacitor electrode EL2 from each other. The dielectric layer DL may be formed to conform to the contour of the first capacitor electrode EL1.

[0063] The dielectric layer DL may include a high dielectric constant material, such as hafnium oxide, hafnium silicon oxide, zirconium oxide, zirconium silicon oxide, aluminum oxide, lanthanum oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, strontium titanium oxide, lithium oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

[0064] In each layer, a plurality of capacitors CP may be arranged along the first direction DR1. In each layer, the plurality of capacitors CP arranged along the first direction DR1 may be electrically connected to the semiconductor patterns SP arranged along the first direction DR1, respectively.

[0065] A plurality of capacitors CP may be arranged along a third direction DR3. A plurality of capacitors CP arranged along the third direction DR3 may share one second capacitor electrode EL2. Each second capacitor electrode EL2 may extend through the first capacitor electrode EL1 of the plurality of layers. Capacitors respectively included in the plurality of layers and arranged along the third direction DR3 may share the second capacitor electrode EL2. For example, the second capacitor electrode EL2 may extend through the first capacitor electrode EL1 of the first layer L1 and the first capacitor electrode EL1 of the second layer L2. Capacitors respectively included in the first layer L1 and the second layer L2 and arranged along the third direction DR3 may share the second capacitor electrode EL2.

[0066] Reference Figure 2 , Figure 1 A unit cell of the semiconductor device may include a semiconductor pattern SP, a bit line structure BLS, a bit line connection portion BLC, a capacitor CP, and a word line structure WLS on a substrate.

[0067] The semiconductor patterns SP may extend in the second direction DR2. Each semiconductor pattern SP may have a first side surface and a second side surface facing each other in the second direction DR2. The first side surface of the semiconductor pattern SP may contact the bit line structure BLS. The second side surface of the semiconductor pattern SP may contact the capacitor CP.

[0068] The bit line structure BLS may include a bit line BL extending in a first direction DR1 and a bit line protrusion BL_P protruding from the bit line BL in a second direction DR2. The first direction and the second direction may be parallel to the substrate and orthogonal to each other.

[0069] The bit line BL may be in contact with the first side surface of the semiconductor pattern SP. The semiconductor pattern SP is located at one side of each bit line BL, and the bit line protrusion BL_P may be located at the other side of each bit line BL. Figure 2 , it is shown that the semiconductor pattern SP and the bit line protrusion BL_P are arranged in a straight line in the second direction DR2; however, the present disclosure is not limited thereto. For example, the bit line protrusion BL_P may be positioned to be misaligned with the semiconductor pattern SP in the second direction DR2.

[0070] The bit line structure BLS may include a bit line connection portion BLC extending from the bit line protrusion BL_P in a third direction DR3 perpendicular to the substrate. The bit line connection portion BLC may extend through the bit line protrusion BL_P in the third direction DR3. Figure 2 , it is shown that the bit line connection portion BLC passes through the bit line protrusion BL_P; however, the bit line connection portion is not limited thereto. For example, the upper surface of the bit line connection portion BLC may be located at a level equal to or lower than the upper surface of the bit line protrusion BL_P, or the lower surface of the bit line connection portion BLC may be located at a level equal to or higher than the lower surface of the bit line protrusion BL_P.

[0071] The word line structure WLS may include a word line WL extending in a third direction DR3 perpendicular to the substrate and a word line protrusion WL_P protruding from the word line WL in the first direction DR1 .

[0072] The word line WL may face a third side surface of an edge of the semiconductor pattern SP connecting the first and second side surfaces at one side, and the word line protrusion WL_P may face an upper surface of the semiconductor pattern SP.

[0073] A region of the semiconductor pattern SP facing the word line structure WLS may function as a channel. For example, a third side surface of the semiconductor pattern SP facing the word line WL and an upper surface of the semiconductor pattern SP facing the word line protrusion WL_P may be a channel region.

[0074] Although not shown in the drawings, a gate insulating layer may be disposed between the word line structure WLS and the semiconductor pattern SP, for example, between the word line WL and the third side surface of the semiconductor pattern SP and between the word line protrusion WL_P and the upper surface of the semiconductor pattern SP.

[0075] The capacitor CP may include a first capacitor electrode EL1 contacting the semiconductor pattern SP, a second capacitor electrode EL2 passing through the first capacitor electrode EL1 in a third direction DR3 perpendicular to the substrate, and a dielectric layer DL interposed between the first capacitor electrode EL1 and the second capacitor electrode EL2 .

[0076] The first capacitor electrode EL1 may have the form of a column surrounded by a sidewall, and the sidewall of the first capacitor electrode EL1 and the second side surface of the semiconductor pattern SP may contact each other. The first capacitor electrode EL1 may have a hollow column shape. The second capacitor electrode EL2 may extend through the inner space of the first capacitor electrode EL1 in the third direction DR3. The first capacitor electrode EL1 may be formed to surround the dielectric layer DL and the second capacitor electrode EL2.

[0077] The semiconductor device may include a word line WL and a bit line connection portion BLC, which extend through a plurality of layers of the stacked structure SS in a third direction DR3 perpendicular to the substrate. The semiconductor device may include an upper wiring layer and a lower wiring layer, and one of the upper wiring layer and the lower wiring layer may be connected to the word line WL, and the other may be connected to the bit line connection portion BLC. Therefore, the areas occupied by the wiring layer connected to the bit line BL and the wiring layer connected to the word line WL on the substrate, respectively, may be reduced, thereby improving the integration of the semiconductor device.

[0078] The semiconductor device may include the word line protrusion WL_P. Since an upper surface of the semiconductor pattern SP facing the word line protrusion WL_P and a third side surface of the semiconductor pattern SP facing the word line WL may be further used as a channel region, an area usable as a channel may be increased.

[0079] In the following, reference will be made to Figure 3 describe Figure 1 and Figure 2 Another example of a word line structure WLS of a semiconductor device. Specifically, Figure 3 Semiconductor devices and Figure 1 and Figure 2 The semiconductor device of the present invention is different only in the structure and shape of the word line protrusion WL_P, and the other components of the semiconductor device may be the same as those of the present invention. Figure 1 and Figure 2 Hereinafter, for the sake of convenience, these differences will be mainly described, and the differences with the above reference may not be described or simplified. Figure 1 and Figure 2 The description content is redundant.

[0080] Reference Figure 3 The word line WL may extend in a third direction DR3 perpendicular to the substrate. The word line WL may face a surface of the semiconductor pattern SP perpendicular to the substrate. For example, the word line WL may face a third side surface of the semiconductor pattern SP.

[0081] The word line protrusion WL_P may protrude from the word line WL in a first direction DR1 parallel to the substrate. The word line protrusion WL_P may face a surface of the semiconductor pattern SP parallel to the substrate. For example, the word line protrusion WL_P may face an upper surface of the semiconductor pattern SP.

[0082] exist Figure 3 In the illustrated implementation, the cross-sectional area of ​​each word line protrusion WL_P may increase as the corresponding word line protrusion proceeds toward the semiconductor pattern SP along the third direction DR3. The cross-sectional area of ​​each word line protrusion WL_P may increase as the corresponding word line protrusion proceeds toward the upper surface of the semiconductor pattern SP.

[0083] A region of the semiconductor pattern SP facing the word line structure WLS may be used as a channel. A third side surface of the semiconductor pattern SP facing the word line WL and an upper surface of the semiconductor pattern SP facing the word line protrusion WL_P may be a channel region. Figure 3 In the implementation shown in FIG. 1 , the upper surface of the semiconductor pattern SP facing the word line protrusion WL_P may be thinner than the upper surface of the semiconductor pattern SP facing the word line protrusion WL_P. Figure 2 The upper surface in the illustrated embodiment is wide, and thus, the channel region of the semiconductor pattern SP may be widened.

[0084] In the following, reference will be made to Figure 4 The planar shape and structure of a memory cell of a semiconductor device are described and reference is made to Figure 5 Describe the cross-sectional shape and structure of a memory cell of a semiconductor device. Figure 4 and Figure 5 In the figure, it is shown that Figure 1 and Figure 2 Although there are differences in the number of layers and the number of units, the above references can be applied identically or similarly. Figure 1 and Figure 2 The content of the description.

[0085] Reference Figure 4 and Figure 5 , the stack structure SS may include a plurality of layers, and the plurality of layers include first to fourth layers L1 , L2 , L3 , and L4 .

[0086] The first to fourth layers L1, L2, L3 and L4 may be sequentially stacked on the substrate. Hereinafter, the above contents regarding the first layer L1 and the second layer L2 may also be applied to two different layers. The description of one layer may also be applied to other layers.

[0087] In each layer, a plurality of semiconductor patterns SP may be arranged along the first direction DR1. For example, a first semiconductor pattern SP1, a second semiconductor pattern SP2, a third semiconductor pattern SP3, and a fourth semiconductor pattern SP4 may be sequentially arranged along the first direction DR1.

[0088] In each layer, a plurality of semiconductor patterns SP arranged along a first direction DR1 may be connected to the same bit line structure BLS. The bit line structure BLS may include a bit line BL extending in the first direction DR1. Each of the plurality of semiconductor patterns SP arranged along the first direction DR1 may be connected to one side of the bit line BL. For example, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4 may be connected to one side of the bit line BL.

[0089] Meanwhile, each of the first to fourth semiconductor patterns SP1 to SP2 to SP3 and SP4 may extend from one side surface of the bit line BL in the second direction DR2 .

[0090] The bit line structure BLS may include a bit line protrusion BL_P protruding from the bit line BL in the second direction DR2. The bit line protrusion BL_P may extend from a surface of the bit line BL facing a contact surface between the bit line and the semiconductor pattern SP in the second direction DR2. The semiconductor pattern SP and the bit line protrusion BL_P may be positioned on both sides relative to the bit line BL. The planar shape of the bit line protrusion BL_P may be, for example, a rectangular shape, but is not limited thereto.

[0091] The bit lines BL respectively included in the plurality of layers may overlap in the third direction DR3. Figure 5 , a first bit line BL1 included in the first layer L1, a second bit line BL2 included in the second layer L2, a third bit line BL3 included in the third layer L3, and a fourth bit line BL4 included in the fourth layer L4 may overlap in the third direction DR3. Figure 4 , it can be shown that the fourth bit line BL4 included in the fourth layer L4 is located on top of the first to fourth layers L1 to L4.

[0092] The bit line protrusions BL_P respectively included in the plurality of layers may not overlap in the third direction DR3. Figure 4, a first bit line protrusion BL_P1 included in the first layer L1, a second bit line protrusion BL_P2 included in the second layer L2, a third bit line protrusion BL_P3 included in the third layer L3, and a fourth bit line protrusion BL_P4 included in the fourth layer L4 may be disposed not to overlap in a planar manner.

[0093] At the same time, Figure 5 Since the insulating layer is omitted, the first bit line protrusion BL_P1, the second bit line protrusion BL_P2, the third bit line protrusion BL_P3, and the fourth bit line protrusion BL_P4 may look like overlapping in the third direction DR3; however, they may not actually overlap in the third direction DR3.

[0094] Reference Figure 4 The first, second, third, and fourth bit line protrusions BL_P1, BL_P2, BL_P3, and BL_P4 may be arranged on a plane along the first direction DR1. The plurality of bit line protrusions BL_P may be disposed in a region overlapping a region in which the plurality of semiconductor patterns SP are arranged in a plane along the first direction DR1 along the second direction DR2.

[0095] The bit line connection portion BLC may extend from the bit line protrusion BL_P in the third direction DR3. The planar shape of the bit line connection portion BLC may be, for example, a circle, but is not limited thereto. As another example, it may be a polygon, such as a rectangle.

[0096] The bit line connection portion BLC may pass through the bit line protrusion BL_P in the third direction DR3. The first bit line connection portion BLC1 may extend through the first bit line protrusion BL_P1, and the second bit line connection portion BLC2 may extend through the second bit line protrusion BL_P2, and the third bit line connection portion BLC3 may extend through the third bit line protrusion BL_P3, and the fourth bit line connection portion BLC4 may extend through the fourth bit line protrusion BL_P4.

[0097] Reference Figure 4 , the first bit line connection part BLC1, the second bit line connection part BLC2, the third bit line connection part BLC3 and the fourth bit line connection part BLC4 may be arranged not to overlap in a plane manner. The first bit line connection part BLC1, the second bit line connection part BLC2, the third bit line connection part BLC3 and the fourth bit line connection part BLC4 may be arranged along the first direction DR1 on a plane. The plurality of bit line connection parts BLC may be arranged in a region overlapping with a region in which the plurality of semiconductor patterns SP are arranged in a plane manner along the first direction DR1 along the second direction DR2.

[0098] The semiconductor device may include a bit line protrusion BL_P extending in a second direction DR2 intersecting the first direction DR1, wherein the bit line BL contacting the semiconductor pattern SP extends in the first direction DR1, and the bit line connection portion BLC and the bit line BL may be connected to each other through the bit line protrusion BL_P. A plurality of bit line protrusions BL_P arranged along a third direction DR3 may be arranged not to overlap along the third direction DR3.

[0099] In the semiconductor device according to the comparative example, a plurality of bit lines BL arranged along the third direction DR3 may extend different lengths along the first direction DR1 to form a step, and the surface exposed due to the step and the wiring layer may be vertically connected. In this case, the area on the substrate occupied by the region where the bit lines BL extend to connect to the wiring layer may increase in proportion to the number of stacked cells.

[0100] According to the semiconductor device, a plurality of bit lines BL arranged along the third direction DR3 may extend substantially the same length in the second direction DR2 so as to form a bit line protrusion BL_P, and the plurality of bit lines BL and the wiring layer may be connected via a bit line connection portion BLC extending from the bit line protrusion BL_P along the third direction DR3. Therefore, the area on the substrate occupied by the region where the bit line BL extends to connect to the wiring layer corresponds to the length of the bit line protrusion BL_P. Therefore, even if the number of stacked units increases, the above-mentioned area does not increase. Compared with the semiconductor device of the comparative example, the semiconductor device can reduce the area on the substrate occupied by the region where the bit line BL extends to connect to the wiring layer. Therefore, the integration of the semiconductor device can be improved.

[0101] Reference Figure 4 In each layer, a plurality of word line structures WLS may be provided. For example, the plurality of word line structures WLS may include a first word line structure WLS1 adjacent to the first semiconductor pattern SP1, a second word line structure WLS2 adjacent to the second semiconductor pattern SP2, a third word line structure WLS3 adjacent to the third semiconductor pattern SP3, and a fourth word line structure WLS4 adjacent to the fourth semiconductor pattern SP4.

[0102] The word line structure WLS may include a word line WL extending in the third direction DR3. The word line WL may overlap the semiconductor pattern SP in the first direction DR1. Each semiconductor pattern SP may have an upper surface, a lower surface, and four side surfaces, and the four side surfaces may include a first side surface and a second side surface facing each other in the second direction DR2 and a third side surface and a fourth side surface facing each other in the first direction DR1. For example, the word line WL may face the third side surface of the semiconductor pattern SP in the first direction DR1.

[0103] Reference Figure 5, each word line WL may extend through a plurality of layers. Each word line WL may extend along the third direction DR3 while facing third side surfaces of a plurality of semiconductor patterns SP arranged along the third direction DR3. For example, the word lines WL of the first word line structure WLS1 may extend in the third direction DR3 while facing third side surfaces of the first semiconductor patterns SP1 respectively included in the first to fourth layers L1 to L4.

[0104] Reference Figure 4 , the word line structure WLS may include a word line protrusion WL_P protruding from the word line WL in the first direction DR1. A planar shape of the word line protrusion WL_P may be, for example, a rectangular shape, but is not limited thereto.

[0105] Reference Figure 5 The word line protrusion WL_P may protrude from a surface of the word line WL facing the semiconductor pattern SP to face an upper surface of the semiconductor pattern SP. The word line protrusion WL_P may overlap the semiconductor pattern SP in the third direction DR3.

[0106] A plurality of word line protrusions WL_P may be connected to one word line WL. The word line WL may extend through a plurality of layers. A plurality of word line protrusions WL_P may protrude from one word line WL passing through a plurality of layers, respectively, and may extend over upper surfaces of semiconductor patterns SP included in a plurality of layers, respectively. A plurality of word line protrusions WL_P may face upper surfaces of semiconductor patterns SP included in a plurality of layers, respectively.

[0107] Reference Figure 5, the first word line structure WLS1 may include a word line WL, a first word line protrusion WL_P1, a second word line protrusion WL_P2, a third word line protrusion WL_P3, and a fourth word line protrusion WL_P4. The word line WL may extend through the first layer L1 to the fourth layer L4. The first word line protrusion WL_P1 may extend over an upper surface of the first semiconductor pattern SP1 included in the first layer L1. The first word line protrusion WL_P1 may face an upper surface of the first semiconductor pattern SP1 included in the first layer L1. The second word line protrusion WL_P2 may extend over an upper surface of the first semiconductor pattern SP1 included in the second layer L2. The second word line protrusion WL_P2 may face an upper surface of the first semiconductor pattern SP1 included in the second layer L2. The third word line protrusion WL_P3 may extend over an upper surface of the first semiconductor pattern SP1 included in the third layer L3. The third word line protrusion WL_P3 may face an upper surface of the first semiconductor pattern SP1 included in the third layer L3. The fourth word line protrusion WL_P4 may extend over the upper surface of the first semiconductor pattern SP1 included in the fourth layer L4. The fourth word line protrusion WL_P4 may face the upper surface of the first semiconductor pattern SP1 included in the fourth layer L4.

[0108] The word line structure WLS of the semiconductor device may include a word line WL facing a side surface of the semiconductor pattern SP and a word line protrusion WL_P protruding from the word line WL in the first direction DR1 to face an upper surface of the semiconductor pattern SP. The semiconductor device can also use an upper surface of the semiconductor pattern SP facing the word line protrusion WL_P and a side surface of the semiconductor pattern SP facing the word line WL as a channel region. Therefore, an area that can be used as a channel can be increased.

[0109] Reference Figure 4 and Figure 5 , the semiconductor pattern SP may be in contact with the sidewall of the first capacitor electrode EL1 of the capacitor CP. The first capacitor electrode EL1 of the capacitor CP may have the form of a column surrounded by the sidewall. The second capacitor electrode EL2 may pass through the inner space of the first capacitor electrode EL1 along the third direction DR3. The dielectric layer DL may be interposed between the first capacitor electrode EL1 and the second capacitor electrode EL2. The first capacitor electrode EL1 may surround the dielectric layer DL and the second capacitor electrode EL2.

[0110] The capacitors CP respectively included in the plurality of layers and overlapped in the third direction DR3 may share one second capacitor electrode EL2. Figure 5, a first capacitor CP1 included in the first layer L1, a second capacitor CP2 included in the second layer L2, a third capacitor CP3 included in the third layer L3, and a fourth capacitor CP4 included in the fourth layer L4 can share a second capacitor electrode EL2, which extends along the third direction DR3 through the first layer L1 to the fourth layer L4.

[0111] For example, the sidewall of the second capacitor electrode EL2 extending along the third direction DR3 between the first capacitor CP1 and the second capacitor CP2 may be surrounded by the dielectric layer DL and the dummy electrode EL1_D. The dummy electrode EL1_D may be electrically insulated from the first capacitor electrode EL1 of the first capacitor CP1 and the first capacitor electrode EL1 of the second capacitor CP2. The width (the width in the first direction DR1 and the width in the second direction DR2) of the dummy electrode EL1_D may be smaller than the width of the first capacitor electrode EL1 of the first capacitor CP1 and the width of the first capacitor electrode EL1 of the second capacitor CP2. The dummy electrode EL1_D may be in contact with the dielectric layer DL of the first capacitor CP1 and the dielectric layer DL of the second capacitor CP2.

[0112] In the following, reference will be made to Figure 6 and Figure 7 A structure in which a bit line structure BLS and a word line structure WLS of a semiconductor device according to some implementations of the present disclosure are connected to a wiring layer is described.

[0113] Figure 6 is a cross-sectional view illustrating an example of a semiconductor device.

[0114] Reference Figure 6 In the semiconductor device, a core region CR and a cell region CLR may be defined on a front surface of a substrate 110, and a peripheral region PR may be defined on a rear surface of the substrate 110. The core region CR and the cell region CLR may be stacked on the front surface of the substrate 110 in the third direction DR3. The peripheral region PR may be located on a rear surface of the substrate 110. The peripheral region PR may be separated from the core region CR by the substrate 110.

[0115] The substrate 110 may be a semiconductor substrate including a semiconductor material, for example, the substrate 110 may include silicon, germanium, silicon germanium, silicon on insulator (SOI), or germanium on insulator (GOI).

[0116] The circuit elements CE formed on the front and rear surfaces of the substrate 110 may include various circuit elements for controlling the operation of the memory cell structure (e.g., stacked structure SS) provided in the cell region CLR. The circuit elements CE may include, for example, transistors, but are not limited thereto. For example, the circuit elements CE may include not only active elements such as transistors, but also passive elements such as capacitors, resistors, inductors, etc.

[0117] When the circuit element CE is a transistor, the circuit element CE may be a planar metal oxide semiconductor field effect transistor (MOSFET), a fin field effect transistor (FinFET), a recessed gate transistor, a gate all around (GAA) transistor, or a multi-bridge channel field effect transistor (MBCFET, where MBCFET is a trademark), but is not limited thereto. Alternatively, the circuit element CE may be composed of a 3D stacked field effect transistor (3DSFET), a complementary field effect transistor (CFET), etc., to which next generation technology has been applied.

[0118] The core region CR may include the circuit element CE, a lower wiring layer 122 connected to the circuit element CE, and a lower inter-wiring insulating layer 120 covering the circuit element CE and the lower wiring layer 122. The lower wiring layer 122 may include various conductive materials, and the lower inter-wiring insulating layer 120 may include various insulating materials.

[0119] On the core region CR, a cell region CLR may be provided. The cell region CLR may include a stacked structure SS. The stacked structure SS is a structure including a plurality of memory cells stacked in three dimensions, and the above reference numerals may be equally applied. Figures 1 to 5 The stack structure SS may be covered by a cell insulating layer 140 .

[0120] Each of the plurality of bit line structures BLS may include a bit line BL extending in a first direction DR1 and a bit line protrusion BL_P protruding from the bit line BL in a second direction DR2. The plurality of bit line structures BLS may be respectively connected to the lower wiring layer 122 through a plurality of bit line connection portions BLC extending in a third direction DR3. Each of the plurality of bit line connection portions BLC may extend through a plurality of layers of the stacked structure SS and be connected to a bit line structure BLS of one of the plurality of layers. Each of the plurality of bit line connection portions BLC may pass through a lower insulating layer 130 between the cell region CLR and the core region CR and be connected to the lower wiring layer 122. The bit line connection portion BLC may be a through-hole member connecting the bit line structure BLS and the lower wiring layer 122.

[0121] Each of the plurality of word line structures WLS may include a word line WL extending in the third direction DR3 and a plurality of word line protrusions WL_P protruding from the word line WL in the first direction DR1. Each of the plurality of word lines WL may extend through a plurality of layers of the stacked structure SS, and each word line WL may connect a plurality of word line protrusions WL_P respectively included in the plurality of layers and arranged along the third direction DR3. Each of the plurality of word lines WL may pass through the upper insulating layer 150 between the cell region CLR and the upper inter-wiring insulating layer 160, and be connected to the upper wiring layer 162. The word line WL may be a through-hole member connecting the word line structure WLS and the upper wiring layer 162.

[0122] The upper wiring layer 162 may be connected to the core region CR and the peripheral region PR through the first through-plug 182. The first through-plug 182 may pass through the upper inter-wiring insulating layer 160, the upper insulating layer 150, the cell insulating layer 140, the lower insulating layer 130, and the lower inter-wiring insulating layer 120, and be connected to the circuit element CE of the core region CR and the contact portions 192 and 194. The contact portions 192 and 194 may pass through the substrate 110 and be connected to the circuit element CE of the peripheral region PR. For example, a signal transmitted from the core region CR may be transmitted to the word line structure WLS through the first through-plug 182, the upper wiring layer 162, and the word line WL. A signal transmitted from the peripheral region PR may be transmitted to the word line structure WLS through the contact portions 192 and 194, the first through-plug 182, the upper wiring layer 162, and the word line WL.

[0123] The upper wiring layer 162 may be connected to a plurality of capacitors CP through the capacitor contacts 172. The upper wiring layer 162 may be connected to the peripheral region PR through the second through-plug 184. The second through-plug 184 may pass through the upper inter-wiring insulating layer 160, the upper insulating layer 150, the cell insulating layer 140, the lower insulating layer 130, the lower inter-wiring insulating layer 120, and the substrate 110, and may be connected to the circuit element CE of the peripheral region PR. For example, power may be supplied from the peripheral region PR to the capacitor CP through the second through-plug 184, the upper wiring layer 162, and the capacitor contacts 172.

[0124] The peripheral region PR may include circuit elements CE, a peripheral wiring layer 212 connected to the circuit elements CE, and a peripheral wiring inter-insulating layer 210 covering the circuit elements CE and the peripheral wiring layer 212. The peripheral wiring layer 212 may include various conductive materials, and the peripheral wiring inter-insulating layer 210 may include various insulating materials.

[0125] The substrate 110 may include a first contact portion 192 and a second contact portion 194. The first contact portion 192 may extend from the front surface of the substrate 110 to the middle between the front surface and the rear surface of the substrate 110. The second contact portion 194 may extend from the rear surface of the substrate 110 to the middle between the front surface and the rear surface of the substrate 110. The second contact portion 194 may be formed to be aligned with the first contact portion 192 and connected to the first contact portion 192 along the third direction DR3.

[0126] The first contact portion 192 and the second contact portion 194 may connect the core region CR and the peripheral region PR. The first contact portion 192 may be connected to the lower wiring layer 122 and the first through-plug 182. The second contact portion 194 may be connected to the peripheral wiring layer 212. The peripheral wiring layer 212 may be connected to the upper wiring layer 162 through the second through-plug 184.

[0127] The semiconductor device may include a word line WL and a bit line connection portion BLC extending in a third direction DR3 perpendicular to the substrate 110. The word line WL may pass through multiple layers of the stacked structure SS and the upper insulating layer 150, and be connected to the upper wiring layer 162. The bit line connection portion BLC may pass through multiple layers of the stacked structure SS and the lower insulating layer 130, and may be connected to the lower wiring layer 122. The word line WL may pass through the upper insulating layer 150 without passing through the lower insulating layer 130. The bit line connection portion BLC may pass through the lower insulating layer 130 without passing through the upper insulating layer 150. Therefore, a semiconductor device in which a wiring layer connected to the word line structure WLS and a wiring layer connected to the bit line structure BLS are vertically separated may be provided. The wiring layer connected to the bit line structure BLS and the wiring layer connected to the word line structure WLS may be stacked in a direction perpendicular to the substrate 110, so that the area occupied by the two wiring layers alone on the substrate 110 may be reduced. Therefore, the integration of the semiconductor device may be improved.

[0128] Figure 7 is a cross-sectional view illustrating an example of a core / peripheral region of a semiconductor device. Figure 7 The semiconductor device can be Figure 6 The semiconductor device of the present invention is only partially different in the structure of the core / peripheral region, and other components of the semiconductor device may be different from Figure 6 Hereinafter, the components of the semiconductor device may not be described or may be simplified. Figure 6 Description Redundant description.

[0129] Reference Figure 7 In the semiconductor device, a core / peripheral region CPR and a cell region CLR may be defined on an upper surface of a substrate 110. The core / peripheral region CPR and the cell region CLR may be stacked on the upper surface of the substrate 110 in the third direction DR3. Figure 6 Unlike in the embodiment of the present invention, the core region and the peripheral region may be located together between the substrate 110 and the cell region CLR.

[0130] The core / peripheral region CPR may include circuit elements CE, a lower wiring layer 312 connected to the circuit elements CE, and a lower inter-wiring insulating layer 310 covering the circuit elements CE and the lower wiring layer 312. The lower wiring layer 312 may include various conductive materials, and the lower inter-wiring insulating layer 310 may include various insulating materials.

[0131] On the core / peripheral region CPR, a cell region CLR may be provided. Each of a plurality of bit line connection portions BLC may pass through the lower insulating layer 130 between the cell region CLR and the core / peripheral region CPR and be connected to the lower wiring layer 312. The bit line connection portion BLC may be a through-hole member connecting the bit line structure BLS and the lower wiring layer 312.

[0132] Each of the plurality of word lines WL may pass through the upper insulating layer 150 between the cell region CLR and the upper inter-wiring insulating layer 160 and be connected to the upper wiring layer 162. The word line WL may be a via member connecting the word line structure WLS and the upper wiring layer 162.

[0133] The upper wiring layer 162 may be connected to the core / peripheral region CPR through the third through-plug 186. The third through-plug 186 may pass through the upper inter-wiring insulating layer 160, the upper insulating layer 150, the cell insulating layer 140, the lower insulating layer 130, and the lower inter-wiring insulating layer 310, and be connected to the lower wiring layer 312 and the circuit element CE of the core / peripheral region CPR. For example, a signal transmitted from the core / peripheral region CPR may be transmitted to the word line structure WLS through the third through-plug 186, the upper wiring layer 162, and the word line WL.

[0134] The upper wiring layer 162 may be connected to a plurality of capacitors CP through capacitor contacts 172. The upper wiring layer 162 may be connected to the core / peripheral region CPR through a fourth through-plug 188. The fourth through-plug 188 may pass through the upper inter-wiring insulating layer 160, the upper insulating layer 150, the cell insulating layer 140, the lower insulating layer 130, and the lower inter-wiring insulating layer 310, and may be connected to the lower wiring layer 312 and the circuit element CE of the core / peripheral region CPR. For example, power may be supplied from the core / peripheral region CPR to the capacitor CP through the fourth through-plug 188, the upper wiring layer 162, and the capacitor contact 172.

[0135] and Figure 6 The implementation is similar to Figure 7The semiconductor device may include a word line WL and a bit line connection portion BLC extending in a third direction DR3 perpendicular to the substrate 110. The word line WL may pass through multiple layers of the stacked structure SS and the upper insulating layer 150, and be connected to the upper wiring layer 162. The bit line connection portion BLC may pass through multiple layers of the stacked structure SS and the lower insulating layer 130, and may be connected to the lower wiring layer 312. The word line WL may pass through the upper insulating layer 150 without passing through the lower insulating layer 130. The bit line connection portion BLC may pass through the lower insulating layer 130 without passing through the upper insulating layer 150. Therefore, a semiconductor device in which a wiring layer connected to the word line structure WLS and a wiring layer connected to the bit line structure BLS are vertically separated may be provided. The wiring layer connected to the bit line structure BLS and the wiring layer connected to the word line structure WLS may be stacked in a direction perpendicular to the substrate 110, so that the area occupied by the two wiring layers alone on the substrate 110 may be reduced. Therefore, the integration of the semiconductor device may be improved.

[0136] In the following, reference will be made to Figures 8 to 26 A method of manufacturing a semiconductor device is described. Figures 8 to 26 According to the method shown, two units can be formed to be stacked in the third direction DR3. Figures 8 to 26 , for convenience, a method of forming a portion of a memory cell structure of a semiconductor device is shown; however, the same method or a similar method may be used to form a memory cell structure in which a plurality of cells are arranged along a first direction DR1 and more cells are stacked in a third direction DR3.

[0137] Figure 8 , Fig.10 , Fig.12 , Fig.14 , Fig.17 , Fig.19 , Fig.21 , Fig.23 and Fig.25 is a perspective view illustrating an example of a method of manufacturing a semiconductor device. Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.16 , Fig.18 , Fig. 20 , Fig. 22 , Fig.24 and Fig.26 is an exemplary cross-sectional view illustrating a method of manufacturing a semiconductor device. Fig. 9 , Fig.11 and Fig.13 is along Figure 8 , Fig.10 and Fig.12 A cross-sectional view taken along lines AA' and CC'. Fig.15 and Fig.18is along Fig.14 and Fig.17 A cross-sectional view taken along lines AA' and BB'. Fig.16 , Fig. 20 , Fig. 22 , Fig.24 and Fig.26 is along Fig.14 , Fig.19 , Fig.21 , Fig.23 and Fig.25 A cross-sectional view taken along line CC'.

[0138] Reference Figure 8 and Fig. 9 , a first indicator structure IS1 and a second indicator structure IS2 may be prepared. The indicator structures IS1 and IS2 may be disposed on a substrate not shown in the drawings.

[0139] In the drawings, the first indication structure IS1 and the second indication structure IS2 are shown to be spaced apart from each other; however, they are intentionally shown to be spaced apart from each other only to show the cross section of the first indication structure IS1, and in reality, the first indication structure IS1 and the second indication structure IS2 may be formed integrally. In other words, on one side of the first indication structure IS1 in the second direction DR2, the second indication structure IS2 may be provided, and although not shown in the drawings, on the other side of the first indication structure IS1, an insulating layer may be provided. In addition, on one side of the second indication structure IS2 in the second direction DR2, the first indication structure IS1 may be provided, and although not shown in the drawings, on the other side of the second indication structure IS2, an insulating layer may be provided.

[0140] Reference Fig.10 and Fig.11 , a trench T may be formed by performing etching on the first indication structure IS1 and the second indication structure IS2. The trench T may include a first portion extending in the first direction DR1 and a second portion extending in the second direction DR2. The first indication structure IS1 may include a first portion of the trench T and a portion of the second portion, and the second indication structure IS2 may include the other portion of the second portion.

[0141] As will be described below, a bit line structure BLS may be formed on a first portion of the trench T. A semiconductor pattern SP and a word line structure WLS may be formed in a second portion of the trench T included in the first indication structure IS1. A capacitor CP may be formed in a second portion of the trench T included in the second indication structure IS2.

[0142] Reference Fig.12 and Fig.13, a plurality of layers may be stacked in the trench T. In the portion of the trench T included in the first indication structure IS1, a semiconductor layer LA including a semiconductor pattern SP, a gate electrode layer LB in which a portion of a gate electrode is formed, and an insulating layer LC may be sequentially stacked, and the process may be repeated. For example, in the portion of the trench T included in the first indication structure IS1, a semiconductor layer LA, a gate electrode layer LB, an insulating layer LC, a semiconductor layer LA, and a gate electrode layer LB may be sequentially formed.

[0143] Each semiconductor layer LA may include a first sacrificial pattern P1 extending in a first direction DR1, a semiconductor pattern SP extending in a second direction DR2 from one side of the first sacrificial pattern P1, and a second sacrificial pattern P2 extending in the second direction DR2 from an opposite side of the first sacrificial pattern P1. Portions of the semiconductor layer LA other than the first sacrificial pattern P1, the second sacrificial pattern P2, and the semiconductor pattern SP may include an insulating material. When forming the semiconductor layer LA, the first sacrificial pattern P1 and the second sacrificial pattern P2 may be formed simultaneously; however, the present disclosure is not limited thereto, and the first sacrificial pattern P1 may be formed first, and then the second sacrificial pattern P2 may be formed.

[0144] The first sacrificial patterns P1 and the semiconductor patterns SP of the plurality of semiconductor layers LA may be formed to overlap in the third direction DR3. The second sacrificial patterns P2 of the plurality of semiconductor layers LA may be formed to not overlap in the third direction DR3.

[0145] The gate electrode layer LB may include a third sacrificial pattern P3 located on an upper surface of a semiconductor pattern SP disposed in the semiconductor layer LA. The third sacrificial pattern P3 may be spaced apart from a bottom surface of the gate electrode layer LB. In the first direction DR1, the third sacrificial pattern P3 may have a width equal to or greater than a width of the semiconductor pattern SP. In the second direction DR2, the third sacrificial pattern P3 may have a width less than a width of the semiconductor pattern SP. Other portions of the gate electrode layer LB except the third sacrificial pattern P3 may include an insulating material.

[0146] The insulating layer LC may include an insulating material.

[0147] The first sacrificial pattern P1, the second sacrificial pattern P2, and the third sacrificial pattern P3 may include, for example, silicon nitride, but are not limited thereto. The semiconductor pattern SP may include a semiconductor material, for example, silicon, but is not limited thereto.

[0148] As described above, portions of the respective layers other than the patterns and the insulating layer LC may include insulating materials. The insulating materials may include materials having an etching selectivity to the first, second, and third sacrificial patterns P1, P2, and P3, such as silicon oxide, but are not limited thereto.

[0149] In the portion of the trench T included in the second indication structure IS2, a sacrificial layer LD, a first insulating layer LE, and a second insulating layer LF may be sequentially stacked, and the process may be repeated. For example, in the portion of the trench T included in the second indication structure IS2, a sacrificial layer LD, a first insulating layer LE, a second insulating layer LF, a sacrificial layer LD, and a first insulating layer LE may be sequentially formed. The sacrificial layer LD may include, for example, silicon nitride, but is not limited thereto. The first insulating layer LE and the second insulating layer LF may include the same insulating material and may be formed integrally. The first insulating layer LE and the second insulating layer LF may include a material having an etching selectivity to the sacrificial layer LD, such as silicon oxide, but is not limited thereto.

[0150] Hereinafter, the first indication structure IS1 including a plurality of layers formed in the trench T may be referred to as a first structure S1. The second indication structure IS2 including a plurality of layers formed in the trench T may be referred to as a second structure S2.

[0151] Reference Figures 14 to 16 , the sacrificial patterns P1, P2, and P3 of the first structure S1 may be replaced with conductive patterns, and through holes H1, H2, and H3 may be formed in the first and second structures S1 and S2. In addition, both end portions of each semiconductor pattern SP may be doped with impurities.

[0152] For example, the sacrificial patterns P1, P2 and P3 may be removed by selective etching to form a conductive pattern. The conductive pattern may include a conductive material. The conductive material may be, for example, any one of a doped semiconductor material (such as doped silicon or doped germanium), a conductive metal nitride (such as titanium nitride or tantalum nitride), a metal (such as tungsten, titanium or tantalum), and a metal-semiconductor compound (such as tungsten silicide, cobalt silicide or titanium silicide).

[0153] The conductive pattern replacing the first sacrificial pattern P1 may be a bit line BL. The conductive pattern replacing the second sacrificial pattern P2 may be a bit line protrusion BL_P. The conductive pattern replacing the third sacrificial pattern P3 may be a word line protrusion WL_P.

[0154] The word line protrusion WL_P may be spaced apart from an upper surface of the semiconductor pattern SP. Between a lower surface of the word line protrusion WL_P and an upper surface of the semiconductor pattern SP, a gate insulating layer may be disposed.

[0155] Subsequently, through holes H1, H2, and H3 may be formed to pass through the first and second structures S1 and S2 in the third direction DR3. The first and second through holes H1, H2 may pass through the first structure S1, and the third through hole H3 may pass through the second structure S2.

[0156] Each of the first through holes H1 may be formed to pass through the bit line protrusion BL_P. The second through holes H2 may be formed to pass through the insulating layer, each of which is located on one of the side surfaces of the corresponding semiconductor pattern SP facing each other in the first direction DR1. The second through holes H2 may be spaced apart from the side surface of the semiconductor pattern SP. The second through holes H2 may contact the word line protrusion WL_P in the first direction DR1. The inner wall of the second through hole H2 may include one surface of each of the word line protrusions WL_P.

[0157] The third through hole H3 may be formed to pass through the vicinity of the center of the second structure S2 in a plan view. Fig.14 , the number of the third through holes H3 is two; however, the number of the third through holes H3 is not limited thereto.

[0158] Reference Fig.17 and Fig.18 , a conductive pattern can be formed by filling the first through hole H1 and the second through hole H2 with a conductive material. For example, each conductive material can be any one of a doped semiconductor material, a conductive metal nitride, a metal, and a metal-semiconductor compound. For example, the conductive material filled in the first through hole H1 can be Fig.14 and Fig.15 The conductive material filled in the second through hole H2 may be the same as the conductive material in the bit line BL and the bit line protrusion BL_P. Fig.14 and Fig.15 The conductive material of the word line protrusion WL_P is the same conductive material.

[0159] The conductive pattern formed in the first through hole H1 may be a bit line connection portion BLC The bit line connection portions BLC may extend through the bit line protrusions BL_P in the third direction DR3 , respectively.

[0160] The conductive pattern formed in the second through hole H2 may be a word line WL. The word line WL may be formed to face one of the side surfaces of each semiconductor pattern SP facing each other in the first direction DR1. Although not shown in the drawings, a gate insulating layer may be provided between the surfaces of the semiconductor pattern SP and the word line WL facing each other.

[0161] Reference Fig.19 and Fig. 20 , the sacrificial layer LD may be removed. For example, the sacrificial layer LD may be removed by performing selective etching through the third through hole H3. The sacrificial layer LD may be removed so that some portions of the upper or lower surfaces of the insulating layers LE and LF are exposed.

[0162] Reference Fig.21 and Fig. 22The first capacitor electrode EL1 may be formed by depositing a conductive material. The conductive material may include, for example, at least one of a metal material, a conductive metal nitride, and a doped semiconductor material.

[0163] The first capacitor electrode EL1 may be formed on an inner surface of the third through hole H3 extending in a direction perpendicular to the substrate (eg, the third direction DR3). The first capacitor electrode EL1 may not be formed on an inner surface of the third through hole H3 extending in a direction parallel to the substrate (eg, the first direction DR1 and the second direction DR2).

[0164] For example, after depositing the conductive material to conform to the inner wall of the third through hole H3, the conductive material deposited on the surface of the inner wall of the third through hole H3 parallel to the substrate may be etched. Thus, the plurality of first capacitor electrodes EL1 may be formed to be separated in the third direction DR3, and the plurality of first capacitor electrodes EL1 may be formed to conform to the surface of the inner wall of the third through hole H3 perpendicular to the substrate. Each of the plurality of first capacitor electrodes EL1 may have the form of a hollow column surrounded by a side wall.

[0165] Reference Fig.23 and Fig.24 , a dielectric layer DL may be formed. The dielectric layer DL may include a high dielectric constant material. The high dielectric constant material may include, for example, hafnium oxide, hafnium silicon oxide, zirconium oxide, zirconium silicon oxide, aluminum oxide, lanthanum oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, strontium titanium oxide, lithium oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

[0166] The dielectric layer DL may be formed on the inner wall of the third through hole H3 to conform to the inner wall. The dielectric layer DL may cover the plurality of first capacitor electrodes EL1 formed on the surface of the inner wall of the third through hole H3 perpendicular to the substrate. The dielectric layer DL may cover the surfaces of the insulating layers LE and LF corresponding to the surfaces of the inner wall of the third through hole H3 parallel to the substrate.

[0167] Reference Fig.25 and Fig.26 The second capacitor electrode EL2 may be formed by filling the remaining space in the third through hole H3 with a conductive material. The conductive material may include, for example, at least one of a metal material, a conductive metal nitride, and a doped semiconductor material.

[0168] exist Fig.25 In FIG. 1 , since the number of the third through holes H3 is two, two separate second capacitor electrodes EL2 may be formed; however, they may function as one electrode.

[0169] The second capacitor electrode EL2 may extend through the second structure S2 in the third direction DR3. Since the second capacitor electrode EL2 is formed, a plurality of capacitors CP may be formed to overlap in the third direction DR3. A plurality of capacitors CP overlapping in the third direction DR3 may share one second capacitor electrode EL2 extending in the third direction DR3.

[0170] The first capacitor electrodes EL1 of the plurality of capacitors CP overlapped in the third direction DR3 may be insulated by a dielectric layer DL formed on a surface of an inner wall of the third through hole H3 parallel to the substrate.

[0171] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of any invention or the scope that can be claimed, but as descriptions of features that can be specific to a specific implementation of a particular invention. Certain features described in the context of separate implementations in this specification can also be implemented in combination in a single implementation. On the contrary, various features described in the context of a single implementation can also be implemented individually or in any suitable sub-combination in multiple implementations. In addition, although features can be described above as working in certain combinations, one or more features from the combination can be removed from the combination in some cases, and the combination can be for sub-combinations or variations of sub-combinations.

[0172] While the present disclosure has been described in connection with what are presently considered to be practical implementations, it should be understood that the present disclosure is not limited to the disclosed implementations. On the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: A stacked structure comprising a plurality of layers stacked on a substrate, Wherein, each of the multiple layers comprises: A bit line structure comprising a bit line extending in a first direction parallel to the substrate; a bit line connection portion connecting the bit line structure and the wiring layer, the bit line connection portion extending in a third direction perpendicular to the substrate; a semiconductor pattern electrically connected to the bit line, the semiconductor pattern extending in a second direction intersecting the first direction; a word line structure including a word line and a word line protrusion, the word line extending in the third direction, the word line protrusion protruding from the word line in the first direction; and a capacitor electrically connected to the semiconductor pattern, wherein the word line faces a first surface of the semiconductor pattern that is perpendicular to the substrate, and The word line protrusion faces a second surface of the semiconductor pattern parallel to the substrate.

2. The semiconductor device according to claim 1, wherein The bit line structure includes a bit line protrusion that protrudes from the bit line in the second direction, and The bit line connection portion extends through the bit line protrusion.

3. The semiconductor device according to claim 1, wherein The bit line connection portion and the word line are connected to two corresponding wiring layers, and the two wiring layers are located in two directions opposite to each other.

4. The semiconductor device according to claim 3, wherein: The bit line connection portion is connected to a lower wiring layer located between the substrate and the stack structure.

5. The semiconductor device according to claim 3, wherein: The word lines are connected to an upper wiring layer, which is located on the stacked structure.

6. The semiconductor device according to claim 1, comprising: A plurality of semiconductor patterns are arranged along the third direction, wherein Each of the plurality of semiconductor patterns is included in each of the plurality of layers, and The plurality of semiconductor patterns face the same word line.

7. The semiconductor device according to claim 1, wherein Each of the plurality of layers includes a plurality of semiconductor patterns arranged along the first direction, and The plurality of semiconductor patterns are connected to the same bit line.

8. The semiconductor device according to claim 7, wherein: The bit line connection portion is disposed in a first region, the first region overlaps with a second region in the second direction on a plane, and the plurality of semiconductor patterns are located in the second region.

9. The semiconductor device according to claim 1, wherein The plurality of layers include a first layer and a second layer, the first layer and the second layer are sequentially stacked on the substrate, and The bit line connection portion in the first layer and the bit line connection portion in the second layer are separated in a plan view.

10. The semiconductor device according to claim 9, wherein The bit line connection portion in the first layer and the bit line connection portion in the second layer are arranged along the first direction on a plane.

11. The semiconductor device according to claim 1, wherein The capacitor in each of the plurality of layers comprises: a first capacitor electrode contacting the semiconductor pattern, the first capacitor electrode being in the form of a pillar surrounded by sidewalls; a second capacitor electrode that passes through the first capacitor electrode in the third direction; and A dielectric layer is located between the first capacitor electrode and the second capacitor electrode.

12. The semiconductor device according to claim 11, wherein The plurality of layers include a first layer and a second layer, the first layer and the second layer are sequentially stacked on the substrate, and The capacitors in the first layer and the capacitors in the second layer are arranged along the third direction and share the same second capacitor electrode.

13. The semiconductor device according to claim 1, wherein When approaching the semiconductor pattern along the third direction, a cross-sectional area of ​​the word line protrusion increases.

14. A semiconductor device comprising: A stacked structure comprising a plurality of layers stacked on a substrate, Wherein, each of the multiple layers comprises: a bit line structure including a bit line and a bit line protrusion, the bit line extending in a first direction parallel to the substrate, the bit line protrusion protruding from the bit line in a second direction intersecting the first direction; a bit line connecting portion extending through the bit line protrusion in a third direction; a semiconductor pattern electrically connected to the bit line, the semiconductor pattern extending in the second direction; a word line structure including a word line and a word line protrusion, the word line extending in the third direction perpendicular to the substrate, the word line protrusion protruding from the word line in the first direction; and a capacitor which is electrically connected to the semiconductor pattern, and The word line faces a first surface of the semiconductor pattern, the word line protrusion faces a second surface of the semiconductor pattern, and the second surface vertically extends from the first surface.

15. The semiconductor device according to claim 14, wherein: The bit line connection portion extends in a direction approaching the substrate and is connected to a lower wiring layer located between the substrate and the stack structure.

16. The semiconductor device according to claim 15, wherein: The word line extends in a direction away from the substrate and is connected to an upper wiring layer that is located on a top of the stack structure.

17. The semiconductor device according to claim 14, wherein: A first side of the bit line is connected to a plurality of semiconductor patterns, a second side of the bit line is connected to a corresponding bit line protrusion, and the plurality of semiconductor patterns are arranged along the first direction.

18. The semiconductor device according to claim 14, wherein: The word line passes through the plurality of layers in the third direction, and A plurality of semiconductor patterns are respectively included in the plurality of layers, and a plurality of second surfaces of the plurality of semiconductor patterns are respectively arranged along the third direction facing a plurality of word line protrusions connected to the word lines.

19. The semiconductor device according to claim 14, wherein: When approaching the semiconductor pattern along the third direction, a cross-sectional area of ​​the word line protrusion increases.

20. A semiconductor device comprising: A bit line structure comprising a bit line and a bit line protrusion, the bit line extending in a first direction parallel to a substrate, the bit line protrusion protruding from the bit line in a second direction intersecting the first direction; a bit line connection portion extending from the bit line protrusion in a third direction perpendicular to the substrate; a semiconductor pattern connected to the bit line, the semiconductor pattern extending in the second direction; a capacitor connected to the semiconductor pattern; as well as A word line structure includes a word line facing a side surface of the semiconductor pattern and extending in the third direction, and a word line protrusion protruding from the word line in the first direction and facing an upper surface of the semiconductor pattern.

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