Dynamic random access memory cell structure

Abstract

The invention provides a DRAM (Dynamic Random Access Memory) unit structure, which comprises a first ring-fence transistor and a second ring-fence transistor, which are respectively provided with a channel with a tubular structure, are sequentially arranged in the vertical direction and are electrically connected in parallel; a storage capacitor having a tubular structure, disposed between the first gate-all-around transistor and the second gate-all-around transistor in a vertical direction, having an inner electrode connected to first source / drain electrodes of the first and second gate-all-around transistors, and an outer electrode connected to a source line; and the bit line extends in the tubular structure formed by the first and second gate-all-around transistors and the storage capacitor along the vertical direction and is connected to the second source / drain electrode of the first and second gate-all-around transistors. In the DRAM unit structure, the inner electrode of the storage capacitor and the source / drain regions and channel regions of the two gate-all-around transistors are formed by the same semiconductor material layer, so that the DRAM unit structure has the advantages of simple structure, good switching performance and the like, and a three-dimensional multi-layer memory array is favorably formed by stacking in the vertical direction.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and more particularly, to a dynamic random access memory (DRAM) cell structure. Background Art

[0002] Since the invention of dynamic random access memory (DRAM) by Intel Corporation in the 1970s, DRAM has been widely used in various computing or control electronic circuit systems.

[0003] A DRAM cell circuit generally consists of a select transistor for selection and a storage capacitor for storing charge (1T1C structure). In a DRAM cell structure that uses a conventional horizontal transistor based on a planar structure, such as a metal oxide semiconductor field effect transistor (MOSFET), to implement the select transistor, the source, gate, and drain of the transistor are arranged in a horizontal direction parallel to the substrate surface. Since the source, gate, and drain of the transistor each occupy an independent area in the horizontal direction, the miniaturization of the DRAM cell circuit structure is limited by the gate length and contact size, and cannot meet the continuous miniaturization requirements of DRAM devices, thereby limiting the further increase in the integration density and bandwidth of DRAM devices.

[0004] Therefore, in recent years, a vertical DRAM cell structure has been proposed, in which the source, gate, and drain of the transistor are arranged in a vertical direction perpendicular to the substrate surface, without additional area occupation, which is conducive to the size miniaturization of the DRAM array structure.

[0005] DRAM manufacturing is a highly competitive industry. The industry continuously needs to reduce the size of individual cells and increase the memory cell density, so that a single memory chip can accommodate more memory.

[0006] The above information disclosed in this background art section is only for understanding the background of the inventive concept, and thus may include information that does not constitute prior art. Summary of the Invention

[0007] To solve the above problems existing in the prior art, the present disclosure proposes a novel vertical dynamic random access memory (DRAM) cell structure.

[0008] According to one aspect of the present disclosure, a dynamic random access memory (DRAM) cell structure is provided, including: a first gate transistor and a second gate transistor, both having a channel with a tubular structure, arranged in sequence in the vertical direction and electrically connected in parallel; a storage capacitor, having a tubular structure, arranged in the vertical direction between the first gate transistor and the second gate transistor, with its inner electrode connected to the first source / drain of the first gate transistor and the second gate transistor, and its outer electrode connected to the source line; and a bit line, extending in the vertical direction inside the tubular structure formed by the first gate transistor, the second gate transistor, and the storage capacitor together and connected to the second source / drain of the first gate transistor and the second gate transistor.

[0009] In the DRAM cell structure according to the present disclosure, a first word line extends in a first horizontal direction and is connected to the gate of the first gate transistor, and a second word line extends in the first horizontal direction and is connected to the gate of the second gate transistor, and the first word line and the second word line overlap in the vertical direction.

[0010] The DRAM cell structure according to the present disclosure includes two gate transistors and a storage capacitor arranged symmetrically in the vertical direction, wherein the inner electrode of the storage capacitor, the source / drain, and the channel regions of the two gate transistors are formed of the same semiconductor material layer, so it has the advantages of simple structure, good switching performance, etc., and is conducive to stacking in the vertical direction to form a three-dimensional multi-layer memory array.

[0011] However, the effects of the present disclosure are not limited to the above effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. It should be understood that the foregoing general description and the following detailed description are both exemplary and explanatory, and are intended to provide further explanation of the claimed present disclosure. Description of the Drawings

[0012] The drawings are included to provide a further understanding of the present disclosure, and the drawings that are incorporated in and constitute a part of this specification illustrate exemplary embodiments of the present disclosure and, together with the specification, are used to explain the inventive concept.

[0013] Figure 1 is an equivalent circuit diagram showing a dynamic random access memory (DRAM) cell structure according to an embodiment of the present disclosure.

[0014] Figure 2 is a perspective view showing a DRAM cell structure according to an embodiment of the present disclosure.

[0015] Figure 3 is a top view showing a DRAM cell structure according to an embodiment of the present disclosure.

[0016] Figure 4 is a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure taken along line AA' in Figure 3 .

[0017] Figure 5 is a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure taken along line BB' in Figure 3 .

[0018] Figure 6 is a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure taken along line CC' in Figure 4 .

[0019] Figure 7 is a cross-sectional view of a DRAM cell structure according to an embodiment of the present disclosure taken along line DD' in Figure 4 .

[0020] Figure 8 is a top view of a DRAM cell structure according to another embodiment of the present disclosure.

[0021] Figure 9 is a cross-sectional view of a DRAM cell structure according to another embodiment of the present disclosure taken along line AA' in Figure 8 .

[0022] Figure 10 is a cross-sectional view of a DRAM cell structure according to another embodiment of the present disclosure taken along line BB' in Figure 8 .

[0023] Figure 11 is a cross-sectional view of a DRAM cell structure according to another embodiment of the present disclosure taken along line CC' in Figure 9 .

[0024] Figure 12 is a cross-sectional view of a DRAM cell structure according to another embodiment of the present disclosure taken along line DD' in Figure 9 .

[0025] Figure 13 is a top view of a DRAM cell structure according to yet another embodiment of the present disclosure.

[0026] Figure 14 is a cross-sectional view of a DRAM cell structure according to yet another embodiment of the present disclosure taken along line AA' in Figure 13 .

[0027] Figure 15 is a cross-sectional view of a DRAM cell structure according to yet another embodiment of the present disclosure taken along line BB' in Figure 13A cross-sectional view of a DRAM cell structure according to another embodiment of the present disclosure taken along line BB'.

[0028] Figure 16 It shows a cross-sectional view of a DRAM cell structure according to another embodiment of the present disclosure taken along line CC' in Figure 14 A cross-sectional view of a DRAM cell structure according to another embodiment of the present disclosure taken along line CC' in

[0029] Figure 17 It shows a cross-sectional view of a DRAM cell structure according to another embodiment of the present disclosure taken along line DD' in Figure 14 A cross-sectional view of a DRAM cell structure according to another embodiment of the present disclosure taken along line DD' in Detailed Embodiments

[0030] In the following description, for purposes of illustration, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments of the present disclosure. As used herein, an "embodiment" is a non-limiting example of an apparatus or method that employs one or more of the inventive concepts disclosed herein. However, it will be apparent that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent configurations. In addition, the various exemplary embodiments may be different, but not necessarily exclusive. For example, specific features of other exemplary embodiments may be used or implemented in some exemplary embodiments without departing from the inventive concept.

[0031] Unless otherwise specified, the described exemplary embodiments are to be understood as providing exemplary features of variations in details that may be implemented in practice for some ways of implementing the inventive concept. Thus, unless otherwise specified, the features, components, modules, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged, and / or reconfigured otherwise without departing from the inventive concept.

[0032] For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be construed to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] Although terms such as "first" and "second" may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0034] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. Additionally, when used in this specification, the terms "comprises" and / or "comprising" mean that the stated features, steps, operations, elements, components, and / or groups thereof are present, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about", and other similar terms are used as approximate terms and not as terms of degree, and are thus used to account for the inherent deviations in measurements, calculations, and / or provided values recognized by those of ordinary skill in the art.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0036] Embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. However, the present disclosure may be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Like reference numerals throughout the figures denote like components. Furthermore, in the drawings, for clarity of illustration, the components are not necessarily drawn to scale, and the proportions and dimensions of the components may be enlarged.

[0037] A dynamic random access memory (DRAM) cell structure according to an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0038] Figure 1 An equivalent circuit diagram of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown.

[0039] As Figure 1 shown, the DRAM cell structure 100 according to an embodiment of the present disclosure may adopt a cell structure of 2T1C (i.e., two select transistors and one storage capacitor). Specifically, the DRAM cell structure 100 may include two gate-all-around (GAA) transistors disposed in sequence in the vertical direction (z direction) and electrically connected in parallel, namely a first GAA transistor T1 and a second GAA transistor T2. Both the first and second GAA transistors T1 and T2 may have (as described below with reference to Figures 2 to 17the channel of the described) tubular structure and serves as a select transistor of the DRAM cell structure 100.

[0040] According to an embodiment of the present disclosure, the first source / drain S / D11 of the first GAA transistor T1 and the first source / drain S / D21 of the second GAA transistor T2 are commonly connected to one plate (inner electrode) of the memory capacitor C, and the second source / drain S / D12 of the first GAA transistor T1 and the second source / drain S / D22 of the second GAA transistor T2 are commonly connected to the bit line BL. According to an embodiment of the present disclosure, the bit line BL may extend in the vertical direction (z direction). In addition, according to an embodiment of the present disclosure, the gate G1 of the first GAA transistor T1 may be connected to the first word line WLA, and the gate G2 of the second GAA transistor T2 may be connected to the second word line WLB. According to an embodiment of the present disclosure, the first word line WLA and the second word line WLB may extend along the first horizontal direction (y direction) and overlap in the vertical direction (z direction). According to an embodiment of the present disclosure, the first word line WLA and the second word line WLB may be shorted together. Alternatively, according to an embodiment of the present disclosure, the first word line WLA and the second word line WLB may also not be shorted together to control the first GAA transistor T1 and the second GAA transistor T2 separately.

[0041] In addition, according to an embodiment of the present disclosure, the other plate (outer electrode) of the storage capacitor C may be connected to the source line SL. Those skilled in the art should recognize that in the DRAM array structure composed of the DRAM cell structure 100 according to the present disclosure, the source lines SL of all the DRAM cell structures may be connected together commonly or in groups, so the source line SL may also be referred to as the "common electrode" herein.

[0042] Figure 2 A perspective view of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown. Figure 3 A top view of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown. Figure 4 It shows along Figure 3 A cross-sectional view of a DRAM cell structure 100 according to an embodiment of the present disclosure taken along the line AA' in Figure 5 It shows along Figure 3 A cross-sectional view of a DRAM cell structure 100 according to an embodiment of the present disclosure taken along the line BB' in Figure 6 It shows along Figure 4 A cross-sectional view of a DRAM cell structure 100 according to an embodiment of the present disclosure taken along the line CC' in Figure 7 It shows along Figure 4A cross-sectional view of a DRAM cell structure 100 according to an embodiment of the present disclosure taken along line DD' in [].

[0043] As Figures 2 to 7 shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include bit line holes extending in the vertical direction (z-direction) (such as the holes located in the center shown in Figure 3 , Figure 6 and Figure 7 with a circular cross-section, for example), and common electrode grooves extending in the first horizontal direction (y-direction) and penetrating the DRAM cell structure 100 in the vertical direction (z-direction) (such as the grooves located on both sides of the central bit line hole shown in Figure 2 , Figure 3 , Figure 4 , Figure 6 and Figure 7 ).

[0044] As Figures 2 to 7 shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a conductor line 109 disposed in the bit line hole. The conductor line 109 extends in the vertical direction (z-direction) and may be used as the bit line BL of the DRAM cell structure 100 as shown in Figure 1 . According to an embodiment of the present disclosure, the material for forming the conductor line 109 may include tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. In particular, according to an embodiment of the present disclosure, the conductor line 109 may have the shape of a cylinder extending in the vertical direction (z-direction). For example, as shown in Figure 3 , Figure 6 and Figure 7 , the conductor line 109 may be a cylinder with a first diameter d1.

[0045] As Figures 2 to 7 shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a semiconductor material layer 107 having a tubular structure and a first isolation material layer 111 disposed in the bit line hole and surrounding the conductor line 109. Specifically, as shown more clearly in Figure 4 and Figure 5 , the upper and lower ends of the semiconductor material layer 107 are in direct contact with the conductor line 109, and the middle part of the semiconductor material layer 107 is separated from the conductor line 109 by the first isolation material layer 111. In other words, according to an embodiment of the present disclosure, both the semiconductor material layer 107 and the first isolation material layer 111 have a tubular structure surrounding the conductor line 109. Although in Figure 3 , Figure 6 and Figure 7In [the example], the tubular structure has a circular cross-section, but the present disclosure is not limited thereto. Those skilled in the art should recognize that the tubular structure may also have a cross-section of any other shape, such as an elliptical, square, or rectangular cross-section. In this case, the cross-sectional shape of the conductor line 109 can be adjusted accordingly.

[0046] According to an embodiment of the present disclosure, the material for forming the first isolation material layer 111 may be a dielectric material commonly used in integrated circuit processes, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, phosphosilicate glass, or a combination thereof. According to an embodiment of the present disclosure, the material for forming the first isolation material layer 111 may also be a low-K material. The low-K material may have a dielectric constant lower than that of silicon oxide. Silicon oxide may have a dielectric constant of about 3.9, and the first isolation material layer 111 may include a low-K material having a dielectric constant of about 3.9 or lower. According to an embodiment of the present disclosure, the low-K material may include porous silicon oxide (SiO 2 ), silicone, fluorosilicate glass (FSG), hydrogen silsesquioxane (HSQ), silicon oxycarbide (SiCOH), or polymer materials such as parylene, polyimide (PI), etc. According to an embodiment of the present disclosure, the material for forming the first isolation material layer 111 may also be a combination of the above dielectric materials and the above low-K materials.

[0047] According to an embodiment of the present disclosure, the material for forming the semiconductor material layer 107 may be a semiconductor thin film material, such as single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, compound semiconductor, oxide semiconductor, sulfide semiconductor, graphene, or a combination thereof. According to an embodiment of the present disclosure, the material for forming the semiconductor material layer 107 may be an oxide semiconductor material, such as indium gallium zinc oxide (IGZO) with different ratios, indium oxide (InO), zinc oxide (ZnO), indium tungsten oxide (InWO), or indium aluminum oxide (InAlO). In particular, according to an embodiment of the present disclosure, the semiconductor material layer 107 may include a single layer of IGZO or a stack of multiple layers of IGZO with different ratios.

[0048] In addition, according to an embodiment of the present disclosure, as described in more detail below, the semiconductor material layer 107 may be formed as Figure 1The source / drain regions and channel regions of the first GAA transistor T1 and the second GAA transistor T2 shown, where the source / drain regions of the first GAA transistor T1 and the second GAA transistor T2 correspond to the first source / drain S / D11 and the second source / drain S / D12 of the first GAA transistor T1 and the first source / drain S / D21 and the second source / drain S / D22 of the second GAA transistor T2. It should be noted here that the source / drain regions described from a structural perspective are equivalent to the source / drains described from a circuit perspective. In addition, according to an embodiment of the present disclosure, the semiconductor material layer 107 may also be formed as Figure 1 the inner electrode of the storage capacitor C shown. Therefore, according to an embodiment of the present disclosure, the storage capacitor C may also have a tubular structure.

[0049] As Figures 2 to 7 shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include two first dielectric layers 106 disposed in the bit line holes and respectively surrounding the upper and lower ends of the semiconductor material layer 107. According to an embodiment of the present disclosure, the two first dielectric layers 106 may be respectively formed as Figure 1 the gate dielectrics of the first GAA transistor T1 and the second GAA transistor T2 shown. As Figure 4 and Figure 5 shown, according to an embodiment of the present disclosure, the first dielectric layer 106 may also have a tubular structure, and the tubular structure has a bent cross-section. In other words, as Figures 2 to 5 shown, in the cross-section along the vertical direction (z direction), the first dielectric layer 106 may have a thinner first portion near the end of the conductor line 109 and a thicker second portion relative to the first portion and away from the end of the conductor line 109, and the first portion and the second portion may be connected by a connecting portion in the horizontal direction. According to an embodiment of the present disclosure, the material for forming the first dielectric layer 106 may include, for example, silicon oxide (SiO 2 ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), lanthanum oxide (La 2 O 3 ) or a combination thereof.

[0050] Therefore, according to an embodiment of the present disclosure, both the first GAA transistor T1 and the second GAA transistor T2 are formed to have a tubular structure and both have a tubular channel.

[0051] As Figures 2 to 7As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a first gate layer 104 below and a second gate layer 105 above that are respectively disposed around a thicker second portion of the first dielectric layer 106 below and above. As Figure 2 and Figure 6 shown, according to an embodiment of the present disclosure, the first gate layer 104 and the second gate layer 105 may have a strip shape with a hole formed in the middle. According to an embodiment of the present disclosure, the first gate layer 104 may correspond to the gate G1 of the first GAA transistor T1 as Figure 1 shown, and the second gate layer 105 may correspond to the gate G2 of the second GAA transistor T2 as Figure 1 shown. In addition, as Figure 2 、 Figure 3 and Figure 5 shown, according to an embodiment of the present disclosure, the first gate layer 104 may extend in the first horizontal direction (y direction) to further correspond to the first word line WLA connected to the first gate G1 of the first GAA transistor T1 as Figure 1 shown. Accordingly, according to an embodiment of the present disclosure, the second gate layer 105 may extend in the first horizontal direction (y direction) to further correspond to the second word line WLB connected to the gate G2 of the second GAA transistor T2 as Figure 1 shown. According to an embodiment of the present disclosure, the first word line WLA and the second word line WLB may be led out from the distal end in the first horizontal direction (y direction).

[0052] Therefore, according to an embodiment of the present disclosure, the DRAM cell structure 100 may have a bit line BL extending in the vertical direction (z direction), and a first word line WLA and a second word line WLB extending in the first horizontal direction (y direction). According to an embodiment of the present disclosure, the bit line BL of the DRAM cell structure 100 may extend inside the tubular structure formed by the first GAA transistor T1, the second GAA transistor T2, and the storage capacitor C in the vertical direction. In addition, according to an embodiment of the present disclosure, the first gate layer 104 and the second gate layer 105 corresponding to the first word line WLA and the second word line WLB of the DRAM cell structure 100 may overlap in the vertical direction (z direction).

[0053] In addition, according to an embodiment of the present disclosure, the materials used to form the first gate layer 104 and the second gate layer 105 may include titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polysilicon / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or a combination thereof.

[0054] like Figures 2 to 7 As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include two second isolation material layers 103 disposed to surround the thinner first portion of the upper and lower first dielectric layers 106, respectively. Figure 2 and Figure 3 As shown, according to an embodiment of the present disclosure, the second isolation material layer 103 may have a strip shape with a hole in the middle. According to an embodiment of the present disclosure, the material used to form the second isolation material layer 103 may include silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiCOH), or aluminum oxide (Al 2 O 3 According to an embodiment of the present disclosure, the first isolation material layer 111 and the second isolation material layer 103 may be formed of the same or different isolation materials.

[0055] like Figure 4 and Figure 5 As shown, according to an embodiment of the present disclosure, as described above, the semiconductor material layer 107 may include a formation indicated by a shadow along the vertical direction (z direction). Figure 1 The first portion 1071 of the channel region of the first and second GAA transistors T1 and T2, and the first portion 1071 formed between Figure 1 The first source / drain region of the first GAA transistor T1 (corresponding to the first source / drain S / D11 of the first GAA transistor T1), the first source / drain region of the second GAA transistor T2 (corresponding to the first source / drain S / D21 of the second GAA transistor T2), and the second portion 1072 of the inner electrode of the memory capacitor C are shown. Therefore, according to an embodiment of the present disclosure, the first source / drain S / D11 of the first GAA transistor T1 and the first source / drain S / D21 of the second GAA transistor T2 are connected to the inner electrode of the memory capacitor C. According to an embodiment of the present disclosure, the first portion 1071 and the second portion 1072 of the semiconductor material layer 107 are separated from the conductor line 109 (bit line BL) by the first isolation material layer 111 surrounding the conductor line 109 (bit line BL).

[0056] According to an embodiment of the present disclosure, the doping type, doping concentration, and / or atomic component ratio of the second portion 1072 of the semiconductor material layer 107 can be changed through material modification processes such as doping and etching, so that it has better conductivity as the inner electrode of the memory capacitor C. That is to say, according to an embodiment of the present disclosure, the first portion 1071 and the second portion 1072 of the semiconductor material layer 107 can have different doping types, doping concentrations, and / or atomic component ratios. According to an embodiment of the present disclosure, when the semiconductor material layer 107 is an IGZO oxide semiconductor, all or part of the gallium (Ga) atoms in the second portion 1072 can be removed through an etching process, for example, to improve its conductivity, or part of the oxygen (O) atoms in the second portion 1072 can be removed through an etching process, for example, to form interstitial metal atoms or oxygen atom vacancies to improve its conductivity.

[0057] In addition, as Figure 4 and Figure 5 shown, according to an embodiment of the present disclosure, as described above, the semiconductor material layer 107 can further include, along the vertical direction (z direction), third portions 1073 at both ends of the contact conductor line 109 that serve as Figure 1 shown, the second source / drain regions (corresponding to the second source / drain S / D12 of the first GAA transistor T1) of the first GAA transistor T1 and the second source / drain regions (corresponding to the second source / drain S / D22 of the second GAA transistor T2) of the second GAA transistor T2, and a first horizontal connection portion 1074 connecting the first portion 1071 and the third portion 1073. Therefore, according to an embodiment of the present disclosure, the third portion 1073 of the semiconductor material layer 107 is in contact with the conductor line 109, so that the second source / drain S / D12 of the first GAA transistor T1 and the second source / drain S / D22 of the second GAA transistor T2 corresponding to the third portion 1073 of the semiconductor material layer 107 are connected to the bit line BL corresponding to the conductor line 109.

[0058] As Figure 3 shown, according to an embodiment of the present disclosure, the third portion 1073 of the tubular semiconductor material layer 107 can have a second diameter d2, which is greater than the first diameter d1 of the conductor line 109. In addition, as Figures 3 to 7 shown, according to an embodiment of the present disclosure, the first portion 1071 and the second portion 1072 of the tubular semiconductor material layer 107 can have a third diameter d3, which is greater than the second diameter d2 of the third portion 1073 of the semiconductor material layer 107.

[0059] As Figures 2 to 7As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a second dielectric layer 108 serving as a capacitive dielectric of the storage capacitor C disposed in the common electrode trench. According to an embodiment of the present disclosure, the second dielectric layer 108 may be conformally formed along the trench wall of the common electrode trench. As Figure 2 and Figure 4 shown, according to an embodiment of the present disclosure, the second dielectric layer 108 may contact two second isolation material layers 103, the first gate layer 104, the second gate layer 105, and a second portion of the semiconductor material layer 107 in a second horizontal direction (x direction). In addition, as Figure 2 and Figure 5 shown, according to an embodiment of the present disclosure, the second dielectric layer 108 may contact a second portion of the semiconductor material layer 107 in a first horizontal direction (y direction). The first horizontal direction, i.e., the y direction, may be perpendicular to the second horizontal direction, i.e., the x direction.

[0060] In addition, according to an embodiment of the present disclosure, the material for forming the second dielectric layer 108 may be a high-K material. The high-K material may have a dielectric constant higher than that of silicon oxide. Silicon oxide may have a dielectric constant of about 3.9, and the second dielectric layer 108 may include a high-K material having a dielectric constant of about 4 or greater. According to an embodiment of the present disclosure, the high-K material may include hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), strontium titanate (SrTiO 3 ) or a combination thereof.

[0061] As Figures 2 to 7 shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include an electrode layer 110 extending along the surface of the second dielectric layer 108 and filling the common electrode trench. According to an embodiment of the present disclosure, the electrode layer 110 may correspond to Figure 1 shown, the external electrode of the storage capacitor C, i.e., the common electrode of the storage capacitor C, and the source line SL. As Figures 2 to 7As shown, according to an embodiment of the present disclosure, the electrode layer 110 corresponding to the external electrode of the storage capacitor C and the source line SL may extend in the first horizontal direction (y direction) and penetrate the DRAM cell structure 100 in the vertical direction (z direction). According to an embodiment of the present disclosure, the material for forming the electrode layer 110 may include titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polysilicon / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or a combination thereof. Therefore, according to an embodiment of the present disclosure, the storage capacitor C of the DRAM cell structure 100 may be formed as a cylindrical capacitor.

[0062] In addition, although not shown in the figures, according to an embodiment of the present disclosure, a third isolation material layer may also be provided between the first gate layer 104 and the second gate layer 105 and the second dielectric layer 108 to reduce the parasitic capacitance and leakage current between the external electrode of the storage capacitor (source line SL) and the gates G1 and G2 of the first and second GAA transistors T1 and T2 (i.e., the first and second word lines WLA and WLB).

[0063] Figure 8 is a top view showing a DRAM cell structure 100' according to another embodiment of the present disclosure. Figure 9 is showing along Figure 8 a cross-sectional view of a DRAM cell structure 100' taken along line AA' in according to another embodiment of the present disclosure. Figure 10 is showing along Figure 8 a cross-sectional view of a DRAM cell structure 100' taken along line BB' in according to another embodiment of the present disclosure. Figure 11 is showing along Figure 9 a cross-sectional view of a DRAM cell structure 100' taken along line CC' in according to another embodiment of the present disclosure. Figure 12 is showing along Figure 9 a cross-sectional view of a DRAM cell structure 100' taken along line DD' in according to another embodiment of the present disclosure. Figures 8 to 12 shown in is the same as the Figures 3 to 7 elements shown in, and the same reference numerals are used to denote the same elements, and for the sake of brevity, repetitive descriptions thereof are not given again.

[0064] Figures 8 to 12 The DRAM cell structure 100' shown in is different from the Figures 3 to 7 DRAM cell structure 100 shown in only in that, as Figure 12As shown, the second portion 1072 of the semiconductor material layer 107 of the tubular structure of the DRAM cell structure 100' has a fourth diameter d4, which is greater than the third diameter d3 of the first portion 1071 of the semiconductor material layer 107. Accordingly, according to an embodiment of the present disclosure, as Figure 9 and Figure 10 shown, the semiconductor material layer 107 of the tubular structure of the DRAM cell structure 100' further includes a second horizontal connection portion 1075 connecting the first portion 1071 and the second portion 1072.

[0065] Compared with Figures 3 to 7 the DRAM cell structure 100 shown, in Figures 8 to 12 the DRAM cell structure 100' shown, since the inner electrode of the storage capacitor C extends outward, the facing area between the inner electrode and the outer electrode of the storage capacitor C increases, so that the capacitance value of the storage capacitor C can be increased.

[0066] Figure 13 is a top view showing a DRAM cell structure 100" according to another embodiment of the present disclosure. Figure 14 is a cross-sectional view showing the DRAM cell structure 100" according to another embodiment of the present disclosure taken along the line AA' in Figure 13 . Figure 15 is a cross-sectional view showing the DRAM cell structure 100" according to another embodiment of the present disclosure taken along the line BB' in Figure 13 . Figure 16 is a cross-sectional view showing the DRAM cell structure 100" according to another embodiment of the present disclosure taken along the line CC' in Figure 14 . Figure 17 is a cross-sectional view showing the DRAM cell structure 100" according to another embodiment of the present disclosure taken along the line DD' in Figure 14 . Figures 13 to 17 Elements identical to those shown in Figures 3 to 7 are denoted by the same reference numerals, and for the sake of brevity, no repetitive description thereof will be given.

[0067] Figures 13 to 17 The difference between the DRAM cell structure 100" shown and Figures 3 to 7 the DRAM cell structure 100 shown is that the DRAM cell structure 100" omits the common electrode groove, and the gate dielectric of the first GAA transistor T1 and the second GAA transistor T2 and the capacitive dielectric of the storage capacitor C are formed by the same dielectric layer, i.e., the third dielectric layer 113. As Figure 14 and Figure 15 shown, according to an embodiment of the present disclosure, the third dielectric layer 113 can be configured to have a tubular structure conformally surrounding the semiconductor layer 107.

[0068] According to an embodiment of the present disclosure, according to an embodiment of the present disclosure, the material for forming the third dielectric layer 113 may be a high-K material, such as hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), niobium oxide (Nb 2 O 5 ), strontium titanate (SrTiO 3 ), or a combination thereof.

[0069] In addition, as shown in Figure 14 and Figure 15 , according to an embodiment of the present disclosure, since the common electrode groove is omitted, an electrical isolation between the electrode layer 110 (corresponding to the outer electrode of the storage capacitor C and the source line SL shown in Figure 1 ) and the first gate layer 104 (corresponding to the gate G1 of the first GAA transistor T1 and the first word line WLA shown in Figure 1 ) and the second gate layer 105 (corresponding to the gate G2 of the second GAA transistor T2 and the second word line WLB shown in Figure 1 ) is achieved by providing a fourth isolation material layer 112 therebetween. According to an embodiment of the present disclosure, the fourth isolation material layer 113 may be formed of the same or different isolation material as the first isolation material layer 111 and / or the second isolation material layer 103.

[0070] Therefore, according to an embodiment of the present disclosure, as shown in Figure 14 , Figure 15 and Figure 17 , in the DRAM cell structure 100", since the source line SL (electrode layer 110) extends in the horizontal directions (x-direction and y-direction), the source line SL can be led out from the distal end in the horizontal directions (x-direction and / or y-direction). Further, since the common electrode groove is omitted and the first gate layer 104 and the second gate layer 105 also extend in the horizontal directions (x-direction and y-direction), different from the DRAM cell structure 100 described above with reference to Figures 3 to 7 , in the DRAM cell structure 100", in addition to the first horizontal direction (y-direction), the first gate layer 104 and the second gate layer 105 can also be led out from the distal end in the second horizontal direction (x-direction).

[0071] According to an embodiment of the present disclosure, as Figures 13 to 17 shown, the DRAM cell structure 100" can further simplify the structure and process, and reduce the manufacturing cost.

[0072] In addition, according to an embodiment of the present disclosure, in the DRAM cell structures 100 to 300, cavities may also be provided in the first isolation material layer 111.

[0073] According to an embodiment of the present disclosure, the DRAM cell structure includes two surrounding gate transistors and a storage capacitor that are mirror-symmetrically arranged in the vertical direction, wherein the inner electrode of the storage capacitor, the source / drain electrodes, and the channel regions of the two surrounding gate transistors are formed by the same semiconductor material layer. Therefore, it has the advantages of simple structure, good switching performance, etc., and is conducive to forming a three-dimensional multi-layer memory array by stacking in the vertical direction. In particular, this cell structure can use two surrounding gate transistors in parallel to increase the on-current of the select transistor, thereby improving the switching speed performance of the memory cell; at the same time, the upper and lower surrounding gate transistors can completely isolate the storage capacitor in the middle, which can avoid the interference of the stored information by external signals or adjacent cells, thereby improving the reliability of the memory cell.

[0074] Moreover, in particular, this cell structure uses a vertical structure to solve the connection problem between the transistor source / drain electrodes and the inner electrode of the storage capacitor, is suitable for the three-dimensional vertical integration of multi-layer DRAM cells, and the vertical structure is suitable for the one-time processing and formation of multi-layer DRAM cells, without multiple epitaxial processes and processing processes, and has a low manufacturing cost.

[0075] Although this document contains many details, these details should not be construed as limiting the scope of the present disclosure or what may be claimed, but rather as descriptions of features that may be specific to particular embodiments. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Additionally, although features may be described above as acting in certain combinations and even initially so claimed, in some cases, one or more features of the combination may be deleted from the claimed combination, and the claimed combination may relate to a sub-combination or a variation of a sub-combination.

Claims

1. A dynamic random access memory DRAM cell structure, comprising: A first all-around gate transistor and a second all-around gate transistor, both having a channel of a tubular structure, are sequentially arranged in a vertical direction and electrically connected in parallel; a storage capacitor having a tubular structure, disposed between the first gate-all-around transistor and the second gate-all-around transistor in a vertical direction, having an inner electrode connected to first sources / drains of the first gate-all-around transistor and the second gate-all-around transistor, and having an outer electrode connected to a source line; as well as A bit line extends vertically inside a tubular structure formed by the first gate-all-around transistor, the second gate-all-around transistor and the storage capacitor and is connected to second sources / drains of the first gate-all-around transistor and the second gate-all-around transistor.

2. The DRAM cell structure according to claim 1, wherein: a first word line extending along a first horizontal direction and connected to a gate of the first gate-all-around transistor, and A second word line extends along the first horizontal direction and is connected to a gate of the second gate-all-around transistor, and the first word line and the second word line overlap in the vertical direction.

3. The DRAM cell structure according to claim 1, wherein: The source / drain regions, the channel regions of the first and second gate-all-around transistors, and the inner electrode of the storage capacitor are formed from the same semiconductor material layer.

4. The DRAM cell structure according to claim 3, wherein: The semiconductor material layer comprises: The first part forms the channel regions of the two all-around gate transistors; a second portion, between the first portions, forming first source / drain regions of the two gate-all-around transistors and an inner electrode of the storage capacitor; The third part forms the second source / drain regions of the two all-around gate transistors; and a first horizontal connecting portion, connecting the first portion and the third portion, wherein the diameter of the second portion of the semiconductor material layer is equal to the diameter of the first portion of the semiconductor material layer, and Wherein, a diameter of the first portion of the semiconductor material layer is greater than a diameter of the third portion of the semiconductor material layer.

5. The DRAM cell structure according to claim 3, wherein: The semiconductor material layer comprises: The first part forms the channel regions of the two all-around gate transistors; a second portion, between the first portions, forming first source / drain regions of the two gate-all-around transistors and an inner electrode of the storage capacitor; The third part forms the second source / drain regions of the two gate-all-around transistors; a first horizontal connecting portion connecting the first portion and the third portion; and a second horizontal connecting portion, connecting the first portion and the second portion, wherein the diameter of the second portion of the semiconductor material layer is greater than the diameter of the first portion of the semiconductor material layer, and Wherein, a diameter of the first portion of the semiconductor material layer is greater than a diameter of the third portion of the semiconductor material layer.

6. The DRAM cell structure according to claim 4 or 5, wherein: The first portion and the second portion of the semiconductor material layer have different doping types, doping concentrations and / or atomic composition ratios.

7. The DRAM cell structure according to claim 3, wherein: The semiconductor material layer includes a single layer of IGZO or a stack of multiple layers of IGZO with different ratios.

8. The DRAM cell structure according to claim 3, wherein: The semiconductor material layer includes single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, compound semiconductor, oxide semiconductor, sulfide semiconductor, graphene or a combination thereof.

9. The DRAM cell structure according to claim 4 or 5, further comprising: A bit line hole extending in the vertical direction through the DRAM cell structure; as well as A common electrode groove extends in the first horizontal direction and penetrates the DRAM unit structure in the vertical direction.

10. The DRAM cell structure according to claim 9, wherein: The bit line and the semiconductor material layer are disposed in the bit line hole, and the semiconductor material layer surrounds the bit line, and A third portion of the semiconductor material layer contacts the bit line, and the first portion and the second portion of the semiconductor material layer are separated from the bit line by a first isolation material layer surrounding the bit line.

11. The DRAM cell structure according to claim 10, wherein: The first isolation material layer is formed of a low-K material.

12. The DRAM cell structure according to claim 10, wherein: The first insulating material layer includes a cavity.

13. The DRAM cell structure according to claim 9, wherein: A capacitor medium and an external electrode of the storage capacitor are disposed in the common electrode groove, and the capacitor medium is in direct contact with the second portion of the semiconductor material layer.

14. The DRAM cell structure according to claim 13, wherein: The source line extends in the common electrode groove along the first horizontal direction and the vertical direction.

15. The DRAM cell structure according to claim 3, wherein: The gate dielectrics of the first gate-all-around transistor and the second gate-all-around transistor and the capacitor dielectric of the storage capacitor are formed by the same dielectric layer.

16. The DRAM cell structure according to claim 15, wherein: The source line extends along the first horizontal direction.

17. The DRAM cell structure according to claim 1, wherein: The capacitance dielectric of the storage capacitor is formed of a high-K material.

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