Semiconductor structure, preparation method thereof and storage system

Abstract

The embodiment of the invention provides a semiconductor structure, a preparation method thereof and a storage system, and aims to reduce electric leakage between two adjacent wires. In the semiconductor structure provided by the embodiment of the invention, a bit line layer is connected with a peripheral circuit layer through a wire in a wiring layer, and the bit line layer comprises a first bit line and a second bit line; a first interval between a first sub-bit line and a second sub-bit line in the first bit line and a second interval between a third sub-bit line and a fourth sub-bit line in the second bit line are staggered in the first direction; the whole of one end, close to the first interval, of the first sub-bit line and one end, close to the first interval, of the second sub-bit line is staggered with the whole of one end, close to the second interval, of the third sub-bit line and one end, close to the second interval, of the fourth sub-bit line in the first direction; the distance between the wire connecting the first sub-bit line and the second sub-bit line and the wire connecting the third sub-bit line and the fourth sub-bit line in the first direction is increased, so that electric leakage between two adjacent wires is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof, and a storage system. Background Art

[0002] The semiconductor structure includes a plurality of bit lines and a plurality of wires, one end of the wire is connected to the bit line, and the other end of the wire is used to connect to the peripheral circuit outside the semiconductor structure to realize the extraction of the bit line. However, the distance between adjacent wires is small, which easily leads to leakage between adjacent wires. Summary of the invention

[0003] Embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, and a storage system, which are intended to reduce leakage between two adjacent conductive lines in a wiring layer.

[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] On the one hand, an embodiment of the present application provides a semiconductor structure, including a bit line layer, the bit line layer including a plurality of first bit lines and a plurality of second bit lines, the first bit lines and the second bit lines both extend along a first direction, the plurality of first bit lines and the plurality of second bit lines are alternately spaced along a second direction, the second direction is perpendicular to the first direction, the first bit line includes a first sub-bit line and a second sub-bit line, the first sub-bit line and the second sub-bit line have a first interval in the first direction, the second bit line includes a third sub-bit line and a fourth sub-bit line, the third sub-bit line and the fourth sub-bit line have a second interval in the first direction; in adjacent first bit lines and second bit lines, the first interval and the second interval are staggered in the first direction.

[0006] In the semiconductor structure provided by the embodiment of the present application, the bit line layer is connected to the peripheral circuit layer through the wires in the wiring layer, so as to realize the lead-out of the bit line layer, the bit line layer includes a first bit line and a second bit line, and a first interval between a first sub-bit line and a second sub-bit line in the first bit line and a second interval between a third sub-bit line and a fourth sub-bit line in the second bit line are staggered in the first direction, and an end of the first sub-bit line close to the first interval, an end of the second sub-bit line close to the first interval, an end of the third sub-bit line close to the second interval, and an end of the fourth sub-bit line close to the second interval are all used to connect the wires in the wiring layer, thereby increasing the distance between the wires connecting the first sub-bit line and the second sub-bit line and the wires connecting the third sub-bit line and the fourth sub-bit line along the first direction, thereby reducing the leakage between adjacent wires in the wiring layer.

[0007] In some embodiments, the semiconductor structure includes a first region and a second region adjacent to each other, the first region and the second region are arranged along a first direction, the first interval is arranged in the first region, and the second interval is arranged in the second region.

[0008] Through the above arrangement, the first interval is located in the first area, so that the end of the second sub-bit line close to the first interval is located in the first area, and the second interval is located in the second area, so that the end of the fourth sub-bit line close to the second interval is located in the second area, so as to increase the distance between the end of the second sub-bit line close to the first interval and the end of the fourth sub-bit line close to the second interval, thereby increasing the distance between the wire connecting the second sub-bit line and the wire connecting the fourth sub-bit line, thereby reducing the leakage between the two wires.

[0009] In some embodiments, first intervals spaced apart in the second direction are aligned in the second direction; and second intervals spaced apart in the second direction are aligned in the second direction.

[0010] Through the above arrangement, the plurality of first intervals are located in a straight line in the second direction. Then, after the first interval is formed, the plurality of first sub-bit lines are aligned in the second direction at one end close to the first interval, and the plurality of second sub-bit lines are aligned in the second direction at one end close to the first interval; and after the second interval is formed, the plurality of third sub-bit lines are aligned in the second direction at one end close to the second interval, and the plurality of fourth sub-bit lines are aligned in the second direction at one end close to the second interval, which can make the bit line layer more regular and facilitate the formation of conductive wires on the first and second bit lines to realize the lead-out of the bit line layer.

[0011] In some embodiments, the semiconductor structure also includes a wiring layer, which is stacked with the bit line layer, a first conductive column is provided at one end of the first sub-bit line close to the first interval, a second conductive column is provided at one end of the second sub-bit line close to the first interval, a third conductive column is provided at one end of the third sub-bit line close to the second interval, and a fourth conductive column is provided at one end of the fourth sub-bit line close to the second interval, and the first conductive column, the second conductive column, the third conductive column and the fourth conductive column are all connected to the wiring layer.

[0012] Through the above arrangement, in the process of leading the current of the bit line layer to the wiring layer through the first conductive pillar, the second conductive pillar, the third conductive pillar and the fourth conductive pillar, the distance between each of the first conductive pillar, the second conductive pillar, the third conductive pillar and the fourth conductive pillar is increased, thereby avoiding leakage between adjacent conductive pillars.

[0013] In some embodiments, the wiring layer includes a first wiring layer and a second wiring layer that are stacked, the first wiring layer is located between the second wiring layer and the bit line layer, the first conductive column, the second conductive column, the third conductive column and the fourth conductive column are all connected to the first wiring layer, and the first wiring layer is connected to the second wiring layer.

[0014] Through the above arrangement, after the bit line layer leads the current to the first wiring layer through the first conductive column, the second conductive column, the third conductive column and the fourth conductive column, the first wiring layer is connected to the second wiring layer to realize the lead-out of the current in the first wiring layer, and the wires in the wiring layer can be respectively arranged in the first wiring layer and the second wiring layer to reduce the complexity of the wires in the first wiring layer, thereby increasing the distance between the wires in the first wiring layer, avoiding leakage of the wires in the first wiring layer, and also reducing the area of ​​the first wiring layer, thereby reducing the volume of the semiconductor structure. On the other hand, the complexity of the wires in the second wiring layer can also be reduced, thereby increasing the distance between the wires in the second wiring layer, avoiding leakage of the wires in the second wiring layer, and similarly reducing the area of ​​the second wiring layer, thereby reducing the volume of the semiconductor structure.

[0015] In some embodiments, the first wiring layer includes a first wire, a second wire, a third wire, and a fourth wire, the first wire is connected to an end of the first sub-bit line close to the first interval through a first conductive column, the second wire is connected to an end of the second sub-bit line close to the first interval through a second conductive column, the third wire is connected to an end of the third sub-bit line close to the second interval through a third conductive column, and the fourth wire is connected to an end of the fourth sub-bit line close to the second interval through a fourth conductive column;

[0016] The second wiring layer includes a fifth wire and a sixth wire. The fifth wire is connected to the first wire and the second wire through a fifth conductive column. The sixth wire is connected to the third wire and the fourth wire through a sixth conductive column.

[0017] Through the above arrangement, in the process of leading the current of the bit line layer to the first wiring layer through the first conductive pillar, the second conductive pillar, the third conductive pillar and the fourth conductive pillar, the distance between the first conductive pillar, the second conductive pillar, the third conductive pillar and the fourth conductive pillar can be avoided to be too small, and leakage between two adjacent conductive pillars can be avoided; in the process of leading the current of the first wiring layer to the second wiring layer through the fifth conductive pillar and the sixth conductive pillar, the fifth conductive pillar is respectively connected to the first wire and the second wire, which can avoid the distance between the two fifth conductive pillars being too small, and leakage between the two fifth conductive pillars can be avoided; and the sixth conductive pillar is respectively connected to the third wire and the fourth wire, which can avoid the distance between the two sixth conductive pillars being too small, and leakage between the two sixth conductive pillars can be avoided.

[0018] In some embodiments, the first conductive wire is parallel to the first sub-bit line, and the projection of the first conductive wire on the bit line layer covers the first conductive column; the second conductive wire is parallel to the second sub-bit line, and the projection of the second conductive wire on the bit line layer covers the second conductive column; the third conductive wire is parallel to the third sub-bit line, and the projection of the third conductive wire on the bit line layer covers the third conductive column; the fourth conductive wire is parallel to the fourth sub-bit line, and the projection of the fourth conductive wire on the bit line layer covers the fourth conductive column.

[0019] Through the above arrangement, the lengths of the first conductive pillar, the second conductive pillar, the third conductive pillar and the fourth conductive pillar can be shortened, thereby shortening the distance between the first wiring layer and the bit line layer, thereby improving the integration of the semiconductor structure.

[0020] In some embodiments, the length of the second wire along the first direction is less than or equal to the length of the first wire along the first direction, and the length of the fourth wire along the first direction is less than or equal to the length of the third wire along the first direction.

[0021] Through the above arrangement, it is possible to avoid the distance between the second wire and the fourth wire being too small, thereby avoiding leakage between the second wire and the fourth wire.

[0022] In some embodiments, the fifth wire is parallel to the first wire, and its projection on the first wiring layer covers the first wire and the second wire. The sixth wire is parallel to the third wire, and its projection on the first wiring layer covers the third wire and the fourth wire.

[0023] Through the above arrangement, the fifth wire and the sixth wire are staggered in the second direction, the distance between the fifth wire and the sixth wire is increased, and leakage between the fifth wire and the sixth wire is avoided.

[0024] In some embodiments, the semiconductor structure also includes multiple third bit lines, a third bit line is provided between adjacent first bit lines and second bit lines, the third bit lines include a fifth sub-bit line and a sixth sub-bit line, the fifth sub-bit line is located between the first sub-bit line and the fourth sub-bit line; the sixth sub-bit line is located between the second sub-bit line and the third sub-bit line.

[0025] Through the above arrangement, the fifth sub-bit line increases the distance between the first sub-bit line and the fourth sub-bit line. On the one hand, the distance between two adjacent first sub-bit lines in the second direction is increased. In the implementation mode in which a plurality of first intervals are aligned in the second direction, the distance between two adjacent first intervals is increased, thereby increasing the distance between the conductors on the two first sub-bit lines, which can reduce the leakage between the conductors on the adjacent first sub-bit lines. On the other hand, the distance between two adjacent fourth sub-bit lines in the second direction is increased. In the implementation mode in which a plurality of second intervals are aligned in the second direction, the distance between two adjacent second intervals is increased, thereby increasing the distance between the conductors on the two fourth sub-bit lines, thereby reducing the leakage between the conductors on the adjacent fourth sub-bit lines. leakage; at the same time, the sixth sub-bit line increases the distance between the second sub-bit line and the third sub-bit line. On the one hand, the distance between two adjacent second sub-bit lines in the second direction is increased. In the implementation mode in which multiple first intervals are aligned in the second direction, the distance between two adjacent first intervals is increased, thereby increasing the distance between the conductors on the two second sub-bit lines to reduce the leakage between the conductors on the adjacent second sub-bit lines; on the other hand, the distance between two third sub-bit lines in the second direction is increased. In the implementation mode in which multiple second intervals are aligned in the second direction, the distance between two adjacent second intervals is increased, thereby increasing the distance between the conductors on the two third sub-bit lines to reduce the leakage between the conductors on the adjacent third sub-bit lines.

[0026] On the other hand, an embodiment of the present application further provides a method for preparing a semiconductor structure, comprising:

[0027] forming a bit line layer, the bit line layer comprising a plurality of first bit lines and a plurality of second bit lines, the first bit lines and the second bit lines both extending along a first direction, the first bit lines and the second bit lines being alternately arranged along a second direction, the second direction being perpendicular to the first direction;

[0028] A portion of the first bit line and a portion of the second bit line are removed to form a first interval on the first bit line and a second interval on the second bit line; the first interval divides the first bit line into a first sub-bit line and a second sub-bit line, and the second interval divides the second bit line into a third sub-bit line and a fourth sub-bit line; the first interval and the second interval are staggered in the second direction.

[0029] In the method for preparing a semiconductor structure provided by an embodiment of the present application, a first interval and a second interval are staggered in a first direction, so that an end of the first sub-bit line close to the first interval and an end of the fourth sub-bit line close to the second interval are staggered in the first direction, and an end of the first sub-bit line close to the first interval, a second sub-bit line close to the first interval, an end of the third sub-bit line close to the second interval, and an end of the fourth sub-bit line close to the second interval are all used to connect wires in a wiring layer, thereby increasing the distance between the wire connecting the first sub-bit line and the second sub-bit line and the wire connecting the third sub-bit line and the fourth sub-bit line along the first direction, thereby reducing leakage between adjacent wires in the wiring layer.

[0030] In some embodiments, the semiconductor structure includes adjacent first and second regions, the first and second regions being arranged along a first direction;

[0031] Removing a portion of the first bit line and a portion of the second bit line to form a first spacer on the first bit line and forming a second spacer on the second bit line includes:

[0032] A portion of the first bit line in the first region is removed to form a first spacer, and a portion of the second bit line in the second region is removed to form a second spacer.

[0033] Through the above arrangement, the end of the second sub-bit line close to the first interval can be located in the first area, and the end of the fourth sub-bit line close to the second interval can be located in the second area, and the distance between the end of the second sub-bit line close to the first interval and the end of the fourth sub-bit line close to the second interval can be increased. When the end of the second sub-bit line close to the first interval and the end of the fourth sub-bit line close to the second interval are connected to the wire, the distance between the wire connecting the second sub-bit line and the wire connecting the fourth sub-bit line can be increased, thereby reducing the leakage between the two wires.

[0034] In some embodiments, after forming the first interval and the second interval, the method further includes:

[0035] A wiring layer is stacked on the bit line layer, a first conductive column is formed at one end of the first sub-bit line close to the first interval, a second conductive column is formed at one end of the second sub-bit line close to the first interval, a third conductive column is formed at one end of the third sub-bit line close to the second interval, and a fourth conductive column is formed at one end of the fourth sub-bit line close to the second interval, and the first conductive column, the second conductive column, the third conductive column and the fourth conductive column are all connected to the wiring layer.

[0036] Through the above arrangement, the first conductive column is formed at one end of the first sub-bit line close to the first interval, the second conductive column is formed at one end of the second sub-bit line close to the first interval, the third conductive column is formed at one end of the third sub-bit line close to the second interval, and the fourth conductive column is formed at one end of the fourth sub-bit line close to the second interval. In the process of leading the current of the bit line layer to the wiring layer through the first conductive column, the second conductive column, the third conductive column and the fourth conductive column, the distance between each of the first conductive column, the second conductive column, the third conductive column and the fourth conductive column is increased to avoid leakage between adjacent conductive columns.

[0037] In some embodiments, the wiring layer includes a first wiring layer and a second wiring layer, and forming the wiring layer in a stacked manner on the bit line layer includes:

[0038] forming a first wiring layer in a stacked manner on the bit line layer and forming a second wiring layer in a stacked manner on the first wiring layer;

[0039] Connecting the first conductive column, the second conductive column, the third conductive column and the fourth conductive column to the wiring layer includes connecting the first conductive column, the second conductive column, the third conductive column and the fourth conductive column to the first wiring layer and connecting the first wiring layer and the second wiring layer.

[0040] Through the above arrangement, the current in the bit line layer is led out through the first wire, the second wire, the third wire and the fourth wire.

[0041] In some embodiments, the first wiring layer includes a first wire, a second wire, a third wire, and a fourth wire, the second wiring layer includes a fifth wire and a sixth wire, and a fifth conductive column and a sixth conductive column are provided between the second wiring layer and the first wiring layer;

[0042] Forming the first wiring layer includes: forming a first wire to connect the first conductive column and the first conductive column; forming a second wire to connect the second conductive column and the second conductive column; forming a third wire to connect the third conductive column and the third conductive column; forming a fourth wire to connect the fourth conductive column and the fourth conductive column;

[0043] Forming the second wiring layer includes: forming a fifth wire and connecting the fifth wire with the first wire and the second wire through a fifth conductive column; forming a sixth wire and connecting the sixth wire with the third wire and the fourth wire through a sixth conductive column.

[0044] Through the above arrangement, the current in the first wiring layer is led out through the fifth wire, the sixth wire, the fifth conductive column, and the sixth conductive column.

[0045] In some embodiments, forming the bit line layer further includes forming a third bit line between adjacent first and second bit lines;

[0046] A portion of the first bit line and a portion of the second bit line are removed to form a first spacer on the first bit line, and before forming a second spacer on the second bit line, the method further includes: removing a portion of the third bit line to form a fifth sub-bit line and a sixth sub-bit line.

[0047] Through the above arrangement, the distance between the first bit line and the second bit line is increased, so that leakage between the wire connecting the first bit line and the wire connecting the second bit line is avoided during the current extraction process between the first bit line and the second bit line; and, by removing a portion of the third bit line and dividing the third bit line into a fifth sub-bit line and a sixth sub-bit line, the fifth sub-bit line can be avoided from being located between two adjacent first sub-bit lines at one end close to the first interval, thereby avoiding connection to the fifth sub-bit line when the end of the first sub-bit line close to the first interval is wired; and the sixth sub-bit line can be avoided from being located between two adjacent third sub-bit lines at one end close to the second interval, thereby avoiding connection to the sixth sub-bit line when the end of the third sub-bit line close to the first interval is wired.

[0048] On the other hand, an embodiment of the present application further provides a storage system, including a controller and the semiconductor structure as described above; the controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

[0049] On the other hand, an embodiment of the present application further provides an electronic device, including a host and the above storage system, wherein the host and the storage system are coupled.

[0050] It can be understood that the beneficial effects that can be achieved by the semiconductor structure preparation method, storage system and electronic device provided by the above embodiments of the present application can refer to the beneficial effects of the semiconductor structure above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0052] Figure 1 A schematic diagram of a three-dimensional structure of a three-dimensional memory in some embodiments of the present application;

[0053] Figure 2 A cross-sectional view of a three-dimensional memory in some embodiments of the present application;

[0054] Figure 3 for Figure 1A cross-sectional view of a memory cell string in the three-dimensional memory along the section line AA' shown;

[0055] Figure 4 An equivalent circuit diagram of a memory cell string in some embodiments of the present application;

[0056] Figure 5 A schematic diagram of a structure of a bit line layer in a semiconductor structure in some embodiments of the present application;

[0057] Figure 6 Another structural schematic diagram of a bit line layer in a semiconductor structure in some embodiments of the present application;

[0058] Figure 7 A schematic diagram of the structure of a first wiring layer in a semiconductor structure in some embodiments of the present application;

[0059] Figure 8 A schematic diagram of the structure of a second wiring layer in a semiconductor structure in some embodiments of the present application;

[0060] Fig. 9 for Figure 8 Cross-sectional view at AA in the middle;

[0061] Fig.10 for Figure 8 Cross-section at the middle BB;

[0062] Fig.11 A flowchart of a method for preparing a semiconductor structure in some embodiments of the present application;

[0063] Fig.12 A schematic diagram of a structure after a bit line layer is formed in some embodiments of the present application;

[0064] Fig.13 This is a schematic diagram of a structure after the first interval and the second interval are formed in some embodiments of the present application;

[0065] Fig.14 This is another structural schematic diagram after a bit line layer is formed in some embodiments of the present application;

[0066] Fig.15 This is a schematic diagram of a structure after a portion of the third bit line is removed in some embodiments of the present application;

[0067] Fig.16 This is another structural schematic diagram after the first interval and the second interval are formed in some embodiments of the present application;

[0068] Fig.17 A schematic diagram of a structure for forming a first conductive column, a second conductive column, a third conductive column, and a fourth conductive column in some embodiments of the present application;

[0069] Fig.18 A schematic diagram of a structure for forming a first wiring layer in some embodiments of the present application;

[0070] Fig.19 This is a schematic diagram of a structure for forming a second wiring layer in some embodiments of the present application;

[0071] Fig. 20 The frame of the storage system in some embodiments of the present application Figure 1 ;

[0072] Fig.21 The frame of the storage system in some embodiments of the present application Figure 2 .

[0073] Description of the drawings: 200, semiconductor structure; 11, semiconductor layer; 130, peripheral circuit layer; 40, memory cell string; 201, bit line layer; 202, wiring layer; 203, first bit line; 204, second bit line; 205, first sub-bit line; 206, second sub-bit line; 207, first interval; 208, third sub-bit line; 209, fourth sub-bit line; 210, second interval; 211, first region; 212, second region; 213, third bit line; 214, fifth sub-bit line; 215, sixth sub-bit line; 216, first conductive column; 217, second conductive column; 218, third conductive column; 219, fourth conductive column; 220, first wiring layer; 221, second wiring layer; 222, first conductive wire; 223, second conductive wire; 224, third conductive wire; 225, fourth conductive wire; 226, fifth conductive wire; 227, sixth conductive wire; 228, fifth conductive column; 229, sixth conductive column. DETAILED DESCRIPTION

[0074] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0075] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0076] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0077] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0078] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments invented here are not necessarily limited to the contents of this document.

[0079] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0080] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0081] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0082] In the context of this application, the meaning of "on", "above", and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" not only means "above" or "over" something, but also includes the meaning of "above" or "over" something without intervening features or layers in between (i.e., directly on something).

[0083] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0084] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0085] The term "three-dimensional memory" refers to a semiconductor device formed by a memory cell transistor string (referred to herein as a "memory cell string", such as a NAND memory cell string) arranged in an array on a main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / vertically" means nominally perpendicular to the main surface (i.e., lateral surface) of the substrate or source layer.

[0086] Please refer to Figure 1 and Figure 2 , the three-dimensional memory 10 extends in the XY plane, the first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the semiconductor layer 11 is located (for example, the plane where the source layer SL is located): the first direction X is, for example, the extension direction of the word line WL, and the second direction Y is, for example, the extension direction of the bit line BL. The third direction Z is perpendicular to the plane where the semiconductor layer 11 is located, that is, perpendicular to the XY plane.

[0087] As used in this application, whether a component (e.g., layer, structure, or device) is "on," "over," or "under" another component (e.g., layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to a substrate or source layer of the semiconductor device in a third direction Z when the substrate or source layer is located in the lowest plane of the semiconductor device in the third direction Z. The same concept is applied throughout the content of this application to describe spatial relationships.

[0088] In order to more clearly illustrate the structure of the device, Figure 2 In the figure, a view of the array area CA and a view of the connection area SS are shown. The view of the array area CA is based on the left coordinate system, and the view of the connection area SS is based on the right coordinate system, that is, the view of the array area CA shows the cross-sectional structure along the Y direction, and the view of the connection area SS shows the cross-sectional structure along the X direction.

[0089] Reference Figure 1 and Figure 2 Some embodiments of the present application provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor layer 11. The three-dimensional memory 10 may also include a device layer 100 coupled to the semiconductor layer 11. The semiconductor layer 11 includes a source layer SL, and the device layer 100 may be disposed on a side of the semiconductor layer 11 away from the source layer SL.

[0090] The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region, and the doped region is doped with a p-type dopant. The source layer SL may also include a non-doped region.

[0091] The semiconductor layer 11 may include memory cell strings 40 arranged in an array. The source layer SL may be coupled to source terminals of the plurality of memory cell strings 40.

[0092] In some embodiments, please refer to Figure 3 and Figure 4 , the memory cell string 40 may include a plurality of transistors T, a transistor T (eg Figure 4 The transistors T1 to T6 in the figure can be set as a memory cell, and these transistors T are connected together to form a memory cell string. A transistor T (for example, each transistor T) can be formed by a semiconductor channel 241 and a gate line G surrounding the semiconductor channel 241. The gate line G is configured to control the conduction state of the transistor.

[0093] Understandably, Figure 1 to Figure 4The number of transistors is only illustrative, and the storage cell string of the three-dimensional memory provided in the embodiment of the present application may also include other numbers of transistors, such as 4, 16, 32, or 64.

[0094] In some embodiments, along the third direction Z, the gate line located at the bottom among the multiple gate lines G (for example, the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source selection gate SGS, and the source selection gate SGS is configured to control the conduction state of the transistor T6, thereby controlling the conduction state of the source channel in the memory cell string 40. The gate line located at the top among the multiple gate lines G (for example, the gate line farthest from the source layer SL among the multiple gate lines G) is constructed as a drain selection gate SGD, and the drain selection gate SGD is configured to control the conduction state of the transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string 40. The gate line located in the middle among the multiple gate lines G can be constructed as a plurality of word lines WL, for example, including word line WL0, word line WL1, word line WL2, and word line WL3. Data writing, reading, and erasing of corresponding memory cells (for example, transistors T) in the memory cell string 40 can be completed through the word lines WL.

[0095] Continue to refer to Figure 1 and Figure 2 In some embodiments, the semiconductor layer 11 may further include a wiring layer 202. The wiring layer 202 may be coupled to the memory cell string 40. The wiring layer 202 may be connected to the drain terminal (i.e., the bit line BL) of the memory cell string 40, and the drain terminal may be coupled to the semiconductor channel of each transistor T in at least one memory cell string 40.

[0096] The semiconductor layer 11 may further include a bit line layer 201. The bit line layer 201 may include one or more first interlayer insulating layers 292, and may further include a plurality of contacts insulated from each other by these first interlayer insulating layers 292. The contacts may include, for example, a bit line contact BL-CNT coupled to the bit line BL, and a drain select gate contact SGD-CNT coupled to the drain select gate SGD. The bit line layer 201 may further include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, for example, a bit line BL, and a word line connection line WL-CL coupled to the word line WL. The material of the first interconnect conductor layer 291 and the contacts may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating material, or other suitable materials.

[0097] The device layer 100 may include peripheral circuits. The peripheral circuits are configured to control and sense the array devices. The peripheral circuits may be any suitable digital, analog, and / or mixed signal control and sensing circuits for supporting the operation (or work) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs) or storage circuits (e.g., static random access memories (SRAMs)).

[0098] In some embodiments, the device layer 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral circuit layer 130 disposed on the substrate 110. The peripheral circuit may include the transistor 120.

[0099] The material of the substrate 110 may be single crystal silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0100] The peripheral circuit layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral circuit layer 130. The peripheral circuit layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled via contacts. The materials of the second interconnect conductor layers 132 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and a combination of one or more metal silicides, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as silicon oxide, silicon nitride, and a combination of one or more high dielectric constant insulating materials, or other suitable materials.

[0101] The peripheral circuit layer 130 can be coupled to the wiring layer 202, so that the semiconductor layer 11 and the device layer 100 can be coupled. Specifically, since the peripheral circuit layer 130 is coupled to the wiring layer 202, the peripheral circuit in the device layer 100 can be coupled to the storage cell string in the semiconductor layer 11 to achieve the transmission of electrical signals between the peripheral circuit and the storage cell string. In some possible implementations, a bonding interface 50 can be provided between the peripheral circuit layer 130 and the wiring layer 202, and the peripheral circuit layer 130 and the wiring layer 202 can be bonded and coupled to each other through the bonding interface 50.

[0102] The semiconductor structure 200 provided in the embodiment of the present application may include a semiconductor layer 11 and a peripheral circuit layer 130. The semiconductor layer 11 and the peripheral circuit layer 130 may be arranged along the Z direction (eg Figure 2 The semiconductor layer 11 may be stacked on one side of the semiconductor layer 11 close to the peripheral circuit layer 130, and a first connection portion may be provided, and the first connection portion is used to connect to the storage cell string 40 inside the semiconductor layer 11; the peripheral circuit layer 130 may include a second connection portion and a transistor, and the second connection portion is connected to the transistor and is located on the side of the transistor close to the semiconductor layer 11, wherein the transistor may include a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS). In the above embodiment, the first connection portion and the second connection portion are bonded, and the connection between the storage cell string 40 and the transistor is achieved through the bonding between the first connection portion and the second connection portion, thereby achieving the connection between the semiconductor layer 11 and the peripheral circuit layer 130.

[0103] Please refer to Figure 5 In the embodiment of the present application, the bit line layer 201 may be located in the semiconductor layer 11 near the peripheral circuit layer 130 (eg Figure 2 ), and the bit line layer 201 is located at one side of the memory cell string 40 (as shown in FIG. Figure 3 as shown) and the first connecting portion.

[0104] In the above implementation, the plane where the bit line layer 201 is located has a first direction and a second direction, the first direction and the second direction are perpendicular to each other, the bit line layer 201 includes a plurality of first bit lines 203 and a plurality of second bit lines 204, wherein the first bit lines 203 and the second bit lines 204 both extend along the first direction, and the plurality of first bit lines 203 and the plurality of second bit lines 204 are alternately arranged along the second direction, and the first bit lines 203 and the second bit lines 204 are both used to connect to the storage cell string 40. The first bit line 203 includes a first sub-bit line 205 and a second sub-bit line 206. Since the first bit line 203 extends along the first direction, the first sub-bit line 205 and the second sub-bit line 206 also extend along the first direction, and a first interval 207 is provided between the first sub-bit line 205 and the second sub-bit line 206. The second bit line 204 includes a third sub-bit line 208 and a fourth sub-bit line 209. Since the second bit line 204 extends along the first direction, the third sub-bit line 208 and the fourth sub-bit line 209 also extend along the first direction, and a second interval 210 is provided between the third sub-bit line 208 and the fourth sub-bit line 209. In the adjacent first bit line 203 and second bit line 204, the first spacer 207 is located on a first straight line parallel to the second direction, the second spacer 210 is located on a second straight line parallel to the second direction, and the first straight line and the second straight line are not colinear, that is, the first spacer 207 and the second spacer 210 are staggered in the first direction, that is, the first spacer 207 and the fourth sub-bit line 209 located between the first sub-bit line 205 and the second sub-bit line 206 are arranged along the second direction, and the second spacer 210 and the second sub-bit line 206 located between the third sub-bit line 208 and the fourth sub-bit line 209 are arranged along the second direction.

[0105] In the above implementation, the wiring layer 202 is located between the bit line layer 201 and the peripheral circuit layer 130 (eg Figure 2 ), the wiring layer 202 and the bit line layer 201 are stacked, the wiring layer 202 is connected to the bit line layer 201 and draws the current of the bit line layer 201 to the peripheral circuit layer 130 (as shown in Figure 2 ). Wherein, the wiring layer 202 may include a plurality of conductive wires, each conductive wire corresponding to a sub-bit line. Exemplarily, a conductive wire is connected to one end of the first sub-bit line 205 close to the first gap 207, for drawing out the current in the first sub-bit line 205; a conductive wire is connected to one end of the second sub-bit line 206 close to the first gap 207, for drawing out the current in the second sub-bit line 206; a conductive wire is connected to one end of the third sub-bit line 208 close to the second gap 210, for drawing out the current in the third sub-bit line 208; a conductive wire is connected to one end of the fourth sub-bit line 209 close to the second gap 210, for drawing out the current in the fourth sub-bit line 209.

[0106] In the semiconductor structure 200 provided by the embodiment of the present application, the bit line layer 201 is connected to the peripheral circuit layer 130 through the wire in the wiring layer 202, so as to realize the extraction of the bit line layer 201. The bit line layer 201 includes a first bit line 203 and a second bit line 204. The first interval 207 between the first sub-bit line 205 and the second sub-bit line 206 in the first bit line 203 and the second interval 210 between the third sub-bit line 208 and the fourth sub-bit line 209 in the second bit line 204 are staggered in the first direction. One end of line 205 close to first spacer 207, one end of second sub-bit line 206 close to first spacer 207, one end of third sub-bit line 208 close to second spacer 210 and one end of fourth sub-bit line 209 close to second spacer 210 are all used to connect wires in wiring layer 202, thereby increasing the distance between the wire connecting first sub-bit line 205 and second sub-bit line 206 and the wire connecting third sub-bit line 208 and fourth sub-bit line 209 along the first direction, thereby reducing leakage between adjacent wires in the wiring layer.

[0107] In some embodiments, one end of the first sub-bit line 205 close to the first interval 207 is connected to a conductive wire and one end of the fourth sub-bit line 209 close to the second interval 210 is connected to a conductive wire. Since the first interval 207 and the second interval 210 are staggered in the first direction, the distance between the end of the first sub-bit line 205 close to the first interval 207 and the end of the fourth sub-bit line 209 close to the second interval 210 in the first direction is increased, thereby increasing the distance between the conductive wire connected to the first sub-bit line 205 and the conductive wire connected to the fourth sub-bit line 209, thereby reducing leakage between the two conductive wires.

[0108] In another embodiment, a conductive wire is connected to one end of the second sub-bit line 206 close to the first interval 207 and a conductive wire is connected to one end of the third sub-bit line 208 close to the second interval 210. Since the first interval 207 and the second interval 210 are staggered in the first direction, the distance between one end of the second sub-bit line 206 close to the first interval 207 and one end of the third sub-bit line 208 close to the second interval 210 in the first direction is increased, thereby increasing the distance between the conductive wire connected to the second sub-bit line 206 and the conductive wire connected to the third sub-bit line 208, thereby reducing leakage between the two conductive wires.

[0109] Continue to refer to Figure 5, the semiconductor structure 200 provided in the embodiment of the present application further includes an adjacent first region 211 and a second region 212, the first region 211 and the second region 212 are arranged along the first direction, the first interval 207 is arranged in the first region 211, and the second interval 210 is arranged in the second region 212. It can be understood that the first region 211 and the second region 212 can be joined, that is, there is no gap between the first region 211 and the second region; accordingly, the boundary line between the first region 211 and the second region 212 is a straight line parallel to the second direction, and the present embodiment does not limit the position of the boundary line along the first direction. Of course, in other embodiments, the first region 211 and the second region 212 can also be arranged at intervals.

[0110] In the above implementation, the first interval 207 between the first sub-bit line 205 and the second sub-bit line 206 is located in the first area 211, and the end of the second sub-bit line 206 close to the first interval 207 is located in the first area 211, and the second interval 210 between the third sub-bit line 208 and the fourth sub-bit line 209 is located in the second area 212, and the end of the fourth sub-bit line 209 close to the second interval 210 is located in the second area 212. It can be ensured that the first interval 207 and the second interval 210 are staggered in the second direction. In the implementation mode of staggered arrangement of the first interval 207 and the second interval 210, the end of the third sub-bit line 208 close to the second interval 210 will not be located between two adjacent first sub-bit lines 205 along the second direction, nor between two adjacent second sub-bit lines 206 along the second direction, one end close to the first interval 207; conversely, the end of the second sub-bit line 206 close to the first interval 207 will not be located between two adjacent third sub-bit lines 208 along the second direction, nor between two adjacent fourth sub-bit lines 209 along the second direction, one end close to the second interval 209.

[0111] In combination with the above implementation, in an implementation in which a conductive wire is connected to one end of the second sub-bit line 206 close to the first interval 207 and a conductive wire is connected to one end of the fourth sub-bit line 209 close to the second interval 210, through the above configuration, the first interval 207 is located in the first area 211, so that the end of the second sub-bit line 206 close to the first interval 207 is located in the first area 211, and the second interval 210 is located in the second area 212, so that the end of the fourth sub-bit line 209 close to the second interval 210 is located in the second area 212, so as to increase the distance between the end of the second sub-bit line 206 close to the first interval 207 and the end of the fourth sub-bit line 209 close to the second interval 210, thereby increasing the distance between the conductive wire connected to the second sub-bit line 206 and the conductive wire connected to the fourth sub-bit line 209, thereby reducing the leakage between the two conductive wires.

[0112] In the above implementation, the position of the first spacer 207 formed on the first bit line 203 can be determined according to the position of the second spacer 210 on the second bit line 204 adjacent to the first bit line 203, and the position of the second spacer 210 formed on the second bit line 204 can be determined according to the position of the first spacer 207 on the first bit line 203 adjacent to the second bit line 204. The first spacers 207 may not be on the same straight line parallel to the second direction in the second direction, and it is only necessary to ensure that each first spacer 207 is located in the first area 211. Similarly, the second spacers 210 may not be on the same straight line parallel to the second direction in the second direction, and it is only necessary to ensure that each second spacer 210 is located in the second area 212. In this way, the first spacers 207 and the second spacers 210 can be staggered in the second direction.

[0113] In the above implementation, each first spacer 207 spaced apart in the second direction may also be aligned in the second direction, and each second spacer 210 spaced apart in the second direction may also be aligned in the second direction. It can be understood that, through the above arrangement, the multiple first spacers 207 are located in a straight line in the second direction. Then, after the first spacer 207 is formed, one end of the multiple first sub-bit lines 205 close to the first spacer 207 is aligned in the second direction, and one end of the multiple second sub-bit lines 206 close to the first spacer 207 is aligned in the second direction; and after the second spacer 210 is formed, one end of the multiple third sub-bit lines 208 close to the second spacer 210 is aligned in the second direction, and one end of the multiple fourth sub-bit lines 209 close to the second spacer 210 is aligned in the second direction, which can make the bit line layer 201 more regular, and facilitate the formation of wires on the first bit lines 203 and the second bit lines 204 to realize the lead-out of the bit line layer 201.

[0114] Please refer to Figure 6 In the above implementation, the semiconductor structure 200 further includes a plurality of third bit lines 213, a third bit line 213 is provided between the adjacent first bit line 203 and the second bit line 204, the third bit line 213 includes a fifth sub-bit line 214 and a sixth sub-bit line 215, the fifth sub-bit line 214 is located between an adjacent first sub-bit line 205 and a fourth sub-bit line 209; the sixth sub-bit line 215 is located between an adjacent second sub-bit line 206 and a third sub-bit line 208. It should be noted that, Figure 6 The curly brackets in the lower right corner are used to indicate that 214 and 215 belong to 213, and 203, 204, and 213 belong to 201.

[0115] Through the above arrangement, the fifth sub-bit line 214 increases the distance between the first sub-bit line 205 and the fourth sub-bit line 209. On the one hand, the distance between two adjacent first sub-bit lines 205 in the second direction is increased. In the implementation mode in which a plurality of first intervals 207 are aligned in the second direction, the distance between two adjacent first intervals 207 is increased, thereby increasing the distance between the wires on the two first sub-bit lines 205, which can reduce the leakage between the wires on the adjacent first sub-bit lines 205. On the other hand, the distance between two adjacent fourth sub-bit lines 209 in the second direction is increased. In the implementation mode in which a plurality of second intervals 210 are aligned in the second direction, the distance between two adjacent second intervals 210 is increased, thereby increasing the distance between the wires on the two fourth sub-bit lines 209, thereby reducing the leakage between the wires on the adjacent fourth sub-bit lines 209. leakage; at the same time, the sixth sub-bit line 215 increases the distance between the second sub-bit line 206 and the third sub-bit line 208. On the one hand, the distance between two adjacent second sub-bit lines 206 in the second direction is increased. In the implementation mode in which multiple first intervals 207 are aligned in the second direction, the distance between two adjacent first intervals 207 is increased, thereby increasing the distance between the wires on the two second sub-bit lines 206 to reduce the leakage between the wires on the adjacent second sub-bit lines 206; on the other hand, the distance between two third sub-bit lines 208 in the second direction is increased. In the implementation mode in which multiple second intervals 210 are aligned in the second direction, the distance between two adjacent second intervals 210 is increased, thereby increasing the distance between the wires on the two third sub-bit lines 208 to reduce the leakage between the wires on the adjacent third sub-bit lines 208.

[0116] In the implementation mode where the third bit line 213 includes the fifth sub-bit line 214 and the sixth sub-bit line 215, the fifth sub-bit line 214 located between the first sub-bit line 205 and the fourth sub-bit line 209 may not be connected to the wire in the wiring layer 202, so as to avoid the problem of leakage between the wires due to the small distance between the wire on the fifth sub-bit line 214 and the wire on the first sub-bit line 205 after the wire is connected to the fifth sub-bit line 214. In other embodiments, the fifth sub-bit line 214 may be located at one end ( Figure 6 The sixth sub-bit line 215 located between the second sub-bit line 206 and the third sub-bit line 208 may not be connected to the wire in the wiring layer 202 to avoid the problem of leakage between the wires due to the small distance between the wire on the sixth sub-bit line 215 and the wire on the second sub-bit line 206 after the wire is connected to the sixth sub-bit line 215. However, in other embodiments, the sixth sub-bit line 215 may be connected to the wire on the end (not shown) of the sixth sub-bit line 215 away from the first region 211. Figure 6The bit line layer 201 may be connected to the conductive lines in the wiring layer 202 to enhance the connection between the bit line layer 201 and the wiring layer 202.

[0117] In the above implementation, the end of the fifth sub-bit line 214 close to the second area 212 is farther from the boundary between the first area 211 and the second area 212 than the end of the first sub-bit line 205 close to the first gap 207, so as to avoid the fifth sub-bit line 214 being located between the ends of two adjacent first sub-bit lines 205 close to the first gap 207, thereby avoiding the wire connecting the first sub-bit line 205 and the fifth sub-bit line 214 at the same time during the process of connecting the wire to the end of the first sub-bit line 205 close to the first gap 207. The end of the sixth sub-bit line 215 close to the first area 211 is farther from the boundary between the first area 211 and the second area 212 than the end of the third sub-bit line 208 close to the second interval 210, so as to avoid the sixth sub-bit line 215 being located between the ends of two adjacent third sub-bit lines 208 close to the second interval 210, thereby avoiding the wire connecting the third sub-bit line 208 and the sixth sub-bit line 215 at the same time during the process of connecting the wire to the end of the third sub-bit line 208 close to the first interval 207.

[0118] In the implementation mode of connecting the wiring layer 202 to the bit line layer 201, the semiconductor structure 200 may further include a first conductive pillar 216, a second conductive pillar 217, a third conductive pillar 218, and a fourth conductive pillar 219, wherein the first conductive pillar 216 is disposed at one end of the first sub-bit line 205 close to the first interval 207, the first conductive pillar 216 is connected to the wiring layer 202, and the first conductive pillar 216 is used to lead the current of the first sub-bit line 205 to the wiring layer 202; the second conductive pillar 217 is disposed at one end of the second sub-bit line 206 close to the first interval 207, the second conductive pillar 217 is connected to the wiring layer 202, and the first conductive pillar 218 is used to lead the current of the first sub-bit line 205 to the wiring layer 202; 202 is connected, the second conductive pillar 217 is used to lead the current of the second sub-bit line 206 to the wiring layer 202; the third conductive pillar 218 is arranged at one end of the third sub-bit line 208 close to the second interval 210, the third conductive pillar 218 is connected to the wiring layer 202, and the third conductive pillar 218 is used to lead the current of the third sub-bit line 208 to the wiring layer 202; the fourth conductive pillar 219 is arranged at one end of the fourth sub-bit line 209 close to the second interval 210, the fourth conductive pillar 219 is connected to the wiring layer 202, and the fourth conductive pillar 219 is used to lead the current of the fourth sub-bit line 209 to the wiring layer 202.

[0119] Through the above arrangement, in the process of leading the current of the bit line layer 201 to the wiring layer 202 through the first conductive pillar 216, the second conductive pillar 217, the third conductive pillar 218 and the fourth conductive pillar 219, the distance between each of the first conductive pillar 216, the second conductive pillar 217, the third conductive pillar 218 and the fourth conductive pillar 219 is increased to avoid leakage between adjacent conductive pillars.

[0120] Please refer to Figure 8 , Fig. 9 and Fig.10 In the above implementation, the wiring layer 202 may include a first wiring layer 220 and a second wiring layer 221 which are stacked, the first wiring layer 220 is located between the second wiring layer 221 and the bit line layer 201, the first conductive pillar 216, the second conductive pillar 217, the third conductive pillar 218 and the fourth conductive pillar 219 are all connected to the first wiring layer 220, and the first wiring layer 220 is connected to the second wiring layer 221. The second wiring layer 221 is used to connect to the peripheral circuit layer 130. It should be noted that Figure 8 The curly brackets in the lower right corner are used to indicate that 214 and 215 belong to 213, 226 and 227 belong to 221, and can also belong to 202. Fig. 9 The curly brackets in the lower right corner are used to indicate that 222 and 223 belong to 220, 226 belongs to 221, and 220 and 221 belong to 202. Fig.10 The curly brackets in the lower right corner are used to indicate that 224 and 225 belong to 220, 227 belongs to 221, and 220 and 221 belong to 202.

[0121] Through the above arrangement, after the bit line layer 201 draws the current to the first wiring layer 220 through the first conductive pillar 216, the second conductive pillar 217, the third conductive pillar 218 and the fourth conductive pillar 219, the first wiring layer 220 is connected to the second wiring layer 221 to realize the drawing of the current in the first wiring layer 220, and the wires in the wiring layer 202 can be respectively arranged in the first wiring layer 220 and the second wiring layer 221 to reduce the complexity of the wires in the first wiring layer 220, thereby increasing the distance between the wires in the first wiring layer 220, avoiding leakage of the wires in the first wiring layer 220, and also reducing the area of ​​the first wiring layer 220, thereby reducing the volume of the semiconductor structure 200. On the other hand, the complexity of the wires in the second wiring layer 221 can also be reduced, thereby increasing the distance between the wires in the second wiring layer 221, and avoiding leakage of the wires in the second wiring layer 221. Similarly, the area of ​​the second wiring layer 221 can also be reduced, thereby reducing the volume of the semiconductor structure 200.

[0122] Please refer to Figure 7In the above implementation, the first wiring layer 220 includes a first wire 222, a second wire 223, a third wire 224 and a fourth wire 225. The first wire 222 is parallel to the first sub-bit line 205. The first wire 222 extends from an end of the first sub-bit line 205 close to the first gap 207 along the first direction to a direction away from the first gap 207. The wires in the second wiring layer 221 can respectively connect the first wire 222 and the second wire 223. The longer the length of the first wire 222 is, the longer the first wire 222 is, and the longer the first wire 222 is, the longer the wire 224 is. Figure 8 During the lead-out process (as shown in the figure), any point on the first wire 222 can be selected as the connection point between the second wiring layer 221 and the first wire 222, which increases the connection selectivity between the second wiring layer 221 and the first wire 222, facilitates the setting of the position of the wire in the second wiring layer 221, avoids the distance between the wire connected to the first wire 222 and the wire connected to the second wire 223 being too small, and further avoids leakage of the wire in the second wiring layer 221. Similarly, the third wire 224 is parallel to the third sub-bit line 208, and the third wire 224 extends from one end of the third sub-bit line 208 close to the second interval 210 along the first direction toward the direction away from the second interval 210, wherein the wires in the second wiring layer 221 can also connect the third wire 224 and the fourth wire 225 respectively. The longer the third wire 224 is, the more any point on the third wire 224 can be selected as the connection point between the second wiring layer 221 and the third wire 224 during the process of the third wire 224 continuing to be led out to the second wiring layer 221, thereby increasing the connection selectivity between the second wiring layer 221 and the third wire 224, facilitating the setting of the position of the wire in the second wiring layer 221, and avoiding the distance between the wire connecting the third wire 224 and the wire connecting the fourth wire 225 being too small, thereby avoiding leakage of the wire in the second wiring layer 221. It should be noted that Figure 7 The curly brackets in the lower right corner are used to indicate that 214 and 215 belong to 213, and 222, 223, 224, and 225 belong to 220, and can also belong to 202.

[0123] Continue to refer to Figure 7The second conductive wire 223 is parallel to the second sub-bit line 206. The second conductive wire 223 extends from one end of the second sub-bit line 206 close to the first interval 207 along the first direction to a direction away from the first interval 207, but the second conductive wire 223 is always located in the first region 211, that is, the length of the second conductive wire 223 along the first direction is less than or equal to the length of the first conductive wire 222 along the first direction, and the length of the fourth conductive wire 225 along the first direction is less than or equal to the length of the third conductive wire 224 along the first direction. The fourth conductive wire 225 is parallel to the fourth sub-bit line 209. The fourth conductive wire 225 extends from one end of the fourth sub-bit line 209 close to the second interval 210 along the first direction to a direction away from the second interval 210, but the fourth conductive wire 225 is always located in the second region 212, that is, the length of the fourth conductive wire 225 along the first direction is less than or equal to the length of the third conductive wire 224 along the first direction.

[0124] Through the above arrangement, it is possible to avoid the distance between the second wire 223 and the fourth wire 225 being too small, thereby preventing leakage between the second wire 223 and the fourth wire 225.

[0125] Continue to refer to Figure 7 In the above implementation, the projection of the first wire 222 on the bit line layer 201 covers the first conductive pillar 216, the projection of the second wire 223 on the bit line layer 201 covers the second conductive pillar 217, the projection of the third wire 224 on the bit line layer 201 covers the third conductive pillar 218, and the projection of the fourth wire 225 on the bit line layer 201 covers the fourth conductive pillar 219. Through the above arrangement, the lengths of the first conductive pillar 216, the second conductive pillar 217, the third conductive pillar 218, and the fourth conductive pillar 219 can be shortened, thereby shortening the distance between the first wiring layer 220 and the bit line layer 201, and improving the integration of the semiconductor structure 200.

[0126] Continue to refer to Figure 7In an implementation in which the semiconductor structure 200 includes a first conductive pillar 216, a second conductive pillar 217, a third conductive pillar 218, and a fourth conductive pillar 219, the first conductive wire 222 is connected to an end of the first sub-bit line 205 close to the first interval 207 through the first conductive pillar 216, the second conductive wire 223 is connected to an end of the second sub-bit line 206 close to the first interval 207 through the second conductive pillar 217, the third conductive wire 224 is connected to an end of the third sub-bit line 208 close to the second interval 210 through the third conductive pillar 218, and the fourth conductive wire 225 is connected to an end of the fourth sub-bit line 209 close to the second interval 210 through the fourth conductive pillar 219. Through the above arrangement, in the process of leading the current of the bit line layer 201 to the first wiring layer 220 through the first conductive pillar 216, the second conductive pillar 217, the third conductive pillar 218 and the fourth conductive pillar 219, it is possible to avoid the distance between the first conductive pillar 216, the second conductive pillar 217, the third conductive pillar 218 and the fourth conductive pillar 219 being too small, and leakage between two adjacent conductive pillars can be avoided.

[0127] Please refer to Figure 8 In the above implementation, the second wiring layer 221 includes a fifth wire 226 and a sixth wire 227, the fifth wire 226 is parallel to the first wire 222, and the fifth wire 226 is in the first wiring layer 220 (such as Figure 7 The projection of the sixth wire 227 on the first wiring layer 220 covers the first wire 222 and the second wire 223, the sixth wire 227 is parallel to the third wire 224, and the projection of the sixth wire 227 on the first wiring layer 220 covers the third wire 224 and the fourth wire 225. In the implementation of the semiconductor structure 200 including the second conductive column 217 and the fourth conductive column 219, one end of the fifth wire 226 covers the second conductive column 217, and the other end of the fifth wire 226 extends in a direction away from the second area 212; one end of the sixth wire 227 covers the fourth conductive column 219, and the other end of the sixth wire 227 extends in a direction away from the first area 211. Through the above arrangement, the fifth wire 226 and the sixth wire 227 are staggered in the second direction, the distance between the fifth wire 226 and the sixth wire 227 is increased, and leakage between the fifth wire 226 and the sixth wire 227 is avoided. It should be noted that Fig. 9 The curly brackets in the lower right corner are used to indicate that 222 and 223 belong to 220, 226 belongs to 221, and 220 and 221 belong to 202.

[0128] Continue to refer to Figure 8In the implementation method of connecting the first wiring layer 220 and the second wiring layer 221, the semiconductor structure 200 may also include a fifth conductive column 228 and a sixth conductive column 229, the fifth wire 226 is connected to the first wire 222 and the second wire 223 through the fifth conductive column 228, and the sixth wire 227 is connected to the third wire 224 and the fourth wire 225 through the sixth conductive column 229. Exemplarily, a fifth conductive column 228 is provided between the first conductive line 222 and the fifth conductive line 226, and a fifth conductive column 228 is provided between the second conductive line 223 and the fifth conductive line 226. The projection of the fifth conductive line 226 on the first wiring layer 220 covers the first conductive line 222 and the second conductive line 223, thereby shortening the length of the fifth conductive column 228. A sixth conductive column 229 is provided between the third conductive line 224 and the sixth conductive line 227, and a sixth conductive column 229 is provided between the fourth conductive line 225 and the sixth conductive line 227. The projection of the sixth conductive line 227 on the first wiring layer 220 covers the third conductive line 224 and the fourth conductive line 225, thereby shortening the length of the sixth conductive column 229. Through the above-mentioned arrangement, in the process of leading the current of the first wiring layer 220 to the second wiring layer 221 through the fifth conductive pillar 228 and the sixth conductive pillar 229, the fifth conductive pillar 228 is respectively connected to the first wire 222 and the second wire 223, which can avoid the distance between the two fifth conductive pillars 228 being too small, and avoid leakage between the two fifth conductive pillars 228; and the sixth conductive pillar 229 is respectively connected to the third wire 224 and the fourth wire 225, which can avoid the distance between the two sixth conductive pillars 229 being too small, and avoid leakage between the two sixth conductive pillars 229.

[0129] The present application also provides a method for preparing a semiconductor structure, which can be used to prepare the semiconductor structure 200 in the above embodiment. Fig.11 , the preparation method may include steps S100-S200:

[0130] S100: forming a bit line layer, the bit line layer comprising a plurality of first bit lines and a plurality of second bit lines, the first bit lines and the second bit lines both extending along a first direction, the first bit lines and the second bit lines alternately arranged along a second direction, the second direction being perpendicular to the first direction.

[0131] Please refer to Fig.12 In step S100, before forming the bit line layer 201, a semiconductor layer 11 (such as Figure 2 As shown), the semiconductor layer 11 includes a plurality of memory cell strings 40 (as shown Figure 3As shown), a plurality of memory cell strings 40 may be arranged in an array with a first direction as the longitudinal direction and a second direction as the transverse direction. In the process of forming a bit line layer 201 on the semiconductor layer 11, each of the plurality of first bit lines 203 formed may be connected to a memory cell string 40 arranged in a row corresponding to the first direction, and each of the plurality of second bit lines 204 formed may be connected to a memory cell string 40 arranged in a row corresponding to the first direction. The first bit lines 203 and the second bit lines 204 are alternately spaced along the second direction.

[0132] S200: removing part of the first bit line and part of the second bit line to form a first interval on the first bit line and a second interval on the second bit line; the first interval divides the first bit line into a first sub-bit line and a second sub-bit line, and the second interval divides the second bit line into a third sub-bit line and a fourth sub-bit line; the first interval and the second interval are staggered in the first direction.

[0133] Please refer to Fig.13 In the above implementation, part of the first bit line 203 in the first region 211 is removed to form a first interval 207, and the first interval 207 divides the first bit line 203 into a first sub-bit line 205 and a second sub-bit line 206. Since the first interval 207 is formed in the first region 211, an end of the first sub-bit line 205 close to the first interval 207 and an end of the second sub-bit line 206 close to the first interval 207 are both located in the first region 211; similarly, part of the second bit line 204 in the second region 212 is removed to form a second interval 210, and the second interval 210 divides the second bit line 204 into a third sub-bit line 208 and a fourth sub-bit line 209. Since the second interval 210 is formed in the second region 212, an end of the third sub-bit line 208 close to the second interval 210 and an end of the fourth sub-bit line 209 close to the second interval 210 are both located in the second region 212.

[0134] In the method for preparing a semiconductor structure provided by an embodiment of the present application, the first spacer 207 and the second spacer 210 are staggered in the first direction, so that an end of the first sub-bit line 205 close to the first spacer 207 and an end of the fourth sub-bit line 209 close to the second spacer 210 are staggered in the first direction, and an end of the first sub-bit line 205 close to the first spacer 207, an end of the second sub-bit line 206 close to the first spacer 207, an end of the third sub-bit line 208 close to the second spacer 210, and an end of the fourth sub-bit line 209 close to the second spacer 210 are all used to connect the wires in the wiring layer 202, thereby increasing the distance between the wires connecting the first sub-bit line 205 and the second sub-bit line 206 and the wires connecting the third sub-bit line 208 and the fourth sub-bit line 209 along the first direction, thereby reducing the leakage between adjacent wires in the wiring layer.

[0135] In one embodiment, one end of the first sub-bit line 205 close to the first interval 207 is connected to a conductive wire, and one end of the fourth sub-bit line 209 close to the second interval 210 is connected to a conductive wire. Since the first interval 207 and the second interval 210 are staggered in the first direction, the distance between the end of the first sub-bit line 205 close to the first interval 207 and the end of the fourth sub-bit line 209 close to the second interval 210 in the first direction is increased, thereby increasing the distance between the conductive wire connected to the first sub-bit line 205 and the conductive wire connected to the fourth sub-bit line 209, thereby reducing leakage between the two conductive wires.

[0136] In another embodiment, a conductive wire is connected to one end of the second sub-bit line 206 close to the first interval 207 and a conductive wire is connected to one end of the third sub-bit line 208 close to the second interval 210. Since the first interval 207 and the second interval 210 are staggered in the first direction, the distance between one end of the second sub-bit line 206 close to the first interval 207 and one end of the third sub-bit line 208 close to the second interval 210 in the first direction is increased, thereby increasing the distance between the conductive wire connected to the second sub-bit line 206 and the conductive wire connected to the third sub-bit line 208, thereby reducing leakage between the two conductive wires.

[0137] In an implementation in which the semiconductor structure 200 includes a first region 211 and a second region 212, the end of the second sub-bit line 206 close to the first interval 207 can be located in the first region 211, and the end of the fourth sub-bit line 209 close to the second interval 210 can be located in the second region 212, so that the distance between the end of the second sub-bit line 206 close to the first interval 207 and the end of the fourth sub-bit line 209 close to the second interval 210 can be increased. In the case where the end of the second sub-bit line 206 close to the first interval 207 and the end of the fourth sub-bit line 209 close to the second interval 210 are connected to the wire, the distance between the wire connected to the second sub-bit line 206 and the wire connected to the fourth sub-bit line 209 can be increased, thereby reducing the leakage between the two wires.

[0138] In another embodiment, please refer to Fig.14 The formation of the bit line layer 201 further includes forming a third bit line 213 between the adjacent first bit line 203 and the second bit line 204; in some embodiments, the third bit line 213 may also be connected to the memory cell string 40 (such as Figure 3 The first bit line 203, the third bit line 213, the second bit line 204, the third bit line 213, and the first bit line 203 are connected in a reciprocating manner in the second direction. Through the above arrangement, the distance between the first bit line 203 and the second bit line 204 is increased, so that leakage between the wire connecting the first bit line 203 and the wire connecting the second bit line 204 is avoided during the current extraction process of the first bit line 203 and the second bit line 204.

[0139] In step S100, after forming the bit line layer 201, the bit line layer 201 of the semiconductor structure 200 may include a first area 211 and a second area 212 that are adjacently arranged, and the first area 211 and the second area 212 are arranged along a first direction, wherein the division of the first area 211 and the second area 212 may be artificially determined. In step S200, removing a portion of the first bit line 203 and a portion of the second bit line 204 to form a first spacer 207 on the first bit line 203, and forming a second spacer 210 on the second bit line 204 includes: removing a portion of the first bit line 203 in the first area 211 to form the first spacer 207, and removing a portion of the second bit line 204 in the second area 212 to form the second spacer 210.

[0140] Please refer to Fig.15 and Fig.16 , removing a portion of the first bit line 203 and a portion of the second bit line 204 to form a first spacer 207 on the first bit line 203, and before forming the second spacer 210 on the second bit line 204, further comprising: removing a portion of the third bit line 213. After removing a portion of the third bit line 213, the third bit line 213 is divided into a fifth sub-bit line 214 and a sixth sub-bit line 215, wherein the fifth sub-bit line 214 is located in the first region 211 and on a side of the first region 211 away from the second region 212, and the sixth sub-bit line 215 is located in the second region 212 and on a side of the second region 212 away from the first region 211. Then, during step S200, first spacer 207 is formed on the side of fifth sub-bit line 214 close to second area 212, that is, after first spacer 207 divides first bit line 203 into first sub-bit line 205 and second sub-bit line 206, one end of first sub-bit line 205 close to first spacer 207 is closer to the boundary between first area 211 and second area 212 than one end of fifth sub-bit line 214 close to second area 212, so as to avoid fifth sub-bit line 214 being located between one end of two adjacent first sub-bit lines 205 close to first spacer 207, thereby avoiding connecting to fifth sub-bit line 214 when one end of first sub-bit line 205 close to first spacer 207 is wired. The second spacer 210 is formed on the side of the sixth sub-bit line 215 close to one area. That is, after the second spacer 210 divides the second bit line 204 into the third sub-bit line 208 and the fourth sub-bit line 209, the end of the third sub-bit line 208 close to the second spacer 210 is closer to the boundary between the first area 211 and the second area 212 than the end of the sixth sub-bit line 215 close to the first area 211, so as to avoid the sixth sub-bit line 215 being located between the ends of two adjacent third sub-bit lines 208 close to the second spacer 210, thereby avoiding the end of the third sub-bit line 208 close to the first spacer 207 from being connected to the sixth sub-bit line 215 when wiring is performed.

[0141] In the method for preparing the semiconductor structure 200 provided in the embodiment of the present application, after forming the first spacer 207 and the second spacer 210 in step S200, the following steps may be further included:

[0142] Please refer to Fig.17 , a wiring layer 202 is formed on the bit line layer 201 (eg Figure 7 and Figure 8 As shown, a first conductive pillar 216 is formed at one end of the first sub-bit line 205 close to the first spacer 207, a second conductive pillar 217 is formed at one end of the second sub-bit line 206 close to the first spacer 207, a third conductive pillar 218 is formed at one end of the third sub-bit line 208 close to the second spacer 210, and a fourth conductive pillar 219 is formed at one end of the fourth sub-bit line 209 close to the second spacer 210, and the first conductive pillar 216, the second conductive pillar 217, the third conductive pillar 218 and the fourth conductive pillar 219 are all connected to the wiring layer 202.

[0143] Through the above arrangement, the first conductive pillar 216 is formed at one end of the first sub-bit line 205 close to the first spacer 207, the second conductive pillar 217 is formed at one end of the second sub-bit line 206 close to the first spacer 207, the third conductive pillar 218 is formed at one end of the third sub-bit line 208 close to the second spacer 210, and the fourth conductive pillar 219 is formed at one end of the fourth sub-bit line 209 close to the second spacer 210. In the process of leading the current of the bit line layer 201 to the wiring layer 202 through the first conductive pillar 216, the second conductive pillar 217, the third conductive pillar 218 and the fourth conductive pillar 219, the distance between each of the first conductive pillar 216, the second conductive pillar 217, the third conductive pillar 218 and the fourth conductive pillar 219 is increased to avoid leakage between adjacent conductive pillars.

[0144] Please refer to Fig.18 and Fig.19 In an implementation in which the wiring layer 202 includes a first wiring layer 220 and a second wiring layer 221, Fig.18 In the embodiment, forming the wiring layer 202 on the bit line layer 201 in a stacked manner may further include:

[0145] A first wiring layer 220 is formed in a stacked manner on the bit line layer 201 and a second wiring layer 221 is formed in a stacked manner on the first wiring layer 220;

[0146] Connecting the first conductive pillar 216, the second conductive pillar 217, the third conductive pillar 218 and the fourth conductive pillar 219 to the wiring layer 202 includes connecting the first conductive pillar 216, the second conductive pillar 217, the third conductive pillar 218 and the fourth conductive pillar 219 to the first wiring layer 220, and connecting the first wiring layer 220 and the second wiring layer 221.

[0147] Through the above arrangement, after the bit line layer 201 draws the current to the first wiring layer 220 through the first conductive pillar 216, the second conductive pillar 217, the third conductive pillar 218 and the fourth conductive pillar 219, the first wiring layer 220 is connected to the second wiring layer 221 to realize the drawing of the current in the first wiring layer 220, and the wires in the wiring layer 202 can be respectively arranged in the first wiring layer 220 and the second wiring layer 221 to reduce the complexity of the wires in the first wiring layer 220, thereby increasing the distance between the wires in the first wiring layer 220, avoiding leakage of the wires in the first wiring layer 220, and also reducing the area of ​​the first wiring layer 220, thereby reducing the volume of the semiconductor structure 200. On the other hand, the complexity of the wires in the second wiring layer 221 can be reduced, thereby increasing the distance between the wires in the second wiring layer 221, and avoiding leakage of the wires in the second wiring layer 221. Similarly, the area of ​​the second wiring layer 221 can be reduced, thereby reducing the volume of the semiconductor structure 200.

[0148] In combination with the implementation method in which the first wiring layer 220 includes a first wire 222, a second wire 223, a third wire 224 and a fourth wire 225, the formation of the first wiring layer 220 in the above implementation method may include: forming a first wire 222 to connect the first conductive column 216 and the first conductive column 222; forming a second conductive column 223 to connect the second conductive column 217 and the second conductive column 223; forming a third conductive column 224 to connect the third conductive column 218 and the third conductive column 224; forming a fourth conductive column 225 to connect the fourth conductive column 219 and the fourth conductive column 225.

[0149] Through the above configuration, the current in the bit line layer 201 is led out through the first wire 222 , the second wire 223 , the third wire 224 and the fourth wire 225 .

[0150] Please refer to Fig.19 , combined with the second wiring layer 221 including the fifth wire 226 and the sixth wire 227, a fifth conductive column 228 and a sixth conductive column 229 are provided between the second wiring layer 221 and the first wiring layer 220. In the above implementation, the second wiring layer 221 is formed including: forming the fifth wire 226, and connecting the fifth wire 226 with the first wire 222 and the second wire 223 through the fifth conductive column 228; forming the sixth wire 227, and connecting the sixth wire 227 with the third wire 224 and the fourth wire 225 through the sixth conductive column 229.

[0151] Through the above arrangement, the current in the first wiring layer 220 is led out through the fifth conductive line 226 , the sixth conductive line 227 , the fifth conductive column 228 , and the sixth conductive column 229 .

[0152] Please refer to Fig. 20 and Fig.21 Some embodiments of the present application further provide a storage system 1000. The storage system 1000 includes a controller 20 and a three-dimensional memory 10, wherein the three-dimensional memory 10 may include the three-dimensional memory 10 described above, and the controller 20 is coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

[0153] The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0154] In some embodiments, reference Fig. 20 The storage system 1000 includes a controller 20 and a three-dimensional memory 10, and the storage system 1000 can be integrated into a memory card.

[0155] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0156] In other embodiments, referring to Fig.21 The storage system 1000 includes a controller 20 and a plurality of three-dimensional memories 10, and the storage system 1000 is integrated into a solid state drive (SSD).

[0157] In the storage system 1000, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0158] In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0159] In some embodiments, the controller 20 may be configured to manage data stored in the three-dimensional memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the three-dimensional memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 10, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 20 is also configured to process error correction codes regarding data read from or written to the three-dimensional memory 10.

[0160] Of course, the controller 20 may also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, the controller 20 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0161] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0162] Some embodiments of the present application also provide an electronic device. The electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0163] The electronic device may include a host and the storage system 1000 described above, wherein the host and the storage system 1000 may be coupled and may further include at least one of a central processing unit (CPU) and a cache.

[0164] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, it includes: A bit line layer, the bit line layer includes a plurality of first bit lines and a plurality of second bit lines, the first bit lines and the second bit lines both extend along a first direction, and the plurality of first bit lines and the plurality of second bit lines are alternately arranged at intervals along a second direction, and the second direction is perpendicular to the first direction; The first bit line includes a first sub-bit line and a second sub-bit line, the first sub-bit line and the second sub-bit line have a first interval in the first direction, the second bit line includes a third sub-bit line and a fourth sub-bit line, the third sub-bit line and the fourth sub-bit line have a second interval in the first direction; among the adjacent first bit line and second bit line, the first interval and the second interval are arranged staggeredly in the first direction.

2. The semiconductor structure according to claim 1, characterized in that, the semiconductor structure includes an adjacent first region and a second region, the first region and the second region are arranged along the first direction, the first interval is arranged in the first region, and the second interval is arranged in the second region.

3. The semiconductor structure according to claim 2, characterized in that, each of the first intervals arranged at intervals in the second direction is aligned in the second direction; each of the second intervals arranged at intervals in the second direction is aligned in the second direction.

4. The semiconductor structure according to claim 3, characterized in that, the semiconductor structure further includes a wiring layer, the wiring layer is arranged in a stacked manner with the bit line layer, a first conductive pillar is provided at one end of the first sub-bit line close to the first interval, a second conductive pillar is provided at one end of the second sub-bit line close to the first interval, a third conductive pillar is provided at one end of the third sub-bit line close to the second interval, and a fourth conductive pillar is provided at one end of the fourth sub-bit line close to the second interval, and the first conductive pillar, the second conductive pillar, the third conductive pillar and the fourth conductive pillar are all connected to the wiring layer.

5. The semiconductor structure according to claim 4, characterized in that, the wiring layer includes a first wiring layer and a second wiring layer arranged in a stacked manner, the first wiring layer is located between the second wiring layer and the bit line layer, the first conductive pillar, the second conductive pillar, the third conductive pillar and the fourth conductive pillar are all connected to the first wiring layer, and the first wiring layer is connected to the second wiring layer.

6. The semiconductor structure according to claim 5, characterized in that, the first wiring layer includes a first wire, a second wire, a third wire and a fourth wire, the first wire is connected to one end of the first sub-bit line close to the first interval through the first conductive pillar, the second wire is connected to one end of the second sub-bit line close to the first interval through the second conductive pillar, the third wire is connected to one end of the third sub-bit line close to the second interval through the third conductive pillar, and the fourth wire is connected to one end of the fourth sub-bit line close to the second interval through the fourth conductive pillar; The second wiring layer includes a fifth wire and a sixth wire. The fifth wire is connected to the first wire and the second wire through a fifth conductive pillar, and the sixth wire is connected to the third wire and the fourth wire through a sixth conductive pillar.

7. The semiconductor structure according to claim 6, wherein, the first wire is parallel to the first sub-bit line, and the projection of the first wire on the bit line layer covers the first conductive pillar; the second wire is parallel to the second sub-bit line, and the projection of the second wire on the bit line layer covers the second conductive pillar; the third wire is parallel to the third sub-bit line, and the projection of the third wire on the bit line layer covers the third conductive pillar; the fourth wire is parallel to the fourth sub-bit line, and the projection of the fourth wire on the bit line layer covers the fourth conductive pillar.

8. The semiconductor structure according to claim 7, wherein, the length of the second wire in the first direction is less than or equal to the length of the first wire in the first direction, and the length of the fourth wire in the first direction is less than or equal to the length of the third wire in the first direction.

9. The semiconductor structure according to claim 6, wherein, the fifth wire is parallel to the first wire, and the projection of the fifth wire on the first wiring layer covers the first wire and the second wire; the sixth wire is parallel to the third wire, and the projection of the sixth wire on the first wiring layer covers the third wire and the fourth wire.

10. The semiconductor structure according to any one of claims 1-9, wherein, the semiconductor structure further includes a plurality of third bit lines. One third bit line is provided between adjacent first bit line and second bit line. The third bit line includes a fifth sub-bit line and a sixth sub-bit line. The fifth sub-bit line is located between the first sub-bit line and the fourth sub-bit line; the sixth sub-bit line is located between the second sub-bit line and the third sub-bit line.

11. A method for manufacturing a semiconductor structure, wherein, it includes: forming a bit line layer, the bit line layer includes a plurality of first bit lines and a plurality of second bit lines. The first bit lines and the second bit lines both extend in a first direction, and the first bit lines and the second bit lines are alternately arranged at intervals in a second direction perpendicular to the first direction; removing a part of the first bit lines and a part of the second bit lines to form a first interval on the first bit lines and a second interval on the second bit lines; the first interval divides the first bit line into a first sub-bit line and a second sub-bit line, and the second interval divides the second bit line into a third sub-bit line and a fourth sub-bit line; the first interval and the second interval are arranged staggeredly in the first direction.

12. The manufacturing method according to claim 11, wherein, the semiconductor structure includes adjacent first region and second region, and the first region and the second region are arranged along the first direction; Removing part of the first bit lines and part of the second bit lines to form a first interval on the first bit lines and a second interval on the second bit lines includes: Removing part of the first bit lines in the first region to form the first interval, and removing part of the second bit lines in the second region to form the second interval.

13. The manufacturing method according to claim 12, wherein, after forming the first interval and the second interval, further comprising: forming a wiring layer on the bit line layer in a stacked manner, forming a first conductive pillar at one end of the first sub-bit line close to the first interval, forming a second conductive pillar at one end of the second sub-bit line close to the first interval, forming a third conductive pillar at one end of the third sub-bit line close to the second interval, forming a fourth conductive pillar at one end of the fourth sub-bit line close to the second interval, and connecting the first conductive pillar, the second conductive pillar, the third conductive pillar, and the fourth conductive pillar to the wiring layer.

14. The manufacturing method according to claim 13, wherein, the wiring layer includes a first wiring layer and a second wiring layer, and forming the wiring layer on the bit line layer in a stacked manner includes: forming the first wiring layer on the bit line layer in a stacked manner and forming the second wiring layer on the first wiring layer in a stacked manner; connecting the first conductive pillar, the second conductive pillar, the third conductive pillar, and the fourth conductive pillar to the wiring layer includes connecting the first conductive pillar, the second conductive pillar, the third conductive pillar, and the fourth conductive pillar to the first wiring layer, and connecting the first wiring layer and the second wiring layer.

15. The manufacturing method according to claim 14, wherein, the first wiring layer includes a first wire, a second wire, a third wire, and a fourth wire, the second wiring layer includes a fifth wire and a sixth wire, and a fifth conductive pillar and a sixth conductive pillar are provided between the second wiring layer and the first wiring layer; forming the first wiring layer includes: forming the first wire and connecting the first conductive pillar and the first wire; forming the second wire and connecting the second conductive pillar and the second wire; forming the third wire and connecting the third conductive pillar and the third wire; forming the fourth wire and connecting the fourth conductive pillar and the fourth wire; forming the second wiring layer includes: forming the fifth wire and connecting the fifth wire to the first wire and the second wire through the fifth conductive pillar; forming the sixth wire and connecting the sixth wire to the third wire and the fourth wire through the sixth conductive pillar.

16. The manufacturing method according to any one of claims 11-15, wherein, forming the bit line layer further includes forming a third bit line between adjacent first bit lines and second bit lines; before removing part of the first bit lines and part of the second bit lines to form a first interval on the first bit lines and a second interval on the second bit lines, further comprising: removing part of the third bit lines to form a fifth sub-bit line and a sixth sub-bit line.

17. A storage system, characterized in that, it includes: a semiconductor structure, which is the semiconductor structure as described in any one of claims 1-8; a controller, coupled to the semiconductor structure to control the semiconductor structure to store data.

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