Semiconductor device and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem of poor stability of the semiconductor device. The semiconductor device includes a memory stack structure and a channel contact. The storage stack structure comprises a stack structure and a plurality of channel structures, the plurality of channel structures penetrate through the stack structure along the stack direction of the stack structure, and the channel structures comprise channel parts. A plurality of channel contact parts which are arranged at intervals are arranged on the surface of one side of the laminated structure in the lamination direction, and the channel contact parts are in contact with the channel parts. Wherein the width of the channel contact part in the first direction is greater than that in the second direction. The first direction intersects with the stacking direction, the first direction intersects with the second direction, and the second direction intersects with the stacking direction. The semiconductor device is applied to the three-dimensional memory so as to realize data reading and writing operation.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and a manufacturing method thereof, a storage system, and an electronic device. Background Art

[0002] As the feature size of memory cells approaches the process limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach an upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND) to increase storage density by arranging storage cells three-dimensionally on a substrate.

[0004] As the number of stacked layers of memory cells in a three-dimensional memory increases, the distance between memory cells decreases, and the existing method for preparing three-dimensional memory results in poor stability of semiconductor devices. Summary of the invention

[0005] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, a storage system, and an electronic device, aiming to solve the problem of poor stability of semiconductor devices.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] On the one hand, a semiconductor device is provided, which includes: a storage stack structure and a channel contact portion. The storage stack structure includes a stack structure and a plurality of channel structures, wherein the plurality of channel structures penetrate the stack structure along the stacking direction of the stack structure, wherein the channel structure includes a channel portion. A plurality of spaced-apart channel contacts are arranged on a side surface of the stack structure along the stacking direction, wherein the channel contact portion contacts the channel portion, wherein the width of the channel contact portion in the first direction is greater than the width in the second direction. The first direction intersects with the stacking direction, the first direction intersects with the second direction, and the second direction intersects with the stacking direction.

[0008] The semiconductor device provided by the above-mentioned embodiment of the present disclosure increases the width of multiple channel contact portions in the first direction, so that the width of the channel contact portion in the first direction is greater than its width in the second direction, thereby effectively increasing the window area of ​​the channel contact portion. When a channel contact portion is formed on a side surface of a channel structure provided with a channel portion, the channel contact portion provided by the present disclosure has a larger contact window, which can achieve precise contact between the channel contact portion and the channel portion, thereby improving the accuracy of the alignment contact between the channel contact portion and the channel portion. At the same time, the channel contact portion with a larger contact window provided by the present disclosure is also conducive to achieving precise contact with subsequent stacked devices, thereby improving the electrical connection effect between the channel contact portion and the channel portion, and between the channel contact portion and the subsequent stacked devices, thereby improving the stability of the semiconductor device.

[0009] In some embodiments, a ratio of a width of the channel contact in the first direction to a width of the channel contact in the second direction is greater than or equal to 1.1 and less than or equal to 1.5.

[0010] In some embodiments, a cross-section of the channel contact portion on a reference plane is a straight-sided ellipse, wherein the reference plane is perpendicular to the stacking direction.

[0011] In some embodiments, the channel contact portion includes two cylindrical surfaces disposed opposite to each other in a first direction and two first planes disposed opposite to each other in a second direction, wherein one cylindrical surface protrudes in a direction away from the other cylindrical surface.

[0012] In some embodiments, the plurality of channel contacts are arranged in a plurality of rows, wherein the plurality of channel contacts in a row are sequentially arranged along the first direction, and the plurality of rows of channel contacts are sequentially arranged along the second direction. The channel contacts in two adjacent rows of channel contacts are staggered in the second direction.

[0013] In some embodiments, an area of ​​a cross section of the channel portion on a reference plane is smaller than an area of ​​a cross section of the channel contact portion on a reference plane, wherein the reference plane is perpendicular to the stacking direction.

[0014] In some embodiments, the semiconductor device further comprises: a plurality of connection portions, which are arranged on a surface of the channel contact portion facing away from the stacked structure, one connection portion contacts one channel contact portion, and the cross-sectional area of ​​the connection portion on the reference plane is smaller than the cross-sectional area of ​​the channel contact portion on the reference plane.

[0015] In some embodiments, the semiconductor device further comprises: a plurality of conductive wires. The plurality of conductive wires are arranged on a side of the plurality of connection portions away from the channel contact portion, the conductive wires extend along the second direction, and one conductive wire contacts at least one connection portion.

[0016] In some embodiments, a ratio of a width of the channel contact portion in the first direction to a spacing between adjacent conductive lines is greater than or equal to 7.

[0017] In some embodiments, the semiconductor device further includes a peripheral device, and the peripheral device is electrically connected to the conductive line.

[0018] On the other hand, a method for preparing a semiconductor device is provided, comprising: forming a storage stack structure, the storage stack structure comprising a stack structure and a plurality of channel structures, the plurality of channel structures penetrating the stack structure along the stacking direction of the stack structure, wherein the channel structure comprises a channel portion. A plurality of spaced channel contact portions are formed on a surface of one side of the stack structure along the stacking direction. The plurality of channel contact portions are respectively in contact with the channel portions of the plurality of channel structures, wherein the width of the channel contact portion in the first direction is greater than the width in the second direction, the first direction intersects with the stacking direction, the first direction intersects with the second direction, and the second direction intersects with the stacking direction.

[0019] In some embodiments, a plurality of spaced-apart channel contacts are formed on a side surface of the stacked structure along a stacking direction, comprising: forming a first insulating layer on a side surface of the stacked structure along the stacking direction. Forming a plurality of spaced-apart first openings on the first insulating layer, wherein the first openings expose the channel portion. The width of the first opening in the first direction is greater than the width of the first opening in the second direction. The channel contact is formed in the first opening.

[0020] In some embodiments, the method for preparing a semiconductor device further includes: forming a second insulating layer on a surface of a side of the plurality of trench contacts away from the stacked structure. Forming a plurality of connection holes on the second insulating layer, wherein the connection holes expose the trench contacts. The cross-sectional area of ​​the connection holes is smaller than the cross-sectional area of ​​the trench contacts on a reference plane, wherein the reference plane is perpendicular to the stacking direction. Forming a connection portion in the connection hole.

[0021] In some embodiments, after forming the connection portion in the connection hole, the method for preparing the semiconductor device further includes: forming a third insulating layer on the second insulating layer, forming a plurality of strip grooves on the third insulating layer, the strip grooves extending along the second direction, and one strip groove exposing at least one connection portion, and forming a conductive line in the strip groove.

[0022] In another aspect, a storage system is provided, comprising: the semiconductor device as described above and a controller. The controller is coupled to the semiconductor device to control the semiconductor device to store data.

[0023] On the other hand, an electronic device is provided, comprising the storage system as described above.

[0024] It can be understood that the beneficial effects that can be achieved by the semiconductor structure preparation method, three-dimensional memory, storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the products involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0026] Figure 1 A structural block diagram of an electronic device provided for some embodiments of the present disclosure;

[0027] Figure 2 A schematic diagram of a three-dimensional structure of a three-dimensional memory provided in some embodiments of the present disclosure;

[0028] Figure 3 A cross-sectional view of a three-dimensional memory provided for some embodiments of the present disclosure;

[0029] Figure 4 for Figure 2 A cross-sectional view of a memory cell string along section line AA' in the memory;

[0030] Figure 5 for Figure 4 Equivalent circuit diagram of the storage cell string in FIG.

[0031] Fig. 6A A top view of a semiconductor device in one embodiment provided for the present disclosure;

[0032] Figure 6B A top view of a semiconductor device in another embodiment provided by the present disclosure;

[0033] Figure 6C A top view of a semiconductor device in yet another embodiment provided for the present disclosure;

[0034] Figure 7 A top view of a trench contact in one embodiment provided for the present disclosure;

[0035] Figure 8 A schematic diagram of the structure of a semiconductor device provided in some embodiments of the present disclosure;

[0036] Fig. 9 A top view of a channel contact portion provided for some embodiments of the present disclosure;

[0037] Fig.10 A top view comparison diagram of a channel contact portion provided in some embodiments of the present disclosure and a channel contact portion in another embodiment;

[0038] Fig.11A A top view of a semiconductor device provided for some embodiments of the present disclosure;

[0039] Fig. 11B A top view of another semiconductor device provided for some embodiments of the present disclosure;

[0040] Fig. 12A A flow chart of a method for preparing a semiconductor device provided for some embodiments of the present disclosure;

[0041] Fig. 12B A flow chart of another method for preparing a semiconductor device provided for some embodiments of the present disclosure;

[0042] Fig.13 A flow chart of another method for preparing a semiconductor device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0044] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0045] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0046] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0047] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0048] Figure 1 A structural block diagram of an electronic device 9000 provided for some embodiments of the present disclosure. The electronic device 9000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein.

[0049] like Figure 1As shown, the electronic device 9000 may include a storage system 910 and a host 920. The storage system 910 may be integrated into various types of storage devices, such as a memory card. The memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital MemorZ Card (SD) card, and a Universal Flash Storage (UFS). In other words, the storage system 910 may be applied to and packaged in different types of electronic products.

[0050] The host 920 may include a processor of the electronic device 9000, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 920 may be configured to send data to the memory 911 or receive data from the memory 911.

[0051] In some embodiments, the storage system 910 may have one or more memories 911 and a controller 912. For example, the controller 912 may be configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment SSD or eMMC, which is used for data storage of mobile devices such as smart phones, tablets, and laptops, as well as enterprise storage arrays. Alternatively, in some examples, the controller 912 is coupled to the memory 911 and the host 920, and is configured to control the data in the memory 911, and can communicate with an external device (such as a host).

[0052] The number of memories 911 in the storage system 910 may be one or more. Figure 1911 as an example. The controller 912 can manage the data stored in each memory 911 and communicate with the host 920. The controller 912 can be configured to control the operation of each memory 911, such as read, write and refresh operations. The controller 912 can also be configured to manage various functions about the data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, the controller 912 is also configured to determine the maximum memory capacity that the computer system can use, the number of memory banks (memorZ bank), the memory type and speed, the memory granule data depth and data width, and other important parameters. Any other suitable function can also be performed by the controller 912. The controller 912 can communicate with an external device (e.g., the host 920) according to a specific communication protocol. For example, the controller 912 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, FireWire protocol, etc.

[0053] Figure 2 A schematic diagram of a three-dimensional structure of a three-dimensional memory provided in some embodiments of the present disclosure, Figure 3 A cross-sectional view of a three-dimensional memory provided for some embodiments of the present disclosure.

[0054] See also Figure 2 and Figure 3 The memory 911 may include a memory stack structure 12, a source layer SL coupled to the memory stack structure 12, and a peripheral device 13 coupled to the memory stack structure 12. The peripheral device 13 may be disposed on a side of the memory stack structure 12 away from the source layer SL.

[0055] The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region, and the doped region is doped with a p-type dopant. The source layer SL may also include a non-doped region.

[0056] The memory stack structure 12 may include memory cell transistor strings (referred to herein as “memory cell strings”, such as NAND memory cell strings) 400 arranged in an array. The source layer SL may be coupled to source terminals of the plurality of memory cell strings 400 .

[0057] Figure 4 for Figure 2 A cross-sectional view of a memory cell string in the memory along the section line AA', Figure 5 for Figure 4 Equivalent circuit diagram of the storage cell string in .

[0058] See also Figure 4 and Figure 5 , the memory cell string 400 may include a channel structure 122 and a plurality of gate lines G, and the plurality of gate lines G may be disposed around the channel structure 122 .

[0059] For example, the channel structure 122 may include a support portion 1226 , and a channel layer 1222 , a tunneling layer 1225 , a charge trapping layer 1224 , and a charge blocking layer 1221 sequentially disposed on the periphery of the support portion 1226 .

[0060] In some examples, the channel structure 122 may further include a channel portion 1223 , wherein the channel portion 1223 is connected between the channel layer 1222 and the channel contact 1331 .

[0061] The memory cell string 400 may include a plurality of transistors T, for example Figure 5 T1-T6 in the figure, wherein one transistor T can be set as a memory cell, and these transistors T are connected together to form a memory cell string.

[0062] One transistor T (for example, each transistor T) may be formed by one gate line G and a portion of the channel structure 122 surrounded by the gate line G. The gate line G is configured to control the conduction state of the transistor.

[0063] It should be noted that Figure 2 to Figure 5 The number of transistors in the embodiment is only illustrative, and the memory cell string of the three-dimensional memory provided in the embodiment of the present disclosure may also include other numbers of transistors, such as 4, 16, 32, 64. In the embodiment of the present disclosure, the number of transistors in the memory cell string is not limited.

[0064] In some examples, along the third direction Z, the gate line located at the bottom of the multiple gate lines G (for example, the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source selection gate SGS, and the source selection gate SGS is configured to control the conduction state of the transistor T6, thereby controlling the conduction state of the source end channel in the memory cell string 400. The gate line located at the top of the multiple gate lines G (for example, the gate line farthest from the source layer SL among the multiple gate lines G) is constructed as a drain selection gate SGD, and the drain selection gate SGD is configured to control the conduction state of the transistor T1, thereby controlling the conduction state of the drain end channel in the memory cell string 400. The gate line located in the middle of the multiple gate lines G can be constructed as a plurality of word lines WL, for example, including word line WL0, word line WL1, word line WL2, and word line WL3. By writing different voltages on the word lines WL, data writing, reading, and erasing of each memory cell (for example, transistor T) in the memory cell string 400 can be completed.

[0065] In some other examples, some gate lines located at the bottom among the plurality of gate lines G (eg, the gate line closest to the source layer SL and its adjacent gate lines) may be constructed as the source select gate SGS.

[0066] Continue to see Figure 2 and Figure 3 In some embodiments, the memory stack structure 12 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include a drain terminal of the memory cell string 400, and the drain terminal may be coupled to a semiconductor channel of each transistor T in at least one memory cell string 400.

[0067] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by the first interlayer insulating layers 292, the contacts including, for example, a bit line contact BL-CNT and a drain select gate contact SGD-CNT. The bit line contact BL-CNT is coupled to the bit line BL, and for example, the bit line contact BL-CNT may include a connection portion 160 and a channel contact portion 1331.

[0068] The drain selection gate contact SGD-CNT is coupled to the drain selection gate SGD. The array interconnect layer 290 may further include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of connection lines, for example, the plurality of connection lines may include a bit line BL, and a word line connection line WL-CL coupled to the word line WL. The material of the first interconnect conductor layer 291 and the contact may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating material, or other suitable materials.

[0069] The peripheral device 13 may include a peripheral circuit. The peripheral circuit is configured to control and sense the array device. The peripheral circuit may be any suitable digital, analog, and / or mixed signal control and sensing circuit for supporting the operation (or work) of the array device, including but not limited to a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor). The peripheral circuit may also include any other circuit compatible with an advanced logic process, including a logic circuit (e.g., a processor and a programmable logic device (PLD) or a storage circuit (e.g., a static random access memory (SRAM)).

[0070] In some embodiments, the peripheral device 13 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuit may include the transistor 120.

[0071] The material of the substrate 110 may be single crystal silicon, or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0072] The peripheral interconnection layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnection layer 130. The peripheral interconnection layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled through contacts. The material of the second interconnect conductor layer 132 and the contact may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0073] The peripheral interconnect layer 130 can be coupled to the array interconnect layer 290, so that the storage stack structure 12 and the peripheral device 13 can be coupled. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuit in the peripheral device 13 can be coupled to the storage cell string in the semiconductor device 10 to achieve the transmission of electrical signals between the peripheral circuit and the storage cell string. In some possible implementations, a bonding interface 500 can be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, and the peripheral interconnect layer 130 and the array interconnect layer 290 can be bonded and coupled to each other through the bonding interface 500.

[0074] Fig. 6A A top view of a semiconductor device 10 in one embodiment provided for the present disclosure; Figure 6B A top view of a semiconductor device 10 in another embodiment provided for the present disclosure; Figure 6C A top view of a semiconductor device 10 in yet another embodiment provided for the present disclosure; Figure 7 A top view of a trench contact 1330 in one embodiment provided for the present disclosure.

[0075] See also Fig. 6A In one embodiment, the channel contact portion 1330 is disposed in the channel portion 1223 (eg Figure 3 ), the connection portion 160 is disposed on the channel contact portion 1330, and the bit line BL is disposed on the connection portion 160. Figure 7 In one embodiment, the width of the channel contact portion 1330 in the first direction X and the width of the channel contact portion 1330 in the second direction Y are both H1.

[0076] Please continue reading Fig. 6ADuring the preparation of the semiconductor device 10, it is necessary to ensure that the channel contact portion 1330 is in precise contact with the channel portion 1223, the connection portion 160 is in precise contact with the channel contact portion 1330, and the bit line BL is in precise contact with the connection portion 160, so as to ensure the stability of the semiconductor device 10. However, the stress generated by the process accumulation may cause an offset between the two adjacent film layers in the stacking direction, thereby causing an alignment deviation. For example, the channel contact portion 1330 and the channel portion 1223 may be offset due to stress, resulting in a deviation between part of the channel contact portion 1330 and the channel portion 1223, thereby affecting the electrical connection effect between the two. Similarly, refer to Figure 6B There may be a deviation between the connection portion 160 and the channel contact portion 1330 due to stress generated by process accumulation. There may also be a deviation between the bit line BL and the connection portion 160 due to stress generated by process accumulation.

[0077] In one embodiment, in order to improve the deviation between the channel contact 1330 and the channel portion 1223, the position of the channel contact 1330 may be adjusted when the channel contact 1330 is manufactured, so as to reduce the deviation between the channel contact 1330 and the channel portion 1223. Therefore, in the process of manufacturing the channel contact 1330, the mask required for manufacturing the channel contact 1330 needs to be modified.

[0078] However, in the subsequent process of preparing the connecting portion 160, SADP (Self-aligned Double Patterning) technology will be used. At this time, the position of the connecting portion 160 will change with the change of the position of the channel contact portion 1330. Therefore, in the process of preparing the connecting portion 160, it is necessary to modify the mask required for preparing the connecting portion 160.

[0079] Similarly, in order to ensure accurate contact between the bit line BL and the connection portion 160 , it is also necessary to modify the mask required for preparing the bit line BL.

[0080] In summary, in one embodiment, in order to ensure the stability of the semiconductor device 10, it is necessary to modify the mask required for preparing the channel contact portion 1330, the mask required for preparing the connecting portion 160, and the mask required for preparing the bit line BL, which makes the preparation process of the semiconductor device 10 more complicated.

[0081] See also Figure 6C In the process of preparing the bit line BL, since the width of the bit line BL is small, after modifying the mask required for preparing the bit line BL, the bit line BL is easily broken.

[0082] Based on this, an embodiment of the present disclosure provides a semiconductor device 10 .

[0083] Figure 8 A schematic diagram of the structure of a semiconductor device 10 provided in some embodiments of the present disclosure; Fig. 9 A top view of a channel contact portion 1331 provided in some embodiments of the present disclosure.

[0084] See also Figure 8 and Fig. 9 , the semiconductor device 10 provided in some embodiments of the present disclosure includes: a storage stack structure 12 and a channel contact portion 1331. The storage stack structure 12 includes a stack structure 121 and a plurality of channel structures 122, wherein the plurality of channel structures 122 penetrate the stack structure 121 along the stacking direction Z of the stack structure 121, wherein the channel structure 122 includes a channel portion 1223. A plurality of spaced-apart channel contacts 1331 are disposed on a side surface of the stack structure 121 along the stacking direction, and the channel contact portion 1331 contacts the channel portion 1223. The width H2 of the channel contact portion 1331 in the first direction X is greater than the width H3 in the second direction Y. The first direction X intersects with the stacking direction Z, the first direction X intersects with the second direction Y, and the second direction Y intersects with the stacking direction Z.

[0085] In the embodiment of the present disclosure, a plurality of spaced-apart channel contacts 1331 are disposed on one side surface of the stacked structure 121 of the semiconductor device 10 , so that the plurality of channel contacts 1331 can be insulated from each other.

[0086] See also Fig. 9 The width H2 of the plurality of channel contacts 1331 in the first direction X is greater than the width H3 thereof in the second direction Y, thereby increasing the window area of ​​the channel contacts 1331. When the channel portions 1223 of the plurality of channel structures 122 are formed on the surface away from the substrate 11, the accuracy of the alignment and contact between the channel contacts 1331 and the channel portions 1223 can be improved.

[0087] In addition, when preparing the channel contact portion 1331, the width H2 of the channel contact portion 1331 in the first direction X can be determined according to the position of the channel portion 1223 and the position of the connecting portion 160 to be subsequently connected. In this way, the enlarged channel contact portion 1331 can contact both the corresponding channel portion 1223 and the corresponding connecting portion 160, thereby reducing the offset between the channel contact portion 1331 and the channel portion 1223, and the offset between the channel contact portion 1331 and the connecting portion 160, thereby improving the reliability of the electrical connection between the channel contact portion 1331 and the channel portion 1223, and the reliability of the electrical connection between the channel contact portion 1331 and the connecting portion 160, thereby improving the stability of the semiconductor device 10.

[0088] Please continue reading Fig. 9 In some embodiments, a ratio of a width H2 of the channel contact portion 1331 in the first direction X to a width H3 of the channel contact portion 1331 in the second direction Y is greater than or equal to 1.1 and less than or equal to 1.5.

[0089] In some examples, H2 / H3 is greater than or equal to 1.1, and therefore, H2≥1.1×H3, so that H2 can be prevented from being too small, for example, H2<1.1×H3. Exemplarily, if H2 is too small, for example, H2<0.5×H3, the window area of ​​the channel contact 1331 in the first direction X is too small, and the channel portion 1223 or the connection portion 160 is difficult to align with the channel contact 1331. Therefore, by making H2 / H3 greater than or equal to 1.1, the window area of ​​the channel contact 1331 can be increased by increasing the value of H2, thereby improving the accuracy of alignment of the channel contact 1331 with the channel portion 1223 or the connection portion 160 in the adjacent film layer, thereby improving the reliability of the electrical connection between the channel contact 1331 and the channel portion 1223 or the connection portion 160.

[0090] In some other examples, H2 / H3 is less than or equal to 1.5, and therefore, H2≤1.5×H3, so that H2 can be prevented from being too large, for example, H2>1.5×H3. Exemplarily, if H2 is too large, for example, H2>2×H3, two adjacent channel contacts 1331 in the first direction X are caused to contact. Therefore, by making H2 / H3 less than or equal to 1.5, it can be prevented that the width H2 of the channel contact 1331 in the first direction X is excessively increased, resulting in the contact of two adjacent channel contacts 1331 in the first direction X, which affects the stability of the semiconductor device 10.

[0091] Please continue reading Fig. 9 In some embodiments, the cross-section of the channel contact portion 1331 on the reference plane is a straight-sided ellipse, wherein the reference plane is perpendicular to the stacking direction Z.

[0092] For example, the channel contact portion 1331 is projected onto the reference plane along the stacking direction Z, and the projected shape of the channel contact portion 1331 is a straight-sided ellipse.

[0093] The straight-sided ellipse means that the projection shape of the channel contact portion 1331 is similar to an ellipse, but is different from an ellipse. For example, in the embodiment of the present disclosure, the cross section of the channel contact portion 1331 on the reference plane includes two first side edges 1332 arranged opposite to each other in the first direction X, and two second side edges 1333 arranged opposite to each other in the second direction Y, wherein the two first side edges 1332 are curves, and one first side edge 1332 protrudes in a direction away from the other first side edge 1332; the two second side edges 1333 are straight lines extending along the second direction Y, and the two second side edges 1333 are parallel.

[0094] In some other embodiments, the projection shape of the channel contact portion 1331 on the reference plane may also be an ellipse, a rectangle, a diamond, etc., which is not limited in this embodiment.

[0095] Fig.10 A top view comparison diagram of a channel contact portion 1331 provided in some embodiments of the present disclosure and a channel contact portion 1330 in another embodiment.

[0096] See also Fig.10 For the convenience of analysis and introduction, in this embodiment, the first channel contact portion represents the channel contact portion 1330 in another embodiment, and the second channel contact portion represents the channel contact portion 1331 of the present disclosure.

[0097] For example, the shape of the first channel contact 1330 is changed by extending the width H1 of the first channel contact 1330 in the first direction X. For example, when the width H1 of the first channel contact 1330 in the first direction X is extended to the left or right by 2x to obtain H2, the second channel contact 1331 will be formed. Point a is used as the geometric center of the first channel contact 1330, and point A is used as the geometric center of the second channel contact 1331. When the shape of the first channel contact 1330 is changed to the second channel contact 1331, the geometric center point a will follow the change in shape and shift to the left or right by x to point A.

[0098] The above-mentioned arrangement forms a second channel contact portion 1331 with a larger window area by changing the width of the first channel contact portion 1330 in the first direction X, thereby providing a larger contact window for the alignment and contact between the adjacent channel portion 1223 or the connecting portion 160 and the second channel contact portion 1331, thereby improving the fault tolerance rate and enhancing the accuracy of the alignment and coverage between the second channel contact portion 1331 and the channel portion 1223 or the connecting portion 160 of the adjacent film layer.

[0099] also, Fig.11A A top view of a semiconductor device 10 provided in some embodiments of the present disclosure is shown. Fig. 11BA top view of another semiconductor device 10 provided for some embodiments of the present disclosure.

[0100] Please continue reading Fig. 6A In one embodiment, in the first direction X, when the first channel contact portion 1330 and the connecting portion 160 are aligned and covered, the connecting portion 160 cannot accurately cover the geometric center position of the first channel contact portion 1330, but is close to any side of the first channel contact portion 1330 in the first direction X. In addition, in the second direction Y, every two rows of connecting portions 160 alternately approach different sides of the first channel contact portion 1330 in the first direction X.

[0101] Therefore, see Fig.10 In the embodiment of the present disclosure, the width H1 of the first channel contact portion 1330 in the first direction X is extended along the side close to the connecting portion 160, thereby obtaining a second channel contact portion 1331 with a width extending from H1 to H2 in the first direction X. In this way, sufficient tolerance space is provided between the connecting portion 160 and the edge of the side close to the connecting portion 160.

[0102] Since in the above embodiment, every two rows of connecting portions 160 are alternately close to different sides of the channel contact portion 1330 in the first direction X, in the embodiment of the present disclosure, every two rows of first channel contact portions 1330 need to alternately extend along the side close to the connecting portion 160 by a width H1 in the first direction X, so as to obtain a top view of the semiconductor device 10 provided with the second channel contact portion 1331 as shown in FIG. Fig.11A After the width H1 of the first channel contact portion 1330 in the first direction X is changed to obtain the second channel contact portion 1331, refer to Fig. 11B Even if the connection portion 160 is aligned and covered with the second channel contact portion 1331, there is a shift in the position of a portion of the second channel contact portion 1331, but the shifted second channel contact portion 1331 can still contact the connection portion 160 to ensure the stability of the electrical connection.

[0103] In summary, the embodiment of the present disclosure selects the direction of the extension width of the first channel contact portion 1330 in the first direction X according to the position where the connecting portion 160 covers the first channel contact portion 1330, so as to increase the distance between the connecting portion 160 and the edge of one side to which it is close, thereby increasing the fault tolerance space of the connecting portion 160 and improving the accuracy of the alignment and coverage of the second channel contact portion 1331 and the connecting portion 160.

[0104] In some embodiments, the channel contact portion 1331 includes two cylindrical surfaces disposed opposite to each other in the first direction X and two first planes disposed opposite to each other in the second direction Y. One cylindrical surface protrudes in a direction away from the other cylindrical surface.

[0105] In the embodiment of the present disclosure, the shape of the channel contact portion 1331 is changed by increasing the width H2 of the channel contact portion 1331 in the first direction X, so that the channel contact portion 1331 has two cylindrical surfaces opposite to each other in the first direction X and two first planes opposite to each other in the second direction Y.

[0106] Please refer to the corresponding Fig. 9 After the shape of the channel contact 1331 is changed, the projections of the two cylinders arranged opposite to each other in the first direction X on the reference plane will appear as arcs, that is, the projections corresponding to the two cylinders are the two first sides 1332. The projections of the two first planes arranged opposite to each other in the second direction Y on the reference plane will appear as straight lines, that is, the projections corresponding to the two first planes are the two second sides 1333.

[0107] In the embodiment of the present disclosure, the change in the shape of the channel contact portion 1331 can achieve a change in the projection shape of the channel contact portion 1331 on the reference plane, thereby increasing the projection area of ​​the channel contact portion 1331 on the reference plane. That is, the window area of ​​the channel contact portion 1331 connecting with the channel portion 1223 or the connecting portion 160 of the adjacent film layer is increased, thereby improving the error tolerance of the alignment process of the channel contact portion 1331 with the channel portion 1223 or the connecting portion 160 of the adjacent film layer, and improving the accuracy of the alignment contact.

[0108] Please continue reading Fig. 9 In some embodiments, the plurality of channel contacts 1331 are arranged in a plurality of rows, wherein the plurality of channel contacts 1331 in a row of channel contacts 1331 are sequentially arranged along the first direction X, and the plurality of rows of channel contacts 1331 are sequentially arranged along the second direction Y. The channel contacts 1331 in two adjacent rows of channel contacts 1331 are staggered in the second direction Y.

[0109] For example, the arrangement of the plurality of channel contacts 1331 should not only avoid contact between two adjacent channel contacts 1331 in the first direction X, but also control the spacing between two adjacent channel contacts 1331 in the second direction Y to avoid contact between two adjacent channel contacts 1331 in the second direction Y, thereby affecting the stability of the semiconductor device 10. In the embodiment of the present disclosure, by arranging the channel contacts 1331 in two adjacent rows of channel contacts 1331 in the second direction Y in a staggered manner, contact between two adjacent channel contacts 1331 in the second direction Y can be avoided, and at the same time, the distribution density of the plurality of channel contacts 1331 inside the semiconductor device 10 can be ensured. That is, in a film layer of the same size, such an arrangement is conducive to increasing the number of channel contacts 1331 and ensuring the distribution density of the channel contacts 1331.

[0110] Please continue reading Figure 8In some embodiments, a cross-sectional area of ​​the channel portion 1223 on a reference plane is smaller than a cross-sectional area of ​​the channel contact portion 1331 on a reference plane, wherein the reference plane is perpendicular to the stacking direction Z.

[0111] For example, the orthographic projection of the channel portion 1223 on the reference plane is located within the range of the orthographic projection of the channel contact portion 1331 on the reference plane.

[0112] With such arrangement, when the channel contact portion 1331 contacts the channel portion 1223 , the contact surface of the channel contact portion 1331 is larger than the contact surface of the channel portion 1223 , which is beneficial for achieving precise coverage of the channel portion 1223 by the channel contact portion 1331 and improving the alignment accuracy between the channel contact portion 1331 and the channel portion 1223 .

[0113] Please continue reading Figure 8 In some embodiments, the semiconductor device 10 further includes: a plurality of connecting portions 160. The plurality of connecting portions 160 are disposed on a surface of the channel contact portion 1331 that is away from the stacked structure 121, one connecting portion 160 is in contact with one channel contact portion 1331, and the cross-sectional area of ​​the connecting portion 160 on the reference plane is smaller than the cross-sectional area of ​​the channel contact portion 1331 on the reference plane.

[0114] For example, the orthographic projection of the connection portion 160 on the reference plane is located within the range of the orthographic projection of the channel contact portion 1331 on the reference plane.

[0115] With such a configuration, when the connecting portion 160 contacts the channel contact portion 1331, the contact surface of the channel contact portion 1331 is larger than the contact surface of the connecting portion 160, which is conducive to setting the connecting portion 160 on the channel contact portion 1331, improving the alignment accuracy between the connecting portion 160 and the channel contact portion 1331, and further improving the electrical connection effect between the connecting portion 160 and the channel contact portion 1331.

[0116] Please continue reading Figure 8 In some embodiments, the semiconductor device 10 further includes: a plurality of conductive wires 190 . The plurality of conductive wires 190 are disposed on a side of the plurality of connection portions 160 away from the channel contact portion 1331 , the conductive wires 190 extend along the second direction, and one conductive wire 190 contacts at least one connection portion 160 .

[0117] For example, the plurality of conductive wires 190 can be used as a plurality of bit lines BL in the semiconductor device 10. In this way, the conductive wires 190 can be electrically connected to the connection portion 160, and then the entire semiconductor device 10 can be electrically connected to other devices through the connection between the conductive wires 190 and the peripheral circuit.

[0118] In some other examples, one conductive line may also be connected to a plurality of channel contacts 1331 in a column of channel contacts 1331 .

[0119] In some other examples, a column of channel contacts 1331 may contact a plurality of conductive lines 190 .

[0120] In some embodiments, a ratio of a width H2 of the channel contact portion 1331 in the first direction X to a spacing between adjacent conductive lines 190 is greater than or equal to 7.

[0121] In the embodiment of the present disclosure, the width H2 of the channel contact portion 1331 in the first direction X can be enlarged according to the position of the channel contact portion 1331 and the offset of the subsequently stacked connecting portion 160, so as to ensure that the channel contact portion 1331 is aligned with the channel portion 1223 and the connecting portion 160 at the same time, thereby simplifying the subsequent position adjustment of the connecting portion 160, and further omitting the position adjustment of the conductive wire 190 that is aligned with the connecting portion 160, thereby effectively reducing the process difficulty, shortening the production cycle and reducing the production cost.

[0122] By enlarging the width H2 of the channel contact portion 1331 in the first direction X, the shape of the channel contact portion 1331 can be changed, thereby increasing the ratio of the width H2 of the channel contact portion 1331 in the first direction X to the spacing between adjacent conductive lines 190, so that the ratio of the width H2 of the channel contact portion 1331 in the first direction X to the spacing between adjacent conductive lines 190 is greater than or equal to 7.

[0123] Based on the semiconductor device 10 provided in some of the above embodiments, the embodiments of the present disclosure further provide a method for preparing the semiconductor device 10 . The method for preparing the semiconductor device 10 can be used to prepare the above-mentioned semiconductor device 10 .

[0124] Fig. 12A A flow chart of a method for manufacturing a semiconductor device 10 provided in some embodiments of the present disclosure; Fig. 12B A flow chart of another method for preparing a semiconductor device 10 provided for some embodiments of the present disclosure.

[0125] See also Fig. 12A The method for preparing the semiconductor device 10 includes the following steps S1 to S2.

[0126] S1. Forming a storage stack structure, the storage stack structure comprising a stack structure and a plurality of channel structures, the plurality of channel structures penetrating the stack structure along a stacking direction of the stack structure, wherein the channel structure comprises a channel portion.

[0127] Please continue reading Figure 8, the storage stack structure 12 can be formed in the substrate 11. Among them, the substrate 11 can be a single crystal silicon (Si) substrate, a single crystal germanium (Ge) substrate, a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate. The material of the substrate 11 can also be a compound semiconductor. For example, the substrate 11 can be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate or a silicon carbide (SiC) substrate. The substrate 11 of the present disclosure can also be prepared using other semiconductor materials commonly used in the art.

[0128] In some embodiments, the plurality of channel structures 122 of the memory stack structure 12 are arranged in rows along the first direction X and in columns along the second direction Y. The plurality of channel portions 1223 at the top of the plurality of channel structures 122 are arranged in rows along the first direction X and in columns along the second direction Y.

[0129] S11, forming an initial stacked structure on a substrate, wherein the initial stacked structure may include a plurality of initial gate dielectric layers and gate replacement layers alternately stacked along a stacking direction Z.

[0130] Here, “alternating stacking” means that after an initial gate dielectric layer 1211 is formed on the substrate 11, a gate replacement layer is formed on the initial gate dielectric layer 1211, and then an initial gate dielectric layer 1211 is formed on the gate replacement layer, thereby alternately stacking.

[0131] In the initial stacked structure, the initial gate dielectric layer 1211 and the gate replacement layer can be formed by a thin film deposition process including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, which is not limited in the present disclosure.

[0132] The thickness of the initial gate dielectric layer 1211 may be the same or different, the thickness of the multiple gate replacement layers may be the same or different, and the thickness of the initial gate dielectric layer 1211 and the gate replacement layer may be set according to specific process requirements. In practical applications, the gate replacement layer may be removed in a subsequent process and replaced by a conductive material to form a gate layer 1212, i.e., a word line WL (e.g., Figure 3 shown).

[0133] For example, the material of the initial gate dielectric layer 1211 may be silicon oxide, and the material of the gate replacement layer may be silicon nitride.

[0134] S12, etching the initial stacked structure to form a channel hole that penetrates the initial stacked structure in the stacking direction Z and extends to the substrate.

[0135] For example, in step S12 , the channel hole may be formed by a dry or wet etching process, and the formed channel hole penetrates the substrate 11 and exposes a portion of the substrate 11 in the stacking direction Z. In other examples, the communication hole may extend into the substrate 11 .

[0136] S13, forming a channel structure in the channel hole. The channel structure may include a charge blocking layer, a charge trapping layer, a tunneling layer, a channel layer and a supporting portion. The charge blocking layer, the charge trapping layer and the tunneling layer may be combined to form a functional layer.

[0137] In step S13, a thin film deposition process such as CVD, PVD, ALD or any combination thereof may be used to sequentially form a functional layer 1220 and a channel layer 1222 on the sidewall of the channel hole. The charge blocking layer 1221 is used to block the outflow of stored charges in the charge capture layer 1224, and the charge capture layer 1224 may pass through the tunneling layer 1225 through the tunneling effect under the action of voltage to achieve writing and erasing of memory data. For example, the material of the charge blocking layer 1221 may be silicon oxide, the material of the charge capture layer 1224 may be nitride, and the material of the tunneling layer 1225 may be oxide. The material of the support portion 1226 may include one or more of an oxide material (e.g., silicon oxide), a nitride material (e.g., silicon nitride), and a nitride oxide (e.g., silicon oxynitride). As an option, a chemical mechanical polishing (CMP) may be used to planarize the top surface of the support portion 1226 in the channel hole. The top surface of the channel hole inner support portion 1226 refers to the surface of the channel hole inner support portion 1226 facing away from the substrate 11 .

[0138] In this embodiment, the channel structure 122 further includes a channel portion 1223 , wherein the channel portion 1223 is located at an end of the channel structure 122 away from the substrate 11 , and the channel portion 1223 is electrically connected to the channel layer 1222 .

[0139] S14, replacing the gate replacement layer with a gate line layer.

[0140] The gate replacement layer in the initial stacked structure is removed to form a gate gap, and then a conductive material is filled in the gate gap to form a gate layer 1212. At this time, multiple gate layers 1212 and multiple initial gate dielectric layers 1211 are alternately stacked to form a stacked structure 121.

[0141] After completing the above step S1, step S2 may be performed.

[0142] S2. Form a plurality of spaced channel contact portions on a surface of one side of the stacking structure along the stacking direction. The plurality of channel contact portions are in contact with the channel portions of the plurality of channel structures, respectively, wherein the width of the channel contact portion in the first direction is greater than the width in the second direction, the first direction intersects with the stacking direction, the first direction intersects with the second direction, and the second direction intersects with the stacking direction.

[0143] Please continue reading Figure 8 In step S2 , a plurality of channel contact portions 1331 are formed on a side surface of the stacked structure 121 , each of which is spaced apart and has a width H2 in the first direction X greater than a width H3 in the second direction Y.

[0144] In some examples, each channel contact 1331 contacts one channel portion 1223 .

[0145] As an example, the channel contact 1331 includes a first conductive material. For example, the first conductive material may include metal tungsten and / or copper.

[0146] In the embodiment of the present disclosure, the window area of ​​the channel contact 1331 can be effectively increased by increasing the width H2 of the channel contact 1331 in the first direction X. Therefore, when the channel contact 1331 is formed on a surface of one side of the plurality of channel structures 122 provided with the channel portion 1223, the channel contact 1331 formed in the embodiment of the present disclosure has a larger contact window, which is conducive to improving the accuracy of the alignment and contact between the channel contact 1331 and the channel portion 1223, thereby improving the reliability of the electrical connection between the channel contact 1331 and the channel portion 1223.

[0147] In some embodiments, see Fig. 12B The above step S2 may further include the following steps S20 to S22.

[0148] S20, forming a first insulating layer on a surface of one side of the stacked structure along a stacking direction.

[0149] For example, the first insulating layer 170 may be formed on a side of the stacked structure 121 away from the substrate 11 by using a thin film deposition process such as CVD, PVD, ALD or any combination thereof.

[0150] For example, the material of the first insulating layer 170 may include one or more of a silicon nitride layer, a silicon oxynitride layer, an aluminum oxide layer, and a zirconium oxide layer.

[0151] S21. Form a plurality of first openings spaced apart from each other on the first insulating layer, wherein the first openings expose the channel portion; wherein a width of the first openings in the first direction is greater than a width of the first openings in the second direction.

[0152] For example, in step S21, a first photoresist layer is formed on a side of the first insulating layer 170 away from the substrate 11, and the first photoresist layer is exposed and developed to pattern the first photoresist layer. The patterned first photoresist layer may be a first mask layer.

[0153] The first insulating layer 170 is etched based on the first mask layer to form a plurality of first openings. For example, the first insulating layer 170 can be etched by dry etching to form a plurality of first openings. The depth of the first opening is not less than the thickness of the first insulating layer 170, thereby exposing the channel portion 1223, so that the filler in the subsequent first opening can contact and be electrically connected to the channel portion 1223.

[0154] The width H2 of each first opening in the first direction X is greater than the width H3 of the first opening in the second direction Y. The plurality of first openings are arranged in a row along the first direction X, and the plurality of rows of first openings are arranged in the first direction Y at intervals.

[0155] S22 , forming a channel contact portion in the first opening.

[0156] A first conductive material is filled in the plurality of first openings to form a plurality of channel contacts 1331. For example, the filled first conductive material may include metal tungsten and copper.

[0157] In the embodiment of the present disclosure, the width H2 of the formed channel contact portion 1331 in the first direction is greater than its width H3 in the second direction, which can increase the window area of ​​the channel contact portion 1331, thereby providing a larger docking window for the adjacent channel portion 1223 or the connecting portion 160, thereby improving the accuracy of alignment and coverage between the channel contact portion 1331 and the channel portion 1223, and between the channel contact portion 1331 and the connecting portion 160.

[0158] In some embodiments, step S22 may include the following steps S221 to S222.

[0159] S221 , depositing a first conductive material, where the first conductive material fills the first opening and covers the first insulating layer.

[0160] For example, in step S221 , the first conductive material may be deposited by using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0161] S222, removing the first conductive material deposited on the first insulating layer.

[0162] For example, in step S222, chemical mechanical polishing (CMP) can be used to remove the first conductive material on the first insulating layer 170. At the same time, since the first conductive material of the first opening can also be removed, the surface of the channel contact portion 1331 facing away from the channel portion 1223 can be planarized.

[0163] In the embodiment of the present disclosure, when forming the first opening, the width H2 of the first opening in the first direction X can be expanded according to the position of the channel portion 1223 and the position of the connecting portion 160 that needs to be connected subsequently, so as to achieve the expansion of the width H2 of the channel contact portion 1331 in the first direction X, so that the expanded channel contact portion 1331 can contact both the corresponding channel portion 1223 and the corresponding connecting portion 160, thereby reducing the offset between the channel contact portion 1331 and the channel portion 1223, as well as the offset between the channel contact portion 1331 and the connecting portion 160, thereby improving the reliability of the electrical connection between the channel contact portion 1331 and the channel portion 1223, as well as the reliability of the electrical connection between the channel contact portion 1331 and the connecting portion 160, thereby improving the stability of the semiconductor device 10.

[0164] Fig.13 A flowchart of another method for preparing a semiconductor device 10 is provided for some embodiments of the present disclosure.

[0165] See also Fig.13 The method for preparing the semiconductor device 10 further includes steps S3 to S5.

[0166] S3. Form a second insulating layer on the surface of the plurality of channel contacts on one side away from the stacked structure.

[0167] Please continue reading Figure 8 In step S3 , the second insulating layer 180 is located on a side of the first insulating layer 170 away from the stacked structure 121 .

[0168] In some embodiments, the second insulating layer 180 may be deposited on a side of the plurality of channel contacts 1331 away from the stacked structure 121 by using existing conventional thin film deposition processes, such as any one or more of CVD, PVD and ALD.

[0169] For example, the material of the second insulating layer 180 can be any suitable insulating material, such as oxide, nitride, etc.

[0170] The material of the second insulating layer 180 may be the same as or different from that of the first insulating layer 170 , and the thickness of the second insulating layer 180 may be the same as or different from that of the first insulating layer 170 .

[0171] S4, forming a plurality of connection holes on the second insulating layer, wherein the connection holes expose the channel contact portions, and the cross-sectional area of ​​the connection holes is smaller than the cross-sectional area of ​​the channel contact portions on a reference plane, wherein the reference plane is perpendicular to the stacking direction.

[0172] In step S4, a second photoresist layer is formed on a side of the second insulating layer 180 away from the channel contact portion 1331, and the second photoresist layer is exposed and developed to pattern the second photoresist layer. The patterned second photoresist layer can serve as a second mask layer.

[0173] The second insulating layer 180 is etched by dry etching using a second mask to obtain a plurality of spaced connection holes 161 , wherein the depth of the connection holes 161 is not less than the thickness of the second insulating layer 180 , thereby exposing the channel contact portions 1331 .

[0174] For example, the cross-sectional area of ​​the connection hole 161 is smaller than the cross-sectional area of ​​the channel contact 1331 on the reference plane, so that the cross-sectional area of ​​the connection part 160 formed subsequently based on the connection hole 161 on the reference plane is smaller than the cross-sectional area of ​​the channel contact 1331 on the reference plane. When the connection part 160 is stacked and arranged on one side of the channel contact 1331, by making the cross-sectional area of ​​the connection part 160 on the reference plane smaller than the cross-sectional area of ​​the channel contact 1331 on the reference plane, the error tolerance of the alignment between the connection part 160 and the channel contact 1331 can be improved, and the alignment accuracy between the connection part 160 and the channel contact 1331 can be increased.

[0175] S5. Forming a connection portion in the connection hole.

[0176] In step S5, the second conductive material may be filled into the connection hole 161 to form the connection portion 160 (eg, Figure 8 As shown in FIG. 1 , the filled second conductive material may include metal tungsten and copper. Then, chemical mechanical polishing may be used to remove the second conductive material protruding from the upper surface of the connecting portion 160, thereby achieving a planarization process on the surface of the connecting portion 160 away from the channel contact portion 1331, so as to facilitate subsequent operations.

[0177] In some embodiments, while the top surface of the connection portion 160 is planarized by chemical mechanical polishing, the redundant second conductive material, the first mask layer, and the second mask layer may be removed at the same time.

[0178] In some other embodiments, the first mask layer may be removed after step S222 , and the second conductive material and the second mask layer may be removed after step S5 .

[0179] Please continue reading Fig.13After forming the connection portion 160 in the connection hole 161 , the method for manufacturing the semiconductor device 10 further includes steps S6 to S8 .

[0180] S6. Form a third insulating layer on the second insulating layer.

[0181] In step S6, an existing conventional thin film deposition process, such as any one or more of CVD, PVD, and ALD, may be used to deposit a third insulating layer 171 on the side of the second insulating layer 180 away from the stacked structure 121. For example, the material of the third insulating layer 171 may be any suitable insulating material, such as oxide, nitride, etc. The material of the third insulating layer 171 may be the same as or different from that of the first insulating layer 170 and the second insulating layer 180; the thickness of the third insulating layer 171 may be the same as or different from that of the first insulating layer 170 and the second insulating layer 180.

[0182] S7. Form a plurality of strip-shaped grooves on the third insulating layer, wherein the strip-shaped grooves extend along the second direction, and each strip-shaped groove exposes at least one connecting portion.

[0183] In step S7 , a strip-shaped groove may be formed on the third insulating layer 171 by etching, and the depth of the strip-shaped groove is greater than or equal to the thickness of the third insulating layer 171 , thereby exposing the connecting portion 160 .

[0184] The strip grooves extend along the second direction Y, and a plurality of strip grooves are arranged in sequence along the first direction X.

[0185] S8. Forming conductive lines in the strip-shaped grooves.

[0186] In step S8, a third conductive material may be filled in the strip-shaped groove to form a conductive line 190. For example, the filled third conductive material may include metal tungsten and copper. As an option, chemical mechanical polishing may be used to planarize the top surface of the third conductive material, and excess third conductive material may be removed. The formed conductive line 190 contacts the connecting portion 160 and realizes electrical connection.

[0187] The conductive line 190 may be the bit line BL provided in some of the above embodiments (eg Figure 2 shown).

[0188] The semiconductor device 10 provided in some of the above embodiments may be a three-dimensional memory 911 , or may be a part of the three-dimensional memory 911 . For example, the semiconductor device 10 may be a memory stack structure 12 .

[0189] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, It is characterized in that include: A storage stack structure, the storage stack structure comprising a stack structure and a plurality of channel structures, the plurality of channel structures penetrating the stack structure along a stacking direction of the stack structure, wherein the channel structure comprises a channel portion; A plurality of spaced-apart channel contact portions are disposed on a side surface of the stacking structure along the stacking direction, and the channel contact portions are in contact with the channel portion, wherein the width of the channel contact portions in the first direction is greater than the width in the second direction, the first direction intersects with the stacking direction, the first direction intersects with the second direction, and the second direction intersects with the stacking direction.

2. The semiconductor device according to claim 1, It is characterized in that A ratio of a width of the channel contact portion in the first direction to a width of the channel contact portion in the second direction is greater than or equal to 1.1 and less than or equal to 1.

5.

3. The semiconductor device according to claim 1, It is characterized in that The cross section of the channel contact portion on a reference plane is a straight-sided ellipse, wherein the reference plane is perpendicular to the stacking direction.

4. The semiconductor device according to claim 1, It is characterized in that The channel contact portion includes two cylindrical surfaces arranged opposite to each other in the first direction and two first planes arranged opposite to each other in the second direction, wherein one cylindrical surface protrudes in a direction away from the other cylindrical surface.

5. The semiconductor device according to claim 1, It is characterized in that The plurality of channel contact portions are arranged in a plurality of rows, wherein the plurality of channel contact portions in a row of channel contact portions are sequentially arranged along a first direction, and the plurality of rows of channel contact portions are sequentially arranged along the second direction; The channel contact portions in two adjacent rows of channel contact portions are arranged alternately in the second direction.

6. The semiconductor device according to any one of claims 1 to 5, It is characterized in that An area of ​​a cross section of the channel portion on a reference plane is smaller than an area of ​​a cross section of the channel contact portion on the reference plane, wherein the reference plane is perpendicular to the stacking direction.

7. The semiconductor device according to claim 6, It is characterized in that Also includes: A plurality of connection parts are arranged on a surface of the channel contact part away from the stacked structure, one connection part contacts one channel contact part, and the cross-sectional area of ​​the connection part on the reference plane is smaller than the cross-sectional area of ​​the channel contact part on the reference plane.

8. The semiconductor device according to claim 7, It is characterized in that Also includes: A plurality of conductive lines are arranged on a side of the plurality of connection portions away from the channel contact portion, the conductive lines extend along the second direction, and one of the conductive lines contacts at least one of the connection portions.

9. The semiconductor device according to claim 8, It is characterized in that A ratio of a width of the channel contact portion in the first direction to a spacing between adjacent conductive lines is greater than or equal to 7.

10. The semiconductor device according to claim 9, It is characterized in that Also includes: The peripheral device is electrically connected to the conductive line.

11. A method for preparing a semiconductor device, It is characterized in that include: forming a storage stack structure, the storage stack structure comprising a stack structure and a plurality of channel structures, the plurality of channel structures penetrating the stack structure along a stacking direction of the stack structure, wherein the channel structure comprises a channel portion; A plurality of spaced-apart channel contacts are formed on a surface of one side of the stacking structure along the stacking direction, and the plurality of channel contacts are respectively in contact with the channel portions of the plurality of channel structures, wherein the width of the channel contact in the first direction is greater than the width in the second direction, the first direction intersects with the stacking direction, the first direction intersects with the second direction, and the second direction intersects with the stacking direction.

12. The preparation method according to claim 11, It is characterized in that The step of forming a plurality of spaced-apart channel contacts on a surface of one side of the stacked structure along the stacking direction comprises: forming a first insulating layer on a surface of one side of the stacked structure along the stacking direction; forming a plurality of first openings spaced apart from each other on the first insulating layer, wherein the first openings expose the channel portion; wherein a width of the first openings in the first direction is greater than a width of the first openings in the second direction; The channel contact is formed in the first opening.

13. The preparation method according to claim 11 or 12, It is characterized in that Also includes: forming a second insulating layer on a surface of the plurality of channel contacts facing away from the stacked structure; forming a plurality of connection holes on the second insulating layer, wherein the connection holes expose the channel contact portion; the cross-sectional area of ​​the connection holes is smaller than the cross-sectional area of ​​the channel contact portion on a reference plane, wherein the reference plane is perpendicular to the stacking direction; A connecting portion is formed in the connecting hole.

14. The preparation method according to claim 13, It is characterized in that After forming the connection portion in the connection hole, the method further comprises: forming a third insulating layer on the second insulating layer; forming a plurality of strip grooves on the third insulating layer, wherein the strip grooves extend along the second direction, and one of the strip grooves exposes at least one of the connecting portions; Conductive lines are formed in the strip-shaped grooves.

15. A storage system, It is characterized in that include: The semiconductor device according to any one of claims 1 to 10; The controller is coupled to the semiconductor device to control the semiconductor device to store data.

16. An electronic device, It is characterized in that Comprising the storage system as claimed in claim 15.

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