Storage array, preparation method thereof and electronic equipment

Abstract

The embodiment of the invention provides a storage array, a preparation method thereof and electronic equipment, and relates to the technical field of storage. The memory array includes a ferroelectric layer, a first electrode layer, a second electrode layer, and at least one functional layer. The first electrode layer and the second electrode layer are arranged on the two sides of the ferroelectric layer respectively. The at least one functional layer is embedded in the first electrode layer and / or the second electrode layer, and the at least one functional layer is in contact with the side surface of the ferroelectric layer. Wherein the thermal expansion coefficient of the functional layer is smaller than that of the ferroelectric layer. In the memory array, the functional layer with a lower coefficient of thermal expansion is arranged on the side surface of the ferroelectric layer, and the functional layer is embedded in the first electrode layer and / or the second electrode layer, so that the formation of an electric field among the first electrode layer, the ferroelectric layer and the second electrode layer is ensured, and meanwhile, pressure stress can be provided for the ferroelectric layer through the functional layer; therefore, the proportion of the crystal grains with the polarization direction parallel to the electric field direction in the ferroelectric layer is improved, and the electrical performance of the memory array is optimized.

Description

Technical Field

[0001] This application relates to the field of storage technologies, and particularly to a storage array, a preparation method thereof, and an electronic device. Background Art

[0002] A memory is a device for storing information. Usually, information is digitized and then stored using media such as electricity, magnetism, or optics. As a new type of memory, Ferroelectric Random Access Memory (FRAM) has been increasingly widely used compared to traditional Dynamic Random Access Memory (DRAM) or flash memory, etc., because it has advantages such as lower read / write voltage, low power consumption, small device size, high read / write speed, good cycling performance, radiation resistance, and non-volatility.

[0003] The non-volatile storage function of FRAM stems from the fact that its ferroelectric polarization flips under the action of an external electric field and releases enough charge to be recognized by the circuit, thus exhibiting storage states such as "0" and "1". Therefore, the storage window of FRAM, that is, the amount of charge released during polarization flipping, is a key factor determining the performance of FRAM. Summary of the Invention

[0004] Embodiments of this application provide a storage array, a preparation method thereof, and an electronic device, aiming to regulate the polarization direction of grains in the ferroelectric layer of the storage array, increase the proportion of grains in the ferroelectric layer whose polarization direction is parallel to the electric field direction, and thus optimize the electrical performance of the storage array.

[0005] To achieve the above object, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a storage array is provided. The storage array includes a ferroelectric layer, a first electrode layer, a second electrode layer, and at least one functional layer.

[0007] Among them, the first electrode layer and the second electrode layer are respectively disposed on both sides of the ferroelectric layer. At least one functional layer is embedded in the first electrode layer and / or the second electrode layer, and at least one functional layer is in contact with the side surface of the ferroelectric layer. Among them, the coefficient of thermal expansion of the functional layer is less than that of the ferroelectric layer.

[0008] In the storage array provided by the embodiments of the present application, a functional layer with a relatively low coefficient of thermal expansion is embedded in the first electrode layer and / or the second electrode layer, and the functional layer is arranged to be in contact with the side surface of the ferroelectric layer (the surface perpendicular to the electric field direction in the ferroelectric layer). During the preparation process of the storage array, especially during the annealing process of the storage array, the functional layer with a relatively small coefficient of thermal expansion can provide a relatively large compressive stress perpendicular to the side surface of the ferroelectric layer (i.e., parallel to the electric field direction) to the side surface of the ferroelectric layer. During the crystallization process of the ferroelectric layer, it is difficult for crystal grains to grow along the direction perpendicular to the side surface of the ferroelectric layer, and most crystal grains tend to grow along the direction parallel to the side surface of the ferroelectric layer. After the ferroelectric layer is crystallized, the longest axes of most crystal grains tend to extend along the direction parallel to the side surface of the ferroelectric layer, that is, the polarization axes (or polarization directions) of the crystal grains mostly tend to extend along the direction perpendicular to the side surface of the ferroelectric layer (i.e., the electric field direction). Therefore, during the polarization reversal process, a sufficient number of reversal charges can be contributed, optimizing the storage performance of the storage array.

[0009] In a possible implementation manner of the first aspect, the coefficient of thermal expansion of the functional layer is smaller than that of the electrode layer in which the functional layer is embedded. This enhances the influence of the functional layer on the polarization orientation of crystal grains in the ferroelectric layer, thereby further increasing the number of crystal grains in the ferroelectric layer with polarization directions parallel to the electric field direction, and further optimizing the storage performance of the storage array.

[0010] In a possible implementation manner of the first aspect, the electrode layer in which the functional layer is embedded includes multiple sub-layers, and at least one functional layer is alternately stacked with the multiple sub-layers along a third direction; the third direction is parallel to the side surface of the ferroelectric layer.

[0011] The functional layer divides the electrode layer in which the functional layer is embedded into multiple sub-layers, so that both the electrode layer in which the functional layer is embedded and the functional layer can be in contact with the side surface of the ferroelectric layer, taking into account both the effective area between the electrode layer in which the functional layer is embedded and the ferroelectric layer and the regulation of the polarization orientation of crystal grains in the ferroelectric layer by the functional layer. In addition, by stacking the functional layer and the sub-layers, the preparation difficulty of the storage array can be effectively reduced, and the preparation efficiency of the storage array can be improved.

[0012] In a possible implementation manner of the first aspect, the storage array further includes a first contact structure. The first contact structure penetrates at least multiple sub-layers and is electrically connected to the multiple sub-layers.

[0013] By arranging the first contact structure to penetrate at least multiple sub-layers, the electrical connection between each sub-layer in the multiple sub-layers and the first contact structure can be effectively achieved. Even when the material of the functional layer is an insulating material, the first contact structure can also avoid the situation where some sub-layers cannot be connected due to the setting of the functional layer.

[0014] In a possible implementation of the first aspect, the electrode layer embedded in the functional layer includes a first sub-layer and a second sub-layer, and the first sub-layer and the second sub-layer are alternately stacked along a third direction. The first sub-layer is in contact with the side surface of the ferroelectric layer; the functional layer is disposed on the same layer as the second sub-layer, and the functional layer is disposed between the ferroelectric layer and the second sub-layer.

[0015] By embedding the functional layer in the second sub-layer and arranging the first sub-layer and the second sub-layer in a stacked manner, electrical conduction between multiple first sub-layers is achieved through the second sub-layer. Even when the material of the functional layer is an insulating material, the presence of the functional layer will not affect the electrical conduction between various parts of the electrode layer (such as the second electrode layer) in which the functional layer is embedded, facilitating the electrical connection between the electrode layer in which the functional layer is embedded and an external circuit.

[0016] In a possible implementation of the first aspect, the memory array further includes a second contact structure. The second contact structure is electrically connected to at least one layer of the first sub-layer or at least one layer of the second sub-layer.

[0017] The second contact structure only needs to be connected to the outermost layer of the sub-layer to achieve electrical conduction between all sub-layers of the electrode layer (such as the second conductive layer) in which the functional layer is embedded and the second contact structure, without the need for cumbersome process steps such as digging holes, reducing the manufacturing difficulty of the memory array and improving the manufacturing efficiency of the memory array.

[0018] In a possible implementation of the first aspect, when the electrode layer (such as the second conductive layer) in which the functional layer is embedded includes multiple sub-layers, the ratio of the thickness of the sub-layer to the thickness of the functional layer is 0.5 to 5; or, when the electrode layer in which the functional layer is embedded includes a first sub-layer and a second sub-layer, the ratio of the thickness of the first sub-layer to the thickness of the functional layer is 0.5 to 5.

[0019] In a possible implementation of the first aspect, the memory array includes multiple functional layers. The multiple functional layers are spaced along the third direction, and the distance between every two adjacent functional layers is equal.

[0020] That is, the multiple functional layers are arranged uniformly along the third direction, so that a compressive stress can be uniformly formed on the side surface of the ferroelectric layer, making the number of grains with the polarization orientation in the same direction as the electric field direction at different positions in the ferroelectric layer approximately the same, improving the consistency of the grain distribution law in the ferroelectric layer, and further enhancing the storage performance of the memory array.

[0021] In a possible implementation of the first aspect, the ferroelectric layer is annular; the ferroelectric layer surrounds the first electrode layer, and the second electrode layer surrounds the ferroelectric layer; the functional layer is embedded in the second electrode layer.

[0022] In a possible implementation of the first aspect, the storage array includes a plurality of storage cells. Each storage cell includes a ferroelectric layer, a first electrode layer, a second electrode layer, and a functional layer. The plurality of storage cells can be arranged along at least one of a first direction, a second direction, and a third direction; the first direction, the second direction, and the third direction are perpendicular to each other in pairs.

[0023] In a possible implementation of the first aspect, the storage array further includes an insulating layer. The insulating layer is disposed between two adjacent storage cells along the third direction. When the ferroelectric layer is annular, the storage cells adjacent along the third direction share the first electrode layer and the ferroelectric layer, and the insulating layer and the second electrode layer are alternately stacked along the third direction. Among them, the thermal expansion coefficient of the insulating layer is less than that of the ferroelectric layer.

[0024] In a possible implementation of the first aspect, the material of the functional layer includes at least one of SiO2, SiN, SiGe, SiC, and h-BN.

[0025] In a second aspect, a memory is provided. The memory includes a peripheral circuit and the storage array provided in any one of the embodiments of the first aspect.

[0026] In a third aspect, an electronic device is provided. The electronic device includes a circuit board and the memory provided in the embodiment of the second aspect. Among them, the circuit board is electrically connected to the memory.

[0027] For the technical effects brought by the memory in the second aspect and the electronic device in the third aspect, reference can be made to the technical effects brought by the design method of the storage array in the first aspect, which will not be elaborated here.

[0028] In a fourth aspect, a method for preparing a storage array is provided. The preparation method includes:

[0029] Form a second electrode layer, and embed at least one functional layer in the second electrode layer. Form a first opening; the first opening penetrates through the second electrode layer and the functional layer. Form a ferroelectric layer on the inner wall of the first opening; the side surfaces of the functional layer and the ferroelectric layer are in contact. Fill the first opening to form a first electrode layer; the first electrode layer and the second electrode layer are disposed on both sides of the ferroelectric layer. Among them, the thermal expansion coefficient of the functional layer is less than that of the ferroelectric layer.

[0030] The steps of the method for preparing the storage array provided by the embodiments of the present application are simple, and a high-performance and good-uniformity storage array can be obtained only by using a relatively simple, low-cost, and mature thin-film deposition process.

[0031] In addition, in this preparation method, there is no need to perform the preparation process on a substrate with a specific lattice constant. The range of selectable substrate materials is wide and less restricted, which can avoid using a preparation method with harsh epitaxial growth conditions and slow growth rate, thus effectively reducing the preparation cost of the storage array, lowering the preparation difficulty, and increasing the production capacity.

[0032] Moreover, this preparation method can be compatible with the existing mature silicon-based semiconductor process, further reducing the preparation difficulty.

[0033] In a possible implementation manner of the fourth aspect, the second electrode layer includes multiple sub-layers. Forming the second electrode layer and embedding a functional layer in the second electrode layer includes forming sub-layers and the functional layer alternately stacked along a third direction; the third direction is parallel to the side surface of the ferroelectric layer.

[0034] In a possible implementation manner of the fourth aspect, the second electrode layer includes a first sub-layer and a second sub-layer. Forming the second electrode layer and embedding a functional layer in the second electrode layer includes:

[0035] Forming the first sub-layer and the second sub-layer alternately stacked along the third direction. After forming the first opening, through the first opening, removing a part of the second sub-layer close to the first opening to form a receiving cavity. Filling the functional layer in the receiving cavity.

[0036] For the technical effects brought by the preparation method in the fourth aspect, reference can be made to the technical effects brought by the design manner of the storage array in the first aspect, which will not be elaborated here.

[0037] In a fifth aspect, a preparation method of a storage array is provided. The preparation method includes:

[0038] Alternately stacking an insulating layer and a functional layer along a third direction. Forming a first opening, and sequentially forming a ferroelectric layer and a first electrode layer in the first opening; the first opening penetrates through the insulating layer and the functional layer; the ferroelectric layer is disposed on the inner wall of the first opening, and the first electrode layer is disposed on a side of the ferroelectric layer away from the inner wall of the first opening; the thermal expansion coefficient of the functional layer is less than that of the ferroelectric layer. Performing annealing. Removing the functional layer, and forming a second electrode layer in the cavity formed after removing the functional layer.

[0039] By replacing the functional layer with the second electrode layer after annealing, the regulation of the polarization orientation of the grains in the ferroelectric layer by the functional layer can be retained during the annealing process. At the same time, after the regulation of the polarization orientation of the grains in the ferroelectric layer is completed, by replacing the functional layer with the second electrode layer, it is possible to avoid sacrificing the effective capacitance area of the ferroelectric capacitor due to the setting of the functional layer, and thus the storage capacity of the storage array can also be taken into account. Description of the Drawings

[0040] Figure 1Schematic diagram of a structure of an electronic device provided by an embodiment of the present application;

[0041] Figure 2 Schematic diagram of a structure of a memory provided by an embodiment of the present application;

[0042] Figure 3 Equivalent circuit diagram of a storage array provided by an embodiment of the present application;

[0043] Figure 4 Schematic diagram of a structure of a ferroelectric capacitor provided by an embodiment of the present application;

[0044] Figure 5 Is along Figure 4 Cross-sectional view along the section line A-A' in

[0045] Figure 6 Schematic diagram of a structure of a storage array provided by an embodiment of the present application;

[0046] Figure 7 Another schematic diagram of a structure of a storage array provided by an embodiment of the present application;

[0047] Figure 8 Is along Figure 7 A cross-sectional view along the section line B-B' in

[0048] Figure 9 Simulation analysis diagram of a storage array provided by an embodiment of the present application;

[0049] Figure 10 A cross-sectional view of a storage array provided by an embodiment of the present application;

[0050] Figure 11 Is along Figure 7 Another cross-sectional view along the section line B-B' in

[0051] Figure 12 Is along Figure 7 Another cross-sectional view along the section line B-B' in

[0052] Figure 13 Is along Figure 7 Another cross-sectional view along the section line B-B' in

[0053] Figure 14 Is along Figure 7 Another cross-sectional view along the section line B-B' in

[0054] Figure 15 Another schematic diagram of a structure of a storage array provided by an embodiment of the present application;

[0055] Figure 16 Is along Figure 15A sectional view of the section line C-C' in

[0056] Figure 17 For along Figure 15 Another sectional view of the section line C-C' in

[0057] Figure 18 、 Figure 19 、 Figure 25 And Figure 31 Is a flowchart for preparing the storage array provided by the embodiments of the present application;

[0058] Figures 20 to 24 、 Figures 26 to 30 And Figures 32 to 34 Are sectional views corresponding to the respective preparation steps of the storage array. Specific embodiments

[0059] Next, the technical solutions in some embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0060] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0061] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. In addition, the specific features, structures, materials or characteristics can be included in any one or more embodiments or examples in any appropriate manner.

[0062] Hereinafter, terms such as "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0063] When describing some embodiments, expressions such as "coupled" and "connected" and their derivatives may be used. The terms "coupled" and "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium. The embodiments disclosed herein are not necessarily limited to the content herein.

[0064] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0065] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0066] As used herein, "parallel", "perpendicular", and "equal" include the described situations and situations similar to the described situations, and the range of the similar situations is within an acceptable deviation range, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurements being discussed and the errors associated with the measurements of specific quantities (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, and the acceptable deviation range of approximate parallelism may be, for example, within 5° deviation; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, and the acceptable deviation range of approximate perpendicularity may also be, for example, within 5° deviation. "Equal" includes absolute equality and approximate equality, and the acceptable deviation range of approximate equality may be, for example, that the difference between the two equal ones is less than or equal to 5% of either one of them.

[0067] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances can be envisioned. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0068] In addition, the scenarios described in the embodiments of this application are for more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those of ordinary skill in the art will know that with the emergence of new scenarios, the technical solutions provided by the embodiments of this application are equally applicable to similar technical problems.

[0069] The embodiments of this application provide an electronic device, which can be, for example, a mobile phone, a tablet computer (Pad), a personal digital assistant (PDA), a television, a smart wearable product (such as a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a charging household small appliance (such as a soymilk maker, a floor sweeping robot), a drone, a radar, an aerospace device, a vehicle-mounted device, a vehicle, or other different types of user devices or terminal devices; the electronic device can also be a network device such as a base station. The embodiments of this application do not impose special restrictions on the specific form of the electronic device.

[0070] Figure 1 FIG. is a schematic structural diagram of an electronic device provided exemplarily for the embodiments of this application.

[0071] Exemplarily, as Figure 1 shown, the electronic device 1000 may include a bus 205 and a system on chip (SoC) 210 connected to the bus 205.

[0072] Among them, the system on chip 210 can be used to process data, such as processing data of application programs, processing image data, and caching temporary data.

[0073] Exemplarily, the system on chip 210 may include an application processor (AP) 211 for processing application programs, a graphics processing unit (GPU) 212 for processing image data, and an on-chip memory 213 for caching high-speed data.

[0074] Exemplarily, the on-chip memory 213 may be a static random access memory (SRAM) or an embedded flash (eflash), etc.

[0075] Exemplarily, the above application processor 211, image processing unit 212, and on-chip memory 213 can be integrated in one die, or can be separately disposed in multiple dies.

[0076] Exemplarily, as Figure 1 shown, the electronic device 1000 may further include an off-chip memory 220 connected to the system-on-chip 210 through a bus 205.

[0077] Exemplarily, the off-chip memory 220 may be a dynamic random access memory (DRAM). The off-chip memory 220 can be used to store volatile data, such as temporary data generated by the system-on-chip 210. The storage capacity of the off-chip memory 220 is generally larger than that of the on-chip memory 213, but the read speed is generally slower than that of the on-chip memory 213.

[0078] Exemplarily, the system-on-chip 210 and the off-chip memory 220 can be encapsulated in a packaging structure, such as using 2.5D (dimension) or 3D packaging, etc., to obtain a faster inter-chip data transfer rate.

[0079] Exemplarily, as Figure 1 shown, the electronic device 1000 may further include a communication chip 230 and a power management chip 240 connected to the system-on-chip 210 through a bus 205.

[0080] Among them, the communication chip 230 can be used for protocol stack processing, or for amplifying and filtering analog radio frequency signals, etc., or for implementing the above functions simultaneously. The power management chip 240 can be used to supply power to other chips.

[0081] It can be understood that Figure 1 the structure of the electronic device 1000 shown in Figure 1 does not constitute a specific limitation on the electronic device 1000. The electronic device 1000 may include more or fewer components than those shown in Figure 1 or may combine some of the components shown in Figure 1 or may be arranged differently from the components shown in

[0082] An embodiment of the present application further provides a memory 100. The memory 100 can be applied to the above-mentioned electronic device 1000. For example, the memory 100 can be the on-chip memory 213 shown in Figure 1 or, the memory 100 can also be the off-chip memory 220 shown in Figure 1 The embodiment of the present application does not limit the specific application scenario of the memory 100.

[0083] Figure 2 This is a schematic structural diagram of the memory 100 provided by the embodiments of the present application.

[0084] Exemplarily, the memory 100 may include one of a ferroelectric random access memory (Ferroelectric Random Access Memory, FeRAM or FRAM) and a ferroelectric field effect transistor (Ferroelectric Filed-Effect-Transistor, FeFET) memory.

[0085] As Figure 2 shown, the memory 100 includes a storage array 10 and a peripheral circuit 20.

[0086] Among them, the storage array 10 is connected to the peripheral circuit 20, and the peripheral circuit 20 is used to control access to the storage array 10. For example, the peripheral circuit 20 can control writing data to the storage array 10 or control reading data from the storage array 10.

[0087] Exemplarily, the peripheral circuit 20 may include a word line selection circuit, a bit line selection circuit, a control circuit, and a read / write circuit.

[0088] Referring to Figure 2 , exemplarily, the storage array 10 may include a plurality of storage cells G distributed in an array.

[0089] Exemplarily, when performing read / write operations on the storage array 10, the read / write circuit transmits control signals to the word line selection circuit and the bit line selection circuit through the control circuit. The word line selection circuit selects a column in the storage array 10, and the bit line selection circuit selects a row in the storage array 10. The word line selection circuit and the bit line selection circuit jointly determine the address of the storage cell G to be accessed.

[0090] Exemplarily, the peripheral circuit 20 may be arranged around the storage array 10. For example, referring to Figure 2 , the peripheral circuit 20 may be arranged on at least one side of the storage array 10.

[0091] Exemplarily, the peripheral circuit 20 may also be stacked with the storage array 10, that is, the storage array 10 may be arranged on the bottom surface or the top surface of the peripheral circuit 20.

[0092] Figure 3 This is a circuit architecture diagram of a storage cell G in the storage array 10 provided by the embodiments of the present application.

[0093] As Figure 3 shown, a storage cell G in the storage array 10 provided by the embodiments of the present application includes a circuit architecture based on a ferroelectric capacitor.

[0094] Exemplarily, as Figure 3 shown, the storage cell G may have a 1T1C (1-transistor-1-capacitor) structure (or 1TnC structure, where n is an integer greater than 1), that is, the storage cell G may include a transistor T and one (or n) ferroelectric capacitors FC. The source of the transistor T is electrically connected to a bit line (BL), the drain is electrically connected to one electrode of the ferroelectric capacitor FC, the gate is electrically connected to a word line (WL), and the other electrode of the ferroelectric capacitor FC is electrically connected to a plate line (PL).

[0095] Alternatively, exemplarily, the storage cell G may have a 1S1C (1-selector-1-capacitor) structure (or 1SnC structure, where n is an integer greater than 1), that is, the storage cell G may include a selector and one (or n) ferroelectric capacitors FC. It can be understood that the transistor T in the 1T1C architecture is replaced by a selector S.

[0096] It can be understood that the circuit architecture of the storage cell G in the embodiments of the present application is not limited to the foregoing examples, and any circuit architecture that uses ferroelectric materials to achieve charge storage is within the protection scope of the embodiments of the present application. For example, the storage cell G in the embodiments of the present application may be a circuit architecture including a ferroelectric capacitor or a ferroelectric transistor.

[0097] Next, the working principle of the storage array 10 will be introduced in conjunction with the structure of the ferroelectric capacitor.

[0098] Figure 4 FIG. is a structural diagram of a ferroelectric capacitor FC.

[0099] As Figure 4 shown, the ferroelectric capacitor FC includes a first electrode layer 1, a second electrode layer 2, and a ferroelectric layer 3 disposed between the first electrode layer 1 and the second electrode layer 2.

[0100] Among them, the material of the ferroelectric layer 3 is a ferroelectric material with spontaneous polarization characteristics. That is, there are ferroelectric phase crystals in the ferroelectric layer 3. When the first electrode layer 1 and the second electrode layer 2 receive voltage signals and generate an external electric field, the external electric field is applied to the ferroelectric layer 3, and the unit cells in the ferroelectric layer 3 are flipped under the action of the external electric field, thereby releasing enough charges to be recognized by the circuit, thus showing a storage state of "0" or "1".

[0101] Figure 5 FIG. is a schematic structural diagram of a corresponding storage array in the related art.

[0102] Refer to Figure 5, in the related art, the material of the ferroelectric layer 3 mainly exists in the form of polycrystals (such as hafnium oxide-based ferroelectric materials), and the polarization orientations of the grains in the ferroelectric layer 3' are disordered (as shown by the arrows in Figure 5 ), resulting in a small proportion of grains in the ferroelectric layer 3' whose polarization orientations are along the electric field direction (for example, the direction from the first electrode layer 1' to the second electrode layer 2'), so that the amount of charge released during the polarization reversal process of the ferroelectric layer 3' is small, affecting the accuracy of the circuit to identify "0" or "1" according to the amount of charge, reducing the storage window of the memory, and severely limiting the improvement of the storage performance of the memory.

[0103] To solve the above technical problems, an embodiment of the present application provides a storage array 10.

[0104] Figure 6 FIG. is a schematic structural diagram of the storage array 10 provided by an embodiment of the present application, Figure 7 FIG. is another schematic structural diagram of the storage array 10 provided by an embodiment of the present application.

[0105] As shown in Figure 6 and Figure 7 , the storage array 10 includes a ferroelectric layer 3, a first electrode layer 1, a second electrode layer 2, and at least one functional layer 4.

[0106] Exemplarily, the material of the ferroelectric layer 3 may include doped hafnium oxide (HfO 2 )-based ferroelectric materials. That is, it includes hafnium oxide and doping materials. Among them, the doping materials may include at least one of zirconium (Zr), titanium (Ti), niobium (Nb), lanthanum (La), cerium (Ce), gadolinium (Gd), yttrium (Y), aluminum (Al), or strontium (Sr).

[0107] Alternatively, exemplarily, the ferroelectric layer 3 may also include perovskite structure materials such as lead zirconate titanate (PbZrTiO 4 ), lead metazirconate (PbZrO 3 ), lead metatitanate (PbTiO 3 ), or lead zirconate titanate piezoelectric ceramics (PZT).

[0108] Exemplarily, the above ferroelectric layer 3 can be prepared by thin film deposition methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0109] Exemplarily, the ferroelectric layer 3 may include a planar setting or a three-dimensional ring setting and other setting methods.

[0110] For example, referring to Figure 6 , the storage array 10 may include a planar capacitor. That is, the first electrode layer 1, the second electrode layer 2, and the ferroelectric layer 3 may all be parallel to the surface of the substrate (e.g., a silicon substrate) on which the storage array 10 is fabricated.

[0111] Alternatively, for example, the storage array 10 may include a vertical fin capacitor. That is, the first electrode layer 1, the second electrode layer 2, and the ferroelectric layer 3 may all be perpendicular to the surface of the substrate on which the storage array 10 is fabricated.

[0112] Or alternatively, for example, referring to Figure 7 , the storage array 10 may include a three-dimensional ring-shaped capacitor. That is, the first electrode layer 1, the second electrode layer 2, and the ferroelectric layer 3 may be arranged in a ring shape, for example, in a square ring shape or a circular ring shape (referring to Figure 7 ). Referring to Figure 7 , the ferroelectric layer 3 is arranged around the first electrode layer 1, and the second electrode layer 2 is arranged around the ferroelectric layer 3.

[0113] It can be understood that the above are only examples of the structure of the storage array 10 and do not constitute a limitation on the structure of the storage array 10.

[0114] Referring to Figure 6 and Figure 7 , the first electrode layer 1 and the second electrode layer 2 are respectively disposed on two side surfaces of the ferroelectric layer 3.

[0115] For example, referring to Figure 6 , in the case where the ferroelectric layer 3 in the storage array 10 is arranged in a plane, the first electrode layer 1 and the second electrode layer 2 are respectively disposed on the upper and lower side surfaces of the ferroelectric layer 3 (taking the orientation in Figure 6 as an example).

[0116] Or alternatively, for example, referring to Figure 7 , in the case where the ferroelectric layer 3 in the storage array 10 is arranged in a ring shape, the first electrode layer 1 and the second electrode layer 2 are respectively disposed on the inner side surface and the outer side surface of the ring of the ferroelectric layer 3.

[0117] Exemplarily, the material of the first electrode layer 1 and / or the second electrode layer 2 may be a metal material, for example, it may include tungsten (W) or titanium nitride (TiN) or other materials with conductive properties.

[0118] In the case where the materials of both the first electrode layer 1 and the second electrode layer 2 are metal materials, the capacitor in the storage array 10 has a metal-insulator-metal (MIM) structure.

[0119] Exemplarily, the material of at least one of the first electrode layer 1 and the second electrode layer 2 may be a semiconductor material, for example, it may include silicon (Si).

[0120] When the material of at least one of the first electrode layer 1 and the second electrode layer 2 is a semiconductor material, the capacitor in the memory array 10 is a metal-insulator-semiconductor (MIS) structure.

[0121] Exemplarily, at least one of the first electrode layer 1 and the second electrode layer 2 can be a composite electrode, that is, at least one of the first electrode layer 1 and the second electrode layer 2 can be composed of a multi-layer conductive layer composite. For example, refer to the following Figure 11 , the first electrode layer 1 can include a first conductive layer 11 and a second conductive layer 12, and the two are stacked and combined to jointly serve as the first electrode layer 1.

[0122] It can be understood that the first electrode layer 1 and the second electrode layer 2 can also include other conductive layer composite methods. The drawings provided in the embodiments of the present application are only exemplary and do not limit their specific structures.

[0123] Refer to Figure 6 and Figure 7 , the functional layer 4 (one or more functional layers 4, Figure 6 and Figure 7 are schematically illustrated with multiple functional layers 4 as an example) is embedded in the first electrode layer 1 and / or the second electrode layer 2.

[0124] That is, the functional layer 4 can be embedded only in the first electrode layer 1, or only in the second electrode layer 2 (refer to Figure 7 , the functional layer 4 is embedded only in the second electrode layer 2), or the functional layer 4 can be embedded in both the first electrode layer 1 and the second electrode layer 2 at the same time (refer to Figure 6 ).

[0125] Figures 11 to 14 is a cross-sectional view along the section line B-B' in Figure 7 .

[0126] Refer to Figure 6 , Figures 11 to 14 , the functional layer 4 is in contact with the side surface of the ferroelectric layer 3.

[0127] It can be understood that the side surface of the ferroelectric layer 3 here refers to the surface perpendicular to the electric field direction in the ferroelectric layer 3. Among them, the electric field direction in the embodiments of the present application refers to the direction of the electric field formed by the potential difference between the first electrode layer 1 and the second electrode layer 2, for example, it can be the direction from the first electrode layer 1 to the second electrode layer 2, or it can be the direction from the second electrode layer 2 to the first electrode layer 1.

[0128] Among them, the coefficient of thermal expansion of the functional layer 4 is less than that of the ferroelectric layer 3.

[0129] For example, the coefficient of thermal expansion of the functional layer 4 can be less than or equal to 5.8×10-6 / °C. For example, the coefficient of thermal expansion of the functional layer 4 can be 0.55×10-6 / °C, 2.35×10-6 / °C, 3×10-6 / °C, 4.578×10-6 / °C, 5.8×10-6 / °C, etc.

[0130] Exemplarily, at least the coefficient of thermal expansion of the functional layer 4 at the annealing temperature of the storage array 10 is less than the coefficient of thermal expansion of the ferroelectric layer 3 at this annealing temperature.

[0131] For example, as the temperature rises (e.g., at the annealing temperature), the coefficient of thermal expansion of some materials in the functional layer 4 may increase accordingly. By controlling the coefficient of thermal expansion of the functional layer 4 at the annealing temperature to be less than the coefficient of thermal expansion of the ferroelectric layer 3 at the annealing temperature, it is ensured that during the annealing process, the functional layer 4 can provide compressive stress to the ferroelectric layer 3, thereby realizing the regulation of the polarization orientation of the grains in the ferroelectric layer 3.

[0132] Among them, the annealing temperature of the storage array 10 refers to the temperature during the rapid thermal annealing treatment of the entire structure of the foregoing first electrode layer 1, second electrode layer 2, ferroelectric layer 3, and functional layer 4 after the entire structure is prepared. After the annealing treatment, ferroelectric phase crystals can be formed by crystallization in the ferroelectric layer 3. For example, this annealing temperature can be 100°C to 1000°C, for example, 200°C to 500°C.

[0133] Exemplarily, the material of the functional layer 4 can include SiO 2 (silicon dioxide), SiN (silicon nitride), SiGe (silicon-germanium alloy), SiC (silicon carbide), and at least one of h-BN (hexagonal boron nitride).

[0134] In the storage array 10 provided by the embodiments of the present application, by embedding the functional layer 4 with a low coefficient of thermal expansion in the first electrode layer 1 and / or the second electrode layer 2, and setting the functional layer 4 to be in contact with the side surface of the ferroelectric layer 3 (the surface perpendicular to the electric field direction in the ferroelectric layer 3), during the preparation process of the storage array 10, especially during the annealing process of the storage array 10, refer to Figure 8 , the functional layer 4 with a smaller coefficient of thermal expansion can provide a large compressive stress N1 perpendicular to the side surface of the ferroelectric layer 3 (i.e., parallel to the electric field direction) to the side surface of the ferroelectric layer 3, so that during the crystallization process of the ferroelectric layer 3, it is difficult for the grains to grow along the direction perpendicular to the side surface of the ferroelectric layer 3, and most of the grains tend to grow along the direction parallel to the side surface of the ferroelectric layer 3. After the ferroelectric layer 3 crystallizes, the longest axis of the grains (refer to Figure 8 L1 in) mostly tends to extend along the direction parallel to the side surface of the ferroelectric layer 3, that is, the polarization axis (or polarization direction, refer to Figure 8Most of the L2) in it tend to extend along the direction perpendicular to the side surface of the ferroelectric layer 3 (i.e., the electric field direction), so that during the polarization reversal process, a sufficient number of reversal charges can be contributed to optimize the storage performance of the storage array 10.

[0135] Figure 9 It is a schematic diagram for the simulation analysis of the storage array 10.

[0136] Figure 9 The abscissa in it is the ratio of the area where the functional layer 4 contacts the side surface of the ferroelectric layer 3 to the total side surface area of the ferroelectric layer 3. For example, in the storage cell G, as the number of layers of the functional layer 4 increases, the ratio of the area where the functional layer 4 contacts the side surface of the ferroelectric layer 3 gradually increases, that is, Figure 9 the abscissa value in it moves to the right.

[0137] Figure 9 The ordinate in it is the ratio of the in-plane stress to the out-of-plane stress of the ferroelectric layer 3.

[0138] Among them, the in-plane stress is the stress perpendicular to the electric field direction in the ferroelectric layer 3 (for example, it can be referred to Figure 8 the direction of the longest axis L1 in it), and the out-of-plane stress is the stress parallel to the electric field direction in the ferroelectric layer 3 (for example, it can be referred to Figure 8 the direction of the polarization axis L2 in it). Figure 9 The larger the ratio of the in-plane stress to the out-of-plane stress in it, the more it indicates that the longest axes of the grains in the ferroelectric layer 3 tend to be distributed along the direction perpendicular to the electric field direction, and the polarization axis tends to be distributed along the electric field direction.

[0139] Such as Figure 9 shown, as the ratio of the functional layer 4 gradually increases, the ratio of the in-plane stress to the out-of-plane stress gradually increases, that is, the number of grains in the ferroelectric layer 3 with the polarization direction distributed along the electric field direction gradually increases, indicating that in the storage array 10 provided by the embodiments of the present application, by setting the functional layer 4, it can indeed effectively affect the polarization direction of the grains in the ferroelectric layer 3, and increase the number of grains in the ferroelectric layer 3 with the polarization direction in the same direction as the electric field direction. For example, refer to Figure 10 , compared with the polarization orientation distribution in the prior art ferroelectric layer 3' (refer to Figure 5 ), in the ferroelectric layer 3 of the embodiments of the present application, most of the polarization directions are parallel to the electric field direction, which can effectively increase the number of reversal charges contributed during the polarization reversal process and optimize the storage performance of the storage array 10.

[0140] In some embodiments, the coefficient of thermal expansion of the functional layer 4 is less than the coefficient of thermal expansion of the electrode layer (the first electrode layer 1 and / or the second electrode layer 2) in which the functional layer 4 is embedded.

[0141] For example, when the coefficient of thermal expansion of the electrode layer (the first electrode layer 1 and / or the second electrode layer 2) embedded in the functional layer 4 is less than that of the ferroelectric layer 3, by setting the coefficient of thermal expansion of the functional layer 4 to be less than that of the electrode layer embedded in the functional layer 4, the influence of the functional layer 4 on the polarization orientation of the grains in the ferroelectric layer 3 can be enhanced, thereby further increasing the number of grains in the ferroelectric layer 3 whose polarization directions are parallel to the electric field direction, and further optimizing the storage performance of the storage array 10.

[0142] For example, when the material of the second electrode layer 2 is tungsten and the functional layer 4 is embedded in the second electrode layer 2, the coefficient of thermal expansion of the functional layer 4 can be less than that of tungsten (especially at the aforementioned annealing temperature).

[0143] In some embodiments, as Figure 11 shown, the electrode layer (taking the second electrode layer 2 as an example for illustrative purposes in the figure) embedded in the functional layer 4 includes a plurality of sub-layers M', and the functional layer 4 (taking a plurality of functional layers 4 as an example in the figure) and the plurality of sub-layers M' are alternately stacked in the third direction Z.

[0144] Among them, the third direction Z is parallel to the side surface of the ferroelectric layer 3.

[0145] By dividing the electrode layer embedded in the functional layer 4 into a plurality of sub-layers M' through the functional layer 4, so that both the electrode layer embedded in the functional layer 4 and the functional layer 4 can be in contact with the side surface of the ferroelectric layer 3, taking into account both the effective area between the electrode layer embedded in the functional layer 4 and the ferroelectric layer 3 and the regulation of the polarization orientation of the grains in the ferroelectric layer 3 by the functional layer 4.

[0146] In addition, by stacking the functional layer 4 and the sub-layers M', the manufacturing difficulty of the storage array 10 can be effectively reduced, and the manufacturing efficiency of the storage array 10 can be improved.

[0147] In some embodiments, as Figure 12 shown, on the basis of Figure 11 , the storage array 10 further includes a first contact structure 51.

[0148] It can be understood that the first contact structure 51 is used to realize the external connection of the electrode layer embedded in the functional layer 4. For example, referring to Figure 12 , the first contact structure 51 is used to externally connect the second electrode layer 2 so that an external circuit can transmit an electrical signal to the second electrode layer 2.

[0149] Referring to Figure 12 , the first contact structure 51 at least penetrates through a plurality of sub-layers M' and is electrically connected to the plurality of sub-layers M'.

[0150] Exemplarily, referring to Figure 12, the first contact structure 51 also penetrates through the functional layer 4 to achieve the electrical connection between the first contact structure 51 and the second electrode layer 2.

[0151] By setting that the first contact structure 51 penetrates through at least multiple sub-layers M', the electrical connection between each sub-layer M' in the multiple sub-layers M' and the first contact structure 51 is effectively achieved. Even when the material of the functional layer 4 is an insulating material, the first contact structure 51 can also avoid the situation where some sub-layers M' cannot be connected due to the setting of the functional layer 4.

[0152] In some embodiments, as Figure 13 shown, the electrode layer embedded in the functional layer 4 (taking the second electrode layer 2 as an example in the figure for illustration) includes a first sub-layer M1 and a second sub-layer M2, and the first sub-layer M1 and the second sub-layer M2 are alternately stacked along the third direction Z.

[0153] Among them, the materials of both the first sub-layer M1 and the second sub-layer M2 can be conductive materials, and they are stacked to achieve conduction.

[0154] For example, the material of the first sub-layer M1 can include tungsten metal, titanium nitride or other conductive materials, and the material of the second sub-layer M2 can also include tungsten metal, titanium nitride or other conductive materials.

[0155] Referring to Figure 13 , the first sub-layer M1 is in contact with the side surface of the ferroelectric layer 3, that is, the area of the first sub-layer M1 in contact with the ferroelectric layer 3 can be used as the effective area of the ferroelectric capacitor.

[0156] Referring to Figure 13 , the functional layer 4 is arranged on the same layer as the second sub-layer M2, and the functional layer 4 is arranged between the ferroelectric layer 3 and the second sub-layer M2. That is, the functional layer 4 is embedded in the second sub-layer M2.

[0157] By embedding the functional layer 4 in the second sub-layer M2 and setting the first sub-layer M1 and the second sub-layer M2 to be stacked, the electrical conduction between multiple first sub-layers M1 is achieved through the second sub-layer M2. Even when the material of the functional layer 4 is an insulating material, the presence of the functional layer 4 still does not affect the electrical conduction between various parts of the electrode layer (such as the second electrode layer 2) in which the functional layer 4 is embedded, which is convenient for the electrode layer in which the functional layer 4 is embedded to be electrically connected to an external circuit.

[0158] In some embodiments, as Figure 14 shown, on the basis of Figure 13 , the memory array 10 further includes a second contact structure 52.

[0159] It can be understood that the second contact structure 52 has the same function as the first contact structure 51, and both are used to realize the electrical connection between the electrode layer embedded in the functional layer 4 and the external circuit.

[0160] The second contact structure 52 is electrically connected to at least one layer of the first sub-layer M1 or at least one layer of the second sub-layer M2. For example, referring to Figure 14 , the second contact structure 52 is electrically connected to the outermost conductive layer (the first sub-layer M1 located at the uppermost layer in the figure).

[0161] That is, on the basis of Figure 13 , the second contact structure 52 does not need to penetrate the entire electrode layer embedded in the functional layer 4. For example, referring to Figure 14 , it only needs to be connected to the outermost sub-layer, and the electrical conduction between all sub-layers of the electrode layer (such as the second conductive layer 2) embedded in the functional layer 4 and the second contact structure 52 can be realized, without complicated process steps such as digging holes in the electrode layer embedded in the functional layer 4, reducing the preparation difficulty of the memory array 10 and improving the preparation efficiency of the memory array 10.

[0162] In some embodiments, the ratio of the side area of the ferroelectric layer 3 contacted by the functional layer 4 to the side area of the ferroelectric layer 3 contacted by the electrode layer (the first conductive layer 1 or the second conductive layer 2) embedded in the functional layer 4 is 0.5 to 5.

[0163] For example, in the case where the electrode layer embedded in the functional layer 4 includes multiple sub-layers M' (that is, the structure shown in Figure 11 or Figure 12 ), the ratio of the sub-layer M' to the thickness of the functional layer 4 is 0.5 to 5. Or, in the case where the electrode layer embedded in the functional layer 4 includes the first sub-layer M1 and the second sub-layer M2 (that is, the structure shown in Figure 13 or Figure 14 ), the ratio of the first sub-layer M1 to the thickness of the functional layer 4 is 0.5 to 5.

[0164] For example, the aforementioned ratio can be 0.5, 1, 2.35, 3.987 or 5.

[0165] Exemplarily, the number of layers of the functional layer 4 can be 1 to 10 layers.

[0166] Exemplarily, the number of layers of the sub-layer M' or the first sub-layer M1 can be 2 to 10 layers.

[0167] In some embodiments, when the storage array 10 includes a plurality of functional layers 4, the plurality of functional layers 4 are arranged at intervals along the third direction Z, and the distance between every two adjacent functional layers 4 is equal. That is, the plurality of functional layers 4 are arranged uniformly along the third direction Z, so that a compressive stress can be uniformly formed on the side surface of the ferroelectric layer 3, making the number of grains with the polarization orientation in the same direction as the electric field direction at different positions in the ferroelectric layer 3 substantially the same, improving the consistency of the grain distribution law in the ferroelectric layer 3, and further enhancing the storage performance of the storage array 10.

[0168] Figure 15 Another structural schematic diagram of the storage array 10 provided by the embodiment of the present application.

[0169] In some embodiments, as Figure 15 shown, the storage array 10 includes a plurality of storage units G.

[0170] Among them, each storage unit G includes the aforementioned ferroelectric layer 3, the first electrode layer 1, the second electrode layer 2, and the functional layer 4.

[0171] It should be noted that, for clear display, Figure 15 the functional layer 4 is not shown, and the setting position of the functional layer 4 can refer to the setting position shown in the foregoing Figures 11 to 14 figure.

[0172] Referring to Figure 15 , the plurality of storage units G can be arranged along at least one of the first direction X, the second direction Y, and the third direction Z.

[0173] Among them, referring to Figure 15 , the first direction X, the second direction Y, and the third direction Z are perpendicular to each other in pairs.

[0174] Exemplarily, referring to Figure 15 , the storage units G arranged along the first direction X can share the same second electrode layer 2, and the storage units G arranged along the third direction Z can share the same first electrode layer 1 or the same ferroelectric layer 3.

[0175] That is, the storage array 10 provided by the embodiment of the present application can be arranged in an array along multiple directions, so that the storage capacity of the storage array 10 can be flexibly adjusted according to requirements.

[0176] It can be understood that an insulating layer can be provided between adjacent second electrode layers 2. Figure 15 In the figure, in order to avoid forming an obstruction, structures such as the insulating layer are not shown.

[0177] In some embodiments, as Figure 16 shown, the storage array 10 further includes an insulating layer 6.

[0178] Refer to Figure 16 , the insulating layer 6 is disposed between two adjacent memory cells G arranged along the third direction Z. For example, it is disposed between two adjacent second conductive layers 2 arranged along the third direction Z.

[0179] Refer to Figure 16 , when the ferroelectric layer 3 is annular, the adjacent memory cells G arranged along the third direction Z share the first electrode layer 1 and the ferroelectric layer 3, and the insulating layer 6 and the second electrode layer 2 are alternately stacked along the third direction Z.

[0180] Among them, the thermal expansion coefficient of the insulating layer 6 is smaller than that of the ferroelectric layer 3.

[0181] By setting the thermal expansion coefficient of the insulating layer 6 to be smaller than that of the ferroelectric layer 3, the polarization orientation of the grains in the ferroelectric layer 3 can be further regulated, which is beneficial to further improving the storage performance of the memory array 10.

[0182] In some embodiments, as Figure 17 shown, the memory array 10 may include a first electrode layer 1, a second electrode layer 2, and a ferroelectric layer 3, and the first electrode layer 1 and the second electrode layer 2 are respectively disposed on both sides of the ferroelectric layer 3.

[0183] Among them, the second electrode layer 2 is replaced by the functional layer 4. For example, during the preparation process, the functional layer 4 and the insulating layer 6 can be alternately stacked first, and after annealing is completed, the functional layer 4 is removed and replaced with the second electrode layer 2.

[0184] It can be understood that the first electrode layer 1, the ferroelectric layer 3, and the functional layer 4 in this embodiment can refer to the descriptions in any of the above embodiments, and will not be elaborated here.

[0185] By replacing the functional layer 4 after annealing to form the conductive second electrode layer 2, the regulation of the polarization orientation of the grains in the ferroelectric layer 3 by the functional layer 4 can be retained during the annealing process. At the same time, after the regulation of the polarization orientation of the grains in the ferroelectric layer 3 is completed, by replacing the functional layer 4 with the conductive second electrode layer 2, it is possible to avoid sacrificing the effective capacitance area of the ferroelectric capacitor due to the setting of the functional layer 4 and improve the storage capacity of the memory array 10.

[0186] The embodiment of the present application also provides a method for manufacturing a memory array 10. The following embodiments will exemplarily illustrate the method for manufacturing the memory array 10 by taking the embedding of the functional layer 4 in the second electrode layer 2 as an example.

[0187] Figure 18 And Figure 19 are some manufacturing flowcharts of the memory array 10 provided by the embodiment of the present application.

[0188] Figures 20 to 24This is a cross-sectional view corresponding to the preparation process of the storage array 10 provided in the embodiments of the present application.

[0189] In some embodiments, as Figure 18 and Figure 19 shown, the preparation method may include the following steps S1 to S4:

[0190] S1: Form a second electrode layer 2, and embed at least one functional layer 4 in the second electrode layer 2.

[0191] Exemplarily, as Figure 19 shown, when the second electrode layer 2 includes a plurality of sub-layers M', this step S1 may include:

[0192] S11: As Figure 20 shown, form sub-layers M' and functional layers 4 that are alternately stacked along the third direction Z.

[0193] Wherein, the third direction Z is parallel to the side surface of the ferroelectric layer 3. The plurality of sub-layers M' constitute the second electrode layer 2.

[0194] S2: As Figure 21 shown, form a first opening K.

[0195] Referring to Figure 21 , the first opening K penetrates through the second electrode layer 2 and the functional layer 4.

[0196] S3: Referring to Figure 22 , form a ferroelectric layer 3 on the inner wall of the first opening K.

[0197] Referring to Figure 22 , the functional layer 4 is in contact with the side surface of the ferroelectric layer 3.

[0198] S4: Referring to Figure 23 , fill the first opening K to form a first electrode layer 1.

[0199] Referring to Figure 23 , the first electrode layer 1 and the second electrode layer 2 are disposed on both sides of the ferroelectric layer 3.

[0200] Among them, the thermal expansion coefficient of the functional layer 4 is less than that of the ferroelectric layer 3. The preparation method of the storage array 10 provided in the foregoing embodiments of the present application has simple steps, and a high-performance and good-uniformity storage array 10 can be obtained only by using a relatively simple, low-cost, and technically mature thin-film deposition process.

[0201] In addition, in this preparation method, the regulation of the polarization orientation of the grains in the ferroelectric layer 3 can be achieved only by setting the functional layer 4. Therefore, there is no need to perform the preparation process of the storage array 10 on a substrate with a specific lattice constant. The selectable range of the substrate material is wide and less restricted, and it is possible to avoid using a preparation method with harsh epitaxial growth conditions and slow growth rate, thereby effectively reducing the preparation cost of the storage array 10, reducing the preparation difficulty, and improving the production capacity.

[0202] Moreover, this preparation method can be compatible with the existing mature silicon-based semiconductor process, further reducing the preparation difficulty.

[0203] Exemplarily, as Figure 24 shown, this preparation method further includes step S5: forming a first contact structure 51.

[0204] Exemplarily, this step S5 may include: forming a through hole penetrating through the multi-layer sub-layers M' in the second electrode layer 2; filling the through hole with a conductive material to form the first contact structure 51.

[0205] Referring to Figure 24 , the first contact structure 51 penetrates through the multi-layer sub-layers M' in the second electrode layer 2 and contacts the multi-layer sub-layers M' to transmit an external electrical signal to the multi-layer sub-layers M', thereby realizing the external connection of the second electrode layer 2.

[0206] Exemplarily, this preparation method may further include annealing the entire storage array 10 to achieve crystallization of the grains in the ferroelectric layer 3.

[0207] Figure 25 This is another preparation flow chart of the storage array 10 provided by the embodiment of the present application.

[0208] Figures 26 to 30 This is a cross-sectional view corresponding to the preparation process of the storage array 10 provided by the embodiment of the present application.

[0209] In some other embodiments, as Figure 25 shown, when the second electrode layer 2 includes a first sub-layer M1 and a second sub-layer M2, the preparation method of the storage array 10 includes steps S1 to S4. Among them, in this embodiment, step S1 may include:

[0210] S12: As Figure 26 shown, forming the first sub-layer M1 and the second sub-layer M2 alternately stacked along the third direction Z.

[0211] S13: As Figure 28As shown, after forming the first opening K, through the first opening K, a part of the second sub-layer M2 close to the first opening K is removed to form the accommodation cavity Q1. The multi-layer first sub-layer M1 and the multi-layer second sub-layer M2 after the removed part form the second electrode layer 2.

[0212] It can be understood that referring to Figure 27 , step S2 can be carried out after step S12 and before step S13. In step S2 of this embodiment, referring to Figure 27 , the first opening K penetrates through the first sub-layer M1 and the second sub-layer M2 in the second electrode layer 2.

[0213] S14: As Figure 29 shown, the functional layer 4 is filled in the accommodation cavity Q1.

[0214] It can be understood that Figures 26 to 29 after the structure formed in Figure 22 , it also includes step S3 (referring to Figure 23 ) and step S4 (referring to

[0215] ), as well as an annealing process, etc., which will not be elaborated here.

[0216] Exemplarily, as Figure 30 shown, this preparation method further includes step S6: forming the second contact structure 52.

[0217] Referring to Figure 30 , the second contact structure 52 can be electrically connected to any one of the first sub-layer M1 and the second sub-layer M2 of the second electrode layer 2. For example, referring to Figure 30 , the second contact structure 52 can be in electrical contact with the first sub-layer M1 located at the uppermost layer in its corresponding second electrode layer 2 to transmit an external electrical signal to the second electrode layer 2.

[0218] In this embodiment, the preparation of the second contact structure 52 can be realized without setting through holes, greatly reducing the preparation difficulty of the external connection structure of the second electrode layer 2 and improving the preparation efficiency.

[0219] Figure 31 This is another preparation flow chart of the storage array 10 provided by the embodiment of the present application.

[0220] Figures 32 to 34 This is a cross-sectional view corresponding to the preparation process of the storage array 10 provided by the embodiment of the present application.

[0221] In some other embodiments, as Figure 31 shown, the method for preparing the storage array 10 includes the following steps N1 to N4:

[0222] N1: As Figure 32 shown, an insulating layer 6 and a functional layer 4 are alternately stacked along the third direction Z.

[0223] N2: A first opening K is formed, and a ferroelectric layer 3 and a first electrode layer 1 are sequentially formed in the first opening K.

[0224] It can be understood that step N2 can refer to the foregoing steps S2 to S4 (i.e., refer to Figures 21 to 23 ), and details are not described herein again.

[0225] Similarly to Figure 23 , in step N2, the first opening K penetrates through the insulating layer 6 and the functional layer 4. The ferroelectric layer 3 is disposed on the inner wall of the first opening K, and the first electrode layer 1 is disposed on the side of the ferroelectric layer 3 away from the inner wall of the first opening K.

[0226] Among them, the thermal expansion coefficient of the functional layer 4 is less than that of the ferroelectric layer 3.

[0227] N3: Annealing is performed.

[0228] N4: As Figure 33 and Figure 34 shown, the functional layer 4 is removed, and a second electrode layer 2 is formed in the cavity Q2 formed after removing the functional layer 4.

[0229] Exemplarily, step N4 may include:

[0230] N41: Referring to Figure 33 , the functional layer 4 is removed to form a cavity Q2.

[0231] N42: Referring to Figure 34 , the cavity Q2 is filled with a conductive material to form a second electrode layer 2.

[0232] By replacing the functional layer 4 with a conductive material after annealing, while satisfying the regulation of the polarization orientation in the ferroelectric layer 3, it can also ensure that there is a sufficient effective capacitance area between the second electrode layer 2 and the ferroelectric layer 3.

[0233] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present disclosure, thinking of changes or substitutions, should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claimed rights.

Claims

1. A storage array, characterized in that, it includes: a ferroelectric layer; a first electrode layer and a second electrode layer, the first electrode layer and the second electrode layer are respectively disposed on both sides of the ferroelectric layer; at least one functional layer, embedded in the first electrode layer and / or the second electrode layer, and the at least one functional layer is in contact with the side surface of the ferroelectric layer; wherein, the coefficient of thermal expansion of the functional layer is less than that of the ferroelectric layer.

2. The storage array according to claim 1, characterized in that, the coefficient of thermal expansion of the functional layer is less than that of the electrode layer in which the functional layer is embedded.

3. The storage array according to claim 1 or 2, characterized in that, the electrode layer in which the functional layer is embedded includes a plurality of sub-layers, and the at least one functional layer and the plurality of sub-layers are alternately stacked in a third direction; the third direction is parallel to the side surface of the ferroelectric layer.

4. The storage array according to claim 3, characterized in that, it further includes: a first contact structure, at least penetrating the plurality of sub-layers and electrically connected to the plurality of sub-layers.

5. The storage array according to claim 1 or 2, characterized in that, the electrode layer in which the functional layer is embedded includes a first sub-layer and a second sub-layer, and the first sub-layer and the second sub-layer are alternately stacked in a third direction; the first sub-layer is in contact with the side surface of the ferroelectric layer; the functional layer is arranged on the same layer as the second sub-layer, and the functional layer is arranged between the ferroelectric layer and the second sub-layer.

6. The storage array according to claim 5, characterized in that, it further includes: a second contact structure, electrically connected to at least one layer of the first sub-layer or at least one layer of the second sub-layer.

7. The storage array according to any one of claims 3 to 6, characterized in that, when the electrode layer in which the functional layer is embedded includes a plurality of sub-layers, the ratio of the thickness of the sub-layer to that of the functional layer is 0.5 to 5; or, when the electrode layer in which the functional layer is embedded includes a first sub-layer and a second sub-layer, the ratio of the thickness of the first sub-layer to that of the functional layer is 0.5 to 5.

8. The storage array according to any one of claims 1 to 7, characterized in that, the storage array includes a plurality of functional layers; the plurality of functional layers are spaced apart in a third direction, and the distance between every two adjacent functional layers is equal.

9. The storage array according to any one of claims 1 to 8, characterized in that, the ferroelectric layer is annular; the ferroelectric layer surrounds the first electrode layer, and the second electrode layer surrounds the ferroelectric layer; the functional layer is embedded in the second electrode layer.

10. The storage array according to any one of claims 1 to 9, characterized in that, it includes: a plurality of storage units, each storage unit includes the ferroelectric layer, the first electrode layer, the second electrode layer and the functional layer; the plurality of storage units can be arranged in at least one of a first direction, a second direction and a third direction; the first direction, the second direction and the third direction are perpendicular to each other in pairs.

11. The storage array according to claim 10, characterized in that, It further includes: An insulating layer disposed between two adjacent memory cells arranged along the third direction; When the ferroelectric layer is annular, the adjacent memory cells arranged along the third direction share the first electrode layer and the ferroelectric layer, and the insulating layer and the second electrode layer are alternately stacked along the third direction; Wherein, the thermal expansion coefficient of the insulating layer is less than that of the ferroelectric layer.

12. The memory array according to any one of claims 1 to 11, Characterized in that The material of the functional layer includes SiO 2 , at least one of SiN, SiGe, SiC, and h-BN.

13. A memory, Characterized in that It includes: The memory array according to any one of claims 1 to 12; A peripheral circuit electrically connected to the memory array.

14. An electronic device, Characterized in that It includes: The memory according to claim 13; A circuit board electrically connected to the memory.

15. A method for manufacturing a memory array, Characterized in that It includes: Forming a second electrode layer and embedding at least one functional layer in the second electrode layer; Forming a first opening; The first opening penetrates the second electrode layer and the functional layer; Forming a ferroelectric layer on the inner wall of the first opening; the functional layer is in contact with the side surface of the ferroelectric layer; Filling the first opening to form a first electrode layer; the first electrode layer and the second electrode layer are disposed on both sides of the ferroelectric layer; Wherein, the thermal expansion coefficient of the functional layer is less than that of the ferroelectric layer.

16. The manufacturing method according to claim 15, Characterized in that The second electrode layer includes a plurality of sub-layers; The forming of the second electrode layer and embedding the functional layer in the second electrode layer includes: Forming sub-layers and functional layers alternately stacked along the third direction; The third direction is parallel to the side surface of the ferroelectric layer.

17. The manufacturing method according to claim 15, Characterized in that The second electrode layer includes a first sub-layer and a second sub-layer; The forming of the second electrode layer and embedding the functional layer in the second electrode layer includes: Forming the first sub-layer and the second sub-layer alternately stacked along the third direction; After forming the first opening, through the first opening, removing a part of the second sub-layer close to the first opening to form a receiving cavity; Filling the functional layer in the receiving cavity.

18. A method for manufacturing a memory array, Characterized in that It includes: Alternately stacking an insulating layer and a functional layer along the third direction; Forming a first opening and sequentially forming a ferroelectric layer and a first electrode layer in the first opening; the first opening penetrates the insulating layer and the functional layer; the ferroelectric layer is disposed on the inner wall of the first opening, and the first electrode layer is disposed on the side of the ferroelectric layer away from the inner wall of the first opening; the thermal expansion coefficient of the functional layer is less than that of the ferroelectric layer; Performing annealing; Removing the functional layer and forming a second electrode layer in the cavity formed after removing the functional layer.

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