Magnetic memory cell and magnetic memory device
By using a hybrid transistor in the magnetic memory cell, connecting the second gate body with the bit line and adjusting the width of the first gate body, the problem of inconsistent writing time in different switching processes is solved, and the effect of improving the memory read and write performance and maintaining reliability is achieved.
Patent Information
- Application Number
- CN202510275910.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-10
- Publication Date
- 2025-05-27
AI Technical Summary
The write time of the magnetic storage unit during parallel and anti-parallel switching processes is different, which affects the overall storage efficiency of the magnetic storage device.
A hybrid transistor is adopted, including an embedded substrate, a top silicon oxide layer and a gate structure, and the second gate body is connected to the bit line, and the write time is optimized by adjusting the width of the first gate body and the voltage of the second gate body.
It realizes that the memory read and write performance is improved and the reliability of the magnetic memory device is maintained without being disturbed by the back gate voltage, avoiding the problems caused by false flips and total dose effects.
Smart Images
Figure CN120050943A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of novel micro-nano electronic devices, and particularly relates to a magnetic storage unit and a magnetic storage device. Background Art
[0002] The second-generation magnetic random access memory (MRAM), that is, the spin transfer torque-magnetic random access memory (STT-MRAM), is an advanced storage technology. Among them, the storage unit of STT-MRAM includes a magnetic tunnel junction (MTJ) for storing information and a transistor. By applying voltages to the gate, source, and drain of the transistor, a perpendicular current is provided for the magnetic tunnel junction to realize the read and write of the magnetic storage unit.
[0003] However, when the magnetic tunnel junction switches, since the driving voltages of the transistor are different during the parallel (P) to anti-parallel (AP) switching and anti-parallel (AP) to parallel (P) switching processes of the magnetic storage unit, the magnitudes of the currents of the transistor are different. To meet the energy threshold required for the magnetic storage unit to flip, the writing times of the magnetic storage unit in the two switching processes are different, which affects the overall storage efficiency of the magnetic storage device. Summary of the Invention
[0004] The purpose of the present invention is to provide a magnetic storage unit and a magnetic storage device, which can solve the problem that the writing times of the magnetic storage unit in the two switching processes are different, affecting the overall storage efficiency of the magnetic storage device.
[0005] To achieve the above purpose, the present invention provides a magnetic storage unit and a magnetic storage device, wherein the magnetic storage unit at least includes a magnetic tunnel junction and a hybrid transistor, and the hybrid transistor includes:
[0006] An embedded substrate, including a substrate and an oxide layer on the substrate, with a groove provided on the oxide layer, and the groove extends to the surface of the substrate;
[0007] A top silicon oxide layer, including two electrode layers and two bridging layers. The two electrode layers are disposed on both sides of the groove to form a source electrode and a drain electrode, and the electrode layers are disposed parallel to the groove. The two bridging layers are disposed parallel to each other, and both ends of each bridging layer are connected to the electrode layers on both sides of the groove;
[0008] The gate structure includes a first gate body and a second gate body. The first gate body is disposed on the groove, and the first gate body fills the groove and covers the bridging layer on the top of the groove. The second gate body is disposed on the oxide layers on both sides of the groove;
[0009] Wherein, the magnetic tunnel junction and the hybrid transistor are connected in series between the bit line and the source line;
[0010] Wherein, the first gate body is electrically connected to the word line, and the second gate body is electrically connected to the bit line.
[0011] In an embodiment of the present invention, the bridging layer is perpendicular to the electrode layer.
[0012] In an embodiment of the present invention, the proportion of the width of the first gate body in the total width of the gate structure ranges from 0.4 to 0.8.
[0013] In an embodiment of the present invention, the first gate body and the second gate body are arranged at the same height.
[0014] In an embodiment of the present invention, the free layer of the magnetic tunnel junction is electrically connected to the bit line, and the fixed layer of the magnetic tunnel junction is electrically connected to the source or drain of the hybrid transistor.
[0015] In an embodiment of the present invention, when the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction are switched from parallel to antiparallel, the word line voltage is less than the fixed operating voltage, the bit line voltage is equal to the first back gate voltage, the source line voltage is equal to 0V voltage, and the back gate voltage is equal to the first back gate voltage.
[0016] In an embodiment of the present invention, when the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction are switched from antiparallel to parallel, the word line voltage is less than the fixed operating voltage, the bit line voltage is equal to the second back gate voltage, the source line voltage is equal to 0V voltage, and the back gate voltage is equal to the second back gate voltage.
[0017] In an embodiment of the present invention, the first back gate voltage is equal to -V DD , where V DD is the fixed operating voltage.
[0018] In an embodiment of the present invention, the second back gate voltage is equal to V DD , where V DD is the fixed operating voltage.
[0019] The present invention also provides a magnetic storage device, including the magnetic storage unit described in any one of the above.
[0020] In summary, for the magnetic storage unit and the magnetic storage device provided by the present invention, a hybrid transistor is arranged in the magnetic storage unit, and the back gate contact is connected to the bit line through the second gate body. When the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction are switched from anti-parallel (AP) to parallel (P), the back gate is positively biased. Different from the conduction of a transistor caused by the opening of the back channel of a traditional SOI or the conduction of the body-source PN junction of a bulk silicon device, other storage units under the control of the same bit line are still controlled by their respective word lines and remain in the off state, without incorrect flipping, thereby achieving the improvement of storage read / write performance while maintaining the reliability of the magnetic storage device without being interfered by the back gate voltage. Secondly, compared with the traditional use of SOI transistors to drive flipping, the magnetic storage unit is not affected by the total dose effect. The total dose effect will accumulate a layer of positive charges in the buried oxide layer of the SOI transistor, causing a layer of negative charges to be induced in the back interface channel, resulting in the conduction of the channel. However, the switching of the back channel of the hybrid transistor is strongly controlled by the word line, so that the leakage path of the back channel current caused by irradiation can be eliminated. Moreover, the back gate power supply can be directly synchronized with the bit line without the need for an additional complex dynamic power supply circuit, simplifying the complexity of the layout and the required area. Finally, according to the customization requirements of different memories, by adjusting the ratio of the width of the first gate body to the total width of the transistor channel, the improvement of the back gate adjustment ability and the anti-hot carrier damage ability of the local magnetic storage unit can be achieved, so as to provide additional protection for the vulnerable and consumable transistors in the storage chip and improve their adjustable ability to cope with problems such as aging. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0022] Figure 1 It is a structural diagram of a magnetic tunnel junction and a magnetic storage unit.
[0023] Figure 2 Figure (a) in [the figure] is a potential distribution diagram and the corresponding current-voltage characteristic diagram before and after applying a back gate voltage to the hybrid transistor. Figure 2 Figure (b) in [the figure] is a potential distribution diagram and the corresponding current-voltage characteristic diagram before and after applying a back gate voltage to the π-gate transistor. Figure 2 Figure (c) in [the figure] is a potential distribution diagram and the corresponding current-voltage characteristic diagram before and after applying a back gate voltage to the surrounding gate transistor.
[0024] Figure 3 It is a circuit diagram and bias voltage of a traditional magnetic storage unit.
[0025] Figure 4Circuit diagram and bias voltage of a magnetic storage cell with negative bit line technology.
[0026] Figure 5 Circuit diagram and bias voltage of a magnetic storage cell using hybrid transistors.
[0027] Figure 6 Structural diagram of the manufacturing process of the top oxide layer in hybrid transistors.
[0028] Figure 7 Structural diagram of the manufacturing process of the gate structure in hybrid transistors. Detailed implementation manners
[0029] For ease of understanding this application, the following will provide a more comprehensive description of this application with reference to the relevant drawings. The preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of this application more thorough and comprehensive.
[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0031] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by terms such as "center", "upper", "lower", "front", "rear", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation of the present invention. The degrees indicated by "high", "low", etc. are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have high or low, and thus cannot be understood as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.
[0032] Please refer to Figure 1As shown, in the present application, the storage unit in the magnetic storage device is a magnetic storage unit, and each magnetic storage unit includes a transistor and a magnetic tunnel junction. Among them, the magnetic tunnel structure includes a free layer, a tunnel junction layer, and a fixed layer, and the tunnel junction layer is disposed between the free layer and the fixed layer. The magnetization of the fixed layer is fixed along the easy magnetization axis direction (Easy - Axis), and the magnetization of the free layer has two stable orientations, which can be parallel (P) or anti - parallel (AP) to the fixed layer respectively. When the magnetization directions of the fixed layer and the free layer are parallel (P), the tunneling probability of electrons in the majority state with the same spin direction in the two ferromagnetic materials is relatively high, the tunneling current is large, and the magnetic tunnel junction presents a low - resistance state. On the contrary, when the magnetization directions of the fixed layer and the free layer are anti - parallel (AP), the tunneling current is small, and the magnetic tunnel junction presents a high - resistance state. The two resistance states of the magnetic tunnel junction can respectively represent binary data "0" and "1". When reading and writing to the storage unit, a voltage can be applied to the gate, source 104, and drain 105 of the transistor to turn on the transistor. Furthermore, a switching current is provided for the magnetic tunnel junction, so that the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction are switched between parallel (P) and anti - parallel (AP).
[0033] Please refer to Figure 1 and Figure 3 As shown, in one embodiment, the magnetic storage unit is connected in series between the bit line BL (Bit Line) and the source line SL (Source Line). That is, the free layer of the magnetic tunnel junction is electrically connected to the bit line BL, the fixed layer is electrically connected to the source / drain of the transistor, the drain / source of the transistor is electrically connected to the source line SL, and the gate of the transistor is electrically connected to the word line WL (Word Line). As Figure 3 In the magnetic storage unit Cell0 in, when the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction are switched from parallel (P) to anti - parallel (AP), the word line voltage V WL applied on the word line WL is the fixed operating voltage V DD , the bit line voltage V BL applied on the bit line BL is 0V voltage, the source line voltage V BL applied on the source line SL is the fixed operating voltage V DD , and the back - gate voltage V B applied on the back - gate is 0V voltage. Among them, the fixed operating voltage V DD is, for example, 1.2V voltage, which can be specifically adjusted according to the driving ability of the transistor under different processes. As Figure 3 In the magnetic storage unit Cell1 in, when the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction are switched from anti - parallel (AP) to parallel (P), the word line voltage V WL applied on the word line WL is the fixed operating voltage V DD , the bit line voltage V BLis V DD is the source line voltage V applied on the source line SL BL is 0V. The back gate voltage V applied on the back gate B is 0V. In a magnetic storage device, if the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction in the magnetic storage cell Cell0 are simultaneously switched from parallel (P) to anti-parallel (AP), and the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction in the magnetic storage cell Cell1 are switched from anti-parallel (AP) to parallel (P), the overdrive voltages of the transistors in the two resistance states are different, resulting in different magnitudes of the drive currents provided by the transistors. Specifically, the overdrive voltage of the transistor in the magnetic storage cell Cell0 is Vov1 = V DD - V x @Cell0, and the overdrive voltage of the transistor in the magnetic storage cell Cell1 is Vov2 = V DD @Cell1. Among them, V x @Cell0 is the source-drain voltage difference of the transistor after the magnetic tunnel junction in the magnetic storage cell Cell0 is voltage-divided, and V x @Cell0 ranges from 0 to V DD . V DD @Cell1 is the fixed operating voltage in the magnetic storage cell Cell1, and V DD @Cell1 is, for example, 1.2V. At this time, to meet the energy threshold required for the magnetic tunnel junction to flip, the magnetic storage cell Cell0 requires a longer write time. At this time, the write time of the magnetic storage cell Cell0 is much longer than that of the magnetic storage cell Cell1. The overall write time of the magnetic storage device is determined by the magnetic storage cell with the longest write time, that is, for example, determined by the write time of the magnetic storage cell Cell0. At this time, the overall write time of the magnetic storage device is much longer than the write time of a normal magnetic storage cell, resulting in an overly long overall write time of the magnetic storage device.
[0034] Please refer to Figure 4 As shown, in some embodiments, under the condition that the reliability of the device gate dielectric deteriorates under a higher voltage difference limit (the limit condition is V WL - V x = V DD) To reduce the time for the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction to switch from antiparallel (AP) to parallel (P), a magnetic storage cell is provided. The magnetic storage cells are connected in series between the bit line BL and the source line SL. That is, the free layer of the magnetic tunnel junction is electrically connected to the bit line BL, the fixed layer is electrically connected to the source / drain of the transistor, the drain / source of the transistor is electrically connected to the source line SL, and the gate of the transistor is electrically connected to the word line WL. It should be noted that in this embodiment, the source line SL of the transistor is electrically connected to the ground terminal, so that when the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction switch from parallel (P) to antiparallel (AP), the voltage value of the bit line BL is less than 0V, thereby increasing the drive current of the transistor, and thus shortening the time for the magnetization directions of the free layer and the fixed layer to switch from parallel (P) to antiparallel (AP). As Figure 4 In the magnetic storage cell Cell0 in WL , when the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction switch from parallel (P) to antiparallel (AP), the word line voltage V DD applied on the word line WL is less than the fixed operating voltage V BL , the bit line voltage V BL applied on the bit line BL is less than 0V, the source line voltage V B applied on the source line SL is 0V, and the back gate voltage V WL applied on the back gate is less than 0V. As shown in the magnetic storage cell Cell1 in the figure, when the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction switch from antiparallel (AP) to parallel (P), the word line voltage V DD applied on the word line WL is less than the fixed operating voltage V BL , the bit line voltage V DD applied on the bit line BL is equal to the fixed operating voltage V BL , the source line voltage V B applied on the source line SL is 0V, and the back gate voltage V Figure 3 shown in the embodiment, Figure 4The overdrive voltage of the transistor of the magnetic storage unit Cell0 increases, thereby increasing the drive current of the transistor, and further shortening the time for the magnetization directions of the free layer and the fixed layer to change from parallel (P) to antiparallel (AP). However, at the same time, the overdrive voltage of the transistor of the storage unit Cell1 decreases, thereby reducing the drive voltage of the transistor, and further shortening the time for the magnetization directions of the free layer and the fixed layer to change from antiparallel (AP) to parallel (P), resulting in a decrease in the write speed of the storage unit Cell1 and making the overall write time of the magnetic storage device uncontrollable.
[0035] Please refer to Figures 5 to 7 As shown, in an embodiment of the present invention, a magnetic storage unit is provided, including a magnetic tunnel junction and a hybrid transistor. Among them, the magnetic storage unit is connected in series between the bit line BL and the source line SL. That is, the free layer of the magnetic tunnel junction is electrically connected to the bit line BL, the fixed layer is electrically connected to the source / drain of the hybrid transistor, the drain / source of the hybrid transistor is electrically connected to the source line SL, and the gate structure 103 of the hybrid transistor includes a first gate body 1031 and a second gate body 1032. The first gate body 1031 is electrically connected to the word line WL, and the second gate body 1032 is electrically connected to the bit line BL.
[0036] Please refer to Figures 6 to 7 As shown, in an embodiment of the present invention, the hybrid transistor includes an embedded substrate 101, a top oxide layer 102, and a gate structure 103. Among them, the top oxide layer 102 disposed on the embedded substrate 101 can form a channel and source / drain regions.
[0037] Specifically, please refer to Figure 6 As shown, in an embodiment of the present invention, the embedded substrate 101 includes a substrate 1011 and an oxide layer 1012, and the oxide layer 1012 is disposed on the substrate 1011. The substrate 1011 is a silicon substrate, and the material of the substrate 1011 can be selected from undoped single-crystalline silicon, single-crystalline silicon doped with impurities, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. In this embodiment, the substrate 1011 is single-crystalline silicon and is undoped single-crystalline silicon. The oxide layer 1012 is disposed on the substrate 1011, and a groove 1013 is disposed on the oxide layer 1012. The groove 1013 extends from the surface of the oxide layer 1012 to the surface of the substrate 1011, that is, the bottom wall of the groove 1013 contacts the substrate 1011, and the side wall of the groove 1013 is perpendicular to the bottom wall. Among them, the oxide layer 1012 is, for example, a silicon oxide layer.
[0038] Please refer to Figure 6As shown, in an embodiment of the present invention, a top silicon oxide layer 102 is formed on an embedded substrate 101, and the top silicon oxide layer 102 is etched such that the etched top silicon oxide layer includes two electrode layers 1021 and two bridging layers 1022. Among them, the two electrode layers 1021 are disposed on both sides of the groove 1013 for forming a source electrode 104 and a drain electrode 105. In this embodiment, the two electrode layers 1021 are arranged parallel to the groove 1013, and the edges of the two electrode layers 1021 and the edges of the groove 1013 respectively have a first spacing. That is, in this embodiment, the distances between the two electrode layers 1021 and the groove 1013 are equal. In other embodiments, the distances between the two electrode layers 1021 and the groove 1013 may also be unequal.
[0039] Please refer to Figure 6 As shown, in an embodiment of the present invention, the two bridging layers 1022 are arranged in parallel, and both ends of each bridging layer 1022 are connected to the electrode layers 1021 on both sides of the groove 1013. That is, one end of each bridging layer 1022 is connected to one electrode layer 1021, and the other end crosses the groove 1013 and is connected to the other electrode layer 1021. In this embodiment, the bridging layer 1022 is arranged perpendicular to the electrode layer 1021. After forming the hybrid transistor, the middle part of the bridging layer 1022 is equivalent to the channel of the hybrid transistor.
[0040] Please refer to Figure 6 As shown, in an embodiment of the present invention, when forming the electrode layer 1021 and the bridging layer 1022, a layer of silicon oxide layer can be deposited on the embedded substrate 101 as the top silicon oxide layer 102 first, and then the top silicon oxide layer 102 in the groove 1013 and the top silicon oxide layer 102 except for the positions where the two electrode layers 1021 and the two bridging layers 1022 are located on the oxide layer 1012 are etched away by dry etching.
[0041] Please refer to Figures 6 to 7As shown, in an embodiment of the present invention, after etching the top silicon oxide layer 102 to form two electrode layers 1021 and two bridging layers 1022, polysilicon is deposited on and on both sides of the groove 1013 using an atomic precipitation process to form a gate structure 103. For the convenience of gate function description, the gate structure 103 is divided into a first gate body 1031 and a second gate body 1032. Among them, the first gate body 1031 fills the groove 1013 and covers the bridging layer 1022 above the groove 1013, and the second gate body 1032 is disposed on the oxide layer 1012 on both sides of the groove 1013, and the second gate body 1032 covers a part of the two bridging layers 1022. And the second gate body 1032 and the first gate body 1031 are set at the same height. At this time, the formed first gate body 1031 surrounds the two bridging layers 1022 directly above the groove 1013, that is, the first gate body 1031 wraps the channel. The second gate bodies 1032 on both sides of the first gate body 1031 cover the bridging layer 1022 from three directions, and the bottom of the bridging layer 1022 where the second gate body 1032 is located contacts the oxide layer 1012 of the embedded substrate 101.
[0042] Please refer to Figure 7 As shown, in an embodiment of the present invention, the width of the first gate body 1031 is defined as the first width, and the width of the second gate body 1032 is defined as the second width. Then the total width of the gate structure 103 is the first width + 2 * the second width. In this application, the ratio of the width of the first gate body 1031 to the total width of the gate structure 103 is adjustable, and the ratio range of the width of the first gate body 1031 to the total width of the gate structure 103 is 0.4 to 0.8.
[0043] Please refer to Figure 7 As shown, in an embodiment of the present invention, after forming the gate structure 103, ions are implanted into the electrode layer 1021 to form a source 104 and a drain 105 of the hybrid gate. Since the source 104 and the drain 105 in the hybrid transistor are symmetrically arranged with respect to the gate structure 103, the specific positions of the source 104 and the drain 105 are not limited in this application.
[0044] Please refer to Figure 2 and Figure 7 As shown, the hybrid transistor formed by the present invention including the first gate body 1031 and the second gate body 1032 overcomes the problem that the leakage current increases significantly when applying a back gate voltage in the traditional π-gate device ( Figure 2 (b) in the figure), which is different from the fully enclosed surrounding gate device that cannot adjust the electrical characteristics of the device through the back gate ( Figure 2 (c) in the figure). The hybrid transistor realizes the ability to adjust the electrical characteristics by the back gate (the second gate body 1032) voltage while retaining the ability to turn off the front gate (the first gate body 1031) to shield the current of the back gate channel.
[0045] Please refer to Figures 5 to 7 As shown, in an embodiment of the present invention, when connecting the hybrid transistor, the first gate body 1031 is electrically connected to the word line WL, and the second gate body 1032 is electrically connected to the bit line BL. At this time, by adaptively adding a back gate bias voltage to the second gate body 1032 on both sides of the gate structure 103 to compensate for the current and speed losses caused by the negative bit line read / write technology, the write time of the magnetic storage unit Cell1 is shortened. At the same time, the first gate body 1031 can isolate the influence on the other magnetic storage units on the same bit line BL when the bit line BL is positively biased, solve the problem of misflipping caused by the positive back gate in the transistor, and the back channel leakage caused by the total dose effect will cause state error codes, optimizing the performance and reliability of the integrated circuit memory.
[0046] Relative to Figure 4 As shown Figure 5 For the magnetic storage unit shown, by adaptively adding a back gate bias voltage to the second gate body 1032 on both sides of the gate structure 103 to compensate for the current and speed losses caused by the negative bit line read / write technology, the write time of the magnetic storage unit Cell1 is shortened. That is, the time for the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction in the magnetic storage unit Cell1 to change from parallel (P) to antiparallel (AP) is shortened. Specifically, for the magnetic storage unit Cell0 in Figure 5 , when the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction change from parallel (P) to antiparallel (AP), the word line voltage V applied on the word line WL WL is less than the fixed operating voltage V DD , the bit line voltage V applied on the bit line BL BL is the first back gate voltage V BL1 , and the first back gate voltage V BL1 is less than 0V, and the first back gate voltage V BL1 is equal to -V DD , so that after the magnetic tunnel junction is voltage-divided, a suitable source-drain voltage difference V of the transistor can still be provided x and overdrive voltage (<V DD -V x ), and then a high drive current is generated for the magnetic tunnel junction to flip. The source line voltage V applied on the source line SL BL is 0V, and the back gate voltage V applied on the back gate B is equal to the first back gate voltage V BL1 . For example, for the magnetic storage unit Cell1 in Figure 5 , when the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction change from antiparallel (AP) to parallel (P), the word line voltage V applied on the word line WL WL is less than the fixed operating voltage V DD, a bit line voltage V applied to the bit line BL BL is equal to the second back gate voltage V BL2 , and the second back gate voltage V BL2 is greater than 0V, and the second back gate voltage V BL is equal to V DD , so that the transistor also obtains a source-drain voltage difference with a similar value after the magnetic tunnel junction is voltage-divided. The deficiency of the overdrive voltage (<V DD ) is compensated by the second back gate voltage V BL2 . The source line voltage V BL applied to the source line SL is 0V, and the back gate voltage V B applied to the back gate is equal to the second back gate voltage V BL2 . If the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction in the magnetic storage cell Cell0 are switched from parallel (P) to anti-parallel (AP) and the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction in the magnetic storage cell Cell1 are switched from anti-parallel (AP) to parallel (P) at the same time, relative to Figure 4 In the embodiment shown, when the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction are switched from anti-parallel (AP) to parallel (P), the bit line BL simultaneously applies a positive voltage to the back gate, effectively compensating for the speed reduction problem caused by the insufficient word line WL voltage in the negative bit line BL technology.
[0047] In summary, the magnetic storage unit provided by this application includes: an embedded substrate, including a substrate and an oxide layer on the substrate, with a groove provided on the oxide layer and the groove extending to the surface of the substrate; a top silicon oxide layer, including two electrode layers and two bridging layers, the two electrode layers are arranged on both sides of the groove to form a source electrode and a drain electrode, and the electrode layers are arranged parallel to the groove, the two bridging layers are arranged in parallel, and both ends of each bridging layer are connected to the electrode layers on both sides of the groove; a gate structure, including a first gate body and a second gate body, the first gate body is arranged on the groove, and the first gate body fills the groove and covers the bridging layer on the top of the groove, the second gate body is arranged on the oxide layer on both sides of the groove, and the second gate body is arranged at the same height as the first gate body; wherein, the magnetic tunnel junction and the hybrid transistor are connected in series between the bit line and the source line; wherein, the first gate body is electrically connected to the word line, and the second gate body is electrically connected to the bit line. For the magnetic storage unit provided by this application, when the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction switch from anti-parallel (AP) to parallel (P), the back gate is positively biased. Different from the conduction of the transistor caused by the opening of the back channel of the traditional SOI or the conduction of the body-source PN junction of the bulk silicon device, other storage units under the control of the same bit line are still controlled by their respective word lines and remain in the off state, and no error flipping will occur, thereby improving the storage read-write performance while maintaining the reliability of the magnetic storage device without being interfered by the back gate voltage. Secondly, compared with the traditional use of SOI transistors to drive the flip, the magnetic storage unit is not affected by the total dose effect. The total dose effect will accumulate a layer of positive charges in the buried oxide layer of the SOI transistor, causing a layer of negative charges to be induced in the back interface channel, making the channel conductive, while the switching of the back channel of the hybrid transistor is strongly controlled by the word line, so that the leakage path of the back channel current caused by irradiation can be eliminated. Furthermore, the back gate power supply can be directly synchronized with the bit line without the need for an additional complex dynamic power supply circuit, simplifying the complexity of the layout and the required area. Finally, according to the customization requirements of different memories, by adjusting the ratio of the width of the first gate body to the total width of the transistor channel, the back gate adjustment ability and the anti-hot carrier damage ability of the local magnetic storage unit can be improved, so as to provide additional protection for the vulnerable and consumable transistors in the storage chip and improve their adjustable ability to cope with problems such as aging.
[0048] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and utilize the present invention well. The present invention is only limited by the claims and their full scope and equivalents.
Claims
1. A magnetic storage unit, characterized in that: At least includes a magnetic tunnel junction and a hybrid transistor, and the hybrid transistor includes: An embedded substrate comprises a base and an oxide layer on the base, wherein the oxide layer is provided with a groove, and the groove extends to the surface of the base; The top silicon oxide layer includes two electrode layers and two bridge layers, wherein the two electrode layers are arranged on both sides of the groove to form a source electrode and a drain electrode, and the electrode layers are arranged in parallel with the groove, and the two bridge layers are arranged in parallel, and both ends of each bridge layer are connected to the electrode layers on both sides of the groove; A gate structure, comprising a first gate body and a second gate body, wherein the first gate body is arranged on the groove, and the first gate body fills the groove and covers the bridge layer at the top of the groove, and the second gate body is arranged on the oxide layer on both sides of the groove; Wherein, the magnetic tunnel junction and the hybrid transistor are connected in series between a bit line and a source line; The first gate body is electrically connected to the word line, and the second gate body is electrically connected to the bit line.
2. A magnetic storage unit according to claim 1, characterized in that: The bridge layer is perpendicular to the electrode layer.
3. A magnetic storage unit according to claim 1, characterized in that: The width of the first gate body accounts for 0.4 to 0.8 of the total width of the gate structure.
4. A magnetic storage unit according to claim 1, characterized in that: The first gate body and the second gate body are arranged at the same height.
5. The magnetic storage unit according to claim 1, characterized in that: The free layer of the magnetic tunnel junction is electrically connected to the bit line, and the fixed layer of the magnetic tunnel junction is electrically connected to the source or drain of the hybrid transistor.
6. A magnetic storage unit according to claim 1, characterized in that: When the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction switch from parallel to antiparallel, the word line voltage is less than the fixed operating voltage, the bit line voltage is equal to the first back gate voltage, the source line voltage is equal to 0V, and the back gate voltage is equal to the first back gate voltage.
7. A magnetic storage unit according to claim 6, characterized in that: When the magnetization directions of the free layer and the fixed layer of the magnetic tunnel junction switch from antiparallel to parallel, the word line voltage is less than the fixed operating voltage, the bit line voltage is equal to the second back gate voltage, the source line voltage is equal to 0V, and the back gate voltage is equal to the second back gate voltage.
8. The magnetic storage unit according to claim 6, characterized in that: The first back gate voltage is equal to -V DD , where V DD is the fixed operating voltage.
9. The magnetic storage unit according to claim 7, characterized in that: The second back gate voltage is equal to V DD , where V DD is the fixed operating voltage.
10. A magnetic storage device, characterized in that: Comprising the magnetic storage unit according to any one of claims 1 to 9.